[llvm-branch-commits] [llvm] [NFC][AMDGPU] Reorganize dasm error tests (PR #215168)

Sun Aug 9 19:35:26 PDT 2026

llvmorg-github-actions[bot] wrote:




@llvm/pr-subscribers-backend-amdgpu

Author: Shilei Tian (shiltian)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/215168.diff


6 Files Affected:

- (removed) llvm/test/MC/Disassembler/AMDGPU/decode-err.txt (-135) 
- (added) llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_err.txt (+43) 
- (added) llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_err.txt (+48) 
- (added) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_err.txt (+38) 
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_err.txt (+10) 
- (added) llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt (+10) 


``````````diff

diff --git a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt b/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
deleted file mode 100644
index e3a10b05ce7e4..0000000000000
--- a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
+++ /dev/null
@@ -1,135 +0,0 @@
-# RUN: llvm-mc -triple=amdgpu9.00 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GCN-ERR %s
-# RUN: llvm-mc -triple=amdgpu9.50 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GFX950-ERR %s
-# RUN: llvm-mc -triple=amdgpu11.00 -disassemble -show-encoding < %s | FileCheck -check-prefixes=W32 %s
-# RUN: llvm-mc -triple=amdgpu11.00 -mattr=+wavefrontsize64 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefixes=W64 %s
-# RUN: llvm-mc -triple=amdgpu12.00 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GFX12-ERR %s
-# RUN: llvm-mc -triple=amdgpu12.50 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GFX1250-ERR %s
-
-# GCN-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xdf,0x00,0x00,0x02
-
-# This is v_readfirstlane_b32 with an SGPR destination that does not fit the
-# 7-bit scalar register encoding of the 8-bit VOP1 vdst field.
-# GCN-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0x05,0xf4,0x7f
-
-# This is v_s_exp_f32 with an SGPR destination that does not fit the 7-bit
-# scalar register encoding of the 8-bit VOP3 vdst field.
-# GFX12-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xfa,0x00,0x80,0xd6,0x01,0x00,0x01,0x02
-
-# this is s_waitcnt_vscnt exec_hi, 0x1234, which is valid on gfx11, but not on gfx12
-# GFX12-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x34,0x12,0x7f,0xbc
-
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xa0,0x4e,0x80,0xbe
-
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xc5,0x4e,0x80,0xbe
-
-# Literal constants are invalid for split barrier operands.
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xff,0x4e,0x80,0xbe,0xbe,0x00,0x00,0x00
-
-# src_private_base (237) and src_private_limit (238) are reserved on targets
-# with globally addressable scratch. Both the 32-bit and the 64-bit operand
-# forms are covered here.
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xed,0x0e,0x80,0xbe
-
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xed,0x01,0xfe,0xbe
-
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xee,0x0e,0x80,0xbe
-
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xee,0x01,0xfe,0xbe
-
-# src_pops_exiting_wave_id (239) is only available on targets that support
-# POPS.
-# GFX12-ERR: [[@LINE+2]]:1: warning: invalid instruction encoding
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0xef,0x0c,0xbf
-
-# src_vccz (251) and src_execz (252) are reserved on GFX11+.
-# GFX12-ERR: [[@LINE+2]]:1: warning: invalid instruction encoding
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xfb,0x0e,0x80,0xbe
-
-# GFX12-ERR: [[@LINE+2]]:1: warning: invalid instruction encoding
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xfc,0x0e,0x80,0xbe
-
-# W32: v_dual_add_f32 v5, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, v3, v1, 0xaf123456 ; encoding: [0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf]
-# W64: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf
-
-# GFX11: v_swap_b16 v5.h, s1/*Invalid register, operand has 'VGPR_16_Lo128' register class*/ ; encoding: [0x01,0xcc,0x0a,0x7f]
-# GFX12: v_swap_b16 v5.h, s1/*Invalid register, operand has 'VGPR_16_Lo128' register class*/ ; encoding: [0x01,0xcc,0x0a,0x7f]
-0x01,0xcc,0x0a,0x7f
-
-# GFX11: v_swap_b16 v5.h, 0x3c00/*Invalid immediate*/ ; encoding: [0x00,0xcc,0x0a,0x7f]
-# GFX12: v_swap_b16 v5.h, 0x3c00/*Invalid immediate*/ ; encoding: [0x00,0xcc,0x0a,0x7f]
-0xf2,0xcc,0x0a,0x7f
-
-# GFX11: v_swap_b16 v5.h, 0x78563412/*Invalid immediate*/ ; encoding: [0x12,0xcc,0x0a,0x7f]
-# GFX12: v_swap_b16 v5.h, 0x78563412/*Invalid immediate*/ ; encoding: [0x12,0xcc,0x0a,0x7f]
-0xff,0xcc,0x0a,0x7f,0x12,0x34,0x56,0x78
-
-# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
-# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
-0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c
-
-# W32: v_wmma_f32_16x16x16_f16 v[16:23], 1.0/*Invalid immediate*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
-# W64: v_wmma_f32_16x16x16_f16 v[16:19], 1.0/*Invalid immediate*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
-0x10,0x40,0x40,0xcc,0xf2,0x10,0x42,0x1c # src0 1.0
-
-# W32: v_wmma_f32_16x16x16_f16 v[16:23], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
-# W64: v_wmma_f32_16x16x16_f16 v[16:19], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
-0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c # src0 sgpr0
-
-# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
-# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
-0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b # src2 1.0
-
-# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
-# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], s[0:3]/*Invalid register, operand has 'VReg_128' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
-0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18 # src2 sgpr0
-
-# this is ds_add_f32 with gds bit which is not valid on gfx12+
-# GFX12-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0x00,0x56,0xd8,0x00,0x01,0x00,0x00
-
-# this is image_msaa_load where samp field for gfx12 VSAMPLE is not all zeros
-# GFX12-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x06,0x00,0x46,0xe4,0x01,0x10,0x80,0x00,0x05,0x06,0x07,0x00
-
-# This is ds_read_b32 with gds bit which is not valid on gfx90a.
-# GFX90A: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0x00,0x6d,0xd8,0x01,0x00,0x00,0x00
-
-# The f8f6f4 source tuples are narrowed down according to cbsz/blgp, but ttmp
-# registers have no 192-bit tuple.
-# GFX950-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0x00,0xae,0xd3,0x00,0xe9,0x00,0x64
-
-# Same, except that the source selector is an inline constant, which is not a
-# register at all.
-# GFX950-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0x00,0xae,0xd3,0xf2,0x00,0x02,0x64
-
-# The wmma source tuples are narrowed down according to the matrix formats, but
-# scalar registers have no 384-bit tuple.
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0x18,0x33,0xcc,0x08,0x30,0xa2,0x04
-
-# This is s_load_b96 with a ttmp destination, which is not a supported
-# 96-bit scalar destination encoding.
-# GFX12-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0xbb,0x00,0xf4,0x00,0x00,0x00,0xf8
-
-# This encoding references a missing trailing literal.
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0x00,0x33,0xcc,0xff,0x68,0x02,0x02
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_err.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_err.txt
new file mode 100644
index 0000000000000..888a96bcfb8ce
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_err.txt
@@ -0,0 +1,43 @@
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
+# RUN: llvm-mc -triple=amdgpu11.00 -disassemble -show-encoding < %s | FileCheck -check-prefix=W32 %s
+# RUN: llvm-mc -triple=amdgpu11.00 -mattr=+wavefrontsize64 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefix=W64 %s
+
+# This VOPD encoding is valid in wave32 mode but invalid in wave64 mode.
+0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf
+# W32: v_dual_add_f32 v5, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, v3, v1, 0xaf123456 ; encoding: [0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf]
+# W64: :[[@LINE-2]]:1: warning: invalid instruction encoding
+
+# v_swap_b16 with an SGPR source.
+0x01,0xcc,0x0a,0x7f
+# W32: v_swap_b16 v5.h, s1/*Invalid register, operand has 'VGPR_16_Lo128' register class*/ ; encoding: [0x01,0xcc,0x0a,0x7f]
+# W64: v_swap_b16 v5.h, s1/*Invalid register, operand has 'VGPR_16_Lo128' register class*/ ; encoding: [0x01,0xcc,0x0a,0x7f]
+
+# v_swap_b16 with an inline constant source.
+0xf2,0xcc,0x0a,0x7f
+# W32: v_swap_b16 v5.h, 1.0/*Invalid immediate*/ ; encoding: [0x00,0xcc,0x0a,0x7f]
+# W64: v_swap_b16 v5.h, 1.0/*Invalid immediate*/ ; encoding: [0x00,0xcc,0x0a,0x7f]
+
+# v_swap_b16 with a literal constant source.
+0xff,0xcc,0x0a,0x7f,0x12,0x34,0x56,0x78
+# W32: v_swap_b16 v5.h, 0x78563412/*Invalid immediate*/ ; encoding: [0x12,0xcc,0x0a,0x7f]
+# W64: v_swap_b16 v5.h, 0x78563412/*Invalid immediate*/ ; encoding: [0x12,0xcc,0x0a,0x7f]
+
+0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c
+# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
+# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
+
+0x10,0x40,0x40,0xcc,0xf2,0x10,0x42,0x1c # src0 1.0
+# W32: v_wmma_f32_16x16x16_f16 v[16:23], 1.0/*Invalid immediate*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
+# W64: v_wmma_f32_16x16x16_f16 v[16:19], 1.0/*Invalid immediate*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
+
+0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c # src0 sgpr0
+# W32: v_wmma_f32_16x16x16_f16 v[16:23], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
+# W64: v_wmma_f32_16x16x16_f16 v[16:19], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
+
+0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b # src2 1.0
+# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
+# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
+
+0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18 # src2 sgpr0
+# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
+# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], s[0:3]/*Invalid register, operand has 'VReg_128' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_err.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_err.txt
new file mode 100644
index 0000000000000..2c1b5a83e6b5c
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_err.txt
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
+# RUN: llvm-mc -triple=amdgpu12.50 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GFX1250-ERR %s
+
+0xa0,0x4e,0x80,0xbe
+# GFX1250-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+0xc5,0x4e,0x80,0xbe
+# GFX1250-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# Literal constants are invalid for split barrier operands.
+0xff,0x4e,0x80,0xbe,0xbe,0x00,0x00,0x00
+# GFX1250-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# src_private_base (237) and src_private_limit (238) are reserved on targets
+# with globally addressable scratch. Both the 32-bit and the 64-bit operand
+# forms are covered here.
+0xed,0x0e,0x80,0xbe
+# GFX1250-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+0xed,0x01,0xfe,0xbe
+# GFX1250-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+0xee,0x0e,0x80,0xbe
+# GFX1250-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+0xee,0x01,0xfe,0xbe
+# GFX1250-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# src_pops_exiting_wave_id (239) is only available on targets that support
+# POPS.
+0x00,0xef,0x0c,0xbf
+# GFX1250-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# src_vccz (251) and src_execz (252) are reserved on GFX11+.
+0xfb,0x0e,0x80,0xbe
+# GFX1250-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+0xfc,0x0e,0x80,0xbe
+# GFX1250-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# The wmma source tuples are narrowed down according to the matrix formats, but
+# scalar registers have no 384-bit tuple.
+0x00,0x18,0x33,0xcc,0x08,0x30,0xa2,0x04
+# GFX1250-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# This encoding references a missing trailing literal.
+0x00,0x00,0x33,0xcc,0xff,0x68,0x02,0x02
+# GFX1250-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_err.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_err.txt
new file mode 100644
index 0000000000000..15b74d2374472
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_err.txt
@@ -0,0 +1,38 @@
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
+# RUN: llvm-mc -triple=amdgpu12.00 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GFX12-ERR %s
+
+# This is v_s_exp_f32 with an SGPR destination that does not fit the 7-bit
+# scalar register encoding of the 8-bit VOP3 vdst field.
+0xfa,0x00,0x80,0xd6,0x01,0x00,0x01,0x02
+# GFX12-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# This is s_waitcnt_vscnt exec_hi, 0x1234, which is valid on gfx11, but not on
+# gfx12.
+0x34,0x12,0x7f,0xbc
+# GFX12-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# src_pops_exiting_wave_id (239) is only available on targets that support
+# POPS.
+0x00,0xef,0x0c,0xbf
+# GFX12-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# src_vccz (251) and src_execz (252) are reserved on GFX11+.
+0xfb,0x0e,0x80,0xbe
+# GFX12-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+0xfc,0x0e,0x80,0xbe
+# GFX12-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# This is ds_add_f32 with the gds bit, which is not valid on gfx12+.
+0x00,0x00,0x56,0xd8,0x00,0x01,0x00,0x00
+# GFX12-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# This is image_msaa_load where the samp field for gfx12 VSAMPLE is not all
+# zeros.
+0x06,0x00,0x46,0xe4,0x01,0x10,0x80,0x00,0x05,0x06,0x07,0x00
+# GFX12-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# This is s_load_b96 with a ttmp destination, which is not a supported 96-bit
+# scalar destination encoding.
+0x00,0xbb,0x00,0xf4,0x00,0x00,0x00,0xf8
+# GFX12-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_err.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_err.txt
index 8a2c275acf02c..2a3f4148f4a70 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_err.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_err.txt
@@ -1,6 +1,16 @@
 # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
 # RUN: llvm-mc -disassemble -triple=amdgpu9.50 -filetype=null < %s 2>&1 | FileCheck --check-prefix=GFX950-ERR %s
 
+# The f8f6f4 source tuples are narrowed down according to cbsz/blgp, but ttmp
+# registers have no 192-bit tuple.
+0x00,0x00,0xae,0xd3,0x00,0xe9,0x00,0x64
+# GFX950-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# Same, except that the source selector is an inline constant, which is not a
+# register at all.
+0x00,0x00,0xae,0xd3,0xf2,0x00,0x02,0x64
+# GFX950-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
 # The 192- and 1024-bit source operands below are vector only. SGPR, ttmp, and
 # special-register selectors cannot satisfy those operand profiles, so the
 # encodings are invalid.
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
new file mode 100644
index 0000000000000..26b3746f30716
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
@@ -0,0 +1,10 @@
+# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
+# RUN: llvm-mc -triple=amdgpu9.00 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GFX9-ERR %s
+
+0xdf,0x00,0x00,0x02
+# GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding
+
+# This is v_readfirstlane_b32 with an SGPR destination that does not fit the
+# 7-bit scalar register encoding of the 8-bit VOP1 vdst field.
+0x00,0x05,0xf4,0x7f
+# GFX9-ERR: :[[@LINE-1]]:1: warning: invalid instruction encoding

``````````

</details>


https://github.com/llvm/llvm-project/pull/215168
