[llvm-branch-commits] [RISC-V] Use an optional offset for Xwch instructions (PR #215005)
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Sat Aug 8 12:08:43 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Alexander Richardson (arichardson)
<details>
<summary>Changes</summary>
Following up on the previous commits to remove unnecessary InstAlias.
This commit was prepared with the help of AI.
---
Full diff: https://github.com/llvm/llvm-project/pull/215005.diff
1 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td (+28-43)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td
index b6318097b00d8..6425513836365 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td
@@ -25,11 +25,13 @@ class QKStackInst<bits<2> funct2, dag outs, dag ins,
// Operand definitions.
//===----------------------------------------------------------------------===//
+def uimm4_optional : OptionalUImmLeafOp<4>;
+
// A 5-bit unsigned immediate where the least significant bit is zero.
-def uimm5_lsb0 : RISCVUImmLsbZeroOp<5, 1>;
+def uimm5_lsb0_optional : OptionalUImmLsbZeroOp<5, 1>;
// A 6-bit unsigned immediate where the least significant bit is zero.
-def uimm6_lsb0 : RISCVUImmLsbZeroOp<6, 1>;
+def uimm6_lsb0_optional : OptionalUImmLsbZeroOp<6, 1>;
//===----------------------------------------------------------------------===//
// Instructions
@@ -38,7 +40,7 @@ let Predicates = [HasVendorXwchc], DecoderNamespace = "Xwchc" in {
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
def QK_C_LBU : RVInst16CL<0b001, OPC_C0, (outs GPRC:$rd),
- (ins BasePtrC:$rs1, uimm5:$imm),
+ (ins BasePtrC:$rs1, uimm5_optional:$imm),
"qk.c.lbu", "$rd, ${imm}(${rs1})">,
Sched<[WriteLDB, ReadMemBase]> {
bits<5> imm;
@@ -49,7 +51,7 @@ def QK_C_LBU : RVInst16CL<0b001, OPC_C0, (outs GPRC:$rd),
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
def QK_C_SB : RVInst16CS<0b101, OPC_C0, (outs),
(ins GPRC:$rs2, BasePtrC:$rs1,
- uimm5:$imm),
+ uimm5_optional:$imm),
"qk.c.sb", "$rs2, ${imm}(${rs1})">,
Sched<[WriteSTB, ReadStoreData, ReadMemBase]> {
bits<5> imm;
@@ -60,7 +62,7 @@ def QK_C_SB : RVInst16CS<0b101, OPC_C0, (outs),
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
def QK_C_LHU : RVInst16CL<0b001, OPC_C2, (outs GPRC:$rd),
- (ins BasePtrC:$rs1, uimm6_lsb0:$imm),
+ (ins BasePtrC:$rs1, uimm6_lsb0_optional:$imm),
"qk.c.lhu", "$rd, ${imm}(${rs1})">,
Sched<[WriteLDH, ReadMemBase]> {
bits<6> imm;
@@ -69,7 +71,7 @@ def QK_C_LHU : RVInst16CL<0b001, OPC_C2, (outs GPRC:$rd),
}
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
def QK_C_SH : RVInst16CS<0b101, OPC_C2, (outs),
- (ins GPRC:$rs2, BasePtrC:$rs1, uimm6_lsb0:$imm),
+ (ins GPRC:$rs2, BasePtrC:$rs1, uimm6_lsb0_optional:$imm),
"qk.c.sh", "$rs2, ${imm}(${rs1})">,
Sched<[WriteSTH, ReadStoreData, ReadMemBase]> {
bits<6> imm;
@@ -79,7 +81,7 @@ def QK_C_SH : RVInst16CS<0b101, OPC_C2, (outs),
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
def QK_C_LBUSP : QKStackInst<0b00, (outs GPRC:$rd_rs2),
- (ins SPMem:$rs1, uimm4:$imm),
+ (ins SPMem:$rs1, uimm4_optional:$imm),
"qk.c.lbusp", "$rd_rs2, ${imm}(${rs1})">,
Sched<[WriteLDB, ReadMemBase]> {
bits<0> rs1;
@@ -89,7 +91,7 @@ def QK_C_LBUSP : QKStackInst<0b00, (outs GPRC:$rd_rs2),
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
def QK_C_SBSP : QKStackInst<0b10, (outs),
(ins GPRC:$rd_rs2, SPMem:$rs1,
- uimm4:$imm),
+ uimm4_optional:$imm),
"qk.c.sbsp", "$rd_rs2, ${imm}(${rs1})">,
Sched<[WriteSTB, ReadStoreData, ReadMemBase]> {
bits<0> rs1;
@@ -99,7 +101,7 @@ def QK_C_SBSP : QKStackInst<0b10, (outs),
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
def QK_C_LHUSP : QKStackInst<0b01, (outs GPRC:$rd_rs2),
- (ins SPMem:$rs1, uimm5_lsb0:$imm),
+ (ins SPMem:$rs1, uimm5_lsb0_optional:$imm),
"qk.c.lhusp", "$rd_rs2, ${imm}(${rs1})">,
Sched<[WriteLDH, ReadMemBase]> {
bits<0> rs1;
@@ -109,7 +111,7 @@ def QK_C_LHUSP : QKStackInst<0b01, (outs GPRC:$rd_rs2),
}
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
def QK_C_SHSP : QKStackInst<0b11, (outs),
- (ins GPRC:$rd_rs2, SPMem:$rs1, uimm5_lsb0:$imm),
+ (ins GPRC:$rd_rs2, SPMem:$rs1, uimm5_lsb0_optional:$imm),
"qk.c.shsp", "$rd_rs2, ${imm}(${rs1})">,
Sched<[WriteSTH, ReadStoreData, ReadMemBase]> {
bits<0> rs1;
@@ -120,42 +122,25 @@ def QK_C_SHSP : QKStackInst<0b11, (outs),
} // Predicates = [HasVendorXwchc], DecoderNamespace = "Xwchc"
-//===----------------------------------------------------------------------===//
-// Assembler Pseudo Instructions
-//===----------------------------------------------------------------------===//
-
-let EmitPriority = 0 in {
-let Predicates = [HasVendorXwchc] in {
-def : InstAlias<"qk.c.lbu $rd, (${rs1})", (QK_C_LBU GPRC:$rd, BasePtrC:$rs1, 0)>;
-def : InstAlias<"qk.c.sb $rs2, (${rs1})", (QK_C_SB GPRC:$rs2, BasePtrC:$rs1, 0)>;
-def : InstAlias<"qk.c.lhu $rd, (${rs1})", (QK_C_LHU GPRC:$rd, BasePtrC:$rs1, 0)>;
-def : InstAlias<"qk.c.sh $rs2, (${rs1})", (QK_C_SH GPRC:$rs2, BasePtrC:$rs1, 0)>;
-def : InstAlias<"qk.c.lbusp $rd, (${rs1})", (QK_C_LBUSP GPRC:$rd, SPMem:$rs1, 0)>;
-def : InstAlias<"qk.c.sbsp $rs2, (${rs1})", (QK_C_SBSP GPRC:$rs2, SPMem:$rs1, 0)>;
-def : InstAlias<"qk.c.lhusp $rd, (${rs1})", (QK_C_LHUSP GPRC:$rd, SPMem:$rs1, 0)>;
-def : InstAlias<"qk.c.shsp $rs2, (${rs1})", (QK_C_SHSP GPRC:$rs2, SPMem:$rs1, 0)>;
-}
-}
-
//===----------------------------------------------------------------------===/
// Compress Instruction tablegen backend.
//===----------------------------------------------------------------------===//
let Predicates = [HasVendorXwchc] in {
-def : CompressPat<(LBU GPRC:$rd, BasePtrC:$rs1, uimm5:$imm),
- (QK_C_LBU GPRC:$rd, BasePtrC:$rs1, uimm5:$imm)>;
-def : CompressPat<(SB GPRC:$rs2, BasePtrC:$rs1, uimm5:$imm),
- (QK_C_SB GPRC:$rs2, BasePtrC:$rs1, uimm5:$imm)>;
-def : CompressPat<(LHU GPRC:$rd, BasePtrC:$rs1, uimm6_lsb0:$imm),
- (QK_C_LHU GPRC:$rd, BasePtrC:$rs1, uimm6_lsb0:$imm)>;
-def : CompressPat<(SH GPRC:$rs2, BasePtrC:$rs1, uimm6_lsb0:$imm),
- (QK_C_SH GPRC:$rs2, BasePtrC:$rs1, uimm6_lsb0:$imm)>;
-def : CompressPat<(LBU GPRC:$rd, SPMem:$rs1, uimm4:$imm),
- (QK_C_LBUSP GPRC:$rd, SPMem:$rs1, uimm4:$imm)>;
-def : CompressPat<(SB GPRC:$rs2, SPMem:$rs1, uimm4:$imm),
- (QK_C_SBSP GPRC:$rs2, SPMem:$rs1, uimm4:$imm)>;
-def : CompressPat<(LHU GPRC:$rd, SPMem:$rs1, uimm5_lsb0:$imm),
- (QK_C_LHUSP GPRC:$rd, SPMem:$rs1, uimm5_lsb0:$imm)>;
-def : CompressPat<(SH GPRC:$rs2, SPMem:$rs1, uimm5_lsb0:$imm),
- (QK_C_SHSP GPRC:$rs2, SPMem:$rs1, uimm5_lsb0:$imm)>;
+def : CompressPat<(LBU GPRC:$rd, BasePtrC:$rs1, uimm5_optional:$imm),
+ (QK_C_LBU GPRC:$rd, BasePtrC:$rs1, uimm5_optional:$imm)>;
+def : CompressPat<(SB GPRC:$rs2, BasePtrC:$rs1, uimm5_optional:$imm),
+ (QK_C_SB GPRC:$rs2, BasePtrC:$rs1, uimm5_optional:$imm)>;
+def : CompressPat<(LHU GPRC:$rd, BasePtrC:$rs1, uimm6_lsb0_optional:$imm),
+ (QK_C_LHU GPRC:$rd, BasePtrC:$rs1, uimm6_lsb0_optional:$imm)>;
+def : CompressPat<(SH GPRC:$rs2, BasePtrC:$rs1, uimm6_lsb0_optional:$imm),
+ (QK_C_SH GPRC:$rs2, BasePtrC:$rs1, uimm6_lsb0_optional:$imm)>;
+def : CompressPat<(LBU GPRC:$rd, SPMem:$rs1, uimm4_optional:$imm),
+ (QK_C_LBUSP GPRC:$rd, SPMem:$rs1, uimm4_optional:$imm)>;
+def : CompressPat<(SB GPRC:$rs2, SPMem:$rs1, uimm4_optional:$imm),
+ (QK_C_SBSP GPRC:$rs2, SPMem:$rs1, uimm4_optional:$imm)>;
+def : CompressPat<(LHU GPRC:$rd, SPMem:$rs1, uimm5_lsb0_optional:$imm),
+ (QK_C_LHUSP GPRC:$rd, SPMem:$rs1, uimm5_lsb0_optional:$imm)>;
+def : CompressPat<(SH GPRC:$rs2, SPMem:$rs1, uimm5_lsb0_optional:$imm),
+ (QK_C_SHSP GPRC:$rs2, SPMem:$rs1, uimm5_lsb0_optional:$imm)>;
}
``````````
</details>
https://github.com/llvm/llvm-project/pull/215005
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