[llvm-branch-commits] [RISC-V] Use an optional offset for Xqc* instructions (PR #215002)
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llvm-branch-commits at lists.llvm.org
Sat Aug 8 12:05:04 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Alexander Richardson (arichardson)
<details>
<summary>Changes</summary>
Following up on the previous commits to remove unnecessary InstAlias.
This commit was prepared with the help of AI.
---
Patch is 25.77 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/215002.diff
5 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+6)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+14-78)
- (modified) llvm/test/MC/RISCV/xqciio-invalid.s (+11-17)
- (modified) llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s (+14-14)
- (modified) llvm/test/MC/RISCV/xqcilsm-invalid.s (+37-25)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index af163b4fc739e..e59e0cfda208e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -337,6 +337,12 @@ class RISCVSImmOp<int bitsNum> : RISCVOp {
class RISCVSImmLeafOp<int bitsNum> :
RISCVSImmOp<bitsNum>, ImmLeaf<XLenVT, "return isInt<" # bitsNum # ">(Imm);">;
+// Variant of RISCVSImmLeafOp for memory-operand offsets that may be omitted
+// entirely, e.g. "qc.e.lb a0, (a1)". See OptionalMemOffsetAsmOperand.
+class OptionalSImmLeafOp<int bitsNum> : RISCVSImmLeafOp<bitsNum> {
+ let ParserMatchClass = OptionalMemOffsetAsmOperand<SImmAsmOperand<bitsNum>>;
+}
+
def FenceArg : AsmOperandClass {
let Name = "FenceArg";
let RenderMethod = "addFenceArgOperands";
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index a72a6d065626e..9175151c7f2ba 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -106,13 +106,7 @@ def uimm10 : RISCVUImmLeafOp<10>;
def uimm11 : RISCVUImmLeafOp<11>;
// A 14-bit unsigned immediate where the least significant two bits are zero.
-def uimm14lsb00 : RISCVOp,
- ImmLeaf<XLenVT, [{return isShiftedUInt<12, 2>(Imm);}]> {
- let ParserMatchClass = UImmAsmOperand<14, "Lsb00">;
- let EncoderMethod = "getImmOpValue";
- let DecoderMethod = "decodeUImmOperand<14>";
- let OperandType = "OPERAND_UIMM14_LSB00";
-}
+def uimm14lsb00_optional : OptionalUImmLsbZeroOp<14, 2>;
def uimm16nonzero : RISCVOp<XLenVT>,
ImmLeaf<XLenVT, [{return (Imm != 0) && isUInt<16>(Imm);}]> {
@@ -161,6 +155,8 @@ def simm20_li : RISCVOp<XLenVT>,
def simm26 : RISCVSImmLeafOp<26>;
+def simm26_optional : OptionalSImmLeafOp<26>;
+
def simm26_nosimm12 : ImmLeaf<XLenVT, [{
return isInt<26>(Imm) && !isInt<12>(Imm);}]>;
@@ -348,7 +344,7 @@ def InsnQC_EI_Mem : DirectiveInsnQC_EI<(outs AnyReg:$rd),
uimm3:$func3,
uimm2:$func2,
AnyReg:$rs1,
- simm26:$imm26),
+ simm26_optional:$imm26),
"$opcode, $func3, $func2, $rd, ${imm26}(${rs1})">;
def InsnQC_EB : DirectiveInsnQC_EB<(outs),
(ins uimm7_opcode:$opcode,
@@ -371,7 +367,7 @@ def InsnQC_ES : DirectiveInsnQC_ES<(outs),
uimm2:$func2,
AnyReg:$rs2,
AnyReg:$rs1,
- simm26:$imm26),
+ simm26_optional:$imm26),
"$opcode, $func3, $func2, $rs2, ${imm26}(${rs1})">;
} // isCodeGenOnly, hasSideEffects, mayLoad, mayStore, hasNoSchedulingInfo, Predicates
@@ -395,14 +391,7 @@ def : InstAlias<".insn_qc.ei $opcode, $func3, $func2, $rd, ${imm26}(${rs1})",
uimm3:$func3,
uimm2:$func2,
AnyReg:$rs1,
- simm26:$imm26)>;
-def : InstAlias<".insn_qc.ei $opcode, $func3, $func2, $rd, (${rs1})",
- (InsnQC_EI_Mem AnyReg:$rd,
- uimm7_opcode:$opcode,
- uimm3:$func3,
- uimm2:$func2,
- AnyReg:$rs1,
- 0)>;
+ simm26_optional:$imm26)>;
def : InstAlias<".insn_qc.eb $opcode, $func3, $func5, $rs1, $imm16, $imm12",
(InsnQC_EB uimm7_opcode:$opcode,
uimm3:$func3,
@@ -422,14 +411,7 @@ def : InstAlias<".insn_qc.es $opcode, $func3, $func2, $rs2, ${imm26}(${rs1})",
uimm2:$func2,
AnyReg:$rs2,
AnyReg:$rs1,
- simm26:$imm26)>;
-def : InstAlias<".insn_qc.es $opcode, $func3, $func2, $rs2, (${rs1})",
- (InsnQC_ES uimm7_opcode:$opcode,
- uimm3:$func3,
- uimm2:$func2,
- AnyReg:$rs2,
- AnyReg:$rs1,
- 0)>;
+ simm26_optional:$imm26)>;
} // EmitPriority = 0, Predicates = [IsRV32]
//===----------------------------------------------------------------------===//
@@ -582,7 +564,7 @@ class QCISELECTICCI<bits<3> funct3, string opcodestr>
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
class QCILoadMultiple<bits<2> funct2, DAGOperand InTyRs2, string opcodestr>
: RVInstRBase<0b111, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
- (ins GPR:$rs1, InTyRs2:$rs2, uimm7_lsb00:$imm),
+ (ins GPR:$rs1, InTyRs2:$rs2, uimm7_lsb00_optional:$imm),
opcodestr, "$rd, $rs2, ${imm}(${rs1})"> {
bits<7> imm;
let Inst{31-25} = {funct2, imm{6-2}};
@@ -594,7 +576,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class QCIStoreMultiple<bits<2> funct2, DAGOperand InTyRd, DAGOperand InTyRs2,
string opcodestr>
: RVInstRBase<0b111, OPC_CUSTOM_1, (outs),
- (ins InTyRd:$rd, GPR:$rs1, InTyRs2:$rs2, uimm7_lsb00:$imm),
+ (ins InTyRd:$rd, GPR:$rs1, InTyRs2:$rs2,
+ uimm7_lsb00_optional:$imm),
opcodestr, "$rd, $rs2, ${imm}(${rs1})"> {
bits<7> imm;
let Inst{31-25} = {funct2, imm{6-2}};
@@ -761,7 +744,7 @@ class QCIRVInstEIBase<bits<3> funct3, bits<2> funct2, dag outs,
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, canFoldAsLoad = 1 in
class QCIRVInstEILoad<bits<3> funct3, bits<2> funct2, string opcodestr>
: QCIRVInstEIBase<funct3, funct2, (outs GPR:$rd),
- (ins BasePtr:$rs1, simm26:$imm), opcodestr,
+ (ins BasePtr:$rs1, simm26_optional:$imm), opcodestr,
"$rd, ${imm}(${rs1})">;
class QCIRVInstESBase<bits<3> funct3, bits<2> funct2, dag outs,
@@ -784,7 +767,7 @@ class QCIRVInstESBase<bits<3> funct3, bits<2> funct2, dag outs,
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class QCIRVInstESStore<bits<3> funct3, bits<2> funct2, string opcodestr>
: QCIRVInstESBase<funct3, funct2, (outs),
- (ins GPR:$rs2, BasePtr:$rs1, simm26:$imm),
+ (ins GPR:$rs2, BasePtr:$rs1, simm26_optional:$imm),
opcodestr, "$rs2, ${imm}(${rs1})">;
class QCIRVInstEAI<bits<3> funct3, bits<1> funct1, string opcodestr>
@@ -1140,7 +1123,7 @@ def QC_C_MILEAVERET : QCIRVInst16CI_NONE<0b10100, "qc.c.mileaveret">;
let Predicates = [HasVendorXqciio, IsRV32] in {
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
def QC_OUTW : RVInstI<0b100, OPC_CUSTOM_0, (outs),
- (ins GPR:$rs2, GPR:$rs1, uimm14lsb00:$imm14),
+ (ins GPR:$rs2, GPR:$rs1, uimm14lsb00_optional:$imm14),
"qc.outw", "$rs2, ${imm14}(${rs1})"> {
bits<5> rs2;
bits<14> imm14;
@@ -1150,7 +1133,7 @@ let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
}
def QC_INW : RVInstI<0b101, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
- (ins GPR:$rs1, uimm14lsb00:$imm14),
+ (ins GPR:$rs1, uimm14lsb00_optional:$imm14),
"qc.inw", "$rd, ${imm14}(${rs1})"> {
bits<14> imm14;
@@ -1250,53 +1233,6 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
// Aliases
//===----------------------------------------------------------------------===//
-let Predicates = [HasVendorXqciio, IsRV32] in {
-let EmitPriority = 0 in {
- def : InstAlias<"qc.outw $rs2, (${rs1})",
- (QC_OUTW GPR:$rs2, GPR:$rs1, 0)>;
- def : InstAlias<"qc.inw $rd, (${rs1})",
- (QC_INW GPRNoX0:$rd, GPR:$rs1, 0)>;
-} // EmitPriority = 0
-} // Predicates = [HasVendorXqciio, IsRV32]
-
-let Predicates = [HasVendorXqcilsm, IsRV32] in {
-let EmitPriority = 0 in {
- def : InstAlias<"qc.swm $rs3, $rs2, (${rs1})",
- (QC_SWM GPRNoX0:$rs3, GPR:$rs1, GPRNoX0:$rs2, 0)>;
- def : InstAlias<"qc.swmi $rs3, $length, (${rs1})",
- (QC_SWMI GPRNoX0:$rs3, GPR:$rs1, uimm5nonzero:$length, 0)>;
- def : InstAlias<"qc.setwm $rs3, $rs2, (${rs1})",
- (QC_SETWM GPR:$rs3, GPR:$rs1, GPRNoX0:$rs2, 0)>;
- def : InstAlias<"qc.setwmi $rs3, $length, (${rs1})",
- (QC_SETWMI GPR:$rs3, GPR:$rs1, uimm5nonzero:$length, 0)>;
- def : InstAlias<"qc.lwm $rd, $rs2, (${rs1})",
- (QC_LWM GPRNoX0:$rd, GPR:$rs1, GPRNoX0:$rs2, 0)>;
- def : InstAlias<"qc.lwmi $rd, $length, (${rs1})",
- (QC_LWMI GPRNoX0:$rd, GPR:$rs1, uimm5nonzero:$length, 0)>;
-} // EmitPriority = 0
-} // Predicates = [HasVendorXqcilsm, IsRV32]
-
-let Predicates = [HasVendorXqcilo, IsRV32] in {
-let EmitPriority = 0 in {
- def : InstAlias<"qc.e.lb $rd, (${rs1})",
- (QC_E_LB GPR:$rd, GPR:$rs1, 0)>;
- def : InstAlias<"qc.e.lbu $rd, (${rs1})",
- (QC_E_LBU GPR:$rd, GPR:$rs1, 0)>;
- def : InstAlias<"qc.e.lh $rd, (${rs1})",
- (QC_E_LH GPR:$rd, GPR:$rs1, 0)>;
- def : InstAlias<"qc.e.lhu $rd, (${rs1})",
- (QC_E_LHU GPR:$rd, GPR:$rs1, 0)>;
- def : InstAlias<"qc.e.lw $rd, (${rs1})",
- (QC_E_LW GPR:$rd, GPR:$rs1, 0)>;
- def : InstAlias<"qc.e.sb $rs2, (${rs1})",
- (QC_E_SB GPR:$rs2, GPR:$rs1, 0)>;
- def : InstAlias<"qc.e.sh $rs2, (${rs1})",
- (QC_E_SH GPR:$rs2, GPR:$rs1, 0)>;
- def : InstAlias<"qc.e.sw $rs2, (${rs1})",
- (QC_E_SW GPR:$rs2, GPR:$rs1, 0)>;
-} // EmitPriority = 0
-} // Predicates = [HasVendorXqcilo, IsRV32]
-
let Predicates = [HasVendorXqcisim, IsRV32] in {
let EmitPriority = 1 in {
def : InstAlias<"qc.c.ptrace", (C_SLLI X0, 0)>;
diff --git a/llvm/test/MC/RISCV/xqciio-invalid.s b/llvm/test/MC/RISCV/xqciio-invalid.s
index 0627f00ac5df5..2cb3a94436395 100644
--- a/llvm/test/MC/RISCV/xqciio-invalid.s
+++ b/llvm/test/MC/RISCV/xqciio-invalid.s
@@ -1,23 +1,20 @@
# Xqciio - Qualcomm uC External Input Output Extension
# RUN: not llvm-mc -triple riscv32 -mattr=+xqciio < %s 2>&1 \
-# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS --implicit-check-not="error:" --implicit-check-not="note:" %s
# RUN: not llvm-mc -triple riscv32 -mattr=-xqciio < %s 2>&1 \
-# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS --implicit-check-not="error:" --implicit-check-not="note:" %s
# CHECK: :[[@LINE+1]]:18: error: expected register
qc.outw x5, 2048(10)
-# CHECK-PLUS: :[[@LINE+3]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK-PLUS: :[[@LINE+2]]:13: note: expected '('
-# CHECK-PLUS: :[[@LINE+1]]:13: note: immediate must be a multiple of 4 bytes in the range [0, 16380]
+# CHECK: :[[@LINE+1]]:13: error: expected '('
qc.outw x5, x10
-# CHECK-MINUS: :[[@LINE+3]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK-MINUS: :[[@LINE+2]]:13: note: expected '('
-# CHECK-MINUS: :[[@LINE+1]]:13: note: immediate must be a multiple of 4 bytes in the range [0, 16380]
+# CHECK: :[[@LINE+1]]:13: error: expected '('
qc.outw x5, x10
-# CHECK-PLUS: :[[@LINE+1]]:13: error: immediate must be a multiple of 4 bytes in the range [0, 16380]
+# CHECK-PLUS: :[[@LINE+2]]:13: error: immediate must be a multiple of 4 bytes in the range [0, 16380]
+# CHECK-MINUS: :[[@LINE+1]]:1: error: invalid instruction
qc.outw x5, 4099(x10)
# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciio' (Qualcomm uC External Input Output Extension)
@@ -27,21 +24,18 @@ qc.outw x5, 2048(x10)
# CHECK: :[[@LINE+1]]:19: error: expected register
qc.inw x23, 16380(17)
-# CHECK-PLUS: :[[@LINE+3]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK-PLUS: :[[@LINE+2]]:13: note: expected '('
-# CHECK-PLUS: :[[@LINE+1]]:13: note: immediate must be a multiple of 4 bytes in the range [0, 16380]
+# CHECK: :[[@LINE+1]]:13: error: expected '('
qc.inw x23, x17
-# CHECK-MINUS: :[[@LINE+3]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK-MINUS: :[[@LINE+2]]:13: note: expected '('
-# CHECK-MINUS: :[[@LINE+1]]:13: note: immediate must be a multiple of 4 bytes in the range [0, 16380]
+# CHECK: :[[@LINE+1]]:13: error: expected '('
qc.inw x23, x17
# CHECK-PLUS: :[[@LINE+2]]:8: error: register must be a GPR excluding zero (x0)
-# CHECK-MINUS: :[[@LINE+1]]:8: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:1: error: invalid instruction
qc.inw x0, 16380(x17)
-# CHECK-PLUS: :[[@LINE+1]]:13: error: immediate must be a multiple of 4 bytes in the range [0, 16380]
+# CHECK-PLUS: :[[@LINE+2]]:13: error: immediate must be a multiple of 4 bytes in the range [0, 16380]
+# CHECK-MINUS: :[[@LINE+1]]:1: error: invalid instruction
qc.inw x23, 16384(x17)
# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciio' (Qualcomm uC External Input Output Extension)
diff --git a/llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s b/llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s
index 6b087979c8ccc..ebfabbbe68a51 100644
--- a/llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s
+++ b/llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s
@@ -1,55 +1,55 @@
# Xqcilo - Qualcomm uC Large Offset Load Store extension
# RUN: not llvm-mc %s -triple=riscv32 -mattr=+xqcilo,+xqcili \
-# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ENABLED %s
+# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ENABLED --implicit-check-not="error:" --implicit-check-not="note:" %s
# RUN: not llvm-mc %s -triple=riscv32 -mattr=-xqcilo \
-# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-DISABLED %s
+# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-DISABLED --implicit-check-not="error:" --implicit-check-not="note:" %s
# CHECK-ENABLED: [[@LINE+4]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK-ENABLED: [[@LINE+3]]:13: note: operand must be a bare symbol name
# CHECK-ENABLED: [[@LINE+2]]:19: note: too few operands for instruction
-# CHECK-DISABLED: :[[@LINE+1]]:13: error: expected '('
+# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
qc.e.lb a0, 0xf000
# CHECK-ENABLED: [[@LINE+4]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK-ENABLED: [[@LINE+3]]:13: note: operand must be a bare symbol name
# CHECK-ENABLED: [[@LINE+2]]:19: note: too few operands for instruction
-# CHECK-DISABLED: :[[@LINE+1]]:13: error: expected '('
+# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
qc.e.lb a0, 0xf000
# CHECK-ENABLED: [[@LINE+4]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK-ENABLED: [[@LINE+3]]:14: note: operand must be a bare symbol name
# CHECK-ENABLED: [[@LINE+2]]:20: note: too few operands for instruction
-# CHECK-DISABLED: :[[@LINE+1]]:14: error: expected '('
+# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
qc.e.lbu a0, 0xf000
# CHECK-ENABLED: [[@LINE+4]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK-ENABLED: [[@LINE+3]]:13: note: operand must be a bare symbol name
# CHECK-ENABLED: [[@LINE+2]]:19: note: too few operands for instruction
-# CHECK-DISABLED: :[[@LINE+1]]:13: error: expected '('
+# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
qc.e.lh a0, 0xf000
# CHECK-ENABLED: [[@LINE+4]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK-ENABLED: [[@LINE+3]]:14: note: operand must be a bare symbol name
# CHECK-ENABLED: [[@LINE+2]]:20: note: too few operands for instruction
-# CHECK-DISABLED: :[[@LINE+1]]:14: error: expected '('
+# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
qc.e.lhu a0, 0xf000
# CHECK-ENABLED: [[@LINE+4]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK-ENABLED: [[@LINE+3]]:13: note: operand must be a bare symbol name
# CHECK-ENABLED: [[@LINE+2]]:19: note: too few operands for instruction
-# CHECK-DISABLED: :[[@LINE+1]]:13: error: expected '('
+# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
qc.e.lw a0, 0xf000
# CHECK-ENABLED: [[@LINE+2]]:13: error: operand must be a bare symbol name
-# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
+# CHECK-DISABLED: [[@LINE+1]]:21: error: expected '('
qc.e.sb a0, 0xf000, t0
# CHECK-ENABLED: [[@LINE+2]]:13: error: operand must be a bare symbol name
-# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
+# CHECK-DISABLED: [[@LINE+1]]:21: error: expected '('
qc.e.sh a0, 0xf000, t0
# CHECK-ENABLED: [[@LINE+2]]:13: error: operand must be a bare symbol name
-# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
+# CHECK-DISABLED: [[@LINE+1]]:21: error: expected '('
qc.e.sw a0, 0xf000, t0
# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcili' (Qualcomm uC Load Large Immediate Extension), 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
@@ -70,13 +70,13 @@ qc.e.sh a0, undefined, t0
qc.e.sw a0, undefined, t0
# CHECK-ENABLED: [[@LINE+2]]:22: error: too few operands for instruction
-# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
+# CHECK-DISABLED: [[@LINE+1]]:13: error: immediate must be an integer in the range [-33554432, 33554431]
qc.e.sb a0, undefined
# CHECK-ENABLED: [[@LINE+2]]:22: error: too few operands for instruction
-# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
+# CHECK-DISABLED: [[@LINE+1]]:13: error: immediate must be an integer in the range [-33554432, 33554431]
qc.e.sh a0, undefined
# CHECK-ENABLED: [[@LINE+2]]:22: error: too few operands for instruction
-# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
+# CHECK-DISABLED: [[@LINE+1]]:13: error: immediate must be an integer in the range [-33554432, 33554431]
qc.e.sw a0, undefined
diff --git a/llvm/test/MC/RISCV/xqcilsm-invalid.s b/llvm/test/MC/RISCV/xqcilsm-invalid.s
index 38e5282969970..63113b31861e9 100644
--- a/llvm/test/MC/RISCV/xqcilsm-invalid.s
+++ b/llvm/test/MC/RISCV/xqcilsm-invalid.s
@@ -1,25 +1,26 @@
# Xqcilsm - Qualcomm uC Load Store Multiple Extension
# RUN: not llvm-mc -triple riscv32 -mattr=+xqcilsm < %s 2>&1 \
-# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS --implicit-check-not="error:" --implicit-check-not="note:" %s
# RUN: not llvm-mc -triple riscv32 -mattr=-xqcilsm < %s 2>&1 \
-# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS --implicit-check-not="error:" --implicit-check-not="note:" %s
# CHECK: :[[@LINE+1]]:20: error: expected register
qc.swm x5, x20, 12(20)
# CHECK-PLUS: :[[@LINE+2]]:8: error: register must be a GPR excluding zero (x0)
-# CHECK-MINUS: :[[@LINE+1]]:8: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:1: error: invalid instruction
qc.swm x0, x20, 12(x3)
# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0)
-# CHECK-MINUS: :[[@LINE+1]]:12: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:1: error: invalid instruction
qc.swm x5, x0, 12(x3)
# CHECK-PLUS: :[[@LINE+2]]:14: error: too few operands for instruction
# CHECK-MINUS: :[[@LINE+1]]:1: error: invalid instruction
qc.swm x5, x3
-# CHECK-PLUS: :[[@LINE+1]]:17: error: immediate must be a multiple of 4 bytes in the range [0, 124]
+# CHECK-PLUS: :[[@LINE+2]]:17: error: immediate must be a multiple of 4 bytes in the range [0, 124]
+# CHECK-MINUS: :[[@LINE+1]]:1: error: invalid instruction
qc.swm x5, x20, 45(x3)
# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
@@ -30,20 +31,23 @@ qc.swm x5, x20, 12(x3)
qc.swmi x10, 4, 20(4)
# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/215002
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