[llvm-branch-commits] [llvm] [RISC-V] Use an optional offset for C/Zc* extension instruction (PR #211674)
Alexander Richardson via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sat Aug 8 11:22:31 PDT 2026
https://github.com/arichardson updated https://github.com/llvm/llvm-project/pull/211674
>From 1fccbd22f587517fbbf2d4316e1bab217cd488e2 Mon Sep 17 00:00:00 2001
From: Alexander Richardson <mail at alexrichardson.me>
Date: Wed, 5 Aug 2026 21:47:37 -0700
Subject: [PATCH] add zcb as well
Created using spr 1.3.8-beta.1-arichardson
---
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 6 ++
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 19 +-----
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 69 +++++++-------------
llvm/lib/Target/RISCV/RISCVInstrInfoZc.td | 53 ++++++---------
llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td | 7 --
llvm/test/MC/RISCV/rv32c-invalid.s | 12 ++--
llvm/test/MC/RISCV/rv32fc-invalid.s | 2 +-
7 files changed, 56 insertions(+), 112 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index bc3c9525a3d72..2a0aa0a592655 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -286,6 +286,12 @@ class RISCVUImmOp<int bitsNum> : RISCVOp {
class RISCVUImmLeafOp<int bitsNum> :
RISCVUImmOp<bitsNum>, ImmLeaf<XLenVT, "return isUInt<" # bitsNum # ">(Imm);">;
+// Variant of RISCVUImmLeafOp for memory-operand offsets that may be omitted
+// entirely, e.g. "c.lbu a0, (a1)". See OptionalMemOffsetAsmOperand.
+class OptionalUImmLeafOp<int bitsNum> : RISCVUImmLeafOp<bitsNum> {
+ let ParserMatchClass = OptionalMemOffsetAsmOperand<UImmAsmOperand<bitsNum>>;
+}
+
class RISCVSImmOp<int bitsNum> : RISCVOp {
let ParserMatchClass = SImmAsmOperand<bitsNum>;
let EncoderMethod = "getImmOpValue";
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 297595413f699..c9ddf54968676 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -206,10 +206,7 @@ def uimm2_opcode : RISCVUImmOp<2> {
let ParserMatchClass = InsnCDirectiveOpcode;
}
-// For memory-operand offsets that may be omitted, e.g. ".insn cl 0, 2, a0, (a1)".
-def uimm5_optional : RISCVUImmLeafOp<5> {
- let ParserMatchClass = OptionalMemOffsetAsmOperand<UImmAsmOperand<5>>;
-}
+def uimm5_optional : OptionalUImmLeafOp<5>;
//===----------------------------------------------------------------------===//
// Instruction Class Templates
@@ -620,20 +617,6 @@ def : InstAlias<"c.ntl.s1", (C_ADD X0, X4)>;
def : InstAlias<"c.ntl.all", (C_ADD X0, X5)>;
} // Predicates = [HasStdExtZca]
-let EmitPriority = 0 in {
-let Predicates = [HasStdExtZca] in {
-}
-
-let Predicates = [HasStdExtZca, IsRV64] in {
-}
-
-let Predicates = [HasStdExtZcf, IsRV32] in {
-}
-
-let Predicates = [HasStdExtZcd] in {
-}
-} // EmitPriority = 0
-
//===----------------------------------------------------------------------===//
// .insn directive instructions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index f0ae8fbd2aab6..21b0ac1eaae11 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1392,13 +1392,14 @@ let hasSideEffects = false, mayLoad = true, mayStore = false, Size = 4,
isCodeGenOnly = false in
class PseudoQCAccessLoad_ri<string opcodestr>
: Pseudo<(outs GPR:$rd),
- (ins BasePtr:$rs1, simm12_optional:$imm12, qc_access_symbol:$expr), [],
- opcodestr, "$rd, ${imm12}(${rs1}), $expr">;
+ (ins BasePtr:$rs1, simm12_optional:$imm12, qc_access_symbol:$expr),
+ [], opcodestr, "$rd, ${imm12}(${rs1}), $expr">;
let hasSideEffects = false, mayLoad = false, mayStore = true, Size = 4,
isCodeGenOnly = false in
class PseudoQCAccessStore_rri<string opcodestr>
- : Pseudo<(outs), (ins GPR:$rs2, BasePtr:$rs1, simm12_optional:$imm12, qc_access_symbol:$expr),
+ : Pseudo<(outs), (ins GPR:$rs2, BasePtr:$rs1, simm12_optional:$imm12,
+ qc_access_symbol:$expr),
[], opcodestr, "$rs2, ${imm12}(${rs1}), $expr">;
@@ -1430,48 +1431,24 @@ class PseudoQCAccessCStore_rri<string opcodestr, DAGOperand immop>
[], opcodestr, "$rs2, ${imm}(${rs1}), $expr">;
let Predicates = [IsRV32, HasStdExtZca] in {
-def PseudoQCAccessC_LW : PseudoQCAccessCLoad_ri<"c.lw", uimm7_lsb00>;
-let EmitPriority = 0 in
-def : InstAlias<"c.lw $rd, (${rs1}), $expr",
- (PseudoQCAccessC_LW GPRC:$rd, BasePtrC:$rs1, 0, qc_access_symbol:$expr)>;
-
-def PseudoQCAccessC_SW : PseudoQCAccessCStore_rri<"c.sw", uimm7_lsb00>;
-let EmitPriority = 0 in
-def : InstAlias<"c.sw $rs2, (${rs1}), $expr",
- (PseudoQCAccessC_SW GPRC:$rs2, BasePtrC:$rs1, 0, qc_access_symbol:$expr)>;
+def PseudoQCAccessC_LW : PseudoQCAccessCLoad_ri<"c.lw", uimm7_lsb00_optional>;
+def PseudoQCAccessC_SW : PseudoQCAccessCStore_rri<"c.sw", uimm7_lsb00_optional>;
}
let Predicates = [IsRV32, HasStdExtZcb] in {
// no C_LB so no PseudoQCAccessC_LB
-def PseudoQCAccessC_LBU : PseudoQCAccessCLoad_ri<"c.lbu", uimm2>;
-def PseudoQCAccessC_LH : PseudoQCAccessCLoad_ri<"c.lh", uimm2_lsb0>;
-def PseudoQCAccessC_LHU : PseudoQCAccessCLoad_ri<"c.lhu", uimm2_lsb0>;
-
-let EmitPriority = 0 in {
-// No c.lb so no alias
-def : InstAlias<"c.lbu $rd, (${rs1}), $expr",
- (PseudoQCAccessC_LBU GPRC:$rd, BasePtrC:$rs1, 0, qc_access_symbol:$expr)>;
-def : InstAlias<"c.lh $rd, (${rs1}), $expr",
- (PseudoQCAccessC_LH GPRC:$rd, BasePtrC:$rs1, 0, qc_access_symbol:$expr)>;
-def : InstAlias<"c.lhu $rd, (${rs1}), $expr",
- (PseudoQCAccessC_LHU GPRC:$rd, BasePtrC:$rs1, 0, qc_access_symbol:$expr)>;
-}
+def PseudoQCAccessC_LBU : PseudoQCAccessCLoad_ri<"c.lbu", uimm2_optional>;
+def PseudoQCAccessC_LH : PseudoQCAccessCLoad_ri<"c.lh", uimm2_lsb0_optional>;
+def PseudoQCAccessC_LHU : PseudoQCAccessCLoad_ri<"c.lhu", uimm2_lsb0_optional>;
-def PseudoQCAccessC_SB : PseudoQCAccessCStore_rri<"c.sb", uimm2>;
-def PseudoQCAccessC_SH : PseudoQCAccessCStore_rri<"c.sh", uimm2_lsb0>;
-
-let EmitPriority = 0 in {
-def : InstAlias<"c.sb $rs2, (${rs1}), $expr",
- (PseudoQCAccessC_SB GPRC:$rs2, BasePtrC:$rs1, 0, qc_access_symbol:$expr)>;
-def : InstAlias<"c.sh $rs2, (${rs1}), $expr",
- (PseudoQCAccessC_SH GPRC:$rs2, BasePtrC:$rs1, 0, qc_access_symbol:$expr)>;
-}
+def PseudoQCAccessC_SB : PseudoQCAccessCStore_rri<"c.sb", uimm2_optional>;
+def PseudoQCAccessC_SH : PseudoQCAccessCStore_rri<"c.sh", uimm2_lsb0_optional>;
}
// FIXME: We would like to add these but they are not supported by CompressPat.
// let Predicates = [HasVendorXqcili, HasStdExtZca] in {
-// def : CompressPat<(PseudoQCAccessLW GPRC:$rd, BasePtrC:$rs1, uimm7_lsb00:$imm, qc_access_symbol:$expr),
-// (PseudoQCAccessC_LW GPRC:$rd, BasePtrC:$rs1, uimm7_lsb00:$imm, qc_access_symbol:$expr)>;
+// def : CompressPat<(PseudoQCAccessLW GPRC:$rd, BasePtrC:$rs1, uimm7_lsb00_optional:$imm, qc_access_symbol:$expr),
+// (PseudoQCAccessC_LW GPRC:$rd, BasePtrC:$rs1, uimm7_lsb00_optional:$imm, qc_access_symbol:$expr)>;
// }
@@ -1885,16 +1862,16 @@ def : CompressPat<(QC_SYNCWF uimm5slist:$imm5), (QC_C_SYNCWF uimm5slist:$imm5)>;
let isCompressOnly = true, Predicates = [HasVendorXqcilo, IsRV32] in {
let append Predicates = [HasStdExtZcb] in {
-def : CompressPat<(QC_E_LBU GPRC:$rd, BasePtrC:$rs1, uimm2:$imm),
- (C_LBU GPRC:$rd, BasePtrC:$rs1, uimm2:$imm)>;
-def : CompressPat<(QC_E_LHU GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0:$imm),
- (C_LHU GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0:$imm)>;
-def : CompressPat<(QC_E_LH GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0:$imm),
- (C_LH GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0:$imm)>;
-def : CompressPat<(QC_E_SB GPRC:$rs2, BasePtrC:$rs1, uimm2:$imm),
- (C_SB GPRC:$rs2, BasePtrC:$rs1, uimm2:$imm)>;
-def : CompressPat<(QC_E_SH GPRC:$rs2, BasePtrC:$rs1, uimm2_lsb0:$imm),
- (C_SH GPRC:$rs2, BasePtrC:$rs1, uimm2_lsb0:$imm)>;
+def : CompressPat<(QC_E_LBU GPRC:$rd, BasePtrC:$rs1, uimm2_optional:$imm),
+ (C_LBU GPRC:$rd, BasePtrC:$rs1, uimm2_optional:$imm)>;
+def : CompressPat<(QC_E_LHU GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0_optional:$imm),
+ (C_LHU GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0_optional:$imm)>;
+def : CompressPat<(QC_E_LH GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0_optional:$imm),
+ (C_LH GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0_optional:$imm)>;
+def : CompressPat<(QC_E_SB GPRC:$rs2, BasePtrC:$rs1, uimm2_optional:$imm),
+ (C_SB GPRC:$rs2, BasePtrC:$rs1, uimm2_optional:$imm)>;
+def : CompressPat<(QC_E_SH GPRC:$rs2, BasePtrC:$rs1, uimm2_lsb0_optional:$imm),
+ (C_SH GPRC:$rs2, BasePtrC:$rs1, uimm2_lsb0_optional:$imm)>;
} // append Predicates = [HasStdExtZcb]
def : CompressPat<(QC_E_LW GPRC:$rd, BasePtrC:$rs1, uimm7_lsb00:$imm),
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index 1beb710e5cdd8..e31346f90fe83 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -15,7 +15,9 @@
// Operand and SDNode transformation definitions.
//===----------------------------------------------------------------------===//
-def uimm2_lsb0 : RISCVUImmLsbZeroOp<2, 1>;
+def uimm2_optional : OptionalUImmLeafOp<2>;
+
+def uimm2_lsb0_optional : OptionalUImmLsbZeroOp<2, 1>;
def uimm8ge32 : RISCVOp {
let ParserMatchClass = UImmAsmOperand<8, "GE32">;
@@ -93,7 +95,7 @@ def negstackadj : RISCVOp<OtherVT> {
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
class CLoadB_ri<bits<6> funct6, string OpcodeStr>
: RVInst16CLB<funct6, OPC_C0, (outs GPRC:$rd),
- (ins BasePtrC:$rs1, uimm2:$imm),
+ (ins BasePtrC:$rs1, uimm2_optional:$imm),
OpcodeStr, "$rd, ${imm}(${rs1})"> {
bits<2> imm;
@@ -104,7 +106,7 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
class CLoadH_ri<bits<6> funct6, bit funct1, string OpcodeStr,
DAGOperand rty = GPRC>
: RVInst16CLH<funct6, funct1, OPC_C0, (outs rty:$rd),
- (ins BasePtrC:$rs1, uimm2_lsb0:$imm),
+ (ins BasePtrC:$rs1, uimm2_lsb0_optional:$imm),
OpcodeStr, "$rd, ${imm}(${rs1})"> {
bits<2> imm;
@@ -114,7 +116,7 @@ class CLoadH_ri<bits<6> funct6, bit funct1, string OpcodeStr,
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class CStoreB_rri<bits<6> funct6, string OpcodeStr>
: RVInst16CSB<funct6, OPC_C0, (outs),
- (ins GPRC:$rs2, BasePtrC:$rs1, uimm2:$imm),
+ (ins GPRC:$rs2, BasePtrC:$rs1, uimm2_optional:$imm),
OpcodeStr, "$rs2, ${imm}(${rs1})"> {
bits<2> imm;
@@ -125,7 +127,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class CStoreH_rri<bits<6> funct6, bit funct1, string OpcodeStr,
DAGOperand rty = GPRC>
: RVInst16CSH<funct6, funct1, OPC_C0, (outs),
- (ins rty:$rs2, BasePtrC:$rs1, uimm2_lsb0:$imm),
+ (ins rty:$rs2, BasePtrC:$rs1, uimm2_lsb0_optional:$imm),
OpcodeStr, "$rs2, ${imm}(${rs1})"> {
bits<2> imm;
@@ -307,34 +309,21 @@ def : CompressPat<(XORI GPRC:$rs1, GPRC:$rs1, -1),
}
let Predicates = [HasStdExtZcb] in{
-def : CompressPat<(LBU GPRC:$rd, BasePtrC:$rs1, uimm2:$imm),
- (C_LBU GPRC:$rd, BasePtrC:$rs1, uimm2:$imm)>;
-def : CompressPat<(LHU GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0:$imm),
- (C_LHU GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0:$imm)>;
-def : CompressPat<(LH GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0:$imm),
- (C_LH GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0:$imm)>;
-def : CompressPat<(SB GPRC:$rs2, BasePtrC:$rs1, uimm2:$imm),
- (C_SB GPRC:$rs2, BasePtrC:$rs1, uimm2:$imm)>;
-def : CompressPat<(SH GPRC:$rs2, BasePtrC:$rs1, uimm2_lsb0:$imm),
- (C_SH GPRC:$rs2, BasePtrC:$rs1, uimm2_lsb0:$imm)>;
+def : CompressPat<(LBU GPRC:$rd, BasePtrC:$rs1, uimm2_optional:$imm),
+ (C_LBU GPRC:$rd, BasePtrC:$rs1, uimm2_optional:$imm)>;
+def : CompressPat<(LHU GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0_optional:$imm),
+ (C_LHU GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0_optional:$imm)>;
+def : CompressPat<(LH GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0_optional:$imm),
+ (C_LH GPRC:$rd, BasePtrC:$rs1, uimm2_lsb0_optional:$imm)>;
+def : CompressPat<(SB GPRC:$rs2, BasePtrC:$rs1, uimm2_optional:$imm),
+ (C_SB GPRC:$rs2, BasePtrC:$rs1, uimm2_optional:$imm)>;
+def : CompressPat<(SH GPRC:$rs2, BasePtrC:$rs1, uimm2_lsb0_optional:$imm),
+ (C_SH GPRC:$rs2, BasePtrC:$rs1, uimm2_lsb0_optional:$imm)>;
let isCompressOnly = true in {
-def : CompressPat<(LH_INX GPRF16C:$rd, BasePtrC:$rs1, uimm2_lsb0:$imm),
- (C_LH_INX GPRF16C:$rd, BasePtrC:$rs1, uimm2_lsb0:$imm)>;
-def : CompressPat<(SH_INX GPRF16C:$rs2, BasePtrC:$rs1, uimm2_lsb0:$imm),
- (C_SH_INX GPRF16C:$rs2, BasePtrC:$rs1, uimm2_lsb0:$imm)>;
+def : CompressPat<(LH_INX GPRF16C:$rd, BasePtrC:$rs1, uimm2_lsb0_optional:$imm),
+ (C_LH_INX GPRF16C:$rd, BasePtrC:$rs1, uimm2_lsb0_optional:$imm)>;
+def : CompressPat<(SH_INX GPRF16C:$rs2, BasePtrC:$rs1, uimm2_lsb0_optional:$imm),
+ (C_SH_INX GPRF16C:$rs2, BasePtrC:$rs1, uimm2_lsb0_optional:$imm)>;
}
}// Predicates = [HasStdExtZcb]
-
-
-//===----------------------------------------------------------------------===//
-// Pseudo Instructions
-//===----------------------------------------------------------------------===//
-
-let Predicates = [HasStdExtZcb] in {
-def : InstAlias<"c.lbu $rd, (${rs1})",(C_LBU GPRC:$rd, GPRC:$rs1, 0), 0>;
-def : InstAlias<"c.lhu $rd, (${rs1})",(C_LHU GPRC:$rd, GPRC:$rs1, 0), 0>;
-def : InstAlias<"c.lh $rd, (${rs1})", (C_LH GPRC:$rd, GPRC:$rs1, 0), 0>;
-def : InstAlias<"c.sb $rd, (${rs1})", (C_SB GPRC:$rd, GPRC:$rs1, 0), 0>;
-def : InstAlias<"c.sh $rd, (${rs1})", (C_SH GPRC:$rd, GPRC:$rs1, 0), 0>;
-}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
index 16467fa424e38..62a1f305249df 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
@@ -71,13 +71,6 @@ def C_SD_RV32 : CStore_rri<0b111, "c.sd", GPRPairCRV32, uimm8_lsb000_optional>,
}
}// Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap"
-//===----------------------------------------------------------------------===//
-// Assembler Pseudo Instructions
-//===----------------------------------------------------------------------===//
-
-let Predicates = [HasStdExtZclsd, IsRV32] in {
-}
-
//===----------------------------------------------------------------------===//
// Compress Instruction tablegen backend.
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/RISCV/rv32c-invalid.s b/llvm/test/MC/RISCV/rv32c-invalid.s
index d63c24e386064..76b1c598ed8f4 100644
--- a/llvm/test/MC/RISCV/rv32c-invalid.s
+++ b/llvm/test/MC/RISCV/rv32c-invalid.s
@@ -108,21 +108,17 @@ c.lui t0, 0x1000000
c.lui t0, foo
# CHECK: [[#@LINE-1]]:11: error: immediate must be in [0xfffe0, 0xfffff] or [1, 31]
-## uimm8_lsb00
+## uimm8_lsb00_optional
c.lwsp ra, 256(sp)
# CHECK: :[[#@LINE-1]]:13: error: immediate must be a multiple of 4 bytes in the range [0, 252]
c.swsp ra, -4(sp)
# CHECK: :[[#@LINE-1]]:13: error: immediate must be a multiple of 4 bytes in the range [0, 252]
-## uimm7_lsb00
+## uimm7_lsb00_optional
c.lw s0, -4(sp)
-# CHECK: :[[#@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[#@LINE-2]]:11: note: expected '('
-# CHECK: :[[#@LINE-3]]:11: note: immediate must be a multiple of 4 bytes in the range [0, 124]
+# CHECK: :[[#@LINE-1]]:11: error: immediate must be a multiple of 4 bytes in the range [0, 124]
c.sw s0, 128(sp)
-# CHECK: :[[#@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[#@LINE-2]]:11: note: expected '('
-# CHECK: :[[#@LINE-3]]:11: note: immediate must be a multiple of 4 bytes in the range [0, 124]
+# CHECK: :[[#@LINE-1]]:11: error: immediate must be a multiple of 4 bytes in the range [0, 124]
## simm9_lsb0
c.bnez s1, -258
diff --git a/llvm/test/MC/RISCV/rv32fc-invalid.s b/llvm/test/MC/RISCV/rv32fc-invalid.s
index 7abdc9cff7d4e..26db1faa61f1a 100644
--- a/llvm/test/MC/RISCV/rv32fc-invalid.s
+++ b/llvm/test/MC/RISCV/rv32fc-invalid.s
@@ -3,7 +3,7 @@
## FPRC
c.flw ft3, 8(a5) # CHECK: :[[@LINE]]:8: error: register must be a FPR
-## uimm8_lsb00
+## uimm8_lsb00_optional
c.flwsp fs1, 256(sp) # CHECK: :[[@LINE]]:15: error: immediate must be a multiple of 4 bytes in the range [0, 252]
c.fswsp fs2, -4(sp) # CHECK: :[[@LINE]]:15: error: immediate must be a multiple of 4 bytes in the range [0, 252]
More information about the llvm-branch-commits
mailing list