[llvm-branch-commits] [llvm] [LoopVectorize] Support vectorization of compressing patterns (PR #214491)

[Benjamin Maxwell via llvm-branch-commits]

MacDue wrote:

> Looks like this isn't working for i8 and i16 loops?

It works, though for AArch64 specifcally we've not wired up the lowering for `compressstore` for those types yet (as they require +sve2p2), so the cost is currently invalid. I can add a target-agnostic test to demonstrate i8/i16 though.  



https://github.com/llvm/llvm-project/pull/214491