[llvm-branch-commits] [llvm] [AMDGPU] Insert exec-forced V_NOP after V_PERM_PK16 (gfx1250 hazard) (PR #214406)

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git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h llvm/lib/Target/AMDGPU/GCNSubtarget.h llvm/lib/Target/AMDGPU/SIFrameLowering.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.h llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 6ae1bdc60..b9abe0db8 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -998,10 +998,11 @@ public:
     return HasGFX1250Insts && getGeneration() == GFX12;
   }
 
-  // V_PERM_PK16 leaves a hazard that must be cleared by an immediately following
-  // "safe" instruction (or an inserted V_NOP). The V_PERM_PK16 instructions are available
-  // whenever the tensor convert LUT instructions are available, but the hazard only
-  // affects the GFX12 (gfx1250) part; gfx13 issues them safely.
+  // V_PERM_PK16 leaves a hazard that must be cleared by an immediately
+  // following "safe" instruction (or an inserted V_NOP). The V_PERM_PK16
+  // instructions are available whenever the tensor convert LUT instructions are
+  // available, but the hazard only affects the GFX12 (gfx1250) part; gfx13
+  // issues them safely.
   bool hasVPermPk16Hazard() const {
     return hasTensorCvtLutInsts() && getGeneration() == GFX12;
   }
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index b10ef2c3d..b2290ad8c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1189,12 +1189,9 @@ public:
   }
 
   static bool isF64Trans(unsigned Opcode) {
-    return Opcode == AMDGPU::V_RCP_F64_e32 ||
-           Opcode == AMDGPU::V_RCP_F64_e64 ||
-           Opcode == AMDGPU::V_RSQ_F64_e32 ||
-           Opcode == AMDGPU::V_RSQ_F64_e64 ||
-           Opcode == AMDGPU::V_SQRT_F64_e32 ||
-           Opcode == AMDGPU::V_SQRT_F64_e64;
+    return Opcode == AMDGPU::V_RCP_F64_e32 || Opcode == AMDGPU::V_RCP_F64_e64 ||
+           Opcode == AMDGPU::V_RSQ_F64_e32 || Opcode == AMDGPU::V_RSQ_F64_e64 ||
+           Opcode == AMDGPU::V_SQRT_F64_e32 || Opcode == AMDGPU::V_SQRT_F64_e64;
   }
 
   static bool isVPermPk16(unsigned Opcode) {

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https://github.com/llvm/llvm-project/pull/214406