[llvm-branch-commits] [llvm] [RISC-V] Use an optional offset for C/Zc* extension instruction (PR #211674)

[Alexander Richardson via llvm-branch-commits]

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@@ -107,14 +107,25 @@ class RISCVUImmLsbZeroOp<int width, int zeros>
   }];
 }
 
+// Variant of RISCVUImmLsbZeroOp for memory-operand offsets that may be
+// omitted entirely, e.g. "c.lw a0, (a1)". See OptionalMemOffsetAsmOperand.
+class OptionalUImmLsbZeroOp<int width, int zeros>
+    : RISCVUImmLsbZeroOp<width, zeros> {
+  defvar Suffix0 = !foldl("", !range(zeros), acc, ignore, !strconcat(acc, "0"));
+  let ParserMatchClass =
+      OptionalMemOffsetAsmOperand<UImmAsmOperand<width, "Lsb" # Suffix0>>;
+}
+
 // A 7-bit unsigned immediate where the least significant two bits are zero.
 def uimm7_lsb00 : RISCVUImmLsbZeroOp<7, 2>;
+def uimm7_lsb00_optional : OptionalUImmLsbZeroOp<7, 2>;
 
 // A 8-bit unsigned immediate where the least significant two bits are zero.
 def uimm8_lsb00 : RISCVUImmLsbZeroOp<8, 2>;
+def uimm8_lsb00_optional : OptionalUImmLsbZeroOp<8, 2>;
 
 // A 8-bit unsigned immediate where the least significant three bits are zero.
-def uimm8_lsb000 : RISCVUImmLsbZeroOp<8, 3>;
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arichardson wrote:

Unlike the other ones above all uses are gone now. I'll remove the other ones as part of updating. the XQCI/etc. files

https://github.com/llvm/llvm-project/pull/211674