[llvm-branch-commits] [llvm] [LoongArch][NFC] Add tests for vector extract comparison combines (PR #214203)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Aug 5 05:04:19 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-loongarch
Author: hev (heiher)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/214203.diff
2 Files Affected:
- (added) llvm/test/CodeGen/LoongArch/lasx/vec-extract-brcond.ll (+137)
- (added) llvm/test/CodeGen/LoongArch/lsx/vec-extract-brcond.ll (+137)
``````````diff
diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-extract-brcond.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-extract-brcond.ll
new file mode 100644
index 0000000000000..e16d9be1a95d9
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/vec-extract-brcond.ll
@@ -0,0 +1,137 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
+
+define void @extract_32xi8_br_eq_0(ptr %src, ptr %dst) nounwind {
+; CHECK-LABEL: extract_32xi8_br_eq_0:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.bu $a0, $vr0, 0
+; CHECK-NEXT: beqz $a0, .LBB0_2
+; CHECK-NEXT: # %bb.1: # %bb2
+; CHECK-NEXT: ori $a0, $zero, 1
+; CHECK-NEXT: st.b $a0, $a1, 0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB0_2: # %bb1
+; CHECK-NEXT: st.b $zero, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %0 = load volatile <32 x i8>, ptr %src
+ %1 = extractelement <32 x i8> %0, i64 0
+ %2 = icmp eq i8 %1, 0
+ br i1 %2, label %bb1, label %bb2
+bb1:
+ store i8 0, ptr %dst
+ ret void
+bb2:
+ store i8 1, ptr %dst
+ ret void
+}
+
+define void @extract_16xi16_br_ne_0(ptr %src, ptr %dst) nounwind {
+; LA32-LABEL: extract_16xi16_br_ne_0:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvld $xr0, $a0, 0
+; LA32-NEXT: vpickve2gr.h $a0, $vr0, 0
+; LA32-NEXT: slli.w $a0, $a0, 16
+; LA32-NEXT: beqz $a0, .LBB1_2
+; LA32-NEXT: # %bb.1: # %bb1
+; LA32-NEXT: st.b $zero, $a1, 0
+; LA32-NEXT: ret
+; LA32-NEXT: .LBB1_2: # %bb2
+; LA32-NEXT: ori $a0, $zero, 1
+; LA32-NEXT: st.b $a0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: extract_16xi16_br_ne_0:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvld $xr0, $a0, 0
+; LA64-NEXT: vpickve2gr.h $a0, $vr0, 0
+; LA64-NEXT: slli.d $a0, $a0, 48
+; LA64-NEXT: beqz $a0, .LBB1_2
+; LA64-NEXT: # %bb.1: # %bb1
+; LA64-NEXT: st.b $zero, $a1, 0
+; LA64-NEXT: ret
+; LA64-NEXT: .LBB1_2: # %bb2
+; LA64-NEXT: ori $a0, $zero, 1
+; LA64-NEXT: st.b $a0, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %0 = load volatile <16 x i16>, ptr %src
+ %1 = extractelement <16 x i16> %0, i64 0
+ %2 = icmp ne i16 %1, 0
+ br i1 %2, label %bb1, label %bb2
+bb1:
+ store i8 0, ptr %dst
+ ret void
+bb2:
+ store i8 1, ptr %dst
+ ret void
+}
+
+define void @extract_8xi32_br_eq_0(ptr %src, ptr %dst) nounwind {
+; CHECK-LABEL: extract_8xi32_br_eq_0:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a0, 0
+; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 0
+; CHECK-NEXT: beqz $a0, .LBB2_2
+; CHECK-NEXT: # %bb.1: # %bb2
+; CHECK-NEXT: ori $a0, $zero, 1
+; CHECK-NEXT: st.b $a0, $a1, 0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB2_2: # %bb1
+; CHECK-NEXT: st.b $zero, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %0 = load volatile <8 x i32>, ptr %src
+ %1 = extractelement <8 x i32> %0, i64 0
+ %2 = icmp eq i32 %1, 0
+ br i1 %2, label %bb1, label %bb2
+bb1:
+ store i8 0, ptr %dst
+ ret void
+bb2:
+ store i8 1, ptr %dst
+ ret void
+}
+
+define void @extract_4xi64_br_ne_0(ptr %src, ptr %dst) nounwind {
+; LA32-LABEL: extract_4xi64_br_ne_0:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvld $xr0, $a0, 0
+; LA32-NEXT: xvpickve2gr.w $a0, $xr0, 1
+; LA32-NEXT: xvpickve2gr.w $a2, $xr0, 0
+; LA32-NEXT: or $a0, $a2, $a0
+; LA32-NEXT: beqz $a0, .LBB3_2
+; LA32-NEXT: # %bb.1: # %bb1
+; LA32-NEXT: st.b $zero, $a1, 0
+; LA32-NEXT: ret
+; LA32-NEXT: .LBB3_2: # %bb2
+; LA32-NEXT: ori $a0, $zero, 1
+; LA32-NEXT: st.b $a0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: extract_4xi64_br_ne_0:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvld $xr0, $a0, 0
+; LA64-NEXT: xvpickve2gr.d $a0, $xr0, 0
+; LA64-NEXT: beqz $a0, .LBB3_2
+; LA64-NEXT: # %bb.1: # %bb1
+; LA64-NEXT: st.b $zero, $a1, 0
+; LA64-NEXT: ret
+; LA64-NEXT: .LBB3_2: # %bb2
+; LA64-NEXT: ori $a0, $zero, 1
+; LA64-NEXT: st.b $a0, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %0 = load volatile <4 x i64>, ptr %src
+ %1 = extractelement <4 x i64> %0, i64 0
+ %2 = icmp ne i64 %1, 0
+ br i1 %2, label %bb1, label %bb2
+bb1:
+ store i8 0, ptr %dst
+ ret void
+bb2:
+ store i8 1, ptr %dst
+ ret void
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-extract-brcond.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-extract-brcond.ll
new file mode 100644
index 0000000000000..e78590b3a62db
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-extract-brcond.ll
@@ -0,0 +1,137 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s --check-prefixes=CHECK,LA64
+
+define void @extract_16xi8_br_eq_0(ptr %src, ptr %dst) nounwind {
+; CHECK-LABEL: extract_16xi8_br_eq_0:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.bu $a0, $vr0, 0
+; CHECK-NEXT: beqz $a0, .LBB0_2
+; CHECK-NEXT: # %bb.1: # %bb2
+; CHECK-NEXT: ori $a0, $zero, 1
+; CHECK-NEXT: st.b $a0, $a1, 0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB0_2: # %bb1
+; CHECK-NEXT: st.b $zero, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %0 = load volatile <16 x i8>, ptr %src
+ %1 = extractelement <16 x i8> %0, i64 0
+ %2 = icmp eq i8 %1, 0
+ br i1 %2, label %bb1, label %bb2
+bb1:
+ store i8 0, ptr %dst
+ ret void
+bb2:
+ store i8 1, ptr %dst
+ ret void
+}
+
+define void @extract_8xi16_br_ne_0(ptr %src, ptr %dst) nounwind {
+; LA32-LABEL: extract_8xi16_br_ne_0:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vld $vr0, $a0, 0
+; LA32-NEXT: vpickve2gr.h $a0, $vr0, 0
+; LA32-NEXT: slli.w $a0, $a0, 16
+; LA32-NEXT: beqz $a0, .LBB1_2
+; LA32-NEXT: # %bb.1: # %bb1
+; LA32-NEXT: st.b $zero, $a1, 0
+; LA32-NEXT: ret
+; LA32-NEXT: .LBB1_2: # %bb2
+; LA32-NEXT: ori $a0, $zero, 1
+; LA32-NEXT: st.b $a0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: extract_8xi16_br_ne_0:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vld $vr0, $a0, 0
+; LA64-NEXT: vpickve2gr.h $a0, $vr0, 0
+; LA64-NEXT: slli.d $a0, $a0, 48
+; LA64-NEXT: beqz $a0, .LBB1_2
+; LA64-NEXT: # %bb.1: # %bb1
+; LA64-NEXT: st.b $zero, $a1, 0
+; LA64-NEXT: ret
+; LA64-NEXT: .LBB1_2: # %bb2
+; LA64-NEXT: ori $a0, $zero, 1
+; LA64-NEXT: st.b $a0, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %0 = load volatile <8 x i16>, ptr %src
+ %1 = extractelement <8 x i16> %0, i64 0
+ %2 = icmp ne i16 %1, 0
+ br i1 %2, label %bb1, label %bb2
+bb1:
+ store i8 0, ptr %dst
+ ret void
+bb2:
+ store i8 1, ptr %dst
+ ret void
+}
+
+define void @extract_4xi32_br_eq_0(ptr %src, ptr %dst) nounwind {
+; CHECK-LABEL: extract_4xi32_br_eq_0:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 0
+; CHECK-NEXT: beqz $a0, .LBB2_2
+; CHECK-NEXT: # %bb.1: # %bb2
+; CHECK-NEXT: ori $a0, $zero, 1
+; CHECK-NEXT: st.b $a0, $a1, 0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB2_2: # %bb1
+; CHECK-NEXT: st.b $zero, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %0 = load volatile <4 x i32>, ptr %src
+ %1 = extractelement <4 x i32> %0, i64 0
+ %2 = icmp eq i32 %1, 0
+ br i1 %2, label %bb1, label %bb2
+bb1:
+ store i8 0, ptr %dst
+ ret void
+bb2:
+ store i8 1, ptr %dst
+ ret void
+}
+
+define void @extract_2xi64_br_ne_0(ptr %src, ptr %dst) nounwind {
+; LA32-LABEL: extract_2xi64_br_ne_0:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vld $vr0, $a0, 0
+; LA32-NEXT: vpickve2gr.w $a0, $vr0, 1
+; LA32-NEXT: vpickve2gr.w $a2, $vr0, 0
+; LA32-NEXT: or $a0, $a2, $a0
+; LA32-NEXT: beqz $a0, .LBB3_2
+; LA32-NEXT: # %bb.1: # %bb1
+; LA32-NEXT: st.b $zero, $a1, 0
+; LA32-NEXT: ret
+; LA32-NEXT: .LBB3_2: # %bb2
+; LA32-NEXT: ori $a0, $zero, 1
+; LA32-NEXT: st.b $a0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: extract_2xi64_br_ne_0:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vld $vr0, $a0, 0
+; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0
+; LA64-NEXT: beqz $a0, .LBB3_2
+; LA64-NEXT: # %bb.1: # %bb1
+; LA64-NEXT: st.b $zero, $a1, 0
+; LA64-NEXT: ret
+; LA64-NEXT: .LBB3_2: # %bb2
+; LA64-NEXT: ori $a0, $zero, 1
+; LA64-NEXT: st.b $a0, $a1, 0
+; LA64-NEXT: ret
+entry:
+ %0 = load volatile <2 x i64>, ptr %src
+ %1 = extractelement <2 x i64> %0, i64 0
+ %2 = icmp ne i64 %1, 0
+ br i1 %2, label %bb1, label %bb2
+bb1:
+ store i8 0, ptr %dst
+ ret void
+bb2:
+ store i8 1, ptr %dst
+ ret void
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/214203
More information about the llvm-branch-commits
mailing list