[llvm-branch-commits] [llvm] [LV][REVEC][AArch64] Proof of concept for re-vectorisation (PR #208213)

[Gaëtan Bossu via llvm-branch-commits]

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@@ -299,11 +299,31 @@ Value *VPTransformState::get(const VPValue *Def, const VPLane &Lane) {
 
   assert(hasVectorValue(Def));
   auto *VecPart = Data.VPV2Vector[Def];
-  if (!VecPart->getType()->isVectorTy()) {
+  // If VecPart's type is the same as the initial pre-vectorisation type,
+  // Def hasn't been vectorised. We are done.
+  Type *InitialTy = Def->getScalarType();
+  if (VecPart->getType() == InitialTy) {
     assert(Lane.isFirstLane() && "cannot get lane > 0 for scalar");
     return VecPart;
   }
+
+  // Last case: Extract a lane of type InitialTy from a vectorised value.
   // TODO: Cache created scalar values.
+  if (auto *InitVTy = dyn_cast<VectorType>(InitialTy)) {
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gbossu wrote:

I've looked into it again and even though we do not support first order recurrences yet, we might still need "vector lane" extraction for liveouts. I've added a commit to test this case.

https://github.com/llvm/llvm-project/pull/208213