[llvm-branch-commits] [llvm] [AMDGPU][GISel] Add RegBankLegalize rules for amdgcn_tanh (PR #214051)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Aug 4 12:52:26 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Chinmay Deshpande (chinmaydd)
<details>
<summary>Changes</summary>
Enable the existing gfx1250 and gfx13 GlobalISel coverage now that tanh operands are assigned to VGPRs.
---
Patch is 39.93 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/214051.diff
2 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll (+570-31)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 66a5e1bb378be..09a44740da349 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -2466,7 +2466,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Div(B32, {{VgprB32}, {IntrId, VgprB32, VgprB32}})
.Div(B64, {{VgprB64}, {IntrId, VgprB64, VgprB64}});
- addRulesForIOpcs({amdgcn_sin, amdgcn_cos}, Standard)
+ addRulesForIOpcs({amdgcn_sin, amdgcn_cos, amdgcn_tanh}, Standard)
.Div(S16, {{Vgpr16}, {IntrId, Vgpr16}})
.Uni(S16, {{UniInVgprS16}, {IntrId, Vgpr16}})
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32}})
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
index 5d8a251570444..75572fe4e121b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-REAL16 %s
; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-FAKE16 %s
-; xUN: llc -global-isel=1 -mtriple=amdgpu12.50 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-REAL16 %s
-; xUN: llc -global-isel=1 -mtriple=amdgpu12.50 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-REAL16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgpu13.10 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX13,GFX13-SDAG-REAL16 %s
; RUN: llc -global-isel=0 -mtriple=amdgpu13.10 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX13,GFX13-SDAG-FAKE16 %s
-; xUN: llc -global-isel=1 -mtriple=amdgpu13.10 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX13,GFX13-GISEL-REAL16 %s
-; xUN: llc -global-isel=1 -mtriple=amdgpu13.10 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX13,GFX13-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu13.10 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX13,GFX13-GISEL-REAL16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu13.10 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX13,GFX13-GISEL-FAKE16 %s
; RUN: not llc -global-isel=0 -mtriple=amdgpu9.50 -filetype=null < %s 2>&1 | FileCheck -check-prefix=ERR %s
; RUN: not llc -global-isel=1 -mtriple=amdgpu9.50 -filetype=null < %s 2>&1 | FileCheck -check-prefix=ERR %s
@@ -154,16 +154,53 @@ define amdgpu_ps float @tanh_f32_constant_100.0() {
}
define amdgpu_ps float @tanh_undef_f32() {
-; GFX1250-LABEL: tanh_undef_f32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: ; return to shader part epilog
+; GFX1250-SDAG-REAL16-LABEL: tanh_undef_f32:
+; GFX1250-SDAG-REAL16: ; %bb.0:
+; GFX1250-SDAG-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-SDAG-REAL16-NEXT: v_nop
+; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog
;
-; GFX13-LABEL: tanh_undef_f32:
-; GFX13: ; %bb.0:
-; GFX13-NEXT: ; return to shader part epilog
+; GFX1250-SDAG-FAKE16-LABEL: tanh_undef_f32:
+; GFX1250-SDAG-FAKE16: ; %bb.0:
+; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-SDAG-FAKE16-NEXT: v_nop
+; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-REAL16-LABEL: tanh_undef_f32:
+; GFX1250-GISEL-REAL16: ; %bb.0:
+; GFX1250-GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-REAL16-NEXT: v_nop
+; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-REAL16-NEXT: v_tanh_f32_e32 v0, s0
+; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-FAKE16-LABEL: tanh_undef_f32:
+; GFX1250-GISEL-FAKE16: ; %bb.0:
+; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-FAKE16-NEXT: v_nop
+; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-FAKE16-NEXT: v_tanh_f32_e32 v0, s0
+; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-SDAG-REAL16-LABEL: tanh_undef_f32:
+; GFX13-SDAG-REAL16: ; %bb.0:
+; GFX13-SDAG-REAL16-NEXT: ; return to shader part epilog
+;
+; GFX13-SDAG-FAKE16-LABEL: tanh_undef_f32:
+; GFX13-SDAG-FAKE16: ; %bb.0:
+; GFX13-SDAG-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-GISEL-REAL16-LABEL: tanh_undef_f32:
+; GFX13-GISEL-REAL16: ; %bb.0:
+; GFX13-GISEL-REAL16-NEXT: v_tanh_f32_e32 v0, s0
+; GFX13-GISEL-REAL16-NEXT: ; return to shader part epilog
+;
+; GFX13-GISEL-FAKE16-LABEL: tanh_undef_f32:
+; GFX13-GISEL-FAKE16: ; %bb.0:
+; GFX13-GISEL-FAKE16-NEXT: v_tanh_f32_e32 v0, s0
+; GFX13-GISEL-FAKE16-NEXT: ; return to shader part epilog
%tanh = call float @llvm.amdgcn.tanh.f32(float undef)
ret float %tanh
}
@@ -183,6 +220,20 @@ define half @tanh_f16(half %src) {
; GFX1250-SDAG-FAKE16-NEXT: v_tanh_f16_e32 v0, v0
; GFX1250-SDAG-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
+; GFX1250-GISEL-REAL16-LABEL: tanh_f16:
+; GFX1250-GISEL-REAL16: ; %bb.0:
+; GFX1250-GISEL-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-REAL16-NEXT: v_tanh_f16_e32 v0.l, v0.l
+; GFX1250-GISEL-REAL16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-GISEL-FAKE16-LABEL: tanh_f16:
+; GFX1250-GISEL-FAKE16: ; %bb.0:
+; GFX1250-GISEL-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-FAKE16-NEXT: v_tanh_f16_e32 v0, v0
+; GFX1250-GISEL-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
; GFX13-SDAG-REAL16-LABEL: tanh_f16:
; GFX13-SDAG-REAL16: ; %bb.0:
; GFX13-SDAG-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -202,6 +253,26 @@ define half @tanh_f16(half %src) {
; GFX13-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX13-SDAG-FAKE16-NEXT: v_tanh_f16_e32 v0, v0
; GFX13-SDAG-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX13-GISEL-REAL16-LABEL: tanh_f16:
+; GFX13-GISEL-REAL16: ; %bb.0:
+; GFX13-GISEL-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_expcnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_samplecnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_bvhcnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX13-GISEL-REAL16-NEXT: v_tanh_f16_e32 v0.l, v0.l
+; GFX13-GISEL-REAL16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX13-GISEL-FAKE16-LABEL: tanh_f16:
+; GFX13-GISEL-FAKE16: ; %bb.0:
+; GFX13-GISEL-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: v_tanh_f16_e32 v0, v0
+; GFX13-GISEL-FAKE16-NEXT: s_set_pc_i64 s[30:31]
%tanh = call half @llvm.amdgcn.tanh.f16(half %src)
ret half %tanh
}
@@ -221,6 +292,20 @@ define half @tanh_f16_neg(half %src) {
; GFX1250-SDAG-FAKE16-NEXT: v_tanh_f16_e64 v0, -v0
; GFX1250-SDAG-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
+; GFX1250-GISEL-REAL16-LABEL: tanh_f16_neg:
+; GFX1250-GISEL-REAL16: ; %bb.0:
+; GFX1250-GISEL-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-REAL16-NEXT: v_tanh_f16_e64 v0.l, -v0.l
+; GFX1250-GISEL-REAL16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-GISEL-FAKE16-LABEL: tanh_f16_neg:
+; GFX1250-GISEL-FAKE16: ; %bb.0:
+; GFX1250-GISEL-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-FAKE16-NEXT: v_tanh_f16_e64 v0, -v0
+; GFX1250-GISEL-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
; GFX13-SDAG-REAL16-LABEL: tanh_f16_neg:
; GFX13-SDAG-REAL16: ; %bb.0:
; GFX13-SDAG-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -240,6 +325,26 @@ define half @tanh_f16_neg(half %src) {
; GFX13-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX13-SDAG-FAKE16-NEXT: v_tanh_f16_e64 v0, -v0
; GFX13-SDAG-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX13-GISEL-REAL16-LABEL: tanh_f16_neg:
+; GFX13-GISEL-REAL16: ; %bb.0:
+; GFX13-GISEL-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_expcnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_samplecnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_bvhcnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX13-GISEL-REAL16-NEXT: v_tanh_f16_e64 v0.l, -v0.l
+; GFX13-GISEL-REAL16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX13-GISEL-FAKE16-LABEL: tanh_f16_neg:
+; GFX13-GISEL-FAKE16: ; %bb.0:
+; GFX13-GISEL-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: v_tanh_f16_e64 v0, -v0
+; GFX13-GISEL-FAKE16-NEXT: s_set_pc_i64 s[30:31]
%fneg = fneg half %src
%tanh = call half @llvm.amdgcn.tanh.f16(half %fneg)
ret half %tanh
@@ -260,6 +365,20 @@ define half @tanh_f16_abs(half %src) {
; GFX1250-SDAG-FAKE16-NEXT: v_tanh_f16_e64 v0, |v0|
; GFX1250-SDAG-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
+; GFX1250-GISEL-REAL16-LABEL: tanh_f16_abs:
+; GFX1250-GISEL-REAL16: ; %bb.0:
+; GFX1250-GISEL-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-REAL16-NEXT: v_tanh_f16_e64 v0.l, |v0.l|
+; GFX1250-GISEL-REAL16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-GISEL-FAKE16-LABEL: tanh_f16_abs:
+; GFX1250-GISEL-FAKE16: ; %bb.0:
+; GFX1250-GISEL-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-FAKE16-NEXT: v_tanh_f16_e64 v0, |v0|
+; GFX1250-GISEL-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
; GFX13-SDAG-REAL16-LABEL: tanh_f16_abs:
; GFX13-SDAG-REAL16: ; %bb.0:
; GFX13-SDAG-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -279,6 +398,26 @@ define half @tanh_f16_abs(half %src) {
; GFX13-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX13-SDAG-FAKE16-NEXT: v_tanh_f16_e64 v0, |v0|
; GFX13-SDAG-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX13-GISEL-REAL16-LABEL: tanh_f16_abs:
+; GFX13-GISEL-REAL16: ; %bb.0:
+; GFX13-GISEL-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_expcnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_samplecnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_bvhcnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX13-GISEL-REAL16-NEXT: v_tanh_f16_e64 v0.l, |v0.l|
+; GFX13-GISEL-REAL16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX13-GISEL-FAKE16-LABEL: tanh_f16_abs:
+; GFX13-GISEL-FAKE16: ; %bb.0:
+; GFX13-GISEL-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: v_tanh_f16_e64 v0, |v0|
+; GFX13-GISEL-FAKE16-NEXT: s_set_pc_i64 s[30:31]
%fabs = call half @llvm.fabs.f16(half %src)
%tanh = call half @llvm.amdgcn.tanh.f16(half %fabs)
ret half %tanh
@@ -299,6 +438,20 @@ define half @tanh_f16_neg_abs(half %src) {
; GFX1250-SDAG-FAKE16-NEXT: v_tanh_f16_e64 v0, -|v0|
; GFX1250-SDAG-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
+; GFX1250-GISEL-REAL16-LABEL: tanh_f16_neg_abs:
+; GFX1250-GISEL-REAL16: ; %bb.0:
+; GFX1250-GISEL-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-REAL16-NEXT: v_tanh_f16_e64 v0.l, -|v0.l|
+; GFX1250-GISEL-REAL16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-GISEL-FAKE16-LABEL: tanh_f16_neg_abs:
+; GFX1250-GISEL-FAKE16: ; %bb.0:
+; GFX1250-GISEL-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-FAKE16-NEXT: v_tanh_f16_e64 v0, -|v0|
+; GFX1250-GISEL-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
; GFX13-SDAG-REAL16-LABEL: tanh_f16_neg_abs:
; GFX13-SDAG-REAL16: ; %bb.0:
; GFX13-SDAG-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -318,6 +471,26 @@ define half @tanh_f16_neg_abs(half %src) {
; GFX13-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX13-SDAG-FAKE16-NEXT: v_tanh_f16_e64 v0, -|v0|
; GFX13-SDAG-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX13-GISEL-REAL16-LABEL: tanh_f16_neg_abs:
+; GFX13-GISEL-REAL16: ; %bb.0:
+; GFX13-GISEL-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_expcnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_samplecnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_bvhcnt 0x0
+; GFX13-GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX13-GISEL-REAL16-NEXT: v_tanh_f16_e64 v0.l, -|v0.l|
+; GFX13-GISEL-REAL16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX13-GISEL-FAKE16-LABEL: tanh_f16_neg_abs:
+; GFX13-GISEL-FAKE16: ; %bb.0:
+; GFX13-GISEL-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX13-GISEL-FAKE16-NEXT: v_tanh_f16_e64 v0, -|v0|
+; GFX13-GISEL-FAKE16-NEXT: s_set_pc_i64 s[30:31]
%fabs = call half @llvm.fabs.f16(half %src)
%fneg = fneg half %fabs
%tanh = call half @llvm.amdgcn.tanh.f16(half %fneg)
@@ -341,6 +514,22 @@ define amdgpu_ps half @tanh_f16_scalar(half inreg %src) {
; GFX1250-SDAG-FAKE16-NEXT: v_tanh_f16_e32 v0, s0
; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
;
+; GFX1250-GISEL-REAL16-LABEL: tanh_f16_scalar:
+; GFX1250-GISEL-REAL16: ; %bb.0:
+; GFX1250-GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-REAL16-NEXT: v_nop
+; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-REAL16-NEXT: v_tanh_f16_e32 v0.l, s0
+; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-FAKE16-LABEL: tanh_f16_scalar:
+; GFX1250-GISEL-FAKE16: ; %bb.0:
+; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-FAKE16-NEXT: v_nop
+; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-FAKE16-NEXT: v_tanh_f16_e32 v0, s0
+; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
+;
; GFX13-SDAG-REAL16-LABEL: tanh_f16_scalar:
; GFX13-SDAG-REAL16: ; %bb.0:
; GFX13-SDAG-REAL16-NEXT: v_tanh_f16_e32 v0.l, s0
@@ -350,6 +539,16 @@ define amdgpu_ps half @tanh_f16_scalar(half inreg %src) {
; GFX13-SDAG-FAKE16: ; %bb.0:
; GFX13-SDAG-FAKE16-NEXT: v_tanh_f16_e32 v0, s0
; GFX13-SDAG-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-GISEL-REAL16-LABEL: tanh_f16_scalar:
+; GFX13-GISEL-REAL16: ; %bb.0:
+; GFX13-GISEL-REAL16-NEXT: v_tanh_f16_e32 v0.l, s0
+; GFX13-GISEL-REAL16-NEXT: ; return to shader part epilog
+;
+; GFX13-GISEL-FAKE16-LABEL: tanh_f16_scalar:
+; GFX13-GISEL-FAKE16: ; %bb.0:
+; GFX13-GISEL-FAKE16-NEXT: v_tanh_f16_e32 v0, s0
+; GFX13-GISEL-FAKE16-NEXT: ; return to shader part epilog
%tanh = call half @llvm.amdgcn.tanh.f16(half %src)
ret half %tanh
}
@@ -371,6 +570,22 @@ define amdgpu_ps half @tanh_f16_constant_4.0() {
; GFX1250-SDAG-FAKE16-NEXT: v_tanh_f16_e32 v0, 4.0
; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
;
+; GFX1250-GISEL-REAL16-LABEL: tanh_f16_constant_4.0:
+; GFX1250-GISEL-REAL16: ; %bb.0:
+; GFX1250-GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-REAL16-NEXT: v_nop
+; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-REAL16-NEXT: v_tanh_f16_e32 v0.l, 4.0
+; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-FAKE16-LABEL: tanh_f16_constant_4.0:
+; GFX1250-GISEL-FAKE16: ; %bb.0:
+; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-FAKE16-NEXT: v_nop
+; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-FAKE16-NEXT: v_tanh_f16_e32 v0, 4.0
+; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
+;
; GFX13-SDAG-REAL16-LABEL: tanh_f16_constant_4.0:
; GFX13-SDAG-REAL16: ; %bb.0:
; GFX13-SDAG-REAL16-NEXT: v_tanh_f16_e32 v0.l, 4.0
@@ -380,6 +595,16 @@ define amdgpu_ps half @tanh_f16_constant_4.0() {
; GFX13-SDAG-FAKE16: ; %bb.0:
; GFX13-SDAG-FAKE16-NEXT: v_tanh_f16_e32 v0, 4.0
; GFX13-SDAG-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-GISEL-REAL16-LABEL: tanh_f16_constant_4.0:
+; GFX13-GISEL-REAL16: ; %bb.0:
+; GFX13-GISEL-REAL16-NEXT: v_tanh_f16_e32 v0.l, 4.0
+; GFX13-GISEL-REAL16-NEXT: ; return to shader part epilog
+;
+; GFX13-GISEL-FAKE16-LABEL: tanh_f16_constant_4.0:
+; GFX13-GISEL-FAKE16: ; %bb.0:
+; GFX13-GISEL-FAKE16-NEXT: v_tanh_f16_e32 v0, 4.0
+; GFX13-GISEL-FAKE16-NEXT: ; return to shader part epilog
%tanh = call half @llvm.amdgcn.tanh.f16(half 4.0)
ret half %tanh
}
@@ -401,6 +626,22 @@ define amdgpu_ps half @tanh_f16_constant_100.0() {
; GFX1250-SDAG-FAKE16-NEXT: v_tanh_f16_e32 v0, 0x5640
; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
;
+; GFX1250-GISEL-REAL16-LABEL: tanh_f16_constant_100.0:
+; GFX1250-GISEL-REAL16: ; %bb.0:
+; GFX1250-GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-REAL16-NEXT: v_nop
+; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-REAL16-NEXT: v_tanh_f16_e32 v0.l, 0x5640
+; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-FAKE16-LABEL: tanh_f16_constant_100.0:
+; GFX1250-GISEL-FAKE16: ; %bb.0:
+; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GFX1250-GISEL-FAKE16-NEXT: v_nop
+; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-FAKE16-NEXT: v_tanh_f16_e32 v0, 0x5640
+; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
+;
; GFX13-SDAG-REAL16-LABEL: tanh_f16_constant_100.0:
; GFX13-SDAG-REAL16: ; %bb.0:
; GFX13-SDAG-REAL16-NEXT: v_tanh_f16_e32 v0.l, 0x5640
@@ -410,21 +651,68 @@ define amdgpu_ps half @tanh_f16_constant_100.0() {
; GFX13-SDAG-FAKE16: ; %bb.0:
; GFX13-SDAG-FAKE16-NEXT: v_tanh_f16_e32 v0, 0x5640
; GFX13-SDAG-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX13-GISEL-REAL16-LABEL: tanh_f16_constant_100.0:
+; GFX13-GISEL-REAL16: ; %bb.0:
+; GFX13-GISEL-REAL16-NEXT: v_tanh_f16_e32 v0.l, 0x5640
+; GFX13-GISEL-REAL16-NEXT: ; return to shader part epilog
+;
+; GFX13-GISEL-FAKE16-LABEL: tanh_f16_constant_100.0:
+; GFX13-GISEL-FAKE16: ; %bb.0:
+; GFX13-GISEL-FAKE16-NEXT: v_tanh_f16_e32 v0, 0x5640
+; GFX13-GISEL-FAKE16-NEXT: ; return to shader part epilog
%tanh = call half @llvm.amdgcn.tanh.f16(half 100.0)
ret half %tanh
}
define amdgpu_ps half @tanh_undef_f16() {
-; GFX1250-LABEL: tanh_undef_f16:
-; G...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/214051
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