[llvm-branch-commits] [RISC-V] Use an optional offset for C/Zclsd extension instruction (PR #211674)

[Craig Topper via llvm-branch-commits]

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@@ -30,14 +30,12 @@ c.sdsp t1, -8(sp) # CHECK: :[[@LINE]]:12: error: immediate must be a multiple of
 c.ld  s0, -8(sp)
 # CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
 # CHECK: :[[@LINE-2]]:7: note: register must be a GPR from x8 to x15
-# CHECK: :[[@LINE-3]]:11: note: invalid operand for instruction
-# CHECK: :[[@LINE-4]]:11: note: immediate must be a multiple of 8 bytes in the range [0, 248]
+# CHECK: :[[@LINE-3]]:11: note: immediate must be a multiple of 8 bytes in the range [0, 248]
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topperc wrote:

The error here is still wrong. s0 is a GPR from x8 to x15. But I guess its confused because it was parsed as GPRPair for RV32 and tried to check against the RV64 pattern.

https://github.com/llvm/llvm-project/pull/211674