[llvm-branch-commits] [llvm] GlobalISel: Add type size guards in tryCombineMergeLike (PR #213702)
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llvm-branch-commits at lists.llvm.org
Mon Aug 3 08:53:18 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Petar Avramovic (petar-avramovic)
<details>
<summary>Changes</summary>
Bug in LegalizationArtifactCombiner when:
DstSize < UnmergeSrcSize case can create unmerge with one element.
DstSize > UnmergeSrcSize case can end up attempting to create merge
with one source element and hits assert(TmpVec.size() > 1).
---
Patch is 33.21 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/213702.diff
5 Files Affected:
- (modified) llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h (+8-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll (+35-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll (+55-23)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll (+55-23)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir (+222-6)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
index 4a8f5297b66ef..2fc510ebcd522 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -998,6 +998,8 @@ class LegalizationArtifactCombiner {
LLT DstTy = MRI.getType(Dst);
Register UnmergeSrc = Unmerge->getSourceReg();
LLT UnmergeSrcTy = MRI.getType(UnmergeSrc);
+ unsigned DstSize = DstTy.getSizeInBits();
+ unsigned UnmergeSrcSize = UnmergeSrcTy.getSizeInBits();
// Recognize copy of UnmergeSrc to Dst.
// Unmerge UnmergeSrc and reassemble it using merge-like opcode into Dst.
@@ -1006,7 +1008,8 @@ class LegalizationArtifactCombiner {
// %Dst:_(Ty) = G_merge_like_opcode %0:_(EltTy), %1, ...
//
// %Dst:_(Ty) = COPY %UnmergeSrc:_(Ty)
- if ((DstTy == UnmergeSrcTy) && (Elt0UnmergeIdx == 0)) {
+ if ((DstSize == UnmergeSrcSize) && (DstTy == UnmergeSrcTy) &&
+ (Elt0UnmergeIdx == 0)) {
if (!isSequenceFromUnmerge(MI, 0, Unmerge, 0, NumMIElts, EltSize,
/*AllowUndef=*/DstTy.isVector()))
return false;
@@ -1027,7 +1030,8 @@ class LegalizationArtifactCombiner {
// %AnotherDst:_(DstTy) = G_merge_like_opcode %2:_(EltTy), %3
//
// %Dst:_(DstTy), %AnotherDst = G_UNMERGE_VALUES %UnmergeSrc
- if (((!DstTy.isVector() && !UnmergeSrcTy.isVector()) ||
+ if ((DstSize < UnmergeSrcSize) &&
+ ((!DstTy.isVector() && !UnmergeSrcTy.isVector()) ||
(DstTy.isVector() && UnmergeSrcTy.isVector() &&
DstTy.getScalarType() == UnmergeSrcTy.getScalarType())) &&
(Elt0UnmergeIdx % NumMIElts == 0) &&
@@ -1054,7 +1058,8 @@ class LegalizationArtifactCombiner {
//
// %Dst:_(DstTy) = G_merge_like_opcode %UnmergeSrc, %AnotherUnmergeSrc
- if ((DstTy.isVector() == UnmergeSrcTy.isVector()) &&
+ if ((DstSize > UnmergeSrcSize) &&
+ (DstTy.isVector() == UnmergeSrcTy.isVector()) &&
getCoverTy(DstTy, UnmergeSrcTy) == DstTy) {
SmallVector<Register, 4> ConcatSources;
unsigned NumElts = Unmerge->getNumDefs();
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
index e114c99c42548..6eebf814f4fd0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GPRIDX %s
-; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,MOVREL %s
-; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GPRIDX %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu8.03-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,MOVREL %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-mesa-mesa3d -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
define float @dyn_extract_v8f32_const_s_v(i32 %sel) {
; GCN-LABEL: dyn_extract_v8f32_const_s_v:
@@ -4668,3 +4668,34 @@ define i32 @v_extract_v64i32_37(ptr addrspace(1) %ptr) {
%elt = extractelement <64 x i32> %vec, i32 37
ret i32 %elt
}
+
+define amdgpu_gs void @extract_v32i1_bitcast_f32(float %x, ptr addrspace(1) %out) {
+; GPRIDX-LABEL: extract_v32i1_bitcast_f32:
+; GPRIDX: ; %bb.0:
+; GPRIDX-NEXT: v_and_b32_e32 v0, 1, v0
+; GPRIDX-NEXT: global_store_dword v[1:2], v0, off
+; GPRIDX-NEXT: s_endpgm
+;
+; MOVREL-LABEL: extract_v32i1_bitcast_f32:
+; MOVREL: ; %bb.0:
+; MOVREL-NEXT: v_and_b32_e32 v0, 1, v0
+; MOVREL-NEXT: flat_store_dword v[1:2], v0
+; MOVREL-NEXT: s_endpgm
+;
+; GFX10-LABEL: extract_v32i1_bitcast_f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: global_store_dword v[1:2], v0, off
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: extract_v32i1_bitcast_f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: global_store_b32 v[1:2], v0, off
+; GFX11-NEXT: s_endpgm
+ %bc = bitcast float %x to <32 x i1>
+ %e = extractelement <32 x i1> %bc, i64 0
+ %z = zext i1 %e to i32
+ store i32 %z, ptr addrspace(1) %out
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index 1e54d1b362133..6844b698473c7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgpu6.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX6 %s
; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s
-; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
-; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgpu10.10-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
-; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX6-LABEL: s_fshl_i7:
@@ -5160,7 +5160,11 @@ define <3 x half> @v_fshl_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX9-NEXT: v_pk_lshlrev_b16 v1, v2, v1
; GFX9-NEXT: v_pk_lshrrev_b16 v2, 1, v3 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v4, v2
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e64 v2, 16, s4
+; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v0
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fshl_v3i16:
@@ -5177,31 +5181,59 @@ define <3 x half> @v_fshl_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX10-NEXT: v_pk_lshlrev_b16 v0, v4, v0
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v5, v1
; GFX10-NEXT: v_pk_lshrrev_b16 v2, v6, v2
+; GFX10-NEXT: v_lshlrev_b32_e64 v4, 16, s4
; GFX10-NEXT: v_pk_lshrrev_b16 v3, v7, v3
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX10-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
+; GFX10-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fshl_v3i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4
-; GFX11-NEXT: v_xor_b32_e32 v7, -1, v5
-; GFX11-NEXT: v_and_b32_e32 v4, 0xf000f, v4
-; GFX11-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
-; GFX11-NEXT: v_and_b32_e32 v5, 0xf000f, v5
-; GFX11-NEXT: v_and_b32_e32 v6, 0xf000f, v6
-; GFX11-NEXT: v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1]
-; GFX11-NEXT: v_and_b32_e32 v7, 0xf000f, v7
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, v4, v0
-; GFX11-NEXT: v_pk_lshlrev_b16 v1, v5, v1
-; GFX11-NEXT: v_pk_lshrrev_b16 v2, v6, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_pk_lshrrev_b16 v3, v7, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_fshl_v3i16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v6, -1, v4
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v7, -1, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xf000f, v4
+; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xf000f, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xf000f, v6
+; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xf000f, v7
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, v4, v0
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, v5, v1
+; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v2, v6, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v3, v7, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fshl_v3i16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v6, -1, v5
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v7, -1, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xf000f, v5
+; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xf000f, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xf000f, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xf000f, v7
+; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v3, v6, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v2, v7, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i16> @llvm.fshl.v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
%cast.result = bitcast <3 x i16> %result to <3 x half>
ret <3 x half> %cast.result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 82dd5756972ca..11b62d825c965 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgpu6.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX6 %s
; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s
-; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
-; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgpu10.10-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
-; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX6-LABEL: s_fshr_i7:
@@ -4866,7 +4866,11 @@ define <3 x half> @v_fshr_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX9-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_lshlrev_b16 v1, v4, v1
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v2, v3
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e64 v2, 16, s4
+; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v0
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fshr_v3i16:
@@ -4883,31 +4887,59 @@ define <3 x half> @v_fshr_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX10-NEXT: v_pk_lshrrev_b16 v2, v4, v2
; GFX10-NEXT: v_pk_lshrrev_b16 v3, v5, v3
; GFX10-NEXT: v_pk_lshlrev_b16 v0, v6, v0
+; GFX10-NEXT: v_lshlrev_b32_e64 v4, 16, s4
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v7, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX10-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
+; GFX10-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fshr_v3i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4
-; GFX11-NEXT: v_xor_b32_e32 v7, -1, v5
-; GFX11-NEXT: v_and_b32_e32 v4, 0xf000f, v4
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
-; GFX11-NEXT: v_and_b32_e32 v5, 0xf000f, v5
-; GFX11-NEXT: v_and_b32_e32 v6, 0xf000f, v6
-; GFX11-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
-; GFX11-NEXT: v_and_b32_e32 v7, 0xf000f, v7
-; GFX11-NEXT: v_pk_lshrrev_b16 v2, v4, v2
-; GFX11-NEXT: v_pk_lshrrev_b16 v3, v5, v3
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, v6, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_pk_lshlrev_b16 v1, v7, v1
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_fshr_v3i16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v6, -1, v4
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v7, -1, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xf000f, v4
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xf000f, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xf000f, v6
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xf000f, v7
+; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v2, v4, v2
+; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v3, v5, v3
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, v6, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, v7, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fshr_v3i16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v6, -1, v5
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v7, -1, v4
+; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xf000f, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xf000f, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xf000f, v6
+; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xf000f, v7
+; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v3, v5, v3
+; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v2, v4, v2
+; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v1, v6, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v0, v7, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i16> @llvm.fshr.v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
%cast.result = bitcast <3 x i16> %result to <3 x half>
ret <3 x half> %cast.result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
index bfe447daf8560..bba06a67d305f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
@@ -1443,12 +1443,228 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](f32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[UV]], [[C]](i32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C1]]
- ; CHECK-NEXT: $vgpr0 = COPY [[AND]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C]](f32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C1]](f32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C2]](f32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(f32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C3]](f32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C4]](f32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(f32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C5]](f32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C6]](f32)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C7]](f32)
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(f32) = G_CONSTANT i32 9
+ ; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C8]](f32)
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(f32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[LSHR9:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C9]](f32)
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(f32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[LSHR10:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C10]](f32)
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(f32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[LSHR11:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C11]](f32)
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(f32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[LSHR12:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C12]](f32)
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(f32) = G_CONSTANT i32 14
+ ; CHECK-NEXT: [[LSHR...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/213702
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