[llvm-branch-commits] [llvm] GlobalISel: Fix floating point unmerge lowering (PR #213703)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Aug 3 08:53:17 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Petar Avramovic (petar-avramovic)
<details>
<summary>Changes</summary>
Bitcast to integer and use integer type for bit twiddling.
---
Patch is 42.81 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/213703.diff
4 Files Affected:
- (modified) llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (+5-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll (+332-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir (+126-188)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir (+5-4)
``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 65d71a481dbdc..87a3ea5bdea59 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -2141,11 +2141,15 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
Register LegalizerHelper::coerceToInteger(Register Val) {
LLT Ty = MRI.getType(Val);
- if (Ty.isScalar())
+ if (Ty.isScalar() && !Ty.isFloat())
return Val;
const DataLayout &DL = MIRBuilder.getDataLayout();
LLT NewTy = LLT::integer(Ty.getSizeInBits());
+
+ if (Ty.isFloat())
+ return MIRBuilder.buildBitcast(NewTy, Val).getReg(0);
+
if (Ty.isPointer()) {
if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace()))
return Register();
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
index 6eebf814f4fd0..bff28f14bbfa5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GPRIDX %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu8.03-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,MOVREL %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-mesa-mesa3d -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
+; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GPRIDX %s
+; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,MOVREL %s
+; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
define float @dyn_extract_v8f32_const_s_v(i32 %sel) {
; GCN-LABEL: dyn_extract_v8f32_const_s_v:
@@ -4672,24 +4672,352 @@ define i32 @v_extract_v64i32_37(ptr addrspace(1) %ptr) {
define amdgpu_gs void @extract_v32i1_bitcast_f32(float %x, ptr addrspace(1) %out) {
; GPRIDX-LABEL: extract_v32i1_bitcast_f32:
; GPRIDX: ; %bb.0:
+; GPRIDX-NEXT: v_bfe_u32 v4, v0, 1, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v4, 1, v4
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 2, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 3, 1
+; GPRIDX-NEXT: v_and_or_b32 v4, v0, 1, v4
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 2, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 3, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 4, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 5, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 4, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 5, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 6, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 7, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 6, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 7, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 8, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 9, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 9, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 10, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 11, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 10, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 11, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 12, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 13, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 12, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 13, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 14, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 15, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 14, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 15, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 17, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 17, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 18, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 19, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 18, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 19, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 20, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 21, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 20, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 21, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 22, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 23, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 22, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 23, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 24, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 25, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 24, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 25, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 26, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 27, 1
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 26, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 27, v6
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_bfe_u32 v5, v0, 28, 1
+; GPRIDX-NEXT: v_bfe_u32 v6, v0, 29, 1
+; GPRIDX-NEXT: v_lshrrev_b32_e32 v3, 31, v0
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v5, 28, v5
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v6, 29, v6
+; GPRIDX-NEXT: v_bfe_u32 v0, v0, 30, 1
+; GPRIDX-NEXT: v_or3_b32 v4, v4, v5, v6
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v0, 30, v0
+; GPRIDX-NEXT: v_lshlrev_b32_e32 v3, 31, v3
+; GPRIDX-NEXT: v_or3_b32 v0, v4, v0, v3
; GPRIDX-NEXT: v_and_b32_e32 v0, 1, v0
; GPRIDX-NEXT: global_store_dword v[1:2], v0, off
; GPRIDX-NEXT: s_endpgm
;
; MOVREL-LABEL: extract_v32i1_bitcast_f32:
; MOVREL: ; %bb.0:
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 1, 1
+; MOVREL-NEXT: v_and_b32_e32 v4, 1, v0
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 1, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 2, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 2, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 3, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 3, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 4, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 4, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 5, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 5, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 6, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 6, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 7, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 7, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 8, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 9, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 9, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 10, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 10, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 11, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 11, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 12, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 12, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 13, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 13, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 14, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 14, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 15, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 15, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 16, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 17, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 17, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 18, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 18, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 19, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 19, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 20, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 20, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 21, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 21, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 22, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 22, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 23, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 23, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 24, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 24, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 25, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 25, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 26, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 26, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 27, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 27, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 28, 1
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 28, v5
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_bfe_u32 v5, v0, 29, 1
+; MOVREL-NEXT: v_lshrrev_b32_e32 v3, 31, v0
+; MOVREL-NEXT: v_lshlrev_b32_e32 v5, 29, v5
+; MOVREL-NEXT: v_bfe_u32 v0, v0, 30, 1
+; MOVREL-NEXT: v_or_b32_e32 v4, v4, v5
+; MOVREL-NEXT: v_lshlrev_b32_e32 v0, 30, v0
+; MOVREL-NEXT: v_or_b32_e32 v0, v4, v0
+; MOVREL-NEXT: v_lshlrev_b32_e32 v3, 31, v3
+; MOVREL-NEXT: v_or_b32_e32 v0, v0, v3
; MOVREL-NEXT: v_and_b32_e32 v0, 1, v0
; MOVREL-NEXT: flat_store_dword v[1:2], v0
; MOVREL-NEXT: s_endpgm
;
; GFX10-LABEL: extract_v32i1_bitcast_f32:
; GFX10: ; %bb.0:
+; GFX10-NEXT: v_bfe_u32 v3, v0, 1, 1
+; GFX10-NEXT: v_bfe_u32 v4, v0, 2, 1
+; GFX10-NEXT: v_bfe_u32 v5, v0, 3, 1
+; GFX10-NEXT: v_bfe_u32 v6, v0, 4, 1
+; GFX10-NEXT: v_bfe_u32 v7, v0, 5, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 1, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 2, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 3, v5
+; GFX10-NEXT: v_bfe_u32 v8, v0, 6, 1
+; GFX10-NEXT: v_bfe_u32 v9, v0, 7, 1
+; GFX10-NEXT: v_and_or_b32 v3, v0, 1, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 4, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 5, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v8, 6, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 7, v9
+; GFX10-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX10-NEXT: v_bfe_u32 v4, v0, 8, 1
+; GFX10-NEXT: v_bfe_u32 v5, v0, 9, 1
+; GFX10-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX10-NEXT: v_bfe_u32 v6, v0, 10, 1
+; GFX10-NEXT: v_bfe_u32 v7, v0, 11, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 9, v5
+; GFX10-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX10-NEXT: v_bfe_u32 v8, v0, 12, 1
+; GFX10-NEXT: v_bfe_u32 v9, v0, 13, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 10, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 11, v7
+; GFX10-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX10-NEXT: v_bfe_u32 v4, v0, 14, 1
+; GFX10-NEXT: v_bfe_u32 v5, v0, 15, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v8, 12, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 13, v9
+; GFX10-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX10-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX10-NEXT: v_bfe_u32 v7, v0, 17, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 14, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 15, v5
+; GFX10-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX10-NEXT: v_bfe_u32 v8, v0, 18, 1
+; GFX10-NEXT: v_bfe_u32 v9, v0, 19, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 17, v7
+; GFX10-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX10-NEXT: v_bfe_u32 v4, v0, 20, 1
+; GFX10-NEXT: v_bfe_u32 v5, v0, 21, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v8, 18, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 19, v9
+; GFX10-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX10-NEXT: v_bfe_u32 v6, v0, 22, 1
+; GFX10-NEXT: v_bfe_u32 v7, v0, 23, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 20, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 21, v5
+; GFX10-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX10-NEXT: v_bfe_u32 v8, v0, 24, 1
+; GFX10-NEXT: v_bfe_u32 v9, v0, 25, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 22, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 23, v7
+; GFX10-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX10-NEXT: v_bfe_u32 v4, v0, 26, 1
+; GFX10-NEXT: v_bfe_u32 v5, v0, 27, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 25, v9
+; GFX10-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX10-NEXT: v_bfe_u32 v6, v0, 28, 1
+; GFX10-NEXT: v_bfe_u32 v7, v0, 29, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 26, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 27, v5
+; GFX10-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX10-NEXT: v_bfe_u32 v8, v0, 30, 1
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 28, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 29, v7
+; GFX10-NEXT: v_lshrrev_b32_e32 v0, 31, v0
+; GFX10-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 30, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 31, v0
+; GFX10-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX10-NEXT: v_or3_b32 v0, v3, v4, v0
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: global_store_dword v[1:2], v0, off
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: extract_v32i1_bitcast_f32:
; GFX11: ; %bb.0:
+; GFX11-NEXT: v_bfe_u32 v3, v0, 1, 1
+; GFX11-NEXT: v_bfe_u32 v4, v0, 2, 1
+; GFX11-NEXT: v_bfe_u32 v5, v0, 3, 1
+; GFX11-NEXT: v_bfe_u32 v6, v0, 4, 1
+; GFX11-NEXT: v_bfe_u32 v7, v0, 5, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 1, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 2, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 3, v5
+; GFX11-NEXT: v_bfe_u32 v8, v0, 6, 1
+; GFX11-NEXT: v_bfe_u32 v9, v0, 7, 1
+; GFX11-NEXT: v_and_or_b32 v3, v0, 1, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 4, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 5, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 6, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 7, v9
+; GFX11-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX11-NEXT: v_bfe_u32 v4, v0, 8, 1
+; GFX11-NEXT: v_bfe_u32 v5, v0, 9, 1
+; GFX11-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX11-NEXT: v_bfe_u32 v6, v0, 10, 1
+; GFX11-NEXT: v_bfe_u32 v7, v0, 11, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 9, v5
+; GFX11-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX11-NEXT: v_bfe_u32 v8, v0, 12, 1
+; GFX11-NEXT: v_bfe_u32 v9, v0, 13, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 10, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 11, v7
+; GFX11-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX11-NEXT: v_bfe_u32 v4, v0, 14, 1
+; GFX11-NEXT: v_bfe_u32 v5, v0, 15, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 12, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 13, v9
+; GFX11-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX11-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-NEXT: v_bfe_u32 v7, v0, 17, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 14, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 15, v5
+; GFX11-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX11-NEXT: v_bfe_u32 v8, v0, 18, 1
+; GFX11-NEXT: v_bfe_u32 v9, v0, 19, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 17, v7
+; GFX11-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX11-NEXT: v_bfe_u32 v4, v0, 20, 1
+; GFX11-NEXT: v_bfe_u32 v5, v0, 21, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 18, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 19, v9
+; GFX11-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX11-NEXT: v_bfe_u32 v6, v0, 22, 1
+; GFX11-NEXT: v_bfe_u32 v7, v0, 23, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 20, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 21, v5
+; GFX11-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX11-NEXT: v_bfe_u32 v8, v0, 24, 1
+; GFX11-NEXT: v_bfe_u32 v9, v0, 25, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 22, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 23, v7
+; GFX11-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX11-NEXT: v_bfe_u32 v4, v0, 26, 1
+; GFX11-NEXT: v_bfe_u32 v5, v0, 27, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 24, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 25, v9
+; GFX11-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX11-NEXT: v_bfe_u32 v6, v0, 28, 1
+; GFX11-NEXT: v_bfe_u32 v7, v0, 29, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 26, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 27, v5
+; GFX11-NEXT: v_or3_b32 v3, v3, v8, v9
+; GFX11-NEXT: v_bfe_u32 v8, v0, 30, 1
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 28, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 29, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 31, v0
+; GFX11-NEXT: v_or3_b32 v3, v3, v4, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 30, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 31, v0
+; GFX11-NEXT: v_or3_b32 v3, v3, v6, v7
+; GFX11-NEXT: v_or3_b32 v0, v3, v4, v0
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-NEXT: global_store_b32 v[1:2], v0, off
; GFX11-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
index bba06a67d305f..ea6d7739874bd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
@@ -1443,227 +1443,165 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C]](f32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_CONSTANT i32 2
- ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C1]](f32)
- ; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_CONSTANT i32 3
- ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C2]](f32)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(f32) = G_CONSTANT i32 4
- ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C3]](f32)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f32) = G_CONSTANT i32 5
- ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C4]](f32)
- ; CHECK-NEXT: [[C5:%[0-9]+]]:_(f32) = G_CONSTANT i32 6
- ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C5]](f32)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_CONSTANT i32 7
- ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C6]](f32)
- ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C7]](f32)
- ; CHECK-NEXT: [[C8:%[0-9]+]]:_(f32) = G_CONSTANT i32 9
- ; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C8]](f32)
- ; CHECK-NEXT: [[C9:%[0-9]+]]:_(f32) = G_CONSTANT i32 10
- ; CHECK-NEXT: [[LSHR9:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C9]](f32)
- ; CHECK-NEXT: [[C10:%[0-9]+]]:_(f32) = G_CONSTANT i32 11
- ; CHECK-NEXT: [[LSHR10:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C10]](f32)
- ; CHECK-NEXT: [[C11:%[0-9]+]]:_(f32) = G_CONSTANT i32 12
- ; CHECK-NEXT: [[LSHR11:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C11]](f32)
- ; CHECK-NEXT: [[C12:%[0-9]+]]:_(f32) = G_CONSTANT i32 13
- ; CHECK-NEXT: [[LSHR12:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C12]](f32)
- ; CHECK-NEXT: [[C13:%[0-9]+]]:_(f32) = G_CONSTANT i32 14
- ; CHECK-NEXT: [[LSHR13:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C13]](f32)
- ; CHECK-NEXT: [[C14:%[0-9]+]]:_(f32) = G_CONSTANT i32 15
- ; CHECK-NEXT: [[LSHR14:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C14]](f32)
- ; CHECK-NEXT: [[C15:%[0-9]+]]:_(f32) = G_CONSTANT i32 16
- ; CHECK-NEXT: [[LSHR15:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C15]...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/213703
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