[llvm-branch-commits] [llvm] GlobalISel: Add type size guards in tryCombineMergeLike (PR #213702)
Petar Avramovic via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Aug 3 08:47:01 PDT 2026
https://github.com/petar-avramovic created https://github.com/llvm/llvm-project/pull/213702
Bug in LegalizationArtifactCombiner when:
DstSize < UnmergeSrcSize case can create unmerge with one element.
DstSize > UnmergeSrcSize case can end up attempting to create merge
with one source element and hits assert(TmpVec.size() > 1).
>From e7b958fb71a2e3277b488fc2a4a197e9140942de Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Mon, 3 Aug 2026 17:37:13 +0200
Subject: [PATCH] GlobalISel: Add type size guards in tryCombineMergeLike
Bug in LegalizationArtifactCombiner when:
DstSize < UnmergeSrcSize case can create unmerge with one element.
DstSize > UnmergeSrcSize case can end up attempting to create merge
with one source element and hits assert(TmpVec.size() > 1).
---
.../GlobalISel/LegalizationArtifactCombiner.h | 11 +-
.../AMDGPU/GlobalISel/extractelement.ll | 39 ++-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll | 78 ++++--
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll | 78 ++++--
.../legalize-extract-vector-elt.mir | 228 +++++++++++++++++-
5 files changed, 375 insertions(+), 59 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
index 4a8f5297b66ef..2fc510ebcd522 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -998,6 +998,8 @@ class LegalizationArtifactCombiner {
LLT DstTy = MRI.getType(Dst);
Register UnmergeSrc = Unmerge->getSourceReg();
LLT UnmergeSrcTy = MRI.getType(UnmergeSrc);
+ unsigned DstSize = DstTy.getSizeInBits();
+ unsigned UnmergeSrcSize = UnmergeSrcTy.getSizeInBits();
// Recognize copy of UnmergeSrc to Dst.
// Unmerge UnmergeSrc and reassemble it using merge-like opcode into Dst.
@@ -1006,7 +1008,8 @@ class LegalizationArtifactCombiner {
// %Dst:_(Ty) = G_merge_like_opcode %0:_(EltTy), %1, ...
//
// %Dst:_(Ty) = COPY %UnmergeSrc:_(Ty)
- if ((DstTy == UnmergeSrcTy) && (Elt0UnmergeIdx == 0)) {
+ if ((DstSize == UnmergeSrcSize) && (DstTy == UnmergeSrcTy) &&
+ (Elt0UnmergeIdx == 0)) {
if (!isSequenceFromUnmerge(MI, 0, Unmerge, 0, NumMIElts, EltSize,
/*AllowUndef=*/DstTy.isVector()))
return false;
@@ -1027,7 +1030,8 @@ class LegalizationArtifactCombiner {
// %AnotherDst:_(DstTy) = G_merge_like_opcode %2:_(EltTy), %3
//
// %Dst:_(DstTy), %AnotherDst = G_UNMERGE_VALUES %UnmergeSrc
- if (((!DstTy.isVector() && !UnmergeSrcTy.isVector()) ||
+ if ((DstSize < UnmergeSrcSize) &&
+ ((!DstTy.isVector() && !UnmergeSrcTy.isVector()) ||
(DstTy.isVector() && UnmergeSrcTy.isVector() &&
DstTy.getScalarType() == UnmergeSrcTy.getScalarType())) &&
(Elt0UnmergeIdx % NumMIElts == 0) &&
@@ -1054,7 +1058,8 @@ class LegalizationArtifactCombiner {
//
// %Dst:_(DstTy) = G_merge_like_opcode %UnmergeSrc, %AnotherUnmergeSrc
- if ((DstTy.isVector() == UnmergeSrcTy.isVector()) &&
+ if ((DstSize > UnmergeSrcSize) &&
+ (DstTy.isVector() == UnmergeSrcTy.isVector()) &&
getCoverTy(DstTy, UnmergeSrcTy) == DstTy) {
SmallVector<Register, 4> ConcatSources;
unsigned NumElts = Unmerge->getNumDefs();
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
index e114c99c42548..6eebf814f4fd0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GPRIDX %s
-; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,MOVREL %s
-; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GPRIDX %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu8.03-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,MOVREL %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-mesa-mesa3d -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
define float @dyn_extract_v8f32_const_s_v(i32 %sel) {
; GCN-LABEL: dyn_extract_v8f32_const_s_v:
@@ -4668,3 +4668,34 @@ define i32 @v_extract_v64i32_37(ptr addrspace(1) %ptr) {
%elt = extractelement <64 x i32> %vec, i32 37
ret i32 %elt
}
+
+define amdgpu_gs void @extract_v32i1_bitcast_f32(float %x, ptr addrspace(1) %out) {
+; GPRIDX-LABEL: extract_v32i1_bitcast_f32:
+; GPRIDX: ; %bb.0:
+; GPRIDX-NEXT: v_and_b32_e32 v0, 1, v0
+; GPRIDX-NEXT: global_store_dword v[1:2], v0, off
+; GPRIDX-NEXT: s_endpgm
+;
+; MOVREL-LABEL: extract_v32i1_bitcast_f32:
+; MOVREL: ; %bb.0:
+; MOVREL-NEXT: v_and_b32_e32 v0, 1, v0
+; MOVREL-NEXT: flat_store_dword v[1:2], v0
+; MOVREL-NEXT: s_endpgm
+;
+; GFX10-LABEL: extract_v32i1_bitcast_f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: global_store_dword v[1:2], v0, off
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: extract_v32i1_bitcast_f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: global_store_b32 v[1:2], v0, off
+; GFX11-NEXT: s_endpgm
+ %bc = bitcast float %x to <32 x i1>
+ %e = extractelement <32 x i1> %bc, i64 0
+ %z = zext i1 %e to i32
+ store i32 %z, ptr addrspace(1) %out
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index 1e54d1b362133..6844b698473c7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgpu6.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX6 %s
; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s
-; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
-; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgpu10.10-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
-; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX6-LABEL: s_fshl_i7:
@@ -5160,7 +5160,11 @@ define <3 x half> @v_fshl_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX9-NEXT: v_pk_lshlrev_b16 v1, v2, v1
; GFX9-NEXT: v_pk_lshrrev_b16 v2, 1, v3 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v4, v2
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e64 v2, 16, s4
+; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v0
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fshl_v3i16:
@@ -5177,31 +5181,59 @@ define <3 x half> @v_fshl_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX10-NEXT: v_pk_lshlrev_b16 v0, v4, v0
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v5, v1
; GFX10-NEXT: v_pk_lshrrev_b16 v2, v6, v2
+; GFX10-NEXT: v_lshlrev_b32_e64 v4, 16, s4
; GFX10-NEXT: v_pk_lshrrev_b16 v3, v7, v3
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX10-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
+; GFX10-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fshl_v3i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4
-; GFX11-NEXT: v_xor_b32_e32 v7, -1, v5
-; GFX11-NEXT: v_and_b32_e32 v4, 0xf000f, v4
-; GFX11-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
-; GFX11-NEXT: v_and_b32_e32 v5, 0xf000f, v5
-; GFX11-NEXT: v_and_b32_e32 v6, 0xf000f, v6
-; GFX11-NEXT: v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1]
-; GFX11-NEXT: v_and_b32_e32 v7, 0xf000f, v7
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, v4, v0
-; GFX11-NEXT: v_pk_lshlrev_b16 v1, v5, v1
-; GFX11-NEXT: v_pk_lshrrev_b16 v2, v6, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_pk_lshrrev_b16 v3, v7, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_fshl_v3i16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v6, -1, v4
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v7, -1, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xf000f, v4
+; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xf000f, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xf000f, v6
+; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xf000f, v7
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, v4, v0
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, v5, v1
+; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v2, v6, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v3, v7, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fshl_v3i16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v6, -1, v5
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v7, -1, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xf000f, v5
+; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v3, 1, v3 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xf000f, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xf000f, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xf000f, v7
+; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v2, 1, v2 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v3, v6, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v2, v7, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i16> @llvm.fshl.v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
%cast.result = bitcast <3 x i16> %result to <3 x half>
ret <3 x half> %cast.result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 82dd5756972ca..11b62d825c965 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgpu6.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX6 %s
; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX8 %s
-; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
-; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgpu10.10-amd-amdpal -o - %s | FileCheck -check-prefixes=GCN,GFX10 %s
; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
-; xUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX6-LABEL: s_fshr_i7:
@@ -4866,7 +4866,11 @@ define <3 x half> @v_fshr_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX9-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_lshlrev_b16 v1, v4, v1
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v2, v3
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e64 v2, 16, s4
+; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v0
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fshr_v3i16:
@@ -4883,31 +4887,59 @@ define <3 x half> @v_fshr_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX10-NEXT: v_pk_lshrrev_b16 v2, v4, v2
; GFX10-NEXT: v_pk_lshrrev_b16 v3, v5, v3
; GFX10-NEXT: v_pk_lshlrev_b16 v0, v6, v0
+; GFX10-NEXT: v_lshlrev_b32_e64 v4, 16, s4
; GFX10-NEXT: v_pk_lshlrev_b16 v1, v7, v1
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX10-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
+; GFX10-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fshr_v3i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4
-; GFX11-NEXT: v_xor_b32_e32 v7, -1, v5
-; GFX11-NEXT: v_and_b32_e32 v4, 0xf000f, v4
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
-; GFX11-NEXT: v_and_b32_e32 v5, 0xf000f, v5
-; GFX11-NEXT: v_and_b32_e32 v6, 0xf000f, v6
-; GFX11-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
-; GFX11-NEXT: v_and_b32_e32 v7, 0xf000f, v7
-; GFX11-NEXT: v_pk_lshrrev_b16 v2, v4, v2
-; GFX11-NEXT: v_pk_lshrrev_b16 v3, v5, v3
-; GFX11-NEXT: v_pk_lshlrev_b16 v0, v6, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_pk_lshlrev_b16 v1, v7, v1
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_fshr_v3i16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v6, -1, v4
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v7, -1, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xf000f, v4
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xf000f, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xf000f, v6
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xf000f, v7
+; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v2, v4, v2
+; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v3, v5, v3
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, v6, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, v7, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: v_fshr_v3i16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v6, -1, v5
+; GFX11-FAKE16-NEXT: v_xor_b32_e32 v7, -1, v4
+; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v1, 1, v1 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xf000f, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xf000f, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xf000f, v6
+; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xf000f, v7
+; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v3, v5, v3
+; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v2, v4, v2
+; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v1, v6, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v0, v7, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i16> @llvm.fshr.v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
%cast.result = bitcast <3 x i16> %result to <3 x half>
ret <3 x half> %cast.result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
index bfe447daf8560..bba06a67d305f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
@@ -1443,12 +1443,228 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](f32)
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[UV]], [[C]](i32)
- ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C1]]
- ; CHECK-NEXT: $vgpr0 = COPY [[AND]](i32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C]](f32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(f32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C1]](f32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(f32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C2]](f32)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(f32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C3]](f32)
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(f32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C4]](f32)
+ ; CHECK-NEXT: [[C5:%[0-9]+]]:_(f32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C5]](f32)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(f32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C6]](f32)
+ ; CHECK-NEXT: [[C7:%[0-9]+]]:_(f32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C7]](f32)
+ ; CHECK-NEXT: [[C8:%[0-9]+]]:_(f32) = G_CONSTANT i32 9
+ ; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C8]](f32)
+ ; CHECK-NEXT: [[C9:%[0-9]+]]:_(f32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[LSHR9:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C9]](f32)
+ ; CHECK-NEXT: [[C10:%[0-9]+]]:_(f32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[LSHR10:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C10]](f32)
+ ; CHECK-NEXT: [[C11:%[0-9]+]]:_(f32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[LSHR11:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C11]](f32)
+ ; CHECK-NEXT: [[C12:%[0-9]+]]:_(f32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[LSHR12:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C12]](f32)
+ ; CHECK-NEXT: [[C13:%[0-9]+]]:_(f32) = G_CONSTANT i32 14
+ ; CHECK-NEXT: [[LSHR13:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C13]](f32)
+ ; CHECK-NEXT: [[C14:%[0-9]+]]:_(f32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[LSHR14:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C14]](f32)
+ ; CHECK-NEXT: [[C15:%[0-9]+]]:_(f32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[LSHR15:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C15]](f32)
+ ; CHECK-NEXT: [[C16:%[0-9]+]]:_(f32) = G_CONSTANT i32 17
+ ; CHECK-NEXT: [[LSHR16:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C16]](f32)
+ ; CHECK-NEXT: [[C17:%[0-9]+]]:_(f32) = G_CONSTANT i32 18
+ ; CHECK-NEXT: [[LSHR17:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C17]](f32)
+ ; CHECK-NEXT: [[C18:%[0-9]+]]:_(f32) = G_CONSTANT i32 19
+ ; CHECK-NEXT: [[LSHR18:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C18]](f32)
+ ; CHECK-NEXT: [[C19:%[0-9]+]]:_(f32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[LSHR19:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C19]](f32)
+ ; CHECK-NEXT: [[C20:%[0-9]+]]:_(f32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[LSHR20:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C20]](f32)
+ ; CHECK-NEXT: [[C21:%[0-9]+]]:_(f32) = G_CONSTANT i32 22
+ ; CHECK-NEXT: [[LSHR21:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C21]](f32)
+ ; CHECK-NEXT: [[C22:%[0-9]+]]:_(f32) = G_CONSTANT i32 23
+ ; CHECK-NEXT: [[LSHR22:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C22]](f32)
+ ; CHECK-NEXT: [[C23:%[0-9]+]]:_(f32) = G_CONSTANT i32 24
+ ; CHECK-NEXT: [[LSHR23:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C23]](f32)
+ ; CHECK-NEXT: [[C24:%[0-9]+]]:_(f32) = G_CONSTANT i32 25
+ ; CHECK-NEXT: [[LSHR24:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C24]](f32)
+ ; CHECK-NEXT: [[C25:%[0-9]+]]:_(f32) = G_CONSTANT i32 26
+ ; CHECK-NEXT: [[LSHR25:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C25]](f32)
+ ; CHECK-NEXT: [[C26:%[0-9]+]]:_(f32) = G_CONSTANT i32 27
+ ; CHECK-NEXT: [[LSHR26:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C26]](f32)
+ ; CHECK-NEXT: [[C27:%[0-9]+]]:_(f32) = G_CONSTANT i32 28
+ ; CHECK-NEXT: [[LSHR27:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C27]](f32)
+ ; CHECK-NEXT: [[C28:%[0-9]+]]:_(f32) = G_CONSTANT i32 29
+ ; CHECK-NEXT: [[LSHR28:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C28]](f32)
+ ; CHECK-NEXT: [[C29:%[0-9]+]]:_(f32) = G_CONSTANT i32 30
+ ; CHECK-NEXT: [[LSHR29:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C29]](f32)
+ ; CHECK-NEXT: [[C30:%[0-9]+]]:_(f32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[LSHR30:%[0-9]+]]:_(f32) = G_LSHR [[COPY]], [[C30]](f32)
+ ; CHECK-NEXT: [[C31:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY [[COPY]](f32)
+ ; CHECK-NEXT: [[C32:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[COPY1]], [[C32]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY [[LSHR]](f32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[COPY2]], [[C32]]
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[AND1]], [[C32]](i32)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND]], [[SHL]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY [[LSHR1]](f32)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[COPY3]], [[C32]]
+ ; CHECK-NEXT: [[C33:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+ ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[AND2]], [[C33]](i32)
+ ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY [[LSHR2]](f32)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[COPY4]], [[C32]]
+ ; CHECK-NEXT: [[C34:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+ ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[AND3]], [[C34]](i32)
+ ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[OR1]], [[SHL2]]
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY [[LSHR3]](f32)
+ ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[COPY5]], [[C32]]
+ ; CHECK-NEXT: [[C35:%[0-9]+]]:_(i32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[AND4]], [[C35]](i32)
+ ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[OR2]], [[SHL3]]
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY [[LSHR4]](f32)
+ ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[COPY6]], [[C32]]
+ ; CHECK-NEXT: [[C36:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+ ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND5]], [[C36]](i32)
+ ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[OR3]], [[SHL4]]
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY [[LSHR5]](f32)
+ ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[COPY7]], [[C32]]
+ ; CHECK-NEXT: [[C37:%[0-9]+]]:_(i32) = G_CONSTANT i32 6
+ ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(i32) = G_SHL [[AND6]], [[C37]](i32)
+ ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[OR4]], [[SHL5]]
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY [[LSHR6]](f32)
+ ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i32) = G_AND [[COPY8]], [[C32]]
+ ; CHECK-NEXT: [[C38:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
+ ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(i32) = G_SHL [[AND7]], [[C38]](i32)
+ ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(i32) = G_OR [[OR5]], [[SHL6]]
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY [[LSHR7]](f32)
+ ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(i32) = G_AND [[COPY9]], [[C32]]
+ ; CHECK-NEXT: [[C39:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(i32) = G_SHL [[AND8]], [[C39]](i32)
+ ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(i32) = G_OR [[OR6]], [[SHL7]]
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY [[LSHR8]](f32)
+ ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(i32) = G_AND [[COPY10]], [[C32]]
+ ; CHECK-NEXT: [[C40:%[0-9]+]]:_(i32) = G_CONSTANT i32 9
+ ; CHECK-NEXT: [[SHL8:%[0-9]+]]:_(i32) = G_SHL [[AND9]], [[C40]](i32)
+ ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(i32) = G_OR [[OR7]], [[SHL8]]
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY [[LSHR9]](f32)
+ ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(i32) = G_AND [[COPY11]], [[C32]]
+ ; CHECK-NEXT: [[C41:%[0-9]+]]:_(i32) = G_CONSTANT i32 10
+ ; CHECK-NEXT: [[SHL9:%[0-9]+]]:_(i32) = G_SHL [[AND10]], [[C41]](i32)
+ ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(i32) = G_OR [[OR8]], [[SHL9]]
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY [[LSHR10]](f32)
+ ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(i32) = G_AND [[COPY12]], [[C32]]
+ ; CHECK-NEXT: [[C42:%[0-9]+]]:_(i32) = G_CONSTANT i32 11
+ ; CHECK-NEXT: [[SHL10:%[0-9]+]]:_(i32) = G_SHL [[AND11]], [[C42]](i32)
+ ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(i32) = G_OR [[OR9]], [[SHL10]]
+ ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY [[LSHR11]](f32)
+ ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(i32) = G_AND [[COPY13]], [[C32]]
+ ; CHECK-NEXT: [[C43:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: [[SHL11:%[0-9]+]]:_(i32) = G_SHL [[AND12]], [[C43]](i32)
+ ; CHECK-NEXT: [[OR11:%[0-9]+]]:_(i32) = G_OR [[OR10]], [[SHL11]]
+ ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(i32) = COPY [[LSHR12]](f32)
+ ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(i32) = G_AND [[COPY14]], [[C32]]
+ ; CHECK-NEXT: [[C44:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
+ ; CHECK-NEXT: [[SHL12:%[0-9]+]]:_(i32) = G_SHL [[AND13]], [[C44]](i32)
+ ; CHECK-NEXT: [[OR12:%[0-9]+]]:_(i32) = G_OR [[OR11]], [[SHL12]]
+ ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(i32) = COPY [[LSHR13]](f32)
+ ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(i32) = G_AND [[COPY15]], [[C32]]
+ ; CHECK-NEXT: [[C45:%[0-9]+]]:_(i32) = G_CONSTANT i32 14
+ ; CHECK-NEXT: [[SHL13:%[0-9]+]]:_(i32) = G_SHL [[AND14]], [[C45]](i32)
+ ; CHECK-NEXT: [[OR13:%[0-9]+]]:_(i32) = G_OR [[OR12]], [[SHL13]]
+ ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(i32) = COPY [[LSHR14]](f32)
+ ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(i32) = G_AND [[COPY16]], [[C32]]
+ ; CHECK-NEXT: [[C46:%[0-9]+]]:_(i32) = G_CONSTANT i32 15
+ ; CHECK-NEXT: [[SHL14:%[0-9]+]]:_(i32) = G_SHL [[AND15]], [[C46]](i32)
+ ; CHECK-NEXT: [[OR14:%[0-9]+]]:_(i32) = G_OR [[OR13]], [[SHL14]]
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(i32) = COPY [[LSHR15]](f32)
+ ; CHECK-NEXT: [[AND16:%[0-9]+]]:_(i32) = G_AND [[COPY17]], [[C32]]
+ ; CHECK-NEXT: [[C47:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+ ; CHECK-NEXT: [[SHL15:%[0-9]+]]:_(i32) = G_SHL [[AND16]], [[C47]](i32)
+ ; CHECK-NEXT: [[OR15:%[0-9]+]]:_(i32) = G_OR [[OR14]], [[SHL15]]
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(i32) = COPY [[LSHR16]](f32)
+ ; CHECK-NEXT: [[AND17:%[0-9]+]]:_(i32) = G_AND [[COPY18]], [[C32]]
+ ; CHECK-NEXT: [[C48:%[0-9]+]]:_(i32) = G_CONSTANT i32 17
+ ; CHECK-NEXT: [[SHL16:%[0-9]+]]:_(i32) = G_SHL [[AND17]], [[C48]](i32)
+ ; CHECK-NEXT: [[OR16:%[0-9]+]]:_(i32) = G_OR [[OR15]], [[SHL16]]
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(i32) = COPY [[LSHR17]](f32)
+ ; CHECK-NEXT: [[AND18:%[0-9]+]]:_(i32) = G_AND [[COPY19]], [[C32]]
+ ; CHECK-NEXT: [[C49:%[0-9]+]]:_(i32) = G_CONSTANT i32 18
+ ; CHECK-NEXT: [[SHL17:%[0-9]+]]:_(i32) = G_SHL [[AND18]], [[C49]](i32)
+ ; CHECK-NEXT: [[OR17:%[0-9]+]]:_(i32) = G_OR [[OR16]], [[SHL17]]
+ ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(i32) = COPY [[LSHR18]](f32)
+ ; CHECK-NEXT: [[AND19:%[0-9]+]]:_(i32) = G_AND [[COPY20]], [[C32]]
+ ; CHECK-NEXT: [[C50:%[0-9]+]]:_(i32) = G_CONSTANT i32 19
+ ; CHECK-NEXT: [[SHL18:%[0-9]+]]:_(i32) = G_SHL [[AND19]], [[C50]](i32)
+ ; CHECK-NEXT: [[OR18:%[0-9]+]]:_(i32) = G_OR [[OR17]], [[SHL18]]
+ ; CHECK-NEXT: [[COPY21:%[0-9]+]]:_(i32) = COPY [[LSHR19]](f32)
+ ; CHECK-NEXT: [[AND20:%[0-9]+]]:_(i32) = G_AND [[COPY21]], [[C32]]
+ ; CHECK-NEXT: [[C51:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[SHL19:%[0-9]+]]:_(i32) = G_SHL [[AND20]], [[C51]](i32)
+ ; CHECK-NEXT: [[OR19:%[0-9]+]]:_(i32) = G_OR [[OR18]], [[SHL19]]
+ ; CHECK-NEXT: [[COPY22:%[0-9]+]]:_(i32) = COPY [[LSHR20]](f32)
+ ; CHECK-NEXT: [[AND21:%[0-9]+]]:_(i32) = G_AND [[COPY22]], [[C32]]
+ ; CHECK-NEXT: [[C52:%[0-9]+]]:_(i32) = G_CONSTANT i32 21
+ ; CHECK-NEXT: [[SHL20:%[0-9]+]]:_(i32) = G_SHL [[AND21]], [[C52]](i32)
+ ; CHECK-NEXT: [[OR20:%[0-9]+]]:_(i32) = G_OR [[OR19]], [[SHL20]]
+ ; CHECK-NEXT: [[COPY23:%[0-9]+]]:_(i32) = COPY [[LSHR21]](f32)
+ ; CHECK-NEXT: [[AND22:%[0-9]+]]:_(i32) = G_AND [[COPY23]], [[C32]]
+ ; CHECK-NEXT: [[C53:%[0-9]+]]:_(i32) = G_CONSTANT i32 22
+ ; CHECK-NEXT: [[SHL21:%[0-9]+]]:_(i32) = G_SHL [[AND22]], [[C53]](i32)
+ ; CHECK-NEXT: [[OR21:%[0-9]+]]:_(i32) = G_OR [[OR20]], [[SHL21]]
+ ; CHECK-NEXT: [[COPY24:%[0-9]+]]:_(i32) = COPY [[LSHR22]](f32)
+ ; CHECK-NEXT: [[AND23:%[0-9]+]]:_(i32) = G_AND [[COPY24]], [[C32]]
+ ; CHECK-NEXT: [[C54:%[0-9]+]]:_(i32) = G_CONSTANT i32 23
+ ; CHECK-NEXT: [[SHL22:%[0-9]+]]:_(i32) = G_SHL [[AND23]], [[C54]](i32)
+ ; CHECK-NEXT: [[OR22:%[0-9]+]]:_(i32) = G_OR [[OR21]], [[SHL22]]
+ ; CHECK-NEXT: [[COPY25:%[0-9]+]]:_(i32) = COPY [[LSHR23]](f32)
+ ; CHECK-NEXT: [[AND24:%[0-9]+]]:_(i32) = G_AND [[COPY25]], [[C32]]
+ ; CHECK-NEXT: [[C55:%[0-9]+]]:_(i32) = G_CONSTANT i32 24
+ ; CHECK-NEXT: [[SHL23:%[0-9]+]]:_(i32) = G_SHL [[AND24]], [[C55]](i32)
+ ; CHECK-NEXT: [[OR23:%[0-9]+]]:_(i32) = G_OR [[OR22]], [[SHL23]]
+ ; CHECK-NEXT: [[COPY26:%[0-9]+]]:_(i32) = COPY [[LSHR24]](f32)
+ ; CHECK-NEXT: [[AND25:%[0-9]+]]:_(i32) = G_AND [[COPY26]], [[C32]]
+ ; CHECK-NEXT: [[C56:%[0-9]+]]:_(i32) = G_CONSTANT i32 25
+ ; CHECK-NEXT: [[SHL24:%[0-9]+]]:_(i32) = G_SHL [[AND25]], [[C56]](i32)
+ ; CHECK-NEXT: [[OR24:%[0-9]+]]:_(i32) = G_OR [[OR23]], [[SHL24]]
+ ; CHECK-NEXT: [[COPY27:%[0-9]+]]:_(i32) = COPY [[LSHR25]](f32)
+ ; CHECK-NEXT: [[AND26:%[0-9]+]]:_(i32) = G_AND [[COPY27]], [[C32]]
+ ; CHECK-NEXT: [[C57:%[0-9]+]]:_(i32) = G_CONSTANT i32 26
+ ; CHECK-NEXT: [[SHL25:%[0-9]+]]:_(i32) = G_SHL [[AND26]], [[C57]](i32)
+ ; CHECK-NEXT: [[OR25:%[0-9]+]]:_(i32) = G_OR [[OR24]], [[SHL25]]
+ ; CHECK-NEXT: [[COPY28:%[0-9]+]]:_(i32) = COPY [[LSHR26]](f32)
+ ; CHECK-NEXT: [[AND27:%[0-9]+]]:_(i32) = G_AND [[COPY28]], [[C32]]
+ ; CHECK-NEXT: [[C58:%[0-9]+]]:_(i32) = G_CONSTANT i32 27
+ ; CHECK-NEXT: [[SHL26:%[0-9]+]]:_(i32) = G_SHL [[AND27]], [[C58]](i32)
+ ; CHECK-NEXT: [[OR26:%[0-9]+]]:_(i32) = G_OR [[OR25]], [[SHL26]]
+ ; CHECK-NEXT: [[COPY29:%[0-9]+]]:_(i32) = COPY [[LSHR27]](f32)
+ ; CHECK-NEXT: [[AND28:%[0-9]+]]:_(i32) = G_AND [[COPY29]], [[C32]]
+ ; CHECK-NEXT: [[C59:%[0-9]+]]:_(i32) = G_CONSTANT i32 28
+ ; CHECK-NEXT: [[SHL27:%[0-9]+]]:_(i32) = G_SHL [[AND28]], [[C59]](i32)
+ ; CHECK-NEXT: [[OR27:%[0-9]+]]:_(i32) = G_OR [[OR26]], [[SHL27]]
+ ; CHECK-NEXT: [[COPY30:%[0-9]+]]:_(i32) = COPY [[LSHR28]](f32)
+ ; CHECK-NEXT: [[AND29:%[0-9]+]]:_(i32) = G_AND [[COPY30]], [[C32]]
+ ; CHECK-NEXT: [[C60:%[0-9]+]]:_(i32) = G_CONSTANT i32 29
+ ; CHECK-NEXT: [[SHL28:%[0-9]+]]:_(i32) = G_SHL [[AND29]], [[C60]](i32)
+ ; CHECK-NEXT: [[OR28:%[0-9]+]]:_(i32) = G_OR [[OR27]], [[SHL28]]
+ ; CHECK-NEXT: [[COPY31:%[0-9]+]]:_(i32) = COPY [[LSHR29]](f32)
+ ; CHECK-NEXT: [[AND30:%[0-9]+]]:_(i32) = G_AND [[COPY31]], [[C32]]
+ ; CHECK-NEXT: [[C61:%[0-9]+]]:_(i32) = G_CONSTANT i32 30
+ ; CHECK-NEXT: [[SHL29:%[0-9]+]]:_(i32) = G_SHL [[AND30]], [[C61]](i32)
+ ; CHECK-NEXT: [[OR29:%[0-9]+]]:_(i32) = G_OR [[OR28]], [[SHL29]]
+ ; CHECK-NEXT: [[COPY32:%[0-9]+]]:_(i32) = COPY [[LSHR30]](f32)
+ ; CHECK-NEXT: [[C62:%[0-9]+]]:_(i32) = G_CONSTANT i32 31
+ ; CHECK-NEXT: [[SHL30:%[0-9]+]]:_(i32) = G_SHL [[COPY32]], [[C62]](i32)
+ ; CHECK-NEXT: [[OR30:%[0-9]+]]:_(i32) = G_OR [[OR29]], [[SHL30]]
+ ; CHECK-NEXT: [[LSHR31:%[0-9]+]]:_(i32) = G_LSHR [[OR30]], [[C31]](i32)
+ ; CHECK-NEXT: [[AND31:%[0-9]+]]:_(i32) = G_AND [[LSHR31]], [[C32]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[AND31]](i32)
%0:_(f32) = COPY $vgpr0
%1:_(<32 x i1>) = G_BITCAST %0
%2:_(i32) = G_CONSTANT i32 0
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