[llvm-branch-commits] [llvm] [AMDGPU] Lower loads and stores for address space 13 (PR #209541)

[Matt Arsenault via llvm-branch-commits]

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@@ -0,0 +1,109 @@
+//===- AMDGPUAssignIdxToM0.cpp - Copy VGPR-memory indices to M0 ----------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+/// Copy the register index of a VGPR "as memory" (address space 13)
+/// V_LOAD_IDX / V_STORE_IDX pseudo into M0, which V_MOVREL[SD] reads when the
+/// pseudo is lowered (see AMDGPULowerVGPREncoding). This runs before register
+/// allocation so the copy to M0 is inserted while the index is still virtual.
+//
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPU.h"
+#include "AMDGPUMachineInstrs.h"
+#include "GCNSubtarget.h"
+#include "SIInstrInfo.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/InitializePasses.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "amdgpu-assign-idx-to-m0"
+
+static bool assignIdxToM0(MachineFunction &MF) {
+  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+
+  // Only movrel takes its index from M0. Subtargets without it index with the
+  // VGPR indexing mode instead, which AMDGPULowerVGPREncoding enables around
+  // the move with s_set_gpr_idx_on, reading the index straight out of its SGPR.
+  if (!ST.hasMovrel())
+    return false;
+
+  const SIInstrInfo *TII = ST.getInstrInfo();
+
+  bool Changed = false;
+  for (MachineBasicBlock &MBB : MF) {
+    for (MachineInstr &MI : MBB) {
+      auto *LdSt = dyn_cast<AMDGPUMI::VLoadStoreIdxInst>(&MI);
+      if (!LdSt)
+        continue;
+
+      MachineOperand &IdxOp = LdSt->getIdxOp();
+      if (!IdxOp.isReg())
+        continue;
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arsenm wrote:

A non-register index would need to be s_mov_b32'd into m0, not ignored?

https://github.com/llvm/llvm-project/pull/209541