[llvm-branch-commits] [llvm] [AMDGPU] Lower loads and stores for address space 13 (PR #209541)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm commented:

My main high level concern is how useful this will be pre-gfx1250. I'm not sure how practically useful this is while still depending on register allocation choices. This obscures key information from RA, while not taking away the RA problem. Given that pre-register-indexing targets will always need a fixed register assignment, RA really needs the strong hint of directly copying to/from a predetermined set of physical registers in the original MIR 

https://github.com/llvm/llvm-project/pull/209541