[llvm-branch-commits] [llvm] ca9e76b - Revert "[llvm][AArch64] Add pipeliner remarks (#213157)"
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sat Aug 1 12:52:26 PDT 2026
Author: Vitaly Buka
Date: 2026-08-01T12:52:21-07:00
New Revision: ca9e76b577d95481d7e67edb549f60bcd5396095
URL: https://github.com/llvm/llvm-project/commit/ca9e76b577d95481d7e67edb549f60bcd5396095
DIFF: https://github.com/llvm/llvm-project/commit/ca9e76b577d95481d7e67edb549f60bcd5396095.diff
LOG: Revert "[llvm][AArch64] Add pipeliner remarks (#213157)"
This reverts commit 25aec49d40d52ab730d360fc362ecd8b46e00db5.
Added:
Modified:
llvm/include/llvm/CodeGen/MachinePipeliner.h
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/include/llvm/CodeGen/WindowScheduler.h
llvm/lib/CodeGen/MachinePipeliner.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.h
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.h
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/test/CodeGen/Hexagon/swp-ws-exp.mir
llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir
llvm/test/CodeGen/PowerPC/sms-remark.ll
Removed:
llvm/test/CodeGen/AArch64/sms-analyzeloop-remarks.mir
llvm/test/CodeGen/AArch64/sms-schedule-remark.mir
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MachinePipeliner.h b/llvm/include/llvm/CodeGen/MachinePipeliner.h
index 3e9c15e729f99..543c4bb772b90 100644
--- a/llvm/include/llvm/CodeGen/MachinePipeliner.h
+++ b/llvm/include/llvm/CodeGen/MachinePipeliner.h
@@ -287,12 +287,6 @@ class LLVM_ABI SwingSchedulerDAG : public ScheduleDAGInstrs {
unsigned MII = 0;
/// The maximum initiation interval between iterations for this schedule.
unsigned MAX_II = 0;
- /// The resource-constrained minimum initiation interval, i.e. the lower
- /// bound on MII imposed by the availability of processor resources.
- unsigned ResMII = 0;
- /// The recurrence-constrained minimum initiation interval, i.e. the lower
- /// bound on MII imposed by loop-carried dependence cycles.
- unsigned RecMII = 0;
/// Set to true if a valid pipelined schedule is found for the loop.
bool Scheduled = false;
MachineLoop &Loop;
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index d3227758fb4e9..4749d06501cb2 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -50,7 +50,6 @@ class MachineLoop;
class MachineLoopInfo;
class MachineMemOperand;
class MachineModuleInfo;
-class MachineOptimizationRemarkEmitter;
class MachineRegisterInfo;
class MCAsmInfo;
class MCInst;
@@ -898,11 +897,8 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
/// Analyze loop L, which must be a single-basic-block loop, and if the
/// conditions can be understood enough produce a PipelinerLoopInfo object.
- /// \p ORE, if non-null, may be used by targets to emit optimization remarks
- /// explaining why the loop was rejected for pipelining.
- virtual std::unique_ptr<PipelinerLoopInfo> analyzeLoopForPipelining(
- MachineBasicBlock *LoopBB,
- MachineOptimizationRemarkEmitter *ORE = nullptr) const {
+ virtual std::unique_ptr<PipelinerLoopInfo>
+ analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
return nullptr;
}
diff --git a/llvm/include/llvm/CodeGen/WindowScheduler.h b/llvm/include/llvm/CodeGen/WindowScheduler.h
index d8dbade1a421c..12b3474dfa784 100644
--- a/llvm/include/llvm/CodeGen/WindowScheduler.h
+++ b/llvm/include/llvm/CodeGen/WindowScheduler.h
@@ -109,10 +109,6 @@ class LLVM_ABI WindowScheduler {
bool run();
- /// Returns the Initiation Interval of the best scheduling result found, or
- /// UINT_MAX if run() has not been called or found no valid schedule.
- unsigned getBestII() const { return BestII; }
-
protected:
/// Two types of ScheduleDAGs are needed, one for creating dependency graphs
/// only, and the other for list scheduling as determined by the target.
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index effde35eb8678..a506165eb75b0 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -585,7 +585,7 @@ bool MachinePipeliner::canPipelineLoop(MachineLoop &L) {
LI.LoopInductionVar = nullptr;
LI.LoopCompare = nullptr;
- LI.LoopPipelinerInfo = TII->analyzeLoopForPipelining(L.getTopBlock(), ORE);
+ LI.LoopPipelinerInfo = TII->analyzeLoopForPipelining(L.getTopBlock());
if (!LI.LoopPipelinerInfo) {
LLVM_DEBUG(dbgs() << "Unable to analyzeLoop, can NOT pipeline Loop\n");
NumFailLoop++;
@@ -716,23 +716,7 @@ bool MachinePipeliner::runWindowScheduler(MachineLoop &L) {
Context.RegClassInfo =
&getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
WindowScheduler WS(&Context, L);
- bool Scheduled = WS.run();
- if (Scheduled) {
- unsigned II = WS.getBestII();
- ORE->emit([&]() {
- return MachineOptimizationRemark(DEBUG_TYPE, "window-schedule",
- L.getStartLoc(), L.getHeader())
- << "Window scheduled with Initiation Interval: "
- << ore::NV("II", II);
- });
- } else {
- ORE->emit([&]() {
- return MachineOptimizationRemarkMissed(DEBUG_TYPE, "window-schedule",
- L.getStartLoc(), L.getHeader())
- << "Failed to find a valid window schedule";
- });
- }
- return Scheduled;
+ return WS.run();
}
bool MachinePipeliner::useSwingModuloScheduler() {
@@ -2913,10 +2897,7 @@ bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) {
<< "Schedule found with Initiation Interval: "
<< ore::NV("II", Schedule.getInitiationInterval())
<< ", MaxStageCount: "
- << ore::NV("MaxStageCount", Schedule.getMaxStageCount())
- << ", ResMII: " << ore::NV("ResMII", ResMII)
- << ", RecMII: " << ore::NV("RecMII", RecMII) << ", Bound: "
- << ore::NV("Bound", ResMII >= RecMII ? "Resource" : "Recurrence");
+ << ore::NV("MaxStageCount", Schedule.getMaxStageCount());
});
} else
Schedule.reset();
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 0773d503802ca..b40188e97a71e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -25,7 +25,6 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
-#include "llvm/Analysis/OptimizationRemarkEmitter.h"
#include "llvm/CodeGen/CFIInstBuilder.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
@@ -37,7 +36,6 @@
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
-#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/StackMaps.h"
@@ -12065,8 +12063,7 @@ static bool getIndVarInfo(Register Reg, const MachineBasicBlock *LoopBB,
}
std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
-AArch64InstrInfo::analyzeLoopForPipelining(
- MachineBasicBlock *LoopBB, MachineOptimizationRemarkEmitter *ORE) const {
+AArch64InstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
// Accept loops that meet the following conditions
// * The conditional branch is BCC
// * The compare instruction is ADDS/SUBS/WHILEXX
@@ -12075,66 +12072,24 @@ AArch64InstrInfo::analyzeLoopForPipelining(
// * The induction variable is incremented/decremented by a single instruction
// * Does not contain CALL or instructions which have unmodeled side effects
- for (MachineInstr &MI : *LoopBB) {
- // This instruction may use NZCV, which interferes with the instruction to
- // be inserted for loop control.
- if (MI.isCall()) {
- if (ORE)
- ORE->emit([&]() {
- return MachineOptimizationRemarkAnalysis("pipeliner", "analyzeLoop",
- &MI)
- << "loop contains a call and therefore cannot be pipelined";
- });
- return nullptr;
- }
- if (MI.hasUnmodeledSideEffects()) {
- if (ORE)
- ORE->emit([&]() {
- return MachineOptimizationRemarkAnalysis("pipeliner", "analyzeLoop",
- &MI)
- << "loop contains an instruction with unmodeled side effects, "
- "and therefore cannot be pipelined";
- });
+ for (MachineInstr &MI : *LoopBB)
+ if (MI.isCall() || MI.hasUnmodeledSideEffects())
+ // This instruction may use NZCV, which interferes with the instruction to
+ // be inserted for loop control.
return nullptr;
- }
- }
MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
SmallVector<MachineOperand, 4> Cond;
- if (analyzeBranch(*LoopBB, TBB, FBB, Cond)) {
- if (ORE)
- ORE->emit([&]() {
- return MachineOptimizationRemarkAnalysis(
- "pipeliner", "analyzeLoop",
- LoopBB->findDebugLoc(LoopBB->getFirstTerminator()), LoopBB)
- << "branch cannot be analyzed";
- });
+ if (analyzeBranch(*LoopBB, TBB, FBB, Cond))
return nullptr;
- }
// Infinite loops are not supported
- if (TBB == LoopBB && FBB == LoopBB) {
- if (ORE)
- ORE->emit([&]() {
- return MachineOptimizationRemarkAnalysis(
- "pipeliner", "analyzeLoop",
- LoopBB->findDebugLoc(LoopBB->getFirstTerminator()), LoopBB)
- << "infinite loops are not supported";
- });
+ if (TBB == LoopBB && FBB == LoopBB)
return nullptr;
- }
// Must be conditional branch
- if (TBB != LoopBB && FBB == nullptr) {
- if (ORE)
- ORE->emit([&]() {
- return MachineOptimizationRemarkAnalysis(
- "pipeliner", "analyzeLoop",
- LoopBB->findDebugLoc(LoopBB->getFirstTerminator()), LoopBB)
- << "loop is not terminated by a conditional branch";
- });
+ if (TBB != LoopBB && FBB == nullptr)
return nullptr;
- }
assert((TBB == LoopBB || FBB == LoopBB) &&
"The Loop must be a single-basic-block loop");
@@ -12142,16 +12097,8 @@ AArch64InstrInfo::analyzeLoopForPipelining(
MachineInstr *CondBranch = &*LoopBB->getFirstTerminator();
const TargetRegisterInfo &TRI = getRegisterInfo();
- if (CondBranch->getOpcode() != AArch64::Bcc) {
- if (ORE)
- ORE->emit([&]() {
- return MachineOptimizationRemarkAnalysis("pipeliner", "analyzeLoop",
- CondBranch)
- << "branch opcode not yet supported for pipelining: "
- << ore::NV("Opcode", getName(CondBranch->getOpcode()));
- });
+ if (CondBranch->getOpcode() != AArch64::Bcc)
return nullptr;
- }
// Normalization for createTripCountGreaterCondition()
if (TBB == LoopBB)
@@ -12183,13 +12130,6 @@ AArch64InstrInfo::analyzeLoopForPipelining(
Comp = &MI;
break;
}
- if (ORE)
- ORE->emit([&]() {
- return MachineOptimizationRemarkAnalysis("pipeliner", "analyzeLoop",
- &MI)
- << "compare instruction not recognized: "
- << ore::NV("Opcode", getName(MI.getOpcode()));
- });
return nullptr;
}
@@ -12198,44 +12138,22 @@ AArch64InstrInfo::analyzeLoopForPipelining(
CompCounterOprNum = 2;
else if (isDefinedOutside(Comp->getOperand(2).getReg(), LoopBB))
CompCounterOprNum = 1;
- else {
- if (ORE)
- ORE->emit([&]() {
- return MachineOptimizationRemarkAnalysis("pipeliner",
- "analyzeLoop", Comp)
- << "neither operand of the compare is loop invariant";
- });
+ else
return nullptr;
- }
}
break;
}
}
- if (!Comp) {
- if (ORE)
- ORE->emit([&]() {
- return MachineOptimizationRemarkAnalysis(
- "pipeliner", "analyzeLoop",
- LoopBB->findDebugLoc(LoopBB->getFirstTerminator()), LoopBB)
- << "no NZCV-modifying compare instruction found";
- });
+ if (!Comp)
return nullptr;
- }
MachineInstr *Update = nullptr;
Register Init;
bool IsUpdatePriorComp;
unsigned UpdateCounterOprNum;
if (!getIndVarInfo(Comp->getOperand(CompCounterOprNum).getReg(), LoopBB,
- Update, UpdateCounterOprNum, Init, IsUpdatePriorComp)) {
- if (ORE)
- ORE->emit([&]() {
- return MachineOptimizationRemarkAnalysis("pipeliner", "analyzeLoop",
- Comp)
- << "loop induction variable pattern not recognized";
- });
+ Update, UpdateCounterOprNum, Init, IsUpdatePriorComp))
return nullptr;
- }
return std::make_unique<AArch64PipelinerLoopInfo>(
LoopBB, CondBranch, Comp, CompCounterOprNum, Update, UpdateCounterOprNum,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 2b30bd912fe44..15bd832de8d25 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -414,9 +414,8 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
const DebugLoc &DL,
int *BytesAdded = nullptr) const override;
- std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> analyzeLoopForPipelining(
- MachineBasicBlock *LoopBB,
- MachineOptimizationRemarkEmitter *ORE = nullptr) const override;
+ std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
+ analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index e6ea273c41b50..a922024b032db 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -6737,8 +6737,7 @@ bool ARMPipelinerLoopInfo::tooMuchRegisterPressure(SwingSchedulerDAG &SSD,
} // namespace
std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
-ARMBaseInstrInfo::analyzeLoopForPipelining(
- MachineBasicBlock *LoopBB, MachineOptimizationRemarkEmitter *ORE) const {
+ARMBaseInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
MachineBasicBlock::iterator I = LoopBB->getFirstTerminator();
MachineBasicBlock *Preheader = *LoopBB->pred_begin();
if (Preheader == LoopBB)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 9ecabf17103c8..94595ab2b338b 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -382,9 +382,8 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
/// Analyze loop L, which must be a single-basic-block loop, and if the
/// conditions can be understood enough produce a PipelinerLoopInfo object.
- std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> analyzeLoopForPipelining(
- MachineBasicBlock *LoopBB,
- MachineOptimizationRemarkEmitter *ORE = nullptr) const override;
+ std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
+ analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
private:
/// Returns an unused general-purpose register which can be used for
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index c2519faa34778..daeb384515578 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -806,8 +806,7 @@ class HexagonPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
} // namespace
std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
-HexagonInstrInfo::analyzeLoopForPipelining(
- MachineBasicBlock *LoopBB, MachineOptimizationRemarkEmitter *ORE) const {
+HexagonInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
// We really "analyze" only hardware loops right now.
MachineBasicBlock::iterator I = LoopBB->getFirstTerminator();
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index f11ac7b7989a5..1901b260926d2 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -139,9 +139,8 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
/// Analyze loop L, which must be a single-basic-block loop, and if the
/// conditions can be understood enough produce a PipelinerLoopInfo object.
- std::unique_ptr<PipelinerLoopInfo> analyzeLoopForPipelining(
- MachineBasicBlock *LoopBB,
- MachineOptimizationRemarkEmitter *ORE = nullptr) const override;
+ std::unique_ptr<PipelinerLoopInfo>
+ analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
/// Return true if it's profitable to predicate
/// instructions with accumulated instruction latency of "NumCycles"
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 8965fd5fe1590..f415a9776da94 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -5790,8 +5790,7 @@ class PPCPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
} // namespace
std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
-PPCInstrInfo::analyzeLoopForPipelining(
- MachineBasicBlock *LoopBB, MachineOptimizationRemarkEmitter *ORE) const {
+PPCInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
// We really "analyze" only hardware loops right now.
MachineBasicBlock::iterator I = LoopBB->getFirstTerminator();
MachineBasicBlock *Preheader = *LoopBB->pred_begin();
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index b99326b829be9..c8a747ac829ec 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -789,9 +789,8 @@ class PPCInstrInfo : public PPCGenInstrInfo {
/// Analyze loop L, which must be a single-basic-block loop, and if the
/// conditions can be understood enough produce a PipelinerLoopInfo object.
- std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> analyzeLoopForPipelining(
- MachineBasicBlock *LoopBB,
- MachineOptimizationRemarkEmitter *ORE = nullptr) const override;
+ std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
+ analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
};
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index bb1a97fe87140..cdc1a8c07c09f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -5394,8 +5394,7 @@ class RISCVPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
} // namespace
std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
-RISCVInstrInfo::analyzeLoopForPipelining(
- MachineBasicBlock *LoopBB, MachineOptimizationRemarkEmitter *ORE) const {
+RISCVInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
SmallVector<MachineOperand, 4> Cond;
if (analyzeBranch(*LoopBB, TBB, FBB, Cond, /*AllowModify=*/false))
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 7f61c850c48b8..c75335ba7d145 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -328,9 +328,8 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
- std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> analyzeLoopForPipelining(
- MachineBasicBlock *LoopBB,
- MachineOptimizationRemarkEmitter *ORE = nullptr) const override;
+ std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
+ analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
bool isHighLatencyDef(int Opc) const override;
diff --git a/llvm/test/CodeGen/AArch64/sms-analyzeloop-remarks.mir b/llvm/test/CodeGen/AArch64/sms-analyzeloop-remarks.mir
deleted file mode 100644
index d043760aaf050..0000000000000
--- a/llvm/test/CodeGen/AArch64/sms-analyzeloop-remarks.mir
+++ /dev/null
@@ -1,168 +0,0 @@
-# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o /dev/null %s -run-pass pipeliner \
-# RUN: -aarch64-enable-pipeliner -pass-remarks-analysis=pipeliner \
-# RUN: -pass-remarks-missed=pipeliner 2>&1 | FileCheck %s
-
-# Regression test for the analyzeLoopForPipelining() optimization remarks:
-# each rejection point in AArch64InstrInfo::analyzeLoopForPipelining() should
-# report a distinct, specific reason via the "pipeliner"/"analyzeLoop" remark,
-# rather than only the generic "The loop structure is not supported" remark
-# from canPipelineLoop().
-
---- |
- define dso_local void @call(ptr noalias nocapture noundef writeonly %a, i32 noundef %n) local_unnamed_addr #0 {
- entry:
- ret void
- }
- declare void @callee()
-
- define dso_local void @infiniteloop(ptr noalias nocapture noundef writeonly %a, i32 noundef %n) local_unnamed_addr #0 {
- entry:
- ret void
- }
-
- define dso_local void @unsupportedbranch(ptr noalias nocapture noundef writeonly %a) local_unnamed_addr #0 {
- entry:
- ret void
- }
-
- define dso_local void @badcompare(ptr noalias nocapture noundef writeonly %a, i32 noundef %n) local_unnamed_addr #0 {
- entry:
- ret void
- }
-
- define dso_local void @noninvariantcompare(i64 noundef %x, i64 noundef %y) local_unnamed_addr #0 {
- entry:
- ret void
- }
-
- define dso_local void @badindvar(i64 noundef %x, i64 noundef %y) local_unnamed_addr #0 {
- entry:
- ret void
- }
-...
----
-name: call
-tracksRegLiveness: true
-body: |
- ; A call in the loop body may use NZCV, which interferes with the
- ; instruction to be inserted for loop control.
- ; CHECK: loop contains a call and therefore cannot be pipelined
- ; CHECK: The loop structure is not supported
- bb.0.entry:
- liveins: $x0, $w1
-
- %10:gpr64sp = COPY $x0
- %11:gpr32common = COPY $w1
-
- bb.1:
- %12:gpr64sp = PHI %10, %bb.0, %13, %bb.1
- %13:gpr64sp = ADDXri %12, 1, 0
- BL @callee, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp
- dead $wzr = SUBSWri %11, 1, 0, implicit-def $nzcv
- Bcc 1, %bb.1, implicit $nzcv
- B %bb.2
-
- bb.2:
-...
----
-name: infiniteloop
-tracksRegLiveness: true
-body: |
- ; Both branch targets are the loop itself: nothing exits the loop.
- ; CHECK: infinite loops are not supported
- ; CHECK: The loop structure is not supported
- bb.0.entry:
- liveins: $x0, $w1
-
- %10:gpr64sp = COPY $x0
- %11:gpr32common = COPY $w1
-
- bb.1:
- %12:gpr64sp = PHI %10, %bb.0, %13, %bb.1
- %13:gpr64sp = ADDXri %12, 1, 0
- dead $wzr = SUBSWri %11, 0, 0, implicit-def $nzcv
- Bcc 0, %bb.1, implicit $nzcv
- B %bb.1
-...
----
-name: unsupportedbranch
-tracksRegLiveness: true
-body: |
- ; The loop terminator is an unconditional branch (Bcc is required).
- ; CHECK: branch opcode not yet supported for pipelining: B
- ; CHECK: The loop structure is not supported
- bb.0.entry:
- liveins: $x0
-
- %10:gpr64sp = COPY $x0
-
- bb.1:
- %12:gpr64sp = PHI %10, %bb.0, %13, %bb.1
- %13:gpr64sp = ADDXri %12, 1, 0
- B %bb.1
-...
----
-name: badcompare
-tracksRegLiveness: true
-body: |
- ; The NZCV-modifying instruction is not a recognized compare opcode.
- ; CHECK: compare instruction not recognized: ANDSWri
- ; CHECK: The loop structure is not supported
- bb.0.entry:
- liveins: $x0, $w1
-
- %10:gpr64sp = COPY $x0
- %11:gpr32common = COPY $w1
-
- bb.1:
- %12:gpr64sp = PHI %10, %bb.0, %13, %bb.1
- %13:gpr64sp = ADDXri %12, 1, 0
- dead $wzr = ANDSWri %11, 1, implicit-def $nzcv
- Bcc 1, %bb.1, implicit $nzcv
- B %bb.2
-
- bb.2:
-...
----
-name: noninvariantcompare
-tracksRegLiveness: true
-body: |
- ; Neither operand of the compare instruction is a loop invariant value.
- ; CHECK: neither operand of the compare is loop invariant
- ; CHECK: The loop structure is not supported
- bb.0.entry:
- liveins: $x0, $x1
- %10:gpr64 = COPY $x0
- %11:gpr64 = COPY $x1
-
- bb.1:
- %12:gpr64 = PHI %11, %bb.0, %13, %bb.1
- %13:gpr64 = ADDXrr %12, %11
- dead $xzr = SUBSXrr %13, %13, implicit-def $nzcv
- Bcc 1, %bb.1, implicit $nzcv
- B %bb.2
-
- bb.2:
-...
----
-name: badindvar
-tracksRegLiveness: true
-body: |
- ; The value compared against is not updated by a recognized increment
- ; instruction.
- ; CHECK: loop induction variable pattern not recognized
- ; CHECK: The loop structure is not supported
- bb.0.entry:
- liveins: $x0, $x1
- %10:gpr64 = COPY $x0
- %11:gpr64 = COPY $x1
-
- bb.1:
- %12:gpr64 = PHI %11, %bb.0, %13, %bb.1
- %13:gpr64 = ORRXrr %12, %12
- dead $xzr = SUBSXrr %12, %10, implicit-def $nzcv
- Bcc 1, %bb.1, implicit $nzcv
- B %bb.2
-
- bb.2:
-...
diff --git a/llvm/test/CodeGen/AArch64/sms-schedule-remark.mir b/llvm/test/CodeGen/AArch64/sms-schedule-remark.mir
deleted file mode 100644
index a5a292c244e10..0000000000000
--- a/llvm/test/CodeGen/AArch64/sms-schedule-remark.mir
+++ /dev/null
@@ -1,83 +0,0 @@
-# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o /dev/null %s -run-pass pipeliner \
-# RUN: -aarch64-enable-pipeliner -pass-remarks-analysis=pipeliner 2>&1 | FileCheck %s
-
-# Regression test for the "schedule" success remark: it should report ResMII,
-# RecMII, and which of the two is the binding constraint on the chosen II, in
-# addition to the Initiation Interval and MaxStageCount that were already
-# reported.
-
-# CHECK: Schedule found with Initiation Interval: 3, MaxStageCount: 2, ResMII: 0, RecMII: 0, Bound: Resource
-
---- |
- define dso_local void @func(ptr noalias nocapture noundef writeonly %a, ptr nocapture noundef readonly %b, i32 noundef %n) local_unnamed_addr #0 {
- entry:
- %cmp6 = icmp sgt i32 %n, 0
- br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
-
- for.body.preheader: ; preds = %entry
- %wide.trip.count = zext nneg i32 %n to i64
- br label %for.body
-
- for.cond.cleanup: ; preds = %for.body, %entry
- ret void
-
- for.body: ; preds = %for.body.preheader, %for.body
- %lsr.iv11 = phi i64 [ %wide.trip.count, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
- %lsr.iv9 = phi ptr [ %b, %for.body.preheader ], [ %scevgep10, %for.body ]
- %lsr.iv = phi ptr [ %a, %for.body.preheader ], [ %scevgep, %for.body ]
- %0 = load float, ptr %lsr.iv9, align 4
- %add = fadd float %0, 1.000000e+00
- store float %add, ptr %lsr.iv, align 4
- %scevgep = getelementptr i8, ptr %lsr.iv, i64 4
- %scevgep10 = getelementptr i8, ptr %lsr.iv9, i64 4
- %lsr.iv.next = add nsw i64 %lsr.iv11, -1
- %exitcond.not = icmp eq i64 %lsr.iv.next, 0
- br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
- }
-
-...
----
-name: func
-tracksRegLiveness: true
-liveins:
- - { reg: '$x0', virtual-reg: '%7' }
- - { reg: '$x1', virtual-reg: '%8' }
- - { reg: '$w2', virtual-reg: '%9' }
-body: |
- bb.0.entry:
- successors: %bb.1(0x50000000), %bb.2(0x30000000)
- liveins: $x0, $x1, $w2
-
- %9:gpr32common = COPY $w2
- %8:gpr64 = COPY $x1
- %7:gpr64 = COPY $x0
- dead $wzr = SUBSWri %9, 1, 0, implicit-def $nzcv
- Bcc 11, %bb.2, implicit $nzcv
- B %bb.1
-
- bb.1.for.body.preheader:
- %11:gpr32 = ORRWrs $wzr, %9, 0
- %0:gpr64all = SUBREG_TO_REG killed %11, %subreg.sub_32
- %14:fpr32 = FMOVSi 112
- B %bb.3
-
- bb.2.for.cond.cleanup:
- RET_ReallyLR
-
- bb.3.for.body:
- successors: %bb.2(0x04000000), %bb.3(0x7c000000)
-
- %1:gpr64sp = PHI %0, %bb.1, %6, %bb.3
- %2:gpr64sp = PHI %8, %bb.1, %5, %bb.3
- %3:gpr64sp = PHI %7, %bb.1, %4, %bb.3
- early-clobber %12:gpr64sp, %13:fpr32 = LDRSpost %2, 4 :: (load (s32) from %ir.lsr.iv9)
- %15:fpr32 = nofpexcept FADDSrr killed %13, %14, implicit $fpcr
- early-clobber %16:gpr64sp = STRSpost killed %15, %3, 4 :: (store (s32) into %ir.lsr.iv)
- %4:gpr64all = COPY %16
- %5:gpr64all = COPY %12
- %17:gpr64 = nsw SUBSXri %1, 1, 0, implicit-def $nzcv
- %6:gpr64all = COPY %17
- Bcc 0, %bb.2, implicit $nzcv
- B %bb.3
-
-...
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-exp.mir b/llvm/test/CodeGen/Hexagon/swp-ws-exp.mir
index 95eba5fe1f9c3..c97fdbf0e09e9 100644
--- a/llvm/test/CodeGen/Hexagon/swp-ws-exp.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-exp.mir
@@ -2,14 +2,9 @@
# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
# RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \
# RUN: | FileCheck %s
-# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner \
-# RUN: -window-sched=force -filetype=null -verify-machineinstrs \
-# RUN: -pass-remarks=pipeliner 2>&1 | FileCheck %s --check-prefix=REMARK
# CHECK: Best window offset is {{[0-9]+}} and Best II is {{[0-9]+}}.
-# REMARK: remark: {{.*}}Window scheduled with Initiation Interval: {{[0-9]+}}
-
--- |
define void @exp_approx_top_six(i32 %N, ptr noalias %x, ptr noalias %y) #0 {
entry:
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir b/llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir
index 4a9a253ae453d..e86ef4376d0ac 100644
--- a/llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir
@@ -9,9 +9,6 @@
# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
# RUN: -window-sched=force -window-region-limit=1 -window-search-ratio=80 \
# RUN: -filetype=null 2>&1 | FileCheck %s --check-prefix=CHECK-SCHED-NOT-NEEDED
-# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner \
-# RUN: -window-sched=force -filetype=null \
-# RUN: -pass-remarks-missed=pipeliner 2>&1 | FileCheck %s --check-prefix=REMARK
# CHECK-INITIALIZE: There are too few MIs in the window region!
# CHECK-INITIALIZE: The WindowScheduler failed to initialize!
@@ -19,8 +16,6 @@
# CHECK-ANALYSE-II: Window scheduling is not needed!
# CHECK-SCHED-NOT-NEEDED: Window scheduling is not needed!
-# REMARK: remark: {{.*}}Failed to find a valid window schedule
-
---
name: relu
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/PowerPC/sms-remark.ll b/llvm/test/CodeGen/PowerPC/sms-remark.ll
index df3f86b4863bb..adecf488c9b1e 100644
--- a/llvm/test/CodeGen/PowerPC/sms-remark.ll
+++ b/llvm/test/CodeGen/PowerPC/sms-remark.ll
@@ -15,7 +15,7 @@
@y = dso_local global [1024 x i32] zeroinitializer, align 4
define dso_local ptr @foo() local_unnamed_addr {
-;ENABLED: Schedule found with Initiation Interval: {{[0-9]+}}, MaxStageCount: {{[0-9]+}}, ResMII: {{[0-9]+}}, RecMII: {{[0-9]+}}, Bound: {{(Recurrence|Resource)}}
+;ENABLED: Schedule found with Initiation Interval
;ENABLED: Pipelined succesfully!
entry:
%.pre = load i32, ptr @y, align 4
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