[llvm-branch-commits] [llvm] [AMDGPU] Support Wave Reduction for true-16 types - 3 (PR #194813)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Apr 29 01:47:30 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Aaditya (easyonaadit)
<details>
<summary>Changes</summary>
Supporting true-16 versions of the reduction intrinsics
Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
---
Patch is 75.98 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/194813.diff
5 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+20-3)
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+4-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll (+257-130)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll (+257-130)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll (+298-151)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 67975b7a7a45a..e60d8919125ef 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5632,6 +5632,7 @@ static uint64_t getIdentityValueForWaveReduction(unsigned Opc) {
case AMDGPU::V_MIN_U16_fake16_e64:
case AMDGPU::V_MIN_U16_t16_e64:
case AMDGPU::V_AND_B16_fake16_e64:
+ case AMDGPU::V_AND_B16_t16_e64:
return 0xffff;
case AMDGPU::V_MIN_I16_e64:
case AMDGPU::V_MIN_I16_opsel_e64:
@@ -5649,7 +5650,9 @@ static uint64_t getIdentityValueForWaveReduction(unsigned Opc) {
case AMDGPU::V_ADD_I16_t16_e64:
case AMDGPU::V_SUB_I16_t16_e64:
case AMDGPU::V_OR_B16_fake16_e64:
+ case AMDGPU::V_OR_B16_t16_e64:
case AMDGPU::V_XOR_B16_fake16_e64:
+ case AMDGPU::V_XOR_B16_t16_e64:
return 0x0;
case AMDGPU::V_MAX_I16_e64:
case AMDGPU::V_MAX_I16_opsel_e64:
@@ -5721,8 +5724,11 @@ static bool is16bitWaveReduceOperation(unsigned Opc) {
Opc == AMDGPU::V_SUB_I16_e64 || Opc == AMDGPU::V_SUB_I16_fake16_e64 ||
Opc == AMDGPU::V_ADD_I16_t16_e64 || Opc == AMDGPU::V_SUB_I16_t16_e64 ||
Opc == AMDGPU::V_AND_B16_fake16_e64 ||
+ Opc == AMDGPU::V_AND_B16_t16_e64 ||
Opc == AMDGPU::V_OR_B16_fake16_e64 ||
- Opc == AMDGPU::V_XOR_B16_fake16_e64;
+ Opc == AMDGPU::V_OR_B16_t16_e64 ||
+ Opc == AMDGPU::V_XOR_B16_fake16_e64 ||
+ Opc == AMDGPU::V_XOR_B16_t16_e64;
}
static bool is32bitWaveReduceOperation(unsigned Opc) {
@@ -5889,8 +5895,10 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
case AMDGPU::S_MAX_I32:
case AMDGPU::V_MAX_F32_e64:
case AMDGPU::V_AND_B16_fake16_e64:
- case AMDGPU::V_OR_B16_fake16_e64:
+ case AMDGPU::V_AND_B16_t16_e64:
case AMDGPU::S_AND_B32:
+ case AMDGPU::V_OR_B16_fake16_e64:
+ case AMDGPU::V_OR_B16_t16_e64:
case AMDGPU::S_OR_B32: {
// Idempotent operations.
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B32), DstReg).addReg(SrcReg);
@@ -5913,6 +5921,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
break;
}
case AMDGPU::V_XOR_B16_fake16_e64:
+ case AMDGPU::V_XOR_B16_t16_e64:
case AMDGPU::S_XOR_B32:
case AMDGPU::S_XOR_B64:
case AMDGPU::V_ADD_I16_e64:
@@ -5949,6 +5958,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
switch (Opc) {
case AMDGPU::V_XOR_B16_fake16_e64:
+ case AMDGPU::V_XOR_B16_t16_e64:
case AMDGPU::S_XOR_B32:
case AMDGPU::S_XOR_B64: {
// Performing an XOR operation on a uniform value
@@ -5962,7 +5972,8 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
.addReg(NewAccumulator->getOperand(0).getReg())
.addImm(1)
.setOperandDead(3); // Dead scc
- if (Opc == AMDGPU::S_XOR_B32 || Opc == AMDGPU::V_XOR_B16_fake16_e64) {
+ if (Opc == AMDGPU::S_XOR_B32 || Opc == AMDGPU::V_XOR_B16_fake16_e64 ||
+ Opc == AMDGPU::V_XOR_B16_t16_e64) {
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), DstReg)
.addReg(SrcReg)
.addReg(ParityRegister);
@@ -6904,6 +6915,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
ST.getGeneration() >= AMDGPUSubtarget::GFX12
? AMDGPU::V_ADD_F64_pseudo_e64
: AMDGPU::V_ADD_F64_e64);
+ case AMDGPU::WAVE_REDUCE_AND_PSEUDO_B16_t16:
+ return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_AND_B16_t16_e64);
case AMDGPU::WAVE_REDUCE_AND_PSEUDO_B16:
return lowerWaveReduce(MI, *BB, *getSubtarget(),
ST.hasTrue16BitInsts() ? AMDGPU::V_AND_B16_fake16_e64
@@ -6912,6 +6925,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_AND_B32);
case AMDGPU::WAVE_REDUCE_AND_PSEUDO_B64:
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_AND_B64);
+ case AMDGPU::WAVE_REDUCE_OR_PSEUDO_B16_t16:
+ return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_OR_B16_t16_e64);
case AMDGPU::WAVE_REDUCE_OR_PSEUDO_B16:
return lowerWaveReduce(MI, *BB, *getSubtarget(),
ST.hasTrue16BitInsts() ? AMDGPU::V_OR_B16_fake16_e64
@@ -6920,6 +6935,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_OR_B32);
case AMDGPU::WAVE_REDUCE_OR_PSEUDO_B64:
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_OR_B64);
+ case AMDGPU::WAVE_REDUCE_XOR_PSEUDO_B16_t16:
+ return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_XOR_B16_t16_e64);
case AMDGPU::WAVE_REDUCE_XOR_PSEUDO_B16:
return lowerWaveReduce(MI, *BB, *getSubtarget(),
ST.hasTrue16BitInsts() ? AMDGPU::V_XOR_B16_fake16_e64
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 8d2432e680a5b..dd9715d7f2e67 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -422,7 +422,10 @@ defvar Operations = [
WaveReduceOp<"umax", "U16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>,
WaveReduceOp<"max", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>,
WaveReduceOp<"add", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>,
- WaveReduceOp<"sub", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>
+ WaveReduceOp<"sub", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>,
+ WaveReduceOp<"and", "B16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>,
+ WaveReduceOp<"or", "B16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>,
+ WaveReduceOp<"xor", "B16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>
];
foreach Op = Operations in {
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
index 0cc033be63b32..3de74ee448bc3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
@@ -11,6 +11,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s
define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX8DAGISEL-LABEL: uniform_value_i16:
@@ -80,52 +84,100 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX10GISEL-NEXT: global_store_short v1, v0, s[0:1]
; GFX10GISEL-NEXT: s_endpgm
;
-; GFX1164DAGISEL-LABEL: uniform_value_i16:
-; GFX1164DAGISEL: ; %bb.0: ; %entry
-; GFX1164DAGISEL-NEXT: s_clause 0x1
-; GFX1164DAGISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v1, s2
-; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX1164DAGISEL-NEXT: s_endpgm
-;
-; GFX1164GISEL-LABEL: uniform_value_i16:
-; GFX1164GISEL: ; %bb.0: ; %entry
-; GFX1164GISEL-NEXT: s_clause 0x1
-; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_and_b32 s2, 0xffff, s2
-; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-NEXT: s_endpgm
-;
-; GFX1132DAGISEL-LABEL: uniform_value_i16:
-; GFX1132DAGISEL: ; %bb.0: ; %entry
-; GFX1132DAGISEL-NEXT: s_clause 0x1
-; GFX1132DAGISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX1132DAGISEL-NEXT: s_endpgm
-;
-; GFX1132GISEL-LABEL: uniform_value_i16:
-; GFX1132GISEL: ; %bb.0: ; %entry
-; GFX1132GISEL-NEXT: s_clause 0x1
-; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_and_b32 s2, 0xffff, s2
-; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-NEXT: s_endpgm
+; GFX1164DAGISEL-FAKE16-LABEL: uniform_value_i16:
+; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1164DAGISEL-FAKE16-NEXT: s_clause 0x1
+; GFX1164DAGISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1164DAGISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v1, s2
+; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX1164DAGISEL-FAKE16-NEXT: s_endpgm
+;
+; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16:
+; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1
+; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1164GISEL-FAKE16-NEXT: s_endpgm
+;
+; GFX1132DAGISEL-FAKE16-LABEL: uniform_value_i16:
+; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1132DAGISEL-FAKE16-NEXT: s_clause 0x1
+; GFX1132DAGISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132DAGISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132DAGISEL-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX1132DAGISEL-FAKE16-NEXT: s_endpgm
+;
+; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16:
+; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1
+; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1132GISEL-FAKE16-NEXT: s_endpgm
+;
+; GFX1164DAGISEL-TRUE16-LABEL: uniform_value_i16:
+; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1164DAGISEL-TRUE16-NEXT: s_clause 0x1
+; GFX1164DAGISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1164DAGISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1164DAGISEL-TRUE16-NEXT: s_endpgm
+;
+; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16:
+; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1
+; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1164GISEL-TRUE16-NEXT: s_endpgm
+;
+; GFX1132DAGISEL-TRUE16-LABEL: uniform_value_i16:
+; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1132DAGISEL-TRUE16-NEXT: s_clause 0x1
+; GFX1132DAGISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132DAGISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1132DAGISEL-TRUE16-NEXT: s_endpgm
+;
+; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16:
+; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1
+; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1132GISEL-TRUE16-NEXT: s_endpgm
entry:
%result = call i16 @llvm.amdgcn.wave.reduce.and.i16(i16 %in, i32 1)
store i16 %result, ptr addrspace(1) %out
@@ -273,85 +325,165 @@ define void @divergnet_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1032GISEL-NEXT: global_store_short v[0:1], v2, off
; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1164DAGISEL-LABEL: divergnet_value_i16:
-; GFX1164DAGISEL: ; %bb.0: ; %entry
-; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164DAGISEL-NEXT: s_mov_b32 s2, 0xffff
-; GFX1164DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
-; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s3, s[0:1]
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
-; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s3
-; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1164DAGISEL-NEXT: v_and_b16 v3, s2, s4
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s2, v3
-; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1
-; GFX1164DAGISEL-NEXT: ; %bb.2:
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2
-; GFX1164DAGISEL-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1164GISEL-LABEL: divergnet_value_i16:
-; GFX1164GISEL: ; %bb.0: ; %entry
-; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164GISEL-NEXT: s_mov_b32 s2, 0xffff
-; GFX1164GISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
-; GFX1164GISEL-NEXT: s_ctz_i32_b64 s3, s[0:1]
-; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1164GISEL-NEXT: v_readlane_b32 s4, v2, s3
-; GFX1164GISEL-NEXT: s_bitset0_b64 s[0:1], s3
-; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1164GISEL-NEXT: v_and_b16 v3, s2, s4
-; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s2, v3
-; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB1_1
-; GFX1164GISEL-NEXT: ; %bb.2:
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s2
-; GFX1164GISEL-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1132DAGISEL-LABEL: divergnet_value_i16:
-; GFX1132DAGISEL: ; %bb.0: ; %entry
-; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1132DAGISEL-NEXT: s_mov_b32 s0, exec_lo
-; GFX1132DAGISEL-NEXT: s_mov_b32 s1, 0xffff
-; GFX1132DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
-; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s2, s0
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1132DAGISEL-NEXT: v_readlane_b32 s3, v2, s2
-; GFX1132DAGISEL-NEXT: s_bitset0_b32 s0, s2
-; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s0, 0
-; GFX1132DAGISEL-NEXT: v_and_b16 v3, s1, s3
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1
-; GFX1132DAGISEL-NEXT: ; %bb.2:
-; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, s1
-; GFX1132DAGISEL-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1132GISEL-LABEL: divergnet_value_i16:
-; GFX1132GISEL: ; %bb.0: ; %entry
-; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_mov_b32 s0, exec_lo
-; GFX1132GISEL-NEXT: s_mov_b32 s1, 0xffff
-; GFX1132GISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
-; GFX1132GISEL-NEXT: s_ctz_i32_b32 s2, s0
-; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1132GISEL-NEXT: v_readlane_b32 s3, v2, s2
-; GFX1132GISEL-NEXT: s_bitset0_b32 s0, s2
-; GFX1132GISEL-NEXT: s_cmp_lg_u32 s0, 0
-; GFX1132GISEL-NEXT: v_and_b16 v3, s1, s3
-; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB1_1
-; GFX1132GISEL-NEXT: ; %bb.2:
-; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s1
-; GFX1132GISEL-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX1164DAGISEL-FAKE16-LABEL: divergnet_value_i16:
+; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec
+; GFX1164DAGISEL-FAKE16-NEXT: s_mov_b32 s2, 0xffff
+; GFX1164DAGISEL-FAKE16-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX1164DAGISEL-FAKE16-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-FAKE16-NEXT: v_readlane_b32 s4, v2, s3
+; GFX1164DAGISEL-FAKE16-NEXT: s_bitset0_b64 s[0:1], s3
+; GFX1164DAGISEL-FAKE16-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX1164DAGISEL-FAKE16-NEXT: v_and_b16 v3, s2, s4
+; GFX1164DAGISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1164DAGISEL-FAKE16-NEXT: v_readfirstlane_b32 s2, v3
+; GFX1164DAGISEL-FAKE16-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1164DAGISEL-FAKE16-NEXT: ; %bb.2:
+; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v2, s2
+; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1164DAGISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1164GISEL-FAKE16-LABEL: divergnet_value_i16:
+; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1164GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164GISEL-FAKE16-NEXT: s_mov_b64 s[0:1], exec
+; GFX1164GISEL-FAKE16-NEXT: s_mov_b32 s2, 0xffff
+; GFX1164GISEL-FAKE16-NEXT: .LBB1_1: ;...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/194813
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