[llvm-branch-commits] [llvm] [AMDGPU] Support Wave Reduction for true-16 types - 1 (PR #194809)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Apr 29 01:46:27 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Aaditya (easyonaadit)
<details>
<summary>Changes</summary>
Supporting true-16 versions of the reduction intrinsics
Supported Ops: `min`, `umin`, `max`, `umax`.
Supports only the iterative stratergy, DPP is yet
to be supported.
---
Patch is 102.63 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/194809.diff
6 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+44-6)
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+17-8)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll (+261-129)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll (+261-130)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll (+276-105)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll (+261-129)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index f7528846c7c19..2f3af3f5bdfa6 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5630,18 +5630,22 @@ static uint64_t getIdentityValueForWaveReduction(unsigned Opc) {
case AMDGPU::V_MIN_U16_e64:
case AMDGPU::V_MIN_U16_opsel_e64:
case AMDGPU::V_MIN_U16_fake16_e64:
+ case AMDGPU::V_MIN_U16_t16_e64:
return 0xffff;
case AMDGPU::V_MIN_I16_e64:
case AMDGPU::V_MIN_I16_opsel_e64:
case AMDGPU::V_MIN_I16_fake16_e64:
+ case AMDGPU::V_MIN_I16_t16_e64:
return 0x7fff;
case AMDGPU::V_MAX_U16_e64:
case AMDGPU::V_MAX_U16_opsel_e64:
case AMDGPU::V_MAX_U16_fake16_e64:
+ case AMDGPU::V_MAX_U16_t16_e64:
return 0x0;
case AMDGPU::V_MAX_I16_e64:
case AMDGPU::V_MAX_I16_opsel_e64:
case AMDGPU::V_MAX_I16_fake16_e64:
+ case AMDGPU::V_MAX_I16_t16_e64:
return 0x8000;
case AMDGPU::S_MIN_U32:
return std::numeric_limits<uint32_t>::max();
@@ -5701,7 +5705,9 @@ static bool is16bitWaveReduceOperation(unsigned Opc) {
Opc == AMDGPU::V_MAX_U16_opsel_e64 ||
Opc == AMDGPU::V_MAX_U16_fake16_e64 || Opc == AMDGPU::V_MAX_U16_e64 ||
Opc == AMDGPU::V_MAX_I16_opsel_e64 ||
- Opc == AMDGPU::V_MAX_I16_fake16_e64 || Opc == AMDGPU::V_MAX_I16_e64;
+ Opc == AMDGPU::V_MAX_I16_fake16_e64 || Opc == AMDGPU::V_MAX_I16_e64 ||
+ Opc == AMDGPU::V_MIN_U16_t16_e64 || Opc == AMDGPU::V_MIN_I16_t16_e64 ||
+ Opc == AMDGPU::V_MAX_U16_t16_e64 || Opc == AMDGPU::V_MAX_I16_t16_e64;
}
static bool is32bitWaveReduceOperation(unsigned Opc) {
@@ -5848,15 +5854,19 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
case AMDGPU::V_MIN_U16_e64:
case AMDGPU::V_MIN_U16_opsel_e64:
case AMDGPU::V_MIN_U16_fake16_e64:
+ case AMDGPU::V_MIN_U16_t16_e64:
case AMDGPU::V_MIN_I16_e64:
case AMDGPU::V_MIN_I16_opsel_e64:
case AMDGPU::V_MIN_I16_fake16_e64:
+ case AMDGPU::V_MIN_I16_t16_e64:
case AMDGPU::V_MAX_U16_e64:
case AMDGPU::V_MAX_U16_opsel_e64:
case AMDGPU::V_MAX_U16_fake16_e64:
+ case AMDGPU::V_MAX_U16_t16_e64:
case AMDGPU::V_MAX_I16_e64:
case AMDGPU::V_MAX_I16_opsel_e64:
case AMDGPU::V_MAX_I16_fake16_e64:
+ case AMDGPU::V_MAX_I16_t16_e64:
case AMDGPU::S_MIN_U32:
case AMDGPU::S_MIN_I32:
case AMDGPU::V_MIN_F32_e64:
@@ -6089,6 +6099,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
bool is16BitOpc = is16bitWaveReduceOperation(Opc);
bool isFPOp = isFloatingPointWaveReduceOperation(Opc);
bool NeedsMovDPP = !is32BitOpc;
+ bool useRealTrue16 = ST.useRealTrue16Insts();
// Create virtual registers required for lowering.
const TargetRegisterClass *WaveMaskRegClass = TRI->getWaveMaskRegClass();
const TargetRegisterClass *DstRegClass = MRI.getRegClass(DstReg);
@@ -6154,9 +6165,18 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
BuildMI(*ComputeLoop, I, DL, TII->get(SFFOpc), FF1Reg)
.addReg(ActiveBitsReg);
if (is32BitOpc || is16BitOpc) {
+ Register ReadLaneSrc = SrcReg;
+ if (useRealTrue16) {
+ // Copy the 16-bit src to a 32-bit vgpr for the v_readlane
+ Register SrcReg32 =
+ MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::COPY), SrcReg32)
+ .addReg(SrcReg);
+ ReadLaneSrc = SrcReg32;
+ }
BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::V_READLANE_B32),
LaneValueReg)
- .addReg(SrcReg)
+ .addReg(ReadLaneSrc)
.addReg(FF1Reg);
if (is16BitOpc) {
Register LaneValVgpr = MRI.createVirtualRegister(SrcRegClass);
@@ -6167,20 +6187,30 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
.addReg(LaneValueReg);
auto OpInstr =
BuildMI(*ComputeLoop, I, DL, TII->get(Opc), VgprResultReg);
- if (isGFX10)
+ if (isGFX10 || useRealTrue16)
OpInstr.addImm(SISrcMods::NONE); // src0 modifier
OpInstr.addReg(AccumulatorReg); // src0
- if (isGFX10)
+ if (isGFX10 || useRealTrue16)
OpInstr.addImm(SISrcMods::NONE); // src1 modifier
OpInstr.addReg(LaneValVgpr); // src1
- if (isGFX10) {
+ if (isGFX10)
OpInstr.addImm(0); // omod
+ if (isGFX10 || useRealTrue16)
OpInstr.addImm(0); // opsel
+ Register ReadFirstLaneSrc = VgprResultReg;
+ if (useRealTrue16) {
+ // Copy the 16-bit src to a 32-bit vgpr for the v_readlane
+ Register VgprResultReg32 =
+ MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::COPY),
+ VgprResultReg32)
+ .addReg(VgprResultReg);
+ ReadFirstLaneSrc = VgprResultReg32;
}
NewAccumulator =
BuildMI(*ComputeLoop, I, DL,
TII->get(AMDGPU::V_READFIRSTLANE_B32), DstReg)
- .addReg(VgprResultReg);
+ .addReg(ReadFirstLaneSrc);
} else if (isFPOp) {
Register LaneValVreg =
MRI.createVirtualRegister(MRI.getRegClass(SrcReg));
@@ -6735,6 +6765,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
const DebugLoc &DL = MI.getDebugLoc();
switch (MI.getOpcode()) {
+ case AMDGPU::WAVE_REDUCE_UMIN_PSEUDO_U16_t16:
+ return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_MIN_U16_t16_e64);
case AMDGPU::WAVE_REDUCE_UMIN_PSEUDO_U16:
return lowerWaveReduce(MI, *BB, *getSubtarget(),
ST.getGeneration() == AMDGPUSubtarget::GFX10
@@ -6742,6 +6774,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
: ST.hasTrue16BitInsts()
? AMDGPU::V_MIN_U16_fake16_e64
: AMDGPU::V_MIN_U16_e64);
+ case AMDGPU::WAVE_REDUCE_MIN_PSEUDO_I16_t16:
+ return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_MIN_I16_t16_e64);
case AMDGPU::WAVE_REDUCE_MIN_PSEUDO_I16:
return lowerWaveReduce(MI, *BB, *getSubtarget(),
ST.getGeneration() == AMDGPUSubtarget::GFX10
@@ -6749,6 +6783,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
: ST.hasTrue16BitInsts()
? AMDGPU::V_MIN_I16_fake16_e64
: AMDGPU::V_MIN_I16_e64);
+ case AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U16_t16:
+ return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_MAX_U16_t16_e64);
case AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U16:
return lowerWaveReduce(MI, *BB, *getSubtarget(),
ST.getGeneration() == AMDGPUSubtarget::GFX10
@@ -6756,6 +6792,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
: ST.hasTrue16BitInsts()
? AMDGPU::V_MAX_U16_fake16_e64
: AMDGPU::V_MAX_U16_e64);
+ case AMDGPU::WAVE_REDUCE_MAX_PSEUDO_I16_t16:
+ return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_MAX_I16_t16_e64);
case AMDGPU::WAVE_REDUCE_MAX_PSEUDO_I16:
return lowerWaveReduce(MI, *BB, *getSubtarget(),
ST.getGeneration() == AMDGPUSubtarget::GFX10
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 42a99233132cb..2d0d9ce0ea1b7 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -350,8 +350,10 @@ def : GCNPat<(i32 (int_amdgcn_set_inactive_chain_arg i32:$src, i32:$inactive)),
// clang-format off
multiclass
- AMDGPUWaveReducePseudoGenerator<string Op, string DataType, ValueType ty, RegisterClass RetReg, SrcRegOrImm9 Reg> {
- let usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0, UseNamedOperandTable = 1, Uses = [EXEC] in {
+ AMDGPUWaveReducePseudoGenerator<string Op, string DataType, ValueType ty, RegisterClass RetReg,
+ SrcRegOrImm9 Reg, True16PredicateClass T16Pred = NoTrue16Predicate> {
+ let usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+ UseNamedOperandTable = 1, Uses = [EXEC], True16Predicate = T16Pred in {
def !toupper(Op) #"_PSEUDO_" #DataType
: VPseudoInstSI<(outs RetReg : $sdst),
(ins Reg : $src, i32imm : $strategy),
@@ -361,12 +363,14 @@ multiclass
// clang-format on
class WaveReduceOp<string OpName, string TypeStr, ValueType Ty,
- RegisterClass ReturnRegisterClass, SrcRegOrImm9 RC> {
+ RegisterClass ReturnRegisterClass, SrcRegOrImm9 RC,
+ True16PredicateClass T16Pred = NoTrue16Predicate> {
string Name = OpName;
string TypeString = TypeStr;
ValueType VT = Ty;
RegisterClass RetReg = ReturnRegisterClass;
SrcRegOrImm9 Reg = RC;
+ True16PredicateClass T16Predicate = T16Pred;
}
// Input list : [Operation_name,
@@ -404,15 +408,20 @@ defvar Operations = [
WaveReduceOp<"fsub", "F32", f32, SGPR_32, VSrc_b32>,
WaveReduceOp<"fsub", "F64", f64, SGPR_64, VSrc_b64>,
- WaveReduceOp<"umin", "U16", i16, SGPR_32, VSrc_b16>,
- WaveReduceOp<"min", "I16", i16, SGPR_32, VSrc_b16>,
- WaveReduceOp<"umax", "U16", i16, SGPR_32, VSrc_b16>,
- WaveReduceOp<"max", "I16", i16, SGPR_32, VSrc_b16>
+ WaveReduceOp<"umin", "U16", i16, SGPR_32, VSrc_b16, NotUseRealTrue16Insts>,
+ WaveReduceOp<"min", "I16", i16, SGPR_32, VSrc_b16, NotUseRealTrue16Insts>,
+ WaveReduceOp<"umax", "U16", i16, SGPR_32, VSrc_b16, NotUseRealTrue16Insts>,
+ WaveReduceOp<"max", "I16", i16, SGPR_32, VSrc_b16, NotUseRealTrue16Insts>,
+ WaveReduceOp<"umin", "U16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>,
+ WaveReduceOp<"min", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>,
+ WaveReduceOp<"umax", "U16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>,
+ WaveReduceOp<"max", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>
];
foreach Op = Operations in {
defm WAVE_REDUCE_ : AMDGPUWaveReducePseudoGenerator<Op.Name, Op.TypeString,
- Op.VT, Op.RetReg, Op.Reg>;
+ Op.VT, Op.RetReg, Op.Reg,
+ Op.T16Predicate>;
}
let usesCustomInserter = 1, Defs = [VCC] in {
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
index a9621efdb15ff..7276ef9a9b681 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
@@ -7,10 +7,14 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s
define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX8DAGISEL-LABEL: uniform_value_i16:
@@ -80,52 +84,100 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX10GISEL-NEXT: global_store_short v1, v0, s[0:1]
; GFX10GISEL-NEXT: s_endpgm
;
-; GFX1164DAGISEL-LABEL: uniform_value_i16:
-; GFX1164DAGISEL: ; %bb.0: ; %entry
-; GFX1164DAGISEL-NEXT: s_clause 0x1
-; GFX1164DAGISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v1, s2
-; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX1164DAGISEL-NEXT: s_endpgm
-;
-; GFX1164GISEL-LABEL: uniform_value_i16:
-; GFX1164GISEL: ; %bb.0: ; %entry
-; GFX1164GISEL-NEXT: s_clause 0x1
-; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_and_b32 s2, 0xffff, s2
-; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-NEXT: s_endpgm
-;
-; GFX1132DAGISEL-LABEL: uniform_value_i16:
-; GFX1132DAGISEL: ; %bb.0: ; %entry
-; GFX1132DAGISEL-NEXT: s_clause 0x1
-; GFX1132DAGISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132DAGISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX1132DAGISEL-NEXT: s_endpgm
-;
-; GFX1132GISEL-LABEL: uniform_value_i16:
-; GFX1132GISEL: ; %bb.0: ; %entry
-; GFX1132GISEL-NEXT: s_clause 0x1
-; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_and_b32 s2, 0xffff, s2
-; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-NEXT: s_endpgm
+; GFX1164DAGISEL-FAKE16-LABEL: uniform_value_i16:
+; GFX1164DAGISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1164DAGISEL-FAKE16-NEXT: s_clause 0x1
+; GFX1164DAGISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1164DAGISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0
+; GFX1164DAGISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164DAGISEL-FAKE16-NEXT: v_mov_b32_e32 v1, s2
+; GFX1164DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX1164DAGISEL-FAKE16-NEXT: s_endpgm
+;
+; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16:
+; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1
+; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1164GISEL-FAKE16-NEXT: s_endpgm
+;
+; GFX1132DAGISEL-FAKE16-LABEL: uniform_value_i16:
+; GFX1132DAGISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1132DAGISEL-FAKE16-NEXT: s_clause 0x1
+; GFX1132DAGISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132DAGISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132DAGISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132DAGISEL-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1132DAGISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX1132DAGISEL-FAKE16-NEXT: s_endpgm
+;
+; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16:
+; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry
+; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1
+; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1132GISEL-FAKE16-NEXT: s_endpgm
+;
+; GFX1164DAGISEL-TRUE16-LABEL: uniform_value_i16:
+; GFX1164DAGISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1164DAGISEL-TRUE16-NEXT: s_clause 0x1
+; GFX1164DAGISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1164DAGISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164DAGISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1164DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1164DAGISEL-TRUE16-NEXT: s_endpgm
+;
+; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16:
+; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1
+; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1164GISEL-TRUE16-NEXT: s_endpgm
+;
+; GFX1132DAGISEL-TRUE16-LABEL: uniform_value_i16:
+; GFX1132DAGISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1132DAGISEL-TRUE16-NEXT: s_clause 0x1
+; GFX1132DAGISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132DAGISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1132DAGISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132DAGISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1132DAGISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1132DAGISEL-TRUE16-NEXT: s_endpgm
+;
+; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16:
+; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry
+; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1
+; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/194809
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