[llvm-branch-commits] [llvm] [AMDGPU] Support Wave Reduction for true-16 types - 3 (PR #194813)

via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Wed Apr 29 01:16:45 PDT 2026 

https://github.com/easyonaadit created https://github.com/llvm/llvm-project/pull/194813

Supporting true-16 versions of the reduction intrinsics
Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.

>From 23d958224c73e68c841f8dbf57cb23ed618a50e9 Mon Sep 17 00:00:00 2001
From: Aaditya <Aaditya.AlokDeshpande at amd.com>
Date: Tue, 28 Apr 2026 15:48:13 +0530
Subject: [PATCH] [AMDGPU] Support Wave Reduction for true-16 types - 3

Supporting true-16 versions of the reduction intrinsics
Supported Ops: `and`, `or`, `xor`.
Supports only the iterative stratergy, DPP is yet
to be supported.
---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp     | 23 ++++++++++++++++---
 llvm/lib/Target/AMDGPU/SIInstructions.td      |  5 +++-
 .../CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll  |  8 +++++++
 .../CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll   |  8 +++++++
 .../CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll  |  8 +++++++
 5 files changed, 48 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index d5285f12f0e82..867df937f38ea 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5632,6 +5632,7 @@ static uint64_t getIdentityValueForWaveReduction(unsigned Opc) {
   case AMDGPU::V_MIN_U16_fake16_e64:
   case AMDGPU::V_MIN_U16_t16_e64:
   case AMDGPU::V_AND_B16_fake16_e64:
+  case AMDGPU::V_AND_B16_t16_e64:
     return 0xffff;
   case AMDGPU::V_MIN_I16_e64:
   case AMDGPU::V_MIN_I16_opsel_e64:
@@ -5649,7 +5650,9 @@ static uint64_t getIdentityValueForWaveReduction(unsigned Opc) {
   case AMDGPU::V_ADD_I16_t16_e64:
   case AMDGPU::V_SUB_I16_t16_e64:
   case AMDGPU::V_OR_B16_fake16_e64:
+  case AMDGPU::V_OR_B16_t16_e64:
   case AMDGPU::V_XOR_B16_fake16_e64:
+  case AMDGPU::V_XOR_B16_t16_e64:
     return 0x0;
   case AMDGPU::V_MAX_I16_e64:
   case AMDGPU::V_MAX_I16_opsel_e64:
@@ -5721,8 +5724,11 @@ static bool is16bitWaveReduceOperation(unsigned Opc) {
          Opc == AMDGPU::V_SUB_I16_e64 || Opc == AMDGPU::V_SUB_I16_fake16_e64 ||
          Opc == AMDGPU::V_ADD_I16_t16_e64 || Opc == AMDGPU::V_SUB_I16_t16_e64 ||
          Opc == AMDGPU::V_AND_B16_fake16_e64 ||
+         Opc == AMDGPU::V_AND_B16_t16_e64 ||
          Opc == AMDGPU::V_OR_B16_fake16_e64 ||
-         Opc == AMDGPU::V_XOR_B16_fake16_e64;
+         Opc == AMDGPU::V_OR_B16_t16_e64 ||
+         Opc == AMDGPU::V_XOR_B16_fake16_e64 ||
+         Opc == AMDGPU::V_XOR_B16_t16_e64;
 }
 
 static bool is32bitWaveReduceOperation(unsigned Opc) {
@@ -5896,8 +5902,10 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
     case AMDGPU::S_MAX_I32:
     case AMDGPU::V_MAX_F32_e64:
     case AMDGPU::V_AND_B16_fake16_e64:
-    case AMDGPU::V_OR_B16_fake16_e64:
+    case AMDGPU::V_AND_B16_t16_e64:
     case AMDGPU::S_AND_B32:
+    case AMDGPU::V_OR_B16_fake16_e64:
+    case AMDGPU::V_OR_B16_t16_e64:
     case AMDGPU::S_OR_B32: {
       // Idempotent operations.
       BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B32), DstReg).addReg(SrcReg);
@@ -5920,6 +5928,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
       break;
     }
     case AMDGPU::V_XOR_B16_fake16_e64:
+    case AMDGPU::V_XOR_B16_t16_e64:
     case AMDGPU::S_XOR_B32:
     case AMDGPU::S_XOR_B64:
     case AMDGPU::V_ADD_I16_e64:
@@ -5956,6 +5965,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
 
       switch (Opc) {
       case AMDGPU::V_XOR_B16_fake16_e64:
+      case AMDGPU::V_XOR_B16_t16_e64:
       case AMDGPU::S_XOR_B32:
       case AMDGPU::S_XOR_B64: {
         // Performing an XOR operation on a uniform value
@@ -5969,7 +5979,8 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
             .addReg(NewAccumulator->getOperand(0).getReg())
             .addImm(1)
             .setOperandDead(3); // Dead scc
-        if (Opc == AMDGPU::S_XOR_B32 || Opc == AMDGPU::V_XOR_B16_fake16_e64) {
+        if (Opc == AMDGPU::S_XOR_B32 || Opc == AMDGPU::V_XOR_B16_fake16_e64 ||
+            Opc == AMDGPU::V_XOR_B16_t16_e64) {
           BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), DstReg)
               .addReg(SrcReg)
               .addReg(ParityRegister);
@@ -6911,6 +6922,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
                            ST.getGeneration() >= AMDGPUSubtarget::GFX12
                                ? AMDGPU::V_ADD_F64_pseudo_e64
                                : AMDGPU::V_ADD_F64_e64);
+  case AMDGPU::WAVE_REDUCE_AND_PSEUDO_B16_t16:
+    return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_AND_B16_t16_e64);
   case AMDGPU::WAVE_REDUCE_AND_PSEUDO_B16:
     return lowerWaveReduce(MI, *BB, *getSubtarget(),
                            ST.hasTrue16BitInsts() ? AMDGPU::V_AND_B16_fake16_e64
@@ -6919,6 +6932,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
     return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_AND_B32);
   case AMDGPU::WAVE_REDUCE_AND_PSEUDO_B64:
     return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_AND_B64);
+  case AMDGPU::WAVE_REDUCE_OR_PSEUDO_B16_t16:
+    return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_OR_B16_t16_e64);
   case AMDGPU::WAVE_REDUCE_OR_PSEUDO_B16:
     return lowerWaveReduce(MI, *BB, *getSubtarget(),
                            ST.hasTrue16BitInsts() ? AMDGPU::V_OR_B16_fake16_e64
@@ -6927,6 +6942,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
     return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_OR_B32);
   case AMDGPU::WAVE_REDUCE_OR_PSEUDO_B64:
     return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_OR_B64);
+  case AMDGPU::WAVE_REDUCE_XOR_PSEUDO_B16_t16:
+    return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_XOR_B16_t16_e64);
   case AMDGPU::WAVE_REDUCE_XOR_PSEUDO_B16:
     return lowerWaveReduce(MI, *BB, *getSubtarget(),
                            ST.hasTrue16BitInsts() ? AMDGPU::V_XOR_B16_fake16_e64
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 8d2432e680a5b..dd9715d7f2e67 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -422,7 +422,10 @@ defvar Operations = [
   WaveReduceOp<"umax", "U16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>,
   WaveReduceOp<"max", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>,
   WaveReduceOp<"add", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>,
-  WaveReduceOp<"sub", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>
+  WaveReduceOp<"sub", "I16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>,
+  WaveReduceOp<"and", "B16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>,
+  WaveReduceOp<"or", "B16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>,
+  WaveReduceOp<"xor", "B16_t16", i16, SGPR_32, VSrcT_b16, UseRealTrue16Insts>
 ];
 
 foreach Op = Operations in {
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
index 8e177bd30b3e4..7ee6d40589441 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
@@ -11,6 +11,10 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s
 
 define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i32 %in) {
 ; GFX8DAGISEL-LABEL: uniform_value_i16:
@@ -3476,6 +3480,10 @@ endif:
 }
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; GFX1132DAGISEL-FAKE16: {{.*}}
+; GFX1132DAGISEL-TRUE16: {{.*}}
 ; GFX1132GISEL-FAKE16: {{.*}}
+; GFX1132GISEL-TRUE16: {{.*}}
 ; GFX1164DAGISEL-FAKE16: {{.*}}
+; GFX1164DAGISEL-TRUE16: {{.*}}
 ; GFX1164GISEL-FAKE16: {{.*}}
+; GFX1164GISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
index 1db97e35a4edf..5a2f8838f6956 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
@@ -11,6 +11,10 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s
 
 define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i32 %in) {
 ; GFX8DAGISEL-LABEL: uniform_value_i16:
@@ -3477,6 +3481,10 @@ endif:
 }
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; GFX1132DAGISEL-FAKE16: {{.*}}
+; GFX1132DAGISEL-TRUE16: {{.*}}
 ; GFX1132GISEL-FAKE16: {{.*}}
+; GFX1132GISEL-TRUE16: {{.*}}
 ; GFX1164DAGISEL-FAKE16: {{.*}}
+; GFX1164DAGISEL-TRUE16: {{.*}}
 ; GFX1164GISEL-FAKE16: {{.*}}
+; GFX1164GISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
index 92c453ae673db..6d304aeba942f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
@@ -11,6 +11,10 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-FAKE16 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-FAKE16 %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL,GFX1164DAGISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL,GFX1164GISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL,GFX1132DAGISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL,GFX1132GISEL-TRUE16 %s
 
 define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i32 %in) {
 ; GFX8DAGISEL-LABEL: uniform_value_i16:
@@ -3988,6 +3992,10 @@ endif:
 }
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; GFX1132DAGISEL-FAKE16: {{.*}}
+; GFX1132DAGISEL-TRUE16: {{.*}}
 ; GFX1132GISEL-FAKE16: {{.*}}
+; GFX1132GISEL-TRUE16: {{.*}}
 ; GFX1164DAGISEL-FAKE16: {{.*}}
+; GFX1164DAGISEL-TRUE16: {{.*}}
 ; GFX1164GISEL-FAKE16: {{.*}}
+; GFX1164GISEL-TRUE16: {{.*}}

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