[llvm-branch-commits] [llvm] Reapply "AMDGPU: Implement getInstSizeVerifyMode" (#194026) (PR #194362)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/194362

This reverts commit 72ca372fa7c9029d2b7a77c59a4cc24530e99e43.

>From 1b1f123c6c0e7cfeb8d63239f44cd3f707fdaaa9 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 24 Apr 2026 20:30:40 +0100
Subject: [PATCH] Reapply "AMDGPU: Implement getInstSizeVerifyMode" (#194026)

This reverts commit 72ca372fa7c9029d2b7a77c59a4cc24530e99e43.
---
 llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp | 22 --------------------
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp       |  7 +++++++
 llvm/lib/Target/AMDGPU/SIInstrInfo.h         |  3 +++
 3 files changed, 10 insertions(+), 22 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
index 56592bde3b1c7..592d1ad6d9195 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
@@ -456,28 +456,6 @@ void AMDGPUAsmPrinter::emitInstruction(const MachineInstr *MI) {
     MCInstLowering.lower(MI, TmpInst);
     EmitToStreamer(*OutStreamer, TmpInst);
 
-#ifdef EXPENSIVE_CHECKS
-    // Check getInstSizeInBytes on explicitly specified CPUs (it cannot
-    // work correctly for the generic CPU).
-    //
-    // The isPseudo check really shouldn't be here, but unfortunately there are
-    // some negative lit tests that depend on being able to continue through
-    // here even when pseudo instructions haven't been lowered.
-    //
-    // We also overestimate branch sizes with the offset bug.
-    if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU()) &&
-        (!STI.hasOffset3fBug() || !MI->isBranch())) {
-      SmallVector<MCFixup, 4> Fixups;
-      SmallVector<char, 16> CodeBytes;
-
-      std::unique_ptr<MCCodeEmitter> InstEmitter(createAMDGPUMCCodeEmitter(
-          *STI.getInstrInfo(), OutContext));
-      InstEmitter->encodeInstruction(TmpInst, CodeBytes, Fixups, STI);
-
-      assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI));
-    }
-#endif
-
     if (DumpCodeInstEmitter) {
       // Disassemble instruction/operands to text
       DisasmLines.resize(DisasmLines.size() + 1);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 77b0eac77fc51..0185082d428f0 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -10002,6 +10002,13 @@ unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   }
 }
 
+TargetInstrInfo::InstSizeVerifyMode
+SIInstrInfo::getInstSizeVerifyMode(const MachineInstr &MI) const {
+  if (MI.isBranch() && ST.hasOffset3fBug())
+    return InstSizeVerifyMode::NoVerify;
+  return InstSizeVerifyMode::ExactSize;
+}
+
 bool SIInstrInfo::mayAccessFlatAddressSpace(const MachineInstr &MI) const {
   if (!isFLAT(MI))
     return false;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 1b9396a1bff11..17a71d3b68ee2 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1614,6 +1614,9 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
 
   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
 
+  InstSizeVerifyMode
+  getInstSizeVerifyMode(const MachineInstr &MI) const override;
+
   bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
 
   std::pair<unsigned, unsigned>