[llvm-branch-commits] [llvm] [X86] lowerV4F32Shuffle - don't use INSERTPS if SHUFPS will suffice (#186468) (PR #194332)
Simon Pilgrim via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Apr 27 03:19:07 PDT 2026
https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/194332
Manual cherry-pick of #186468 into 22.x
If we have 2 or more undef/undemanded elements, the INSERTPS replaces those with explicit zero'd elements which can cause infinite loops later on in shuffle combining depending on whether we demand those elements or not.
I'll try to improve the (minor) v2f32 regressions in a follow up, but I need to fix the infinite loop first.
Fixes #186403 #194132
>From d003f9a97ffa415e6497de91d10be1ae3e31fff4 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Fri, 13 Mar 2026 19:31:20 +0000
Subject: [PATCH] [X86] lowerV4F32Shuffle - don't use INSERTPS if SHUFPS will
suffice (#186468)
If we have 2 or more undef/undemanded elements, the INSERTPS replaces
those with explicit zero'd elements which can cause infinite loops later
on in shuffle combining depending on whether we demand those elements or
not.
I'll try to improve the (minor) v2f32 regressions in a follow up, but I
need to fix the infinite loop first.
Fixes #186403
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 13 +-
llvm/test/CodeGen/X86/avx2-masked-gather.ll | 12 +-
.../X86/masked_gather_scatter_widen.ll | 3 +-
llvm/test/CodeGen/X86/masked_store_trunc.ll | 12 +-
.../CodeGen/X86/masked_store_trunc_ssat.ll | 12 +-
.../CodeGen/X86/masked_store_trunc_usat.ll | 12 +-
.../vector-interleaved-load-i16-stride-7.ll | 60 ++++-----
.../vector-interleaved-store-i16-stride-7.ll | 28 ++--
.../vector-interleaved-store-i32-stride-5.ll | 64 ++++-----
.../vector-interleaved-store-i32-stride-7.ll | 126 +++++++++---------
.../test/CodeGen/X86/vector-shuffle-128-v4.ll | 34 ++---
.../X86/vector-shuffle-combining-sse41.ll | 41 ++++++
.../CodeGen/X86/vector-shuffle-combining.ll | 59 +++-----
13 files changed, 239 insertions(+), 237 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 5935f2eb344e1..cc255251ee235 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -13915,19 +13915,18 @@ static SDValue lowerV4F32Shuffle(const SDLoc &DL, ArrayRef<int> Mask,
// when the V2 input is targeting element 0 of the mask -- that is the fast
// case here.
if (NumV2Elements == 1 && Mask[0] >= 4)
- if (SDValue V = lowerShuffleAsElementInsertion(
- DL, MVT::v4f32, V1, V2, Mask, Zeroable, Subtarget, DAG))
+ if (SDValue V = lowerShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2, Mask,
+ Zeroable, Subtarget, DAG))
return V;
- if (Subtarget.hasSSE41()) {
+ if (Subtarget.hasSSE41() && !isSingleSHUFPSMask(Mask)) {
// Use INSERTPS if we can complete the shuffle efficiently.
if (SDValue V = lowerShuffleAsInsertPS(DL, V1, V2, Mask, Zeroable, DAG))
return V;
- if (!isSingleSHUFPSMask(Mask))
- if (SDValue BlendPerm = lowerShuffleAsBlendAndPermute(DL, MVT::v4f32, V1,
- V2, Mask, DAG))
- return BlendPerm;
+ if (SDValue BlendPerm =
+ lowerShuffleAsBlendAndPermute(DL, MVT::v4f32, V1, V2, Mask, DAG))
+ return BlendPerm;
}
// Use low/high mov instructions. These are only valid in SSE1 because
diff --git a/llvm/test/CodeGen/X86/avx2-masked-gather.ll b/llvm/test/CodeGen/X86/avx2-masked-gather.ll
index 2429536bdb15f..169c0313d6a45 100644
--- a/llvm/test/CodeGen/X86/avx2-masked-gather.ll
+++ b/llvm/test/CodeGen/X86/avx2-masked-gather.ll
@@ -9,7 +9,8 @@ declare <2 x i32> @llvm.masked.gather.v2i32(<2 x ptr> %ptrs, i32 %align, <2 x i1
define <2 x i32> @masked_gather_v2i32(ptr %ptr, <2 x i1> %masks, <2 x i32> %passthro) {
; X86-LABEL: masked_gather_v2i32:
; X86: # %bb.0: # %entry
-; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
+; X86-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[2,3]
; X86-NEXT: vpslld $31, %xmm0, %xmm0
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
@@ -58,7 +59,8 @@ entry:
define <4 x i32> @masked_gather_v2i32_concat(ptr %ptr, <2 x i1> %masks, <2 x i32> %passthro) {
; X86-LABEL: masked_gather_v2i32_concat:
; X86: # %bb.0: # %entry
-; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
+; X86-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[2,3]
; X86-NEXT: vpslld $31, %xmm0, %xmm0
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
@@ -110,7 +112,8 @@ declare <2 x float> @llvm.masked.gather.v2float(<2 x ptr> %ptrs, i32 %align, <2
define <2 x float> @masked_gather_v2float(ptr %ptr, <2 x i1> %masks, <2 x float> %passthro) {
; X86-LABEL: masked_gather_v2float:
; X86: # %bb.0: # %entry
-; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
+; X86-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[2,3]
; X86-NEXT: vpslld $31, %xmm0, %xmm0
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
@@ -160,7 +163,8 @@ entry:
define <4 x float> @masked_gather_v2float_concat(ptr %ptr, <2 x i1> %masks, <2 x float> %passthro) {
; X86-LABEL: masked_gather_v2float_concat:
; X86: # %bb.0: # %entry
-; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
+; X86-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[2,3]
; X86-NEXT: vpslld $31, %xmm0, %xmm0
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
diff --git a/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll b/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
index 5b5280601ea71..b4cab9a325c93 100644
--- a/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
+++ b/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
@@ -353,7 +353,8 @@ define <2 x i32> @test_gather_v2i32_data_index(ptr %base, <2 x i32> %ind, <2 x i
;
; WIDEN_AVX2-LABEL: test_gather_v2i32_data_index:
; WIDEN_AVX2: # %bb.0:
-; WIDEN_AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero
+; WIDEN_AVX2-NEXT: vxorps %xmm3, %xmm3, %xmm3
+; WIDEN_AVX2-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm3[2,3]
; WIDEN_AVX2-NEXT: vpslld $31, %xmm1, %xmm1
; WIDEN_AVX2-NEXT: vpgatherdd %xmm1, (%rdi,%xmm0,4), %xmm2
; WIDEN_AVX2-NEXT: vmovdqa %xmm2, %xmm0
diff --git a/llvm/test/CodeGen/X86/masked_store_trunc.ll b/llvm/test/CodeGen/X86/masked_store_trunc.ll
index ecf4fbb603a8f..3116649d85677 100644
--- a/llvm/test/CodeGen/X86/masked_store_trunc.ll
+++ b/llvm/test/CodeGen/X86/masked_store_trunc.ll
@@ -1808,9 +1808,9 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, ptr %p, <2 x i64> %mask) {
; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpcmpeqq %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero
+; AVX1-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
+; AVX1-NEXT: vpxor %xmm3, %xmm1, %xmm1
+; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[2,3]
; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX1-NEXT: vmaskmovps %xmm0, %xmm1, (%rdi)
; AVX1-NEXT: retq
@@ -1819,9 +1819,9 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, ptr %p, <2 x i64> %mask) {
; AVX2: # %bb.0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpcmpeqq %xmm2, %xmm1, %xmm1
-; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm1
-; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero
+; AVX2-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
+; AVX2-NEXT: vpxor %xmm3, %xmm1, %xmm1
+; AVX2-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[2,3]
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX2-NEXT: vpmaskmovd %xmm0, %xmm1, (%rdi)
; AVX2-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll b/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
index 57b0577ac7cc9..2e0f0c30056af 100644
--- a/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
+++ b/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
@@ -2603,9 +2603,9 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, ptr %p, <2 x i64> %mask) {
; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpcmpeqq %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero
+; AVX1-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
+; AVX1-NEXT: vpxor %xmm3, %xmm1, %xmm1
+; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[2,3]
; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [2147483647,2147483647]
; AVX1-NEXT: # xmm2 = mem[0,0]
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm3
@@ -2622,9 +2622,9 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, ptr %p, <2 x i64> %mask) {
; AVX2: # %bb.0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpcmpeqq %xmm2, %xmm1, %xmm1
-; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm1
-; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero
+; AVX2-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
+; AVX2-NEXT: vpxor %xmm3, %xmm1, %xmm1
+; AVX2-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[2,3]
; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm2 = [2147483647,2147483647]
; AVX2-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm3
; AVX2-NEXT: vblendvpd %xmm3, %xmm0, %xmm2, %xmm0
diff --git a/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll b/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
index 0386d9531723d..a49916cbb854c 100644
--- a/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
+++ b/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
@@ -2278,9 +2278,9 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, ptr %p, <2 x i64> %mask) {
; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpcmpeqq %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero
+; AVX1-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
+; AVX1-NEXT: vpxor %xmm3, %xmm1, %xmm1
+; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[2,3]
; AVX1-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; AVX1-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vblendvpd %xmm2, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
@@ -2292,9 +2292,9 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, ptr %p, <2 x i64> %mask) {
; AVX2: # %bb.0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpcmpeqq %xmm2, %xmm1, %xmm1
-; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
-; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm1
-; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero
+; AVX2-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
+; AVX2-NEXT: vpxor %xmm3, %xmm1, %xmm1
+; AVX2-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[2,3]
; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX2-NEXT: vblendvpd %xmm2, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll b/llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
index e89248a5474c7..f9b06d6f55d59 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
@@ -1220,7 +1220,7 @@ define void @load_i16_stride7_vf8(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
; AVX-NEXT: vpshufd {{.*#+}} xmm9 = xmm0[0,1,0,3]
; AVX-NEXT: vpshufhw {{.*#+}} xmm9 = xmm9[0,1,2,3,4,7,6,7]
; AVX-NEXT: vpunpckhdq {{.*#+}} xmm8 = xmm9[2],xmm8[2],xmm9[3],xmm8[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm9 = zero,xmm5[2],xmm7[2],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm9 = xmm5[2,2],xmm7[2,2]
; AVX-NEXT: vpblendw {{.*#+}} xmm8 = xmm8[0,1,2],xmm9[3,4],xmm8[5,6,7]
; AVX-NEXT: vpblendw {{.*#+}} xmm6 = xmm8[0,1,2,3,4],xmm6[5,6,7]
; AVX-NEXT: vpsrld $16, %xmm2, %xmm8
@@ -2450,7 +2450,7 @@ define void @load_i16_stride7_vf16(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vpunpckhdq {{.*#+}} xmm15 = xmm14[2],xmm13[2],xmm14[3],xmm13[3]
; AVX-NEXT: vmovaps 32(%rdi), %xmm1
; AVX-NEXT: vmovaps 48(%rdi), %xmm13
-; AVX-NEXT: vinsertps {{.*#+}} xmm9 = zero,xmm1[2],xmm13[2],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm9 = xmm1[2,2],xmm13[2,2]
; AVX-NEXT: vmovaps %xmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpblendw {{.*#+}} xmm9 = xmm15[0,1,2],xmm9[3,4],xmm15[5,6,7]
@@ -2656,8 +2656,8 @@ define void @load_i16_stride7_vf16(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vandps %ymm1, %ymm9, %ymm1
; AVX-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; AVX-NEXT: vinsertps $41, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 16-byte Folded Reload
-; AVX-NEXT: # xmm1 = zero,xmm1[1],mem[0],zero
+; AVX-NEXT: vshufps $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 16-byte Folded Reload
+; AVX-NEXT: # xmm1 = xmm1[1,1],mem[1,1]
; AVX-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm5[2],xmm15[2],xmm5[3],xmm15[3]
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm5[0,1,2],xmm1[3,4],xmm5[5,6,7]
; AVX-NEXT: vpblendw {{.*#+}} xmm5 = xmm2[0],xmm6[1],xmm2[2,3,4,5,6,7]
@@ -4980,7 +4980,7 @@ define void @load_i16_stride7_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vpunpckhdq {{.*#+}} xmm0 = xmm3[2],xmm0[2],xmm3[3],xmm0[3]
; AVX-NEXT: vmovaps 32(%rdi), %xmm6
; AVX-NEXT: vmovaps 48(%rdi), %xmm7
-; AVX-NEXT: vinsertps {{.*#+}} xmm3 = zero,xmm6[2],xmm7[2],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm3 = xmm6[2,2],xmm7[2,2]
; AVX-NEXT: vmovaps %xmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vmovaps %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpblendw {{.*#+}} xmm3 = xmm0[0,1,2],xmm3[3,4],xmm0[5,6,7]
@@ -5021,9 +5021,9 @@ define void @load_i16_stride7_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vpshufd {{.*#+}} xmm3 = xmm14[2,2,3,3]
; AVX-NEXT: vmovdqa %xmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpunpckhdq {{.*#+}} xmm2 = xmm2[2],xmm3[2],xmm2[3],xmm3[3]
-; AVX-NEXT: vmovaps 256(%rdi), %xmm5
-; AVX-NEXT: vmovaps 272(%rdi), %xmm11
-; AVX-NEXT: vinsertps {{.*#+}} xmm3 = zero,xmm5[2],xmm11[2],zero
+; AVX-NEXT: vmovaps 272(%rdi), %xmm5
+; AVX-NEXT: vmovaps 256(%rdi), %xmm11
+; AVX-NEXT: vshufps {{.*#+}} xmm3 = xmm11[2,2],xmm5[2,2]
; AVX-NEXT: vmovaps %xmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vmovaps %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[3,4],xmm2[5,6,7]
@@ -5105,7 +5105,7 @@ define void @load_i16_stride7_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm9 # 16-byte Reload
; AVX-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm9[0],xmm1[0],xmm9[1],xmm1[1],xmm9[2],xmm1[2],xmm9[3],xmm1[3]
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
-; AVX-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm5[4],xmm11[4],xmm5[5],xmm11[5],xmm5[6],xmm11[6],xmm5[7],xmm11[7]
+; AVX-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm11[4],xmm5[4],xmm11[5],xmm5[5],xmm11[6],xmm5[6],xmm11[7],xmm5[7]
; AVX-NEXT: vpshufb %xmm4, %xmm1, %xmm1
; AVX-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm11 # 16-byte Reload
; AVX-NEXT: vpblendw {{.*#+}} xmm4 = xmm14[0],xmm11[1],xmm14[2,3,4,5,6,7]
@@ -5460,8 +5460,8 @@ define void @load_i16_stride7_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vandps %ymm4, %ymm2, %ymm2
; AVX-NEXT: vorps %ymm1, %ymm2, %ymm1
; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
-; AVX-NEXT: vinsertps $41, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2, %xmm2 # 16-byte Folded Reload
-; AVX-NEXT: # xmm2 = zero,xmm2[1],mem[0],zero
+; AVX-NEXT: vshufps $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm2, %xmm2 # 16-byte Folded Reload
+; AVX-NEXT: # xmm2 = xmm2[1,1],mem[1,1]
; AVX-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload
; AVX-NEXT: vpunpckhdq (%rsp), %xmm4, %xmm4 # 16-byte Folded Reload
; AVX-NEXT: # xmm4 = xmm4[2],mem[2],xmm4[3],mem[3]
@@ -5498,8 +5498,8 @@ define void @load_i16_stride7_vf32(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vandps %ymm4, %ymm11, %ymm4
; AVX-NEXT: vorps %ymm2, %ymm4, %ymm2
; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload
-; AVX-NEXT: vinsertps $41, {{[-0-9]+}}(%r{{[sb]}}p), %xmm4, %xmm4 # 16-byte Folded Reload
-; AVX-NEXT: # xmm4 = zero,xmm4[1],mem[0],zero
+; AVX-NEXT: vshufps $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm4, %xmm4 # 16-byte Folded Reload
+; AVX-NEXT: # xmm4 = xmm4[1,1],mem[1,1]
; AVX-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm5 # 16-byte Reload
; AVX-NEXT: vpunpckhdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm5, %xmm5 # 16-byte Folded Reload
; AVX-NEXT: # xmm5 = xmm5[2],mem[2],xmm5[3],mem[3]
@@ -10217,7 +10217,7 @@ define void @load_i16_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vmovaps 32(%rdi), %xmm3
; AVX-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vmovaps 48(%rdi), %xmm6
-; AVX-NEXT: vinsertps {{.*#+}} xmm3 = zero,xmm3[2],xmm6[2],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm3 = xmm3[2,2],xmm6[2,2]
; AVX-NEXT: vmovaps %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpblendw {{.*#+}} xmm3 = xmm0[0,1,2],xmm3[3,4],xmm0[5,6,7]
; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65535,65535,65535,65535,0,0,0,0,0,65535,65535,65535,65535,65535,65535]
@@ -10257,9 +10257,9 @@ define void @load_i16_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vmovdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,2,3,3]
; AVX-NEXT: vpunpckhdq {{.*#+}} xmm2 = xmm2[2],xmm3[2],xmm2[3],xmm3[3]
-; AVX-NEXT: vmovaps 480(%rdi), %xmm5
-; AVX-NEXT: vmovaps 496(%rdi), %xmm15
-; AVX-NEXT: vinsertps {{.*#+}} xmm3 = zero,xmm5[2],xmm15[2],zero
+; AVX-NEXT: vmovaps 496(%rdi), %xmm5
+; AVX-NEXT: vmovaps 480(%rdi), %xmm15
+; AVX-NEXT: vshufps {{.*#+}} xmm3 = xmm15[2,2],xmm5[2,2]
; AVX-NEXT: vmovaps %xmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vmovaps %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[3,4],xmm2[5,6,7]
@@ -10313,10 +10313,10 @@ define void @load_i16_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vpshufd {{.*#+}} xmm3 = xmm12[2,2,3,3]
; AVX-NEXT: vmovdqa %xmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpunpckhdq {{.*#+}} xmm2 = xmm2[2],xmm3[2],xmm2[3],xmm3[3]
-; AVX-NEXT: vmovaps 256(%rdi), %xmm9
; AVX-NEXT: vmovaps 272(%rdi), %xmm3
; AVX-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX-NEXT: vinsertps {{.*#+}} xmm3 = zero,xmm9[2],xmm3[2],zero
+; AVX-NEXT: vmovaps 256(%rdi), %xmm9
+; AVX-NEXT: vshufps {{.*#+}} xmm3 = xmm9[2,2],xmm3[2,2]
; AVX-NEXT: vmovaps %xmm9, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[3,4],xmm2[5,6,7]
; AVX-NEXT: vmovdqa 304(%rdi), %xmm4
@@ -10369,10 +10369,10 @@ define void @load_i16_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vmovdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,2,3,3]
; AVX-NEXT: vpunpckhdq {{.*#+}} xmm2 = xmm2[2],xmm3[2],xmm2[3],xmm3[3]
-; AVX-NEXT: vmovaps 704(%rdi), %xmm14
; AVX-NEXT: vmovaps 720(%rdi), %xmm3
; AVX-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX-NEXT: vinsertps {{.*#+}} xmm3 = zero,xmm14[2],xmm3[2],zero
+; AVX-NEXT: vmovaps 704(%rdi), %xmm14
+; AVX-NEXT: vshufps {{.*#+}} xmm3 = xmm14[2,2],xmm3[2,2]
; AVX-NEXT: vmovaps %xmm14, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[3,4],xmm2[5,6,7]
; AVX-NEXT: vmovdqa 752(%rdi), %xmm4
@@ -10457,7 +10457,7 @@ define void @load_i16_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; AVX-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
; AVX-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,5],xmm3[6,7]
-; AVX-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm5[4],xmm15[4],xmm5[5],xmm15[5],xmm5[6],xmm15[6],xmm5[7],xmm15[7]
+; AVX-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm15[4],xmm5[4],xmm15[5],xmm5[5],xmm15[6],xmm5[6],xmm15[7],xmm5[7]
; AVX-NEXT: vmovdqa %xmm4, %xmm1
; AVX-NEXT: vpshufb %xmm4, %xmm3, %xmm3
; AVX-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
@@ -11252,8 +11252,8 @@ define void @load_i16_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vorps %ymm3, %ymm4, %ymm3
; AVX-NEXT: vmovups %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX-NEXT: vmovaps (%rsp), %xmm4 # 16-byte Reload
-; AVX-NEXT: vinsertps $41, {{[-0-9]+}}(%r{{[sb]}}p), %xmm4, %xmm4 # 16-byte Folded Reload
-; AVX-NEXT: # xmm4 = zero,xmm4[1],mem[0],zero
+; AVX-NEXT: vshufps $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm4, %xmm4 # 16-byte Folded Reload
+; AVX-NEXT: # xmm4 = xmm4[1,1],mem[1,1]
; AVX-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 # 16-byte Reload
; AVX-NEXT: vpunpckhdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm3, %xmm5 # 16-byte Folded Reload
; AVX-NEXT: # xmm5 = xmm3[2],mem[2],xmm3[3],mem[3]
@@ -11292,8 +11292,8 @@ define void @load_i16_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vandnps %ymm4, %ymm3, %ymm4
; AVX-NEXT: vandps %ymm3, %ymm5, %ymm5
; AVX-NEXT: vorps %ymm4, %ymm5, %ymm4
-; AVX-NEXT: vinsertps $41, {{[-0-9]+}}(%r{{[sb]}}p), %xmm15, %xmm5 # 16-byte Folded Reload
-; AVX-NEXT: # xmm5 = zero,xmm15[1],mem[0],zero
+; AVX-NEXT: vshufps $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm15, %xmm5 # 16-byte Folded Reload
+; AVX-NEXT: # xmm5 = xmm15[1,1],mem[1,1]
; AVX-NEXT: vpunpckhdq {{.*#+}} xmm6 = xmm11[2],xmm14[2],xmm11[3],xmm14[3]
; AVX-NEXT: vpblendw {{.*#+}} xmm5 = xmm6[0,1,2],xmm5[3,4],xmm6[5,6,7]
; AVX-NEXT: vpblendw {{.*#+}} xmm6 = xmm2[0],xmm8[1],xmm2[2,3,4,5,6,7]
@@ -11322,8 +11322,8 @@ define void @load_i16_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vandps %ymm3, %ymm6, %ymm6
; AVX-NEXT: vorps %ymm5, %ymm6, %ymm5
; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; AVX-NEXT: vinsertps $41, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm6 # 16-byte Folded Reload
-; AVX-NEXT: # xmm6 = zero,xmm0[1],mem[0],zero
+; AVX-NEXT: vshufps $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm6 # 16-byte Folded Reload
+; AVX-NEXT: # xmm6 = xmm0[1,1],mem[1,1]
; AVX-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; AVX-NEXT: vpunpckhdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm7 # 16-byte Folded Reload
; AVX-NEXT: # xmm7 = xmm0[2],mem[2],xmm0[3],mem[3]
@@ -11362,8 +11362,8 @@ define void @load_i16_stride7_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, pt
; AVX-NEXT: vandps %ymm3, %ymm7, %ymm7
; AVX-NEXT: vorps %ymm6, %ymm7, %ymm6
; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; AVX-NEXT: vinsertps $41, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm7 # 16-byte Folded Reload
-; AVX-NEXT: # xmm7 = zero,xmm0[1],mem[0],zero
+; AVX-NEXT: vshufps $85, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm7 # 16-byte Folded Reload
+; AVX-NEXT: # xmm7 = xmm0[1,1],mem[1,1]
; AVX-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; AVX-NEXT: vpunpckhdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm8 # 16-byte Folded Reload
; AVX-NEXT: # xmm8 = xmm0[2],mem[2],xmm0[3],mem[3]
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
index fafb69be0d380..a4299ffe7a736 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
@@ -1097,7 +1097,7 @@ define void @store_i16_stride7_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX-NEXT: vandps %ymm7, %ymm8, %ymm7
; AVX-NEXT: vpsrldq {{.*#+}} xmm9 = xmm10[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX-NEXT: vpblendw {{.*#+}} xmm9 = xmm9[0,1,2],xmm1[3],xmm9[4,5,6,7]
-; AVX-NEXT: vshufps {{.*#+}} xmm10 = xmm10[0,2],xmm1[1,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm10 = xmm10[2,2],xmm1[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm9, %ymm10, %ymm9
; AVX-NEXT: vandnps %ymm9, %ymm8, %ymm8
; AVX-NEXT: vorps %ymm7, %ymm8, %ymm7
@@ -2141,7 +2141,7 @@ define void @store_i16_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm10[0],xmm5[0],xmm10[1],xmm5[1],xmm10[2],xmm5[2],xmm10[3],xmm5[3]
; AVX-NEXT: vpsrldq {{.*#+}} xmm11 = xmm4[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX-NEXT: vpblendw {{.*#+}} xmm11 = xmm11[0,1,2],xmm12[3],xmm11[4,5,6,7]
-; AVX-NEXT: vshufps {{.*#+}} xmm7 = xmm4[0,2],xmm12[1,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm7 = xmm4[2,2],xmm12[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm11, %ymm7, %ymm7
; AVX-NEXT: vmovaps {{.*#+}} ymm11 = [65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535]
; AVX-NEXT: vandps %ymm1, %ymm11, %ymm1
@@ -2169,7 +2169,7 @@ define void @store_i16_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vpslldq {{.*#+}} xmm7 = zero,zero,xmm8[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
; AVX-NEXT: vpshufd {{.*#+}} xmm11 = xmm13[0,1,0,1]
; AVX-NEXT: vpblendw {{.*#+}} xmm7 = xmm7[0,1,2,3,4],xmm11[5],xmm7[6,7]
-; AVX-NEXT: vshufps {{.*#+}} xmm11 = xmm8[0,2],xmm13[1,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm11 = xmm8[2,2],xmm13[1,1]
; AVX-NEXT: vmovaps %xmm8, %xmm14
; AVX-NEXT: vinsertf128 $1, %xmm11, %ymm7, %ymm7
; AVX-NEXT: vmovaps {{.*#+}} ymm11 = [65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535]
@@ -4421,7 +4421,7 @@ define void @store_i16_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm14[0],xmm0[0],xmm14[1],xmm0[1],xmm14[2],xmm0[2],xmm14[3],xmm0[3]
; AVX-NEXT: vpsrldq {{.*#+}} xmm15 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX-NEXT: vpblendw {{.*#+}} xmm15 = xmm15[0,1,2],xmm6[3],xmm15[4,5,6,7]
-; AVX-NEXT: vshufps {{.*#+}} xmm14 = xmm0[0,2],xmm6[1,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm14 = xmm0[2,2],xmm6[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm15, %ymm14, %ymm14
; AVX-NEXT: vmovaps {{.*#+}} ymm15 = [65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535]
; AVX-NEXT: vandps %ymm7, %ymm15, %ymm7
@@ -4453,7 +4453,7 @@ define void @store_i16_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovdqa %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpshufd {{.*#+}} xmm4 = xmm5[0,1,0,1]
; AVX-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3,4],xmm4[5],xmm2[6,7]
-; AVX-NEXT: vshufps {{.*#+}} xmm4 = xmm7[0,2],xmm5[1,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm4 = xmm7[2,2],xmm5[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm4, %ymm2, %ymm2
; AVX-NEXT: vmovaps {{.*#+}} ymm4 = [65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535]
; AVX-NEXT: vandps %ymm4, %ymm3, %ymm3
@@ -4543,7 +4543,7 @@ define void @store_i16_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vpsrldq {{.*#+}} xmm1 = xmm5[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3],xmm1[4,5,6,7]
-; AVX-NEXT: vshufps {{.*#+}} xmm3 = xmm5[0,2],xmm2[1,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm3 = xmm5[2,2],xmm2[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
; AVX-NEXT: vmovaps {{.*#+}} ymm2 = [65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535]
; AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
@@ -4576,7 +4576,7 @@ define void @store_i16_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm13 # 16-byte Reload
; AVX-NEXT: vpshufd {{.*#+}} xmm3 = xmm13[0,1,0,1]
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4],xmm3[5],xmm1[6,7]
-; AVX-NEXT: vshufps {{.*#+}} xmm3 = xmm5[0,2],xmm13[1,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm3 = xmm5[2,2],xmm13[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
; AVX-NEXT: vmovaps {{.*#+}} ymm3 = [65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535]
; AVX-NEXT: vandps %ymm3, %ymm0, %ymm0
@@ -9411,7 +9411,7 @@ define void @store_i16_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vpsrldq {{.*#+}} xmm1 = xmm3[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX-NEXT: vmovdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[3],xmm1[4,5,6,7]
-; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm3[0,2],xmm4[1,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm3[2,2],xmm4[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX-NEXT: vmovaps {{.*#+}} ymm4 = [65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535]
; AVX-NEXT: vandps %ymm4, %ymm0, %ymm0
@@ -9449,7 +9449,7 @@ define void @store_i16_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,xmm13[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
; AVX-NEXT: vpshufd {{.*#+}} xmm2 = xmm3[0,1,0,1]
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4],xmm2[5],xmm1[6,7]
-; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm13[0,2],xmm3[1,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm13[2,2],xmm3[1,1]
; AVX-NEXT: vmovaps %xmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX-NEXT: vmovaps {{.*#+}} ymm14 = [65535,65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535]
@@ -9548,7 +9548,7 @@ define void @store_i16_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX-NEXT: vmovdqa %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2],xmm5[3],xmm2[4,5,6,7]
-; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm5[1,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[2,2],xmm5[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX-NEXT: vandps %ymm4, %ymm0, %ymm0
; AVX-NEXT: vandnps %ymm1, %ymm4, %ymm1
@@ -9587,7 +9587,7 @@ define void @store_i16_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,xmm7[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
; AVX-NEXT: vpshufd {{.*#+}} xmm7 = xmm11[0,1,0,1]
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4],xmm7[5],xmm1[6,7]
-; AVX-NEXT: vshufps {{.*#+}} xmm7 = xmm2[0,2],xmm11[1,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm7 = xmm2[2,2],xmm11[1,1]
; AVX-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vinsertf128 $1, %xmm7, %ymm1, %ymm1
; AVX-NEXT: vandps %ymm0, %ymm14, %ymm0
@@ -9688,7 +9688,7 @@ define void @store_i16_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vpsrldq {{.*#+}} xmm8 = xmm7[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX-NEXT: vmovdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vpblendw {{.*#+}} xmm8 = xmm8[0,1,2],xmm6[3],xmm8[4,5,6,7]
-; AVX-NEXT: vshufps {{.*#+}} xmm7 = xmm7[0,2],xmm6[1,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm7 = xmm7[2,2],xmm6[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm8, %ymm7, %ymm7
; AVX-NEXT: vmovaps {{.*#+}} ymm1 = [65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535]
; AVX-NEXT: vandps %ymm1, %ymm0, %ymm0
@@ -9727,7 +9727,7 @@ define void @store_i16_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vpslldq {{.*#+}} xmm15 = zero,zero,xmm6[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
; AVX-NEXT: vpshufd {{.*#+}} xmm6 = xmm2[0,1,0,1]
; AVX-NEXT: vpblendw {{.*#+}} xmm6 = xmm15[0,1,2,3,4],xmm6[5],xmm15[6,7]
-; AVX-NEXT: vshufps {{.*#+}} xmm15 = xmm0[0,2],xmm2[1,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm15 = xmm0[2,2],xmm2[1,1]
; AVX-NEXT: vmovdqa %xmm0, %xmm10
; AVX-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vinsertf128 $1, %xmm15, %ymm6, %ymm6
@@ -9821,7 +9821,7 @@ define void @store_i16_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vorps %ymm6, %ymm12, %ymm6
; AVX-NEXT: vpsrldq {{.*#+}} xmm12 = xmm7[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX-NEXT: vpblendw {{.*#+}} xmm12 = xmm12[0,1,2],xmm0[3],xmm12[4,5,6,7]
-; AVX-NEXT: vshufps {{.*#+}} xmm7 = xmm7[0,2],xmm0[1,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm7 = xmm7[2,2],xmm0[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm12, %ymm7, %ymm7
; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65535,0,0,0,65535,65535,65535,65535,0,0,0,65535,65535,65535,65535]
; AVX-NEXT: vandps %ymm0, %ymm6, %ymm6
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
index d83f969dd0339..1eef9e25a4dbe 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
@@ -342,14 +342,14 @@ define void @store_i32_stride5_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX-NEXT: vblendps {{.*#+}} xmm4 = xmm4[0,1],xmm0[2,3]
; AVX-NEXT: vshufps {{.*#+}} xmm5 = xmm1[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm5 = xmm0[0,1,2],xmm5[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm5 = xmm3[1],zero,xmm5[2,3]
+; AVX-NEXT: vshufps {{.*#+}} xmm5 = xmm3[1,1],xmm5[2,3]
; AVX-NEXT: vinsertf128 $1, %xmm4, %ymm5, %ymm4
; AVX-NEXT: vbroadcastf128 {{.*#+}} ymm5 = mem[0,1,0,1]
; AVX-NEXT: vblendps {{.*#+}} ymm4 = ymm4[0],ymm5[1],ymm4[2,3,4,5],ymm5[6],ymm4[7]
; AVX-NEXT: vunpcklps {{.*#+}} xmm6 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm7 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX-NEXT: vmovlhps {{.*#+}} xmm6 = xmm7[0],xmm6[0]
-; AVX-NEXT: vinsertps {{.*#+}} xmm7 = zero,xmm0[1],xmm1[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm7 = xmm0[1,1],xmm1[1,1]
; AVX-NEXT: vinsertps {{.*#+}} xmm7 = xmm7[0,1,2],xmm2[1]
; AVX-NEXT: vinsertf128 $1, %xmm7, %ymm6, %ymm6
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm5[4,5,6,7]
@@ -695,7 +695,7 @@ define void @store_i32_stride5_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX-NEXT: vmovaps 16(%rsi), %xmm6
; AVX-NEXT: vmovaps (%rdi), %xmm7
; AVX-NEXT: vmovaps 16(%rdi), %xmm8
-; AVX-NEXT: vinsertps {{.*#+}} xmm4 = zero,xmm7[1],xmm5[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm4 = xmm7[1,1],xmm5[1,1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm9 = xmm7[0],xmm5[0],xmm7[1],xmm5[1]
; AVX-NEXT: vinsertf128 $1, %xmm4, %ymm9, %ymm4
; AVX-NEXT: vmovaps (%rcx), %xmm9
@@ -718,7 +718,7 @@ define void @store_i32_stride5_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX-NEXT: vblendps {{.*#+}} ymm5 = ymm5[0],ymm13[1],ymm5[2,3,4,5],ymm13[6],ymm5[7]
; AVX-NEXT: vshufps {{.*#+}} xmm7 = xmm6[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm7 = xmm8[0,1,2],xmm7[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm6 = zero,xmm8[1],xmm6[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm6 = xmm8[1,1],xmm6[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm7, %ymm6, %ymm6
; AVX-NEXT: vshufps {{.*#+}} ymm7 = ymm3[1,1],ymm1[1,1],ymm3[5,5],ymm1[5,5]
; AVX-NEXT: vperm2f128 {{.*#+}} ymm7 = ymm7[2,3,2,3]
@@ -1350,7 +1350,7 @@ define void @store_i32_stride5_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vblendps {{.*#+}} xmm15 = xmm13[0,1,2],xmm15[3]
; AVX-NEXT: vinsertf128 $1, %xmm13, %ymm15, %ymm15
; AVX-NEXT: vblendps {{.*#+}} ymm10 = ymm10[0,1],ymm15[2,3],ymm10[4,5],ymm15[6,7]
-; AVX-NEXT: vinsertps {{.*#+}} xmm15 = zero,xmm13[1],xmm14[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm15 = xmm13[1,1],xmm14[1,1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm13 = xmm13[0],xmm14[0],xmm13[1],xmm14[1]
; AVX-NEXT: vmovaps 32(%rdi), %xmm14
; AVX-NEXT: vinsertf128 $1, %xmm15, %ymm13, %ymm13
@@ -1370,7 +1370,7 @@ define void @store_i32_stride5_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vblendps {{.*#+}} xmm10 = xmm14[0,1,2],xmm10[3]
; AVX-NEXT: vinsertf128 $1, %xmm14, %ymm10, %ymm10
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm10[2,3],ymm0[4,5],ymm10[6,7]
-; AVX-NEXT: vinsertps {{.*#+}} xmm13 = zero,xmm14[1],xmm15[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm13 = xmm14[1,1],xmm15[1,1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm14 = xmm14[0],xmm15[0],xmm14[1],xmm15[1]
; AVX-NEXT: vbroadcastf128 {{.*#+}} ymm15 = mem[0,1,0,1]
; AVX-NEXT: vblendps {{.*#+}} ymm10 = ymm0[0],ymm15[1],ymm0[2,3,4,5],ymm15[6],ymm0[7]
@@ -1384,7 +1384,7 @@ define void @store_i32_stride5_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovaps 48(%rsi), %xmm12
; AVX-NEXT: vshufps {{.*#+}} xmm13 = xmm12[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm13 = xmm0[0,1,2],xmm13[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[1],xmm12[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm12[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm13, %ymm0, %ymm0
; AVX-NEXT: vshufps {{.*#+}} ymm12 = ymm3[1,1],ymm1[1,1],ymm3[5,5],ymm1[5,5]
; AVX-NEXT: vmovaps %ymm1, %ymm6
@@ -1413,7 +1413,7 @@ define void @store_i32_stride5_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2],ymm8[3,4],ymm0[5,6,7]
; AVX-NEXT: vshufps {{.*#+}} xmm8 = xmm9[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm8 = xmm15[0,1,2],xmm8[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm9 = zero,xmm15[1],xmm9[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm9 = xmm15[1,1],xmm9[1,1]
; AVX-NEXT: vmovaps (%rdx), %ymm14
; AVX-NEXT: vinsertf128 $1, %xmm8, %ymm9, %ymm8
; AVX-NEXT: vmovaps (%rcx), %ymm9
@@ -2777,7 +2777,7 @@ define void @store_i32_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovaps 32(%rsi), %xmm0
; AVX-NEXT: vmovaps (%rdi), %xmm4
; AVX-NEXT: vmovaps 32(%rdi), %xmm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm4[1],xmm3[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm4[1,1],xmm3[1,1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm5 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm5, %ymm5
; AVX-NEXT: vmovaps (%rcx), %xmm6
@@ -2800,7 +2800,7 @@ define void @store_i32_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vblendps {{.*#+}} ymm3 = ymm5[0,1],ymm3[2,3],ymm5[4,5],ymm3[6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0],ymm9[1],ymm3[2,3,4,5],ymm9[6],ymm3[7]
; AVX-NEXT: vmovups %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
-; AVX-NEXT: vinsertps {{.*#+}} xmm3 = zero,xmm1[1],xmm0[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm3 = xmm1[1,1],xmm0[1,1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm4 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; AVX-NEXT: vinsertf128 $1, %xmm3, %ymm4, %ymm3
; AVX-NEXT: vunpcklps {{.*#+}} xmm4 = xmm8[0],xmm2[0],xmm8[1],xmm2[1]
@@ -2821,7 +2821,7 @@ define void @store_i32_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX-NEXT: vmovaps 64(%rsi), %xmm0
; AVX-NEXT: vmovaps 64(%rdi), %xmm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm1[1],xmm0[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[1,1],xmm0[1,1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm3 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
; AVX-NEXT: vmovaps 64(%rcx), %xmm3
@@ -2844,7 +2844,7 @@ define void @store_i32_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX-NEXT: vmovaps 96(%rsi), %xmm0
; AVX-NEXT: vmovaps 96(%rdi), %xmm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm1[1],xmm0[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[1,1],xmm0[1,1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm3 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
; AVX-NEXT: vmovaps 96(%rcx), %xmm3
@@ -2870,7 +2870,7 @@ define void @store_i32_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm5[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm4[0,1,2],xmm0[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm4[1],xmm5[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm4[1,1],xmm5[1,1]
; AVX-NEXT: vmovaps 16(%rdx), %xmm3
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
; AVX-NEXT: vshufps {{.*#+}} ymm2 = ymm13[1,1],ymm12[1,1],ymm13[5,5],ymm12[5,5]
@@ -2891,7 +2891,7 @@ define void @store_i32_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovaps 48(%rsi), %xmm1
; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm2 = xmm0[0,1,2],xmm2[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vmovaps 32(%rdx), %ymm1
; AVX-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -2918,7 +2918,7 @@ define void @store_i32_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovaps 80(%rsi), %xmm1
; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm2 = xmm0[0,1,2],xmm2[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vmovaps 64(%rdx), %ymm9
; AVX-NEXT: vmovaps 64(%rcx), %ymm8
@@ -2944,7 +2944,7 @@ define void @store_i32_stride5_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovaps 112(%rsi), %xmm1
; AVX-NEXT: vshufps {{.*#+}} xmm6 = xmm1[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm6 = xmm0[0,1,2],xmm6[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm6, %ymm0, %ymm6
; AVX-NEXT: vmovaps 96(%rdx), %ymm3
; AVX-NEXT: vmovaps 96(%rcx), %ymm2
@@ -5569,7 +5569,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovaps 32(%rsi), %xmm0
; AVX-NEXT: vmovaps (%rdi), %xmm4
; AVX-NEXT: vmovaps 32(%rdi), %xmm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm4[1],xmm3[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm4[1,1],xmm3[1,1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm5 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm5, %ymm5
; AVX-NEXT: vmovaps (%rcx), %xmm6
@@ -5592,7 +5592,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vblendps {{.*#+}} ymm3 = ymm5[0,1],ymm3[2,3],ymm5[4,5],ymm3[6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0],ymm9[1],ymm3[2,3,4,5],ymm9[6],ymm3[7]
; AVX-NEXT: vmovups %ymm3, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
-; AVX-NEXT: vinsertps {{.*#+}} xmm3 = zero,xmm1[1],xmm0[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm3 = xmm1[1,1],xmm0[1,1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm4 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; AVX-NEXT: vinsertf128 $1, %xmm3, %ymm4, %ymm3
; AVX-NEXT: vunpcklps {{.*#+}} xmm4 = xmm8[0],xmm2[0],xmm8[1],xmm2[1]
@@ -5613,7 +5613,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX-NEXT: vmovaps 64(%rsi), %xmm0
; AVX-NEXT: vmovaps 64(%rdi), %xmm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm1[1],xmm0[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[1,1],xmm0[1,1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm3 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
; AVX-NEXT: vmovaps 64(%rcx), %xmm3
@@ -5636,7 +5636,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX-NEXT: vmovaps 96(%rsi), %xmm0
; AVX-NEXT: vmovaps 96(%rdi), %xmm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm1[1],xmm0[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[1,1],xmm0[1,1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm3 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
; AVX-NEXT: vmovaps 96(%rcx), %xmm3
@@ -5659,7 +5659,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX-NEXT: vmovaps 128(%rsi), %xmm0
; AVX-NEXT: vmovaps 128(%rdi), %xmm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm1[1],xmm0[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[1,1],xmm0[1,1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm3 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
; AVX-NEXT: vmovaps 128(%rcx), %xmm3
@@ -5682,7 +5682,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX-NEXT: vmovaps 160(%rsi), %xmm0
; AVX-NEXT: vmovaps 160(%rdi), %xmm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm1[1],xmm0[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[1,1],xmm0[1,1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm3 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
; AVX-NEXT: vmovaps 160(%rcx), %xmm3
@@ -5705,7 +5705,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX-NEXT: vmovaps 192(%rsi), %xmm0
; AVX-NEXT: vmovaps 192(%rdi), %xmm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm1[1],xmm0[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[1,1],xmm0[1,1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm3 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
; AVX-NEXT: vmovaps 192(%rcx), %xmm3
@@ -5728,7 +5728,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; AVX-NEXT: vmovaps 224(%rsi), %xmm0
; AVX-NEXT: vmovaps 224(%rdi), %xmm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm1[1],xmm0[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[1,1],xmm0[1,1]
; AVX-NEXT: vunpcklps {{.*#+}} xmm3 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
; AVX-NEXT: vmovaps 224(%rcx), %xmm3
@@ -5753,7 +5753,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovaps 16(%rdi), %xmm1
; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm0[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm2 = xmm1[0,1,2],xmm2[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm1[1],xmm0[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[1,1],xmm0[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vmovaps (%rdx), %ymm1
; AVX-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -5780,7 +5780,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovaps 48(%rsi), %xmm1
; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm2 = xmm0[0,1,2],xmm2[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vmovaps 32(%rdx), %ymm1
; AVX-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -5810,7 +5810,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovaps 80(%rsi), %xmm1
; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm2 = xmm0[0,1,2],xmm2[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vmovaps 64(%rdx), %ymm1
; AVX-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -5840,7 +5840,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovaps 112(%rsi), %xmm1
; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm2 = xmm0[0,1,2],xmm2[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vmovaps 96(%rdx), %ymm1
; AVX-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -5870,7 +5870,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovaps 144(%rsi), %xmm1
; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm2 = xmm0[0,1,2],xmm2[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vmovaps 128(%rdx), %ymm2
; AVX-NEXT: vmovups %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -5899,7 +5899,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovaps 176(%rsi), %xmm1
; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm2 = xmm0[0,1,2],xmm2[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vmovaps 160(%rdx), %ymm1
; AVX-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -5928,7 +5928,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovaps 208(%rsi), %xmm1
; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm2 = xmm0[0,1,2],xmm2[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vmovaps 192(%rdx), %ymm10
; AVX-NEXT: vmovaps 192(%rcx), %ymm9
@@ -5954,7 +5954,7 @@ define void @store_i32_stride5_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vmovaps 240(%rsi), %xmm1
; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm1[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm2 = xmm0[0,1,2],xmm2[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vmovaps 224(%rdx), %ymm4
; AVX-NEXT: vmovaps 224(%rcx), %ymm3
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
index bfd1e3ece2009..b63474e8ea773 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
@@ -475,7 +475,7 @@ define void @store_i32_stride7_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX-NEXT: vshufps {{.*#+}} ymm7 = ymm7[2,0],ymm2[2,1],ymm7[6,4],ymm2[6,5]
; AVX-NEXT: vshufps {{.*#+}} xmm9 = xmm5[2,2,2,2]
; AVX-NEXT: vblendps {{.*#+}} xmm9 = xmm4[0,1,2],xmm9[3]
-; AVX-NEXT: vinsertps {{.*#+}} xmm10 = zero,xmm6[1],xmm0[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm10 = xmm6[1,1],xmm0[1,1]
; AVX-NEXT: vinsertps {{.*#+}} xmm10 = xmm5[1],xmm10[1,2,3]
; AVX-NEXT: vinsertf128 $1, %xmm9, %ymm10, %ymm9
; AVX-NEXT: vblendps {{.*#+}} ymm7 = ymm9[0,1,2],ymm7[3,4,5],ymm9[6,7]
@@ -529,7 +529,7 @@ define void @store_i32_stride7_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm9
; AVX2-NEXT: vshufps {{.*#+}} ymm10 = ymm7[1,1,1,1,5,5,5,5]
; AVX2-NEXT: vblendps {{.*#+}} ymm9 = ymm10[0,1,2,3,4],ymm9[5],ymm10[6,7]
-; AVX2-NEXT: vinsertps {{.*#+}} xmm5 = zero,xmm5[1],xmm0[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm5 = xmm5[1,1],xmm0[1,1]
; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm10 = [5,0,2,6,5,0,2,6]
; AVX2-NEXT: # ymm10 = mem[0,1,0,1]
; AVX2-NEXT: vpermps %ymm4, %ymm10, %ymm10
@@ -579,7 +579,7 @@ define void @store_i32_stride7_vf4(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX2-FP-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm9
; AVX2-FP-NEXT: vshufps {{.*#+}} ymm10 = ymm7[1,1,1,1,5,5,5,5]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm9 = ymm10[0,1,2,3,4],ymm9[5],ymm10[6,7]
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm5 = zero,xmm5[1],xmm0[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm5 = xmm5[1,1],xmm0[1,1]
; AVX2-FP-NEXT: vbroadcastf128 {{.*#+}} ymm10 = [5,0,2,6,5,0,2,6]
; AVX2-FP-NEXT: # ymm10 = mem[0,1,0,1]
; AVX2-FP-NEXT: vpermps %ymm4, %ymm10, %ymm10
@@ -1013,7 +1013,7 @@ define void @store_i32_stride7_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX-NEXT: vinsertf128 $1, %xmm9, %ymm9, %ymm9
; AVX-NEXT: vmovaps (%rcx), %xmm15
; AVX-NEXT: vmovaps (%rdx), %xmm14
-; AVX-NEXT: vinsertps {{.*#+}} xmm10 = zero,xmm14[1],xmm15[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm10 = xmm14[1,1],xmm15[1,1]
; AVX-NEXT: vblendps {{.*#+}} ymm9 = ymm9[0],ymm10[1,2],ymm9[3,4,5,6,7]
; AVX-NEXT: vmovaps (%rax), %xmm10
; AVX-NEXT: vinsertf128 $1, %xmm10, %ymm0, %ymm13
@@ -1100,7 +1100,7 @@ define void @store_i32_stride7_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX2-NEXT: vblendps {{.*#+}} ymm8 = ymm10[0,1,2,3,4],ymm8[5],ymm10[6,7]
; AVX2-NEXT: vmovaps (%rcx), %xmm12
; AVX2-NEXT: vmovaps (%rdx), %xmm13
-; AVX2-NEXT: vinsertps {{.*#+}} xmm10 = zero,xmm13[1],xmm12[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm10 = xmm13[1,1],xmm12[1,1]
; AVX2-NEXT: vmovaps (%rdi), %xmm14
; AVX2-NEXT: vmovaps (%rsi), %xmm15
; AVX2-NEXT: vshufps {{.*#+}} xmm11 = xmm15[1,1,2,2]
@@ -1204,7 +1204,7 @@ define void @store_i32_stride7_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm8 = ymm10[0,1,2,3,4],ymm8[5],ymm10[6,7]
; AVX2-FP-NEXT: vmovaps (%rcx), %xmm12
; AVX2-FP-NEXT: vmovaps (%rdx), %xmm13
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm10 = zero,xmm13[1],xmm12[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm10 = xmm13[1,1],xmm12[1,1]
; AVX2-FP-NEXT: vmovaps (%rdi), %xmm14
; AVX2-FP-NEXT: vmovaps (%rsi), %xmm15
; AVX2-FP-NEXT: vshufps {{.*#+}} xmm11 = xmm15[1,1,2,2]
@@ -1309,7 +1309,7 @@ define void @store_i32_stride7_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm6 = ymm9[0,1,2,3,4],ymm6[5],ymm9[6,7]
; AVX2-FCP-NEXT: vmovaps (%rcx), %xmm11
; AVX2-FCP-NEXT: vmovaps (%rdx), %xmm12
-; AVX2-FCP-NEXT: vinsertps {{.*#+}} xmm9 = zero,xmm12[1],xmm11[1],zero
+; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm9 = xmm12[1,1],xmm11[1,1]
; AVX2-FCP-NEXT: vmovaps (%rdi), %xmm13
; AVX2-FCP-NEXT: vmovaps (%rsi), %xmm14
; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm15 = xmm14[1,1,2,2]
@@ -2112,7 +2112,7 @@ define void @store_i32_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vunpckhpd {{.*#+}} xmm3 = xmm12[1],xmm9[1]
; AVX-NEXT: vshufps {{.*#+}} xmm3 = xmm9[1,1],xmm3[0,2]
; AVX-NEXT: vinsertf128 $1, %xmm3, %ymm3, %ymm3
-; AVX-NEXT: vinsertps {{.*#+}} xmm4 = zero,xmm14[1],xmm13[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm4 = xmm14[1,1],xmm13[1,1]
; AVX-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0],ymm4[1,2],ymm3[3,4,5,6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm2 = ymm3[0,1,2],ymm2[3,4,5],ymm3[6,7]
; AVX-NEXT: vmovups %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -2140,7 +2140,7 @@ define void @store_i32_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX-NEXT: vmovaps (%rcx), %xmm7
; AVX-NEXT: vmovaps (%rdx), %xmm12
-; AVX-NEXT: vinsertps {{.*#+}} xmm1 = zero,xmm12[1],xmm7[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm12[1,1],xmm7[1,1]
; AVX-NEXT: vmovaps %xmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3,4,5,6,7]
; AVX-NEXT: vmovaps (%r9), %xmm3
@@ -2319,7 +2319,7 @@ define void @store_i32_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-NEXT: vmovaps 32(%rcx), %xmm12
; AVX2-NEXT: vmovaps 32(%rdx), %xmm10
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm10[1],xmm12[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm2 = xmm10[1,1],xmm12[1,1]
; AVX2-NEXT: vmovaps (%rdi), %xmm11
; AVX2-NEXT: vmovaps %xmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-NEXT: vmovaps 32(%rdi), %xmm7
@@ -2341,7 +2341,7 @@ define void @store_i32_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-NEXT: vblendps {{.*#+}} xmm2 = xmm2[0,1],xmm11[2],xmm2[3]
; AVX2-NEXT: vpermpd {{.*#+}} ymm2 = ymm2[0,1,2,1]
; AVX2-NEXT: vmovaps (%rdx), %xmm13
-; AVX2-NEXT: vinsertps {{.*#+}} xmm4 = zero,xmm13[1],xmm3[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm4 = xmm13[1,1],xmm3[1,1]
; AVX2-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0],ymm4[1,2],ymm2[3,4,5,6,7]
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0,1,2],ymm0[3,4,5],ymm2[6,7]
; AVX2-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -2570,7 +2570,7 @@ define void @store_i32_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FP-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FP-NEXT: vmovaps 32(%rcx), %xmm12
; AVX2-FP-NEXT: vmovaps 32(%rdx), %xmm10
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm10[1],xmm12[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm2 = xmm10[1,1],xmm12[1,1]
; AVX2-FP-NEXT: vmovaps (%rdi), %xmm11
; AVX2-FP-NEXT: vmovaps %xmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FP-NEXT: vmovaps 32(%rdi), %xmm7
@@ -2592,7 +2592,7 @@ define void @store_i32_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FP-NEXT: vblendps {{.*#+}} xmm2 = xmm2[0,1],xmm11[2],xmm2[3]
; AVX2-FP-NEXT: vpermpd {{.*#+}} ymm2 = ymm2[0,1,2,1]
; AVX2-FP-NEXT: vmovaps (%rdx), %xmm13
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm4 = zero,xmm13[1],xmm3[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm4 = xmm13[1,1],xmm3[1,1]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0],ymm4[1,2],ymm2[3,4,5,6,7]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0,1,2],ymm0[3,4,5],ymm2[6,7]
; AVX2-FP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -2820,7 +2820,7 @@ define void @store_i32_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FCP-NEXT: vmovaps %xmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FCP-NEXT: vmovaps 32(%rcx), %xmm11
; AVX2-FCP-NEXT: vmovaps 32(%rdx), %xmm10
-; AVX2-FCP-NEXT: vinsertps {{.*#+}} xmm1 = zero,xmm10[1],xmm11[1],zero
+; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm1 = xmm10[1,1],xmm11[1,1]
; AVX2-FCP-NEXT: vmovaps (%rdi), %xmm12
; AVX2-FCP-NEXT: vmovaps %xmm12, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FCP-NEXT: vmovaps 32(%rdi), %xmm9
@@ -2843,7 +2843,7 @@ define void @store_i32_stride7_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FCP-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,2,1]
; AVX2-FCP-NEXT: vmovaps (%rdx), %xmm2
; AVX2-FCP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FCP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm8[1],zero
+; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm8[1,1]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FCP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -4657,7 +4657,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm6[1],xmm5[1]
; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm5[1,1],xmm1[0,2]
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm9[1],xmm8[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm9[1,1],xmm8[1,1]
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -4717,7 +4717,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm5[1],xmm7[1]
; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm7[1,1],xmm1[0,2]
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm9[1],xmm6[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm9[1,1],xmm6[1,1]
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -4778,7 +4778,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm6[1],xmm7[1]
; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm7[1,1],xmm1[0,2]
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm10[1],xmm9[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm10[1,1],xmm9[1,1]
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -4835,7 +4835,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm6[1],xmm2[1]
; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm2[1,1],xmm1[0,2]
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm15 = zero,xmm3[1],xmm4[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm15 = xmm3[1,1],xmm4[1,1]
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm15[1,2],ymm1[3,4,5,6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -5153,7 +5153,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-NEXT: vmovaps 32(%rcx), %xmm4
; AVX2-NEXT: vmovaps %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-NEXT: vmovaps (%rdx), %xmm8
-; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = zero,xmm8[1],xmm12[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm1 = xmm8[1,1],xmm12[1,1]
; AVX2-NEXT: vmovaps (%rdi), %xmm6
; AVX2-NEXT: vmovaps 32(%rdi), %xmm11
; AVX2-NEXT: vmovaps %xmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -5175,7 +5175,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0,1],xmm11[2],xmm1[3]
; AVX2-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,2,1]
; AVX2-NEXT: vmovaps 32(%rdx), %xmm9
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm9[1],xmm4[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm2 = xmm9[1,1],xmm4[1,1]
; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -5200,7 +5200,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-NEXT: vmovaps 64(%rcx), %xmm2
; AVX2-NEXT: vmovaps %xmm2, (%rsp) # 16-byte Spill
; AVX2-NEXT: vmovaps 64(%rdx), %xmm13
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm13[1],xmm2[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm2 = xmm13[1,1],xmm2[1,1]
; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -5225,7 +5225,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-NEXT: vmovaps 96(%rdx), %xmm2
; AVX2-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -5674,7 +5674,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FP-NEXT: vmovaps 32(%rcx), %xmm4
; AVX2-FP-NEXT: vmovaps %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FP-NEXT: vmovaps (%rdx), %xmm8
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm1 = zero,xmm8[1],xmm12[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm1 = xmm8[1,1],xmm12[1,1]
; AVX2-FP-NEXT: vmovaps (%rdi), %xmm6
; AVX2-FP-NEXT: vmovaps 32(%rdi), %xmm11
; AVX2-FP-NEXT: vmovaps %xmm11, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -5696,7 +5696,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FP-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0,1],xmm11[2],xmm1[3]
; AVX2-FP-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,2,1]
; AVX2-FP-NEXT: vmovaps 32(%rdx), %xmm9
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm9[1],xmm4[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm2 = xmm9[1,1],xmm4[1,1]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -5721,7 +5721,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FP-NEXT: vmovaps 64(%rcx), %xmm2
; AVX2-FP-NEXT: vmovaps %xmm2, (%rsp) # 16-byte Spill
; AVX2-FP-NEXT: vmovaps 64(%rdx), %xmm13
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm13[1],xmm2[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm2 = xmm13[1,1],xmm2[1,1]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -5746,7 +5746,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FP-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FP-NEXT: vmovaps 96(%rdx), %xmm2
; AVX2-FP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -6199,7 +6199,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FCP-NEXT: vmovaps %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FCP-NEXT: vmovaps (%rdx), %xmm1
; AVX2-FCP-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FCP-NEXT: vinsertps {{.*#+}} xmm1 = zero,xmm1[1],xmm2[1],zero
+; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; AVX2-FCP-NEXT: vmovaps (%rdi), %xmm9
; AVX2-FCP-NEXT: vmovaps 32(%rdi), %xmm7
; AVX2-FCP-NEXT: vmovaps %xmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -6222,7 +6222,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FCP-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,2,1]
; AVX2-FCP-NEXT: vmovaps 32(%rdx), %xmm2
; AVX2-FCP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FCP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm6[1],zero
+; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm6[1,1]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FCP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -6248,7 +6248,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FCP-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FCP-NEXT: vmovaps 64(%rdx), %xmm2
; AVX2-FCP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FCP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FCP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -6274,7 +6274,7 @@ define void @store_i32_stride7_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FCP-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FCP-NEXT: vmovaps 96(%rdx), %xmm2
; AVX2-FCP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FCP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FCP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -9651,7 +9651,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm6[1],xmm5[1]
; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm5[1,1],xmm1[0,2]
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm8[1],xmm7[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm8[1,1],xmm7[1,1]
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -9711,7 +9711,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm9[1],xmm6[1]
; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm6[1,1],xmm1[0,2]
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm12[1],xmm10[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm12[1,1],xmm10[1,1]
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -9772,7 +9772,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm7[1],xmm6[1]
; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm6[1,1],xmm1[0,2]
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm5[1],xmm9[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm5[1,1],xmm9[1,1]
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -9833,7 +9833,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm5[1],xmm3[1]
; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm3[1,1],xmm1[0,2]
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm9[1],xmm7[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm9[1,1],xmm7[1,1]
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -9893,7 +9893,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm5[1],xmm4[1]
; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm4[1,1],xmm1[0,2]
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm9[1],xmm7[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm9[1,1],xmm7[1,1]
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -9954,7 +9954,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm11[1],xmm6[1]
; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm6[1,1],xmm1[0,2]
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm3[1],xmm7[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm3[1,1],xmm7[1,1]
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -10014,7 +10014,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vunpckhpd {{.*#+}} xmm1 = xmm12[1],xmm3[1]
; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm3[1,1],xmm1[0,2]
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
-; AVX-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm6[1],xmm7[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm2 = xmm6[1,1],xmm7[1,1]
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -10158,7 +10158,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
; AVX-NEXT: vmovaps 224(%rcx), %xmm4
; AVX-NEXT: vmovaps 224(%rdx), %xmm12
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm12[1],xmm4[1],zero
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm12[1,1],xmm4[1,1]
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm0[1,2],ymm1[3,4,5,6,7]
; AVX-NEXT: vbroadcastss 228(%r8), %ymm14
; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2],ymm14[3],ymm1[4,5,6,7]
@@ -10686,7 +10686,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-NEXT: vmovaps 32(%rcx), %xmm3
; AVX2-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-NEXT: vmovaps (%rdx), %xmm9
-; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = zero,xmm9[1],xmm10[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm1 = xmm9[1,1],xmm10[1,1]
; AVX2-NEXT: vmovaps (%rdi), %xmm7
; AVX2-NEXT: vmovaps 32(%rdi), %xmm8
; AVX2-NEXT: vmovaps %xmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -10710,7 +10710,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0,1],xmm8[2],xmm1[3]
; AVX2-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,2,1]
; AVX2-NEXT: vmovaps 32(%rdx), %xmm8
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm8[1],xmm3[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm2 = xmm8[1,1],xmm3[1,1]
; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -10736,7 +10736,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-NEXT: vmovaps 64(%rdx), %xmm2
; AVX2-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -10762,7 +10762,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-NEXT: vmovaps 96(%rdx), %xmm2
; AVX2-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -10788,7 +10788,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-NEXT: vmovaps 128(%rdx), %xmm2
; AVX2-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -10814,7 +10814,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-NEXT: vmovaps 160(%rdx), %xmm2
; AVX2-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -10840,7 +10840,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-NEXT: vmovaps 192(%rdx), %xmm2
; AVX2-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -11027,7 +11027,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-NEXT: vshufps {{.*#+}} xmm2 = xmm4[1,1,2,2]
; AVX2-NEXT: vblendps {{.*#+}} xmm2 = xmm2[0,1],xmm5[2],xmm2[3]
; AVX2-NEXT: vpermpd {{.*#+}} ymm2 = ymm2[0,1,2,1]
-; AVX2-NEXT: vinsertps {{.*#+}} xmm15 = zero,xmm1[1],xmm0[1],zero
+; AVX2-NEXT: vshufps {{.*#+}} xmm15 = xmm1[1,1],xmm0[1,1]
; AVX2-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0],ymm15[1,2],ymm2[3,4,5,6,7]
; AVX2-NEXT: vbroadcastss 228(%r8), %ymm14
; AVX2-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2],ymm14[3],ymm2[4,5,6,7]
@@ -11755,7 +11755,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FP-NEXT: vmovaps 32(%rcx), %xmm3
; AVX2-FP-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FP-NEXT: vmovaps (%rdx), %xmm9
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm1 = zero,xmm9[1],xmm10[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm1 = xmm9[1,1],xmm10[1,1]
; AVX2-FP-NEXT: vmovaps (%rdi), %xmm7
; AVX2-FP-NEXT: vmovaps 32(%rdi), %xmm8
; AVX2-FP-NEXT: vmovaps %xmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
@@ -11779,7 +11779,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FP-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0,1],xmm8[2],xmm1[3]
; AVX2-FP-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,2,1]
; AVX2-FP-NEXT: vmovaps 32(%rdx), %xmm8
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm8[1],xmm3[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm2 = xmm8[1,1],xmm3[1,1]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -11805,7 +11805,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FP-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FP-NEXT: vmovaps 64(%rdx), %xmm2
; AVX2-FP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -11831,7 +11831,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FP-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FP-NEXT: vmovaps 96(%rdx), %xmm2
; AVX2-FP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -11857,7 +11857,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FP-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FP-NEXT: vmovaps 128(%rdx), %xmm2
; AVX2-FP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -11883,7 +11883,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FP-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FP-NEXT: vmovaps 160(%rdx), %xmm2
; AVX2-FP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -11909,7 +11909,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FP-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FP-NEXT: vmovaps 192(%rdx), %xmm2
; AVX2-FP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -12096,7 +12096,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FP-NEXT: vshufps {{.*#+}} xmm2 = xmm4[1,1,2,2]
; AVX2-FP-NEXT: vblendps {{.*#+}} xmm2 = xmm2[0,1],xmm5[2],xmm2[3]
; AVX2-FP-NEXT: vpermpd {{.*#+}} ymm2 = ymm2[0,1,2,1]
-; AVX2-FP-NEXT: vinsertps {{.*#+}} xmm15 = zero,xmm1[1],xmm0[1],zero
+; AVX2-FP-NEXT: vshufps {{.*#+}} xmm15 = xmm1[1,1],xmm0[1,1]
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0],ymm15[1,2],ymm2[3,4,5,6,7]
; AVX2-FP-NEXT: vbroadcastss 228(%r8), %ymm14
; AVX2-FP-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2],ymm14[3],ymm2[4,5,6,7]
@@ -12827,7 +12827,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FCP-NEXT: vmovaps %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FCP-NEXT: vmovaps (%rdx), %xmm1
; AVX2-FCP-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FCP-NEXT: vinsertps {{.*#+}} xmm1 = zero,xmm1[1],xmm2[1],zero
+; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[1,1]
; AVX2-FCP-NEXT: vmovaps (%rdi), %xmm8
; AVX2-FCP-NEXT: vmovaps %xmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FCP-NEXT: vmovaps 32(%rdi), %xmm6
@@ -12854,7 +12854,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FCP-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,2,1]
; AVX2-FCP-NEXT: vmovaps 32(%rdx), %xmm2
; AVX2-FCP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FCP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm5[1],zero
+; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm5[1,1]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FCP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -12880,7 +12880,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FCP-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FCP-NEXT: vmovaps 64(%rdx), %xmm2
; AVX2-FCP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FCP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FCP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -12906,7 +12906,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FCP-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FCP-NEXT: vmovaps 96(%rdx), %xmm2
; AVX2-FCP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FCP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FCP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -12932,7 +12932,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FCP-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FCP-NEXT: vmovaps 128(%rdx), %xmm2
; AVX2-FCP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FCP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FCP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -12958,7 +12958,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FCP-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FCP-NEXT: vmovaps 160(%rdx), %xmm2
; AVX2-FCP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FCP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FCP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -12984,7 +12984,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FCP-NEXT: vmovaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX2-FCP-NEXT: vmovaps 192(%rdx), %xmm2
; AVX2-FCP-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; AVX2-FCP-NEXT: vinsertps {{.*#+}} xmm2 = zero,xmm2[1],xmm3[1],zero
+; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,1],xmm3[1,1]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0],ymm2[1,2],ymm1[3,4,5,6,7]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5],ymm1[6,7]
; AVX2-FCP-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
@@ -13156,7 +13156,7 @@ define void @store_i32_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX2-FCP-NEXT: vpermpd {{.*#+}} ymm2 = ymm2[0,1,2,1]
; AVX2-FCP-NEXT: vmovaps 224(%rcx), %xmm3
; AVX2-FCP-NEXT: vmovaps 224(%rdx), %xmm6
-; AVX2-FCP-NEXT: vinsertps {{.*#+}} xmm5 = zero,xmm6[1],xmm3[1],zero
+; AVX2-FCP-NEXT: vshufps {{.*#+}} xmm5 = xmm6[1,1],xmm3[1,1]
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0],ymm5[1,2],ymm2[3,4,5,6,7]
; AVX2-FCP-NEXT: vbroadcastss 228(%r8), %ymm4
; AVX2-FCP-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2],ymm4[3],ymm2[4,5,6,7]
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll b/llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
index 9ec24c447c2cc..51d2594d6f43b 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
@@ -695,35 +695,17 @@ define <4 x float> @shuffle_v4f32_zz4z(<4 x float> %a) {
}
define <4 x float> @shuffle_v4f32_zuu4(<4 x float> %a) {
-; SSE2-LABEL: shuffle_v4f32_zuu4:
-; SSE2: # %bb.0:
-; SSE2-NEXT: xorps %xmm1, %xmm1
-; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
-; SSE2-NEXT: movaps %xmm1, %xmm0
-; SSE2-NEXT: retq
-;
-; SSE3-LABEL: shuffle_v4f32_zuu4:
-; SSE3: # %bb.0:
-; SSE3-NEXT: xorps %xmm1, %xmm1
-; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
-; SSE3-NEXT: movaps %xmm1, %xmm0
-; SSE3-NEXT: retq
-;
-; SSSE3-LABEL: shuffle_v4f32_zuu4:
-; SSSE3: # %bb.0:
-; SSSE3-NEXT: xorps %xmm1, %xmm1
-; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
-; SSSE3-NEXT: movaps %xmm1, %xmm0
-; SSSE3-NEXT: retq
-;
-; SSE41-LABEL: shuffle_v4f32_zuu4:
-; SSE41: # %bb.0:
-; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,zero,zero,xmm0[0]
-; SSE41-NEXT: retq
+; SSE-LABEL: shuffle_v4f32_zuu4:
+; SSE: # %bb.0:
+; SSE-NEXT: xorps %xmm1, %xmm1
+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0]
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: retq
;
; AVX-LABEL: shuffle_v4f32_zuu4:
; AVX: # %bb.0:
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,zero,zero,xmm0[0]
+; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,0],xmm0[0,0]
; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 poison, i32 poison, i32 4>
ret <4 x float> %shuffle
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll
index ac5830604461c..ed7024bd2490a 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll
@@ -214,3 +214,44 @@ define <16 x i8> @PR50049(ptr %p1, ptr %p2) {
%r = mul <16 x i8> %s1, %s2
ret <16 x i8> %r
}
+
+define <4 x float> @PR186403(<4 x float> %0, <4 x float> %1) {
+; SSE-LABEL: PR186403:
+; SSE: # %bb.0:
+; SSE-NEXT: movss {{.*#+}} xmm1 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[0,0]
+; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2,3]
+; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
+; SSE-NEXT: retq
+;
+; AVX1-LABEL: PR186403:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vbroadcastss {{.*#+}} xmm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
+; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[2,3]
+; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2,3]
+; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: PR186403:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
+; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[2,3]
+; AVX2-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
+; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2,3]
+; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: PR186403:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
+; AVX512-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[2,3]
+; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
+; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2,3]
+; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
+; AVX512-NEXT: retq
+ %3 = shufflevector <4 x float> <float poison, float poison, float 1.000000e+00, float poison>, <4 x float> %0, <4 x i32> <i32 5, i32 poison, i32 2, i32 poison>
+ %4 = shufflevector <4 x float> %3, <4 x float> splat (float 0x7FF8000000000000), <4 x i32> <i32 0, i32 5, i32 2, i32 poison>
+ %5 = insertelement <4 x float> %4, float 1.000000e+00, i64 3
+ ret <4 x float> %5
+}
+
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining.ll
index 35e1c5a559a95..f5401eee04240 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining.ll
@@ -517,30 +517,18 @@ define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i3
}
define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
-; SSE2-LABEL: combine_bitwise_ops_test3c:
-; SSE2: # %bb.0:
-; SSE2-NEXT: xorps %xmm1, %xmm0
-; SSE2-NEXT: xorps %xmm1, %xmm1
-; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
-; SSE2-NEXT: retq
-;
-; SSSE3-LABEL: combine_bitwise_ops_test3c:
-; SSSE3: # %bb.0:
-; SSSE3-NEXT: xorps %xmm1, %xmm0
-; SSSE3-NEXT: xorps %xmm1, %xmm1
-; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
-; SSSE3-NEXT: retq
-;
-; SSE41-LABEL: combine_bitwise_ops_test3c:
-; SSE41: # %bb.0:
-; SSE41-NEXT: xorps %xmm1, %xmm0
-; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
-; SSE41-NEXT: retq
+; SSE-LABEL: combine_bitwise_ops_test3c:
+; SSE: # %bb.0:
+; SSE-NEXT: xorps %xmm1, %xmm0
+; SSE-NEXT: xorps %xmm1, %xmm1
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
+; SSE-NEXT: retq
;
; AVX-LABEL: combine_bitwise_ops_test3c:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
+; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
; AVX-NEXT: retq
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
@@ -587,32 +575,19 @@ define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i3
}
define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
-; SSE2-LABEL: combine_bitwise_ops_test6c:
-; SSE2: # %bb.0:
-; SSE2-NEXT: xorps %xmm1, %xmm0
-; SSE2-NEXT: xorps %xmm1, %xmm1
-; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,3]
-; SSE2-NEXT: movaps %xmm1, %xmm0
-; SSE2-NEXT: retq
-;
-; SSSE3-LABEL: combine_bitwise_ops_test6c:
-; SSSE3: # %bb.0:
-; SSSE3-NEXT: xorps %xmm1, %xmm0
-; SSSE3-NEXT: xorps %xmm1, %xmm1
-; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,3]
-; SSSE3-NEXT: movaps %xmm1, %xmm0
-; SSSE3-NEXT: retq
-;
-; SSE41-LABEL: combine_bitwise_ops_test6c:
-; SSE41: # %bb.0:
-; SSE41-NEXT: xorps %xmm1, %xmm0
-; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,zero,xmm0[1,3]
-; SSE41-NEXT: retq
+; SSE-LABEL: combine_bitwise_ops_test6c:
+; SSE: # %bb.0:
+; SSE-NEXT: xorps %xmm1, %xmm0
+; SSE-NEXT: xorps %xmm1, %xmm1
+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,3]
+; SSE-NEXT: movaps %xmm1, %xmm0
+; SSE-NEXT: retq
;
; AVX-LABEL: combine_bitwise_ops_test6c:
; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,zero,xmm0[1,3]
+; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,1],xmm0[1,3]
; AVX-NEXT: retq
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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