[llvm-branch-commits] [llvm] [LoongArch] Support VBIT{CLR, SET, REV}I patterns for non-native element sizes (PR #193719)

[via llvm-branch-commits]

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@@ -1517,6 +1517,15 @@ def : Pat<(and (v8i32 LASX256:$xj), (v8i32 (vsplat_uimm_inv_pow2 uimm5:$imm))),
 def : Pat<(and (v4i64 LASX256:$xj), (v4i64 (vsplat_uimm_inv_pow2 uimm6:$imm))),
           (XVBITCLRI_D LASX256:$xj, uimm6:$imm)>;
 
+foreach vt = [v16i16, v8i32, v4i64] in {
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wangleiat wrote:

Consider renaming the LASX register placeholder `vj` to `xj` to better align with LoongArch register naming conventions.

https://github.com/llvm/llvm-project/pull/193719