[llvm-branch-commits] [llvm] [amdgpu-cfi: 7/9]: [AMDGPU] Implement CFI for CSR spills (PR #183150)

[Matt Arsenault via llvm-branch-commits]

================
@@ -2440,6 +2514,22 @@ MachineInstr *SIFrameLowering::buildCFI(MachineBasicBlock &MBB,
       .setMIFlag(flag);
 }
 
+MachineInstr *SIFrameLowering::buildCFIForVRegToVRegSpill(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+    const DebugLoc &DL, const MCRegister Reg, const MCRegister RegCopy) const {
+  MachineFunction &MF = *MBB.getParent();
+  const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo();
+  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+
+  unsigned MaskReg = MCRI.getDwarfRegNum(
----------------
arsenm wrote:

```suggestion
  MCRegister MaskReg = MCRI.getDwarfRegNum(
```

https://github.com/llvm/llvm-project/pull/183150