[llvm-branch-commits] [llvm] release/22.x: MIPSr6: Fix COPY of reg:fgr64cc without fcmp in the same BB (#185820) (PR #186008)

[YunQiang Su via llvm-branch-commits]

wzssyqa wrote:

> This issue specifically addresses a cross-MBB copy of fgr64cc assertions. @wzssyqa I'm wondering if it can be easily modified like this? Only add `Mips::FGR64CCRegClass.contains(SrcReg)`.
> 
> ```diff
> --- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
> +++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
> @@ -171,8 +171,8 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
>        return;
>      } else if (Mips::MSACtrlRegClass.contains(SrcReg)) {
>        Opc = Mips::CFCMSA;
> -    } else if (Mips::FGR64RegClass.contains(SrcReg) &&
> -               (I->getFlag(MachineInstr::MIFlag::NoSWrap) ||
> +    } else if (Mips::FGR64CCRegClass.contains(SrcReg) || 
> +           (Mips::FGR64RegClass.contains(SrcReg) &&
>                  isWritedByFCMP(I, SrcReg))) {
>        Opc = Mips::MFC1_D64;
>      }
> ```

Here I use `MIFlag::NoSWrap` to mark only lowest bit of this register is used.
I am worrying that if we allow any fgr here may break something else.

https://github.com/llvm/llvm-project/pull/186008