[llvm-branch-commits] [llvm] [AMDGPU] DPP wave reduction for double types - 1 (PR #189390)

[via llvm-branch-commits]

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@@ -858,6 +858,884 @@ entry:
   ret void
 }
 
+define void @divergent_value_double_dpp(ptr addrspace(1) %out, double %in) {
+; GFX8DAGISEL-LABEL: divergent_value_double_dpp:
+; GFX8DAGISEL:       ; %bb.0: ; %entry
+; GFX8DAGISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8DAGISEL-NEXT:    s_xor_saveexec_b64 s[4:5], -1
+; GFX8DAGISEL-NEXT:    buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
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easyonaadit wrote:

These are inserted by PEI.
For non-entry functions which use WWM, the registers which take part in the WWM calculations are spilt and restored in the prolog and epilog to preserve the inactive lanes.
I'm not sure why the same register is spilt multiple times, might be some corner case in the spilling logic, I'll have to look into it as a follow up.

https://github.com/llvm/llvm-project/pull/189390