[llvm-branch-commits] [llvm] [LSR] Preserve LCSSA in SCEVRewriter (PR #191665)

[Aiden Grossman via llvm-branch-commits]

https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/191665

>From e471b6bb34dc9b9fd50dd77f128a22ee57a82b5f Mon Sep 17 00:00:00 2001
From: Aiden Grossman <aidengrossman at google.com>
Date: Sat, 11 Apr 2026 21:05:02 +0000
Subject: [PATCH] test

Created using spr 1.3.7
---
 .../X86/lcssa-preservation-regression.ll      | 49 +++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 llvm/test/Transforms/LoopStrengthReduce/X86/lcssa-preservation-regression.ll

diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/lcssa-preservation-regression.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/lcssa-preservation-regression.ll
new file mode 100644
index 0000000000000..d2eb71bfb1700
--- /dev/null
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/lcssa-preservation-regression.ll
@@ -0,0 +1,49 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt < %s -passes="loop-reduce" -S | FileCheck %s
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @regression1() {
+; CHECK-LABEL: define void @regression1() {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    br label %[[LOOP1_HEADER:.*]]
+; CHECK:       [[LOOP1_HEADER]]:
+; CHECK-NEXT:    br label %[[LOOP1:.*]]
+; CHECK:       [[LOOP1]]:
+; CHECK-NEXT:    [[PHI:%.*]] = phi i32 [ 0, %[[LOOP1_HEADER]] ], [ 1, %[[LOOP1]] ]
+; CHECK-NEXT:    br i1 false, label %[[LOOP2_HEADER:.*]], label %[[LOOP1]]
+; CHECK:       [[LOOP2_HEADER]]:
+; CHECK-NEXT:    [[PHI_LCSSA1:%.*]] = phi i32 [ [[PHI]], %[[LOOP1]] ]
+; CHECK-NEXT:    [[TMP0:%.*]] = add nuw nsw i32 [[PHI_LCSSA1]], 1
+; CHECK-NEXT:    br label %[[LOOP2:.*]]
+; CHECK:       [[LOOP2]]:
+; CHECK-NEXT:    [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP2]] ], [ [[TMP0]], %[[LOOP2_HEADER]] ]
+; CHECK-NEXT:    [[SELECT:%.*]] = select i1 false, i32 [[LSR_IV]], i32 0
+; CHECK-NEXT:    [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
+; CHECK-NEXT:    br i1 false, label %[[EXIT:.*]], label %[[LOOP2]]
+; CHECK:       [[EXIT]]:
+; CHECK-NEXT:    br label %[[LOOP1_HEADER]]
+;
+entry:
+  br label %loop1.header
+
+loop1.header:                                              ; preds = %exit, %entry
+  br label %loop1
+
+loop1:                                              ; preds = %loop1, %loop1.header
+  %phi = phi i32 [ 0, %loop1.header ], [ 1, %loop1 ]
+  br i1 false, label %loop2.header, label %loop1
+
+loop2.header:                                              ; preds = %loop1
+  br label %loop2
+
+loop2:                                              ; preds = %loop2.header, %loop2
+  %phi5 = phi i32 [ %add, %loop2 ], [ %phi, %loop2.header ]
+  %add = add i32 %phi5, 1
+  %select = select i1 false, i32 %add, i32 0
+  br i1 false, label %exit, label %loop2
+
+exit:                                              ; preds = %loop2
+  br label %loop1.header
+}