[llvm-branch-commits] [llvm] [IVUsers] Look through loop-external single-value phi nodes (PR #191684)
Aiden Grossman via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sat Apr 11 23:54:07 PDT 2026
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/191684
>From 74b5f01c859861d35f3ced443e542690452e189d Mon Sep 17 00:00:00 2001
From: Aiden Grossman <aidengrossman at google.com>
Date: Sun, 12 Apr 2026 06:53:54 +0000
Subject: [PATCH] update
Created using spr 1.3.7
---
.../divergence-temporal-divergent-reg.ll | 8 +--
.../AMDGPU/GlobalISel/regbankselect-mui.ll | 10 ++--
.../AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll | 30 ++++++-----
...p-var-out-of-divergent-loop-swdev407790.ll | 5 +-
.../CodeGen/PowerPC/P10-stack-alignment.ll | 4 +-
llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll | 53 +++++++++++--------
llvm/test/CodeGen/PowerPC/ctrloops.ll | 2 +-
llvm/test/CodeGen/PowerPC/sms-cpy-1.ll | 41 +++++++-------
.../X86/expander-reused-value-insert-point.ll | 4 +-
.../normalization-during-scev-expansion.ll | 51 +++++++++---------
.../callbr-critical-edge-splitting.ll | 14 +++--
.../Transforms/LoopStrengthReduce/funclet.ll | 35 ++++++------
12 files changed, 133 insertions(+), 124 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
index d4e5487828c48..04bcd5d24f754 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
@@ -5,14 +5,14 @@ define void @temporal_divergent_i32(float %val, ptr %addr) {
; GFX10-LABEL: temporal_divergent_i32:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_mov_b32 s5, -1
+; GFX10-NEXT: s_mov_b32 s5, 0
; GFX10-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: .LBB0_1: ; %loop
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: s_add_i32 s5, s5, 1
; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s5
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v0
; GFX10-NEXT: v_mov_b32_e32 v3, s5
+; GFX10-NEXT: s_add_i32 s5, s5, 1
; GFX10-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB0_1
@@ -40,14 +40,14 @@ define void @temporal_divergent_i32_multiple_use(float %val, ptr %addr, ptr %add
; GFX10-LABEL: temporal_divergent_i32_multiple_use:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_mov_b32 s5, -1
+; GFX10-NEXT: s_mov_b32 s5, 0
; GFX10-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: .LBB1_1: ; %loop
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: s_add_i32 s5, s5, 1
; GFX10-NEXT: v_cvt_f32_u32_e32 v5, s5
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v0
; GFX10-NEXT: v_mov_b32_e32 v5, s5
+; GFX10-NEXT: s_add_i32 s5, s5, 1
; GFX10-NEXT: s_or_b32 s4, vcc_lo, s4
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4
; GFX10-NEXT: s_cbranch_execnz .LBB1_1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
index fa280a852383b..eb362787cf4a7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
@@ -427,14 +427,14 @@ exit:
define amdgpu_ps void @divergent_because_of_temporal_divergent_use(float %val, ptr addrspace(1) %addr) {
; OLD_RBS-LABEL: divergent_because_of_temporal_divergent_use:
; OLD_RBS: ; %bb.0: ; %entry
-; OLD_RBS-NEXT: s_mov_b32 s0, -1
-; OLD_RBS-NEXT: v_mov_b32_e32 v3, s0
; OLD_RBS-NEXT: s_mov_b32 s0, 0
+; OLD_RBS-NEXT: v_mov_b32_e32 v4, s0
; OLD_RBS-NEXT: .LBB15_1: ; %loop
; OLD_RBS-NEXT: ; =>This Inner Loop Header: Depth=1
-; OLD_RBS-NEXT: v_add_nc_u32_e32 v3, 1, v3
+; OLD_RBS-NEXT: v_mov_b32_e32 v3, v4
; OLD_RBS-NEXT: v_cvt_f32_u32_e32 v4, v3
; OLD_RBS-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v0
+; OLD_RBS-NEXT: v_add_nc_u32_e32 v4, 1, v3
; OLD_RBS-NEXT: s_or_b32 s0, vcc_lo, s0
; OLD_RBS-NEXT: s_andn2_b32 exec_lo, exec_lo, s0
; OLD_RBS-NEXT: s_cbranch_execnz .LBB15_1
@@ -446,14 +446,14 @@ define amdgpu_ps void @divergent_because_of_temporal_divergent_use(float %val, p
;
; NEW_RBS-LABEL: divergent_because_of_temporal_divergent_use:
; NEW_RBS: ; %bb.0: ; %entry
-; NEW_RBS-NEXT: s_mov_b32 s1, -1
+; NEW_RBS-NEXT: s_mov_b32 s1, 0
; NEW_RBS-NEXT: s_mov_b32 s0, 0
; NEW_RBS-NEXT: .LBB15_1: ; %loop
; NEW_RBS-NEXT: ; =>This Inner Loop Header: Depth=1
-; NEW_RBS-NEXT: s_add_i32 s1, s1, 1
; NEW_RBS-NEXT: v_cvt_f32_u32_e32 v3, s1
; NEW_RBS-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v0
; NEW_RBS-NEXT: v_mov_b32_e32 v3, s1
+; NEW_RBS-NEXT: s_add_i32 s1, s1, 1
; NEW_RBS-NEXT: s_or_b32 s0, vcc_lo, s0
; NEW_RBS-NEXT: s_andn2_b32 exec_lo, exec_lo, s0
; NEW_RBS-NEXT: s_cbranch_execnz .LBB15_1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
index a6659b2b1dd0d..281ce86a446d7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
@@ -354,12 +354,12 @@ define amdgpu_cs_chain void @control_flow(<3 x i32> inreg %sgpr, ptr inreg %call
; GISEL12-NEXT: s_and_saveexec_b32 s3, s8
; GISEL12-NEXT: s_cbranch_execz .LBB3_4
; GISEL12-NEXT: ; %bb.1: ; %shader.preheader
-; GISEL12-NEXT: v_add_nc_u32_e32 v1, -1, v12
+; GISEL12-NEXT: v_mov_b32_e32 v2, v12
; GISEL12-NEXT: s_mov_b32 s4, 0
; GISEL12-NEXT: .LBB3_2: ; %shader
; GISEL12-NEXT: ; =>This Inner Loop Header: Depth=1
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GISEL12-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GISEL12-NEXT: v_mov_b32_e32 v1, v2
; GISEL12-NEXT: s_or_saveexec_b32 s8, -1
; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v1, s8
@@ -368,9 +368,9 @@ define amdgpu_cs_chain void @control_flow(<3 x i32> inreg %sgpr, ptr inreg %call
; GISEL12-NEXT: s_wait_alu depctr_va_sdst(0)
; GISEL12-NEXT: v_mov_b32_e32 v0, s9
; GISEL12-NEXT: s_mov_b32 exec_lo, s8
-; GISEL12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v13, v1
+; GISEL12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v13
; GISEL12-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GISEL12-NEXT: v_mov_b32_e32 v11, v0
+; GISEL12-NEXT: v_dual_mov_b32 v11, v0 :: v_dual_add_nc_u32 v2, 1, v1
; GISEL12-NEXT: s_or_b32 s4, vcc_lo, s4
; GISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -419,20 +419,20 @@ define amdgpu_cs_chain void @control_flow(<3 x i32> inreg %sgpr, ptr inreg %call
; DAGISEL12-NEXT: s_and_saveexec_b32 s3, s8
; DAGISEL12-NEXT: s_cbranch_execz .LBB3_4
; DAGISEL12-NEXT: ; %bb.1: ; %shader.preheader
-; DAGISEL12-NEXT: v_add_nc_u32_e32 v1, -1, v12
+; DAGISEL12-NEXT: v_mov_b32_e32 v2, v12
; DAGISEL12-NEXT: s_mov_b32 s4, 0
; DAGISEL12-NEXT: .LBB3_2: ; %shader
; DAGISEL12-NEXT: ; =>This Inner Loop Header: Depth=1
; DAGISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; DAGISEL12-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; DAGISEL12-NEXT: v_mov_b32_e32 v1, v2
; DAGISEL12-NEXT: s_or_saveexec_b32 s8, -1
; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v1, s8
; DAGISEL12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL12-NEXT: v_cmp_ne_u32_e64 s9, 0, v0
; DAGISEL12-NEXT: s_mov_b32 exec_lo, s8
-; DAGISEL12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v13, v1
-; DAGISEL12-NEXT: v_mov_b32_e32 v11, s9
+; DAGISEL12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v13
+; DAGISEL12-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_add_nc_u32 v2, 1, v1
; DAGISEL12-NEXT: s_or_b32 s4, vcc_lo, s4
; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
@@ -472,17 +472,18 @@ define amdgpu_cs_chain void @control_flow(<3 x i32> inreg %sgpr, ptr inreg %call
; GISEL10-NEXT: s_and_saveexec_b32 s3, s8
; GISEL10-NEXT: s_cbranch_execz .LBB3_4
; GISEL10-NEXT: ; %bb.1: ; %shader.preheader
-; GISEL10-NEXT: v_add_nc_u32_e32 v1, -1, v12
+; GISEL10-NEXT: v_mov_b32_e32 v2, v12
; GISEL10-NEXT: s_mov_b32 s4, 0
; GISEL10-NEXT: .LBB3_2: ; %shader
; GISEL10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GISEL10-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; GISEL10-NEXT: v_mov_b32_e32 v1, v2
; GISEL10-NEXT: s_or_saveexec_b32 s8, -1
; GISEL10-NEXT: v_cndmask_b32_e64 v0, 0x47, v1, s8
; GISEL10-NEXT: v_cmp_ne_u32_e64 s9, 0, v0
; GISEL10-NEXT: v_mov_b32_e32 v0, s9
; GISEL10-NEXT: s_mov_b32 exec_lo, s8
-; GISEL10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v13, v1
+; GISEL10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v13
+; GISEL10-NEXT: v_add_nc_u32_e32 v2, 1, v1
; GISEL10-NEXT: v_mov_b32_e32 v11, v0
; GISEL10-NEXT: s_or_b32 s4, vcc_lo, s4
; GISEL10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4
@@ -520,16 +521,17 @@ define amdgpu_cs_chain void @control_flow(<3 x i32> inreg %sgpr, ptr inreg %call
; DAGISEL10-NEXT: s_and_saveexec_b32 s3, s8
; DAGISEL10-NEXT: s_cbranch_execz .LBB3_4
; DAGISEL10-NEXT: ; %bb.1: ; %shader.preheader
-; DAGISEL10-NEXT: v_add_nc_u32_e32 v1, -1, v12
+; DAGISEL10-NEXT: v_mov_b32_e32 v2, v12
; DAGISEL10-NEXT: s_mov_b32 s4, 0
; DAGISEL10-NEXT: .LBB3_2: ; %shader
; DAGISEL10-NEXT: ; =>This Inner Loop Header: Depth=1
-; DAGISEL10-NEXT: v_add_nc_u32_e32 v1, 1, v1
+; DAGISEL10-NEXT: v_mov_b32_e32 v1, v2
; DAGISEL10-NEXT: s_or_saveexec_b32 s8, -1
; DAGISEL10-NEXT: v_cndmask_b32_e64 v0, 0x47, v1, s8
; DAGISEL10-NEXT: v_cmp_ne_u32_e64 s9, 0, v0
; DAGISEL10-NEXT: s_mov_b32 exec_lo, s8
-; DAGISEL10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v13, v1
+; DAGISEL10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v13
+; DAGISEL10-NEXT: v_add_nc_u32_e32 v2, 1, v1
; DAGISEL10-NEXT: v_mov_b32_e32 v11, s9
; DAGISEL10-NEXT: s_or_b32 s4, vcc_lo, s4
; DAGISEL10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4
diff --git a/llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll b/llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
index dfd4870787e62..2cce66cf52692 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
+++ b/llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
@@ -39,7 +39,7 @@ define void @machinesink_loop_variable_out_of_divergent_loop(i32 %arg, i1 %cmp49
; CHECK-NEXT: ; %bb.4: ; %for.body51.preheader
; CHECK-NEXT: ; in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: v_mov_b32_e32 v4, v2
-; CHECK-NEXT: s_mov_b32 s9, 4
+; CHECK-NEXT: s_mov_b32 s9, 1
; CHECK-NEXT: s_mov_b32 s8, 0
; CHECK-NEXT: s_branch .LBB0_6
; CHECK-NEXT: .p2align 6
@@ -64,8 +64,9 @@ define void @machinesink_loop_variable_out_of_divergent_loop(i32 %arg, i1 %cmp49
; CHECK-NEXT: s_cbranch_execz .LBB0_5
; CHECK-NEXT: ; %bb.7: ; %if.then112
; CHECK-NEXT: ; in Loop: Header=BB0_6 Depth=2
+; CHECK-NEXT: s_add_i32 s10, s9, 3
; CHECK-NEXT: v_mov_b32_e32 v3, 0
-; CHECK-NEXT: v_mov_b32_e32 v4, s9
+; CHECK-NEXT: v_mov_b32_e32 v4, s10
; CHECK-NEXT: ds_write_b32 v3, v4
; CHECK-NEXT: s_branch .LBB0_5
; CHECK-NEXT: .LBB0_8: ; %for.body159.preheader
diff --git a/llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll b/llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
index b0bafd1aa9b82..8e12c7a5db3a9 100644
--- a/llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
+++ b/llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
@@ -177,7 +177,7 @@ define dso_local void @test_Array() nounwind {
; CHECK-LE-NEXT: sth r6, 2(r5)
; CHECK-LE-NEXT: addi r5, r5, 2
; CHECK-LE-NEXT: bdnz .LBB2_1
-; CHECK-LE-NEXT: .LBB2_2: # %for.cond.cleanup
+; CHECK-LE-NEXT: .LBB2_2: # %for.end
; CHECK-LE-NEXT: addi r3, r1, 48
; CHECK-LE-NEXT: bl test_arr
; CHECK-LE-NEXT: nop
@@ -208,7 +208,7 @@ define dso_local void @test_Array() nounwind {
; CHECK-BE-NEXT: sth r6, 2(r4)
; CHECK-BE-NEXT: addi r4, r4, 2
; CHECK-BE-NEXT: bdnz .LBB2_1
-; CHECK-BE-NEXT: .LBB2_2: # %for.cond.cleanup
+; CHECK-BE-NEXT: .LBB2_2: # %for.end
; CHECK-BE-NEXT: addi r3, r1, 128
; CHECK-BE-NEXT: bl test_arr
; CHECK-BE-NEXT: nop
diff --git a/llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll b/llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll
index 9d2d70d5a4b92..b0ffbd876a900 100644
--- a/llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll
+++ b/llvm/test/CodeGen/PowerPC/ctrloops-pseudo.ll
@@ -363,6 +363,12 @@ define i32 @test4(i32 %inp) {
; AIX64-NEXT: {{ $}}
; AIX64-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
; AIX64-NEXT: [[COPY1:%[0-9]+]]:gprc_and_gprc_nor0 = COPY [[COPY]].sub_32
+ ; AIX64-NEXT: [[LDtoc:%[0-9]+]]:g8rc = LDtoc target-flags(ppc-tlsgdm) @tls_var, $x2 :: (load (s64) from got)
+ ; AIX64-NEXT: [[LDtoc1:%[0-9]+]]:g8rc = LDtoc target-flags(ppc-tlsgd) @tls_var, $x2 :: (load (s64) from got)
+ ; AIX64-NEXT: [[TLSGDAIX8_:%[0-9]+]]:g8rc = TLSGDAIX8 killed [[LDtoc1]], killed [[LDtoc]]
+ ; AIX64-NEXT: [[COPY2:%[0-9]+]]:gprc = COPY [[TLSGDAIX8_]].sub_32
+ ; AIX64-NEXT: [[ADD4_:%[0-9]+]]:gprc_and_gprc_nor0 = ADD4 [[COPY1]], killed [[COPY2]]
+ ; AIX64-NEXT: [[ADDI:%[0-9]+]]:gprc = ADDI killed [[ADD4_]], 1
; AIX64-NEXT: [[CMPWI:%[0-9]+]]:crrc = CMPWI [[COPY1]], 1
; AIX64-NEXT: [[LI:%[0-9]+]]:gprc_and_gprc_nor0 = LI 1
; AIX64-NEXT: BCC 12, [[CMPWI]], %bb.4
@@ -374,7 +380,7 @@ define i32 @test4(i32 %inp) {
; AIX64-NEXT: successors: %bb.1(0x80000000)
; AIX64-NEXT: {{ $}}
; AIX64-NEXT: [[PHI:%[0-9]+]]:gprc = PHI [[LI]], %bb.3, [[COPY1]], %bb.0
- ; AIX64-NEXT: [[SUBF:%[0-9]+]]:gprc = SUBF [[PHI]], [[COPY1]]
+ ; AIX64-NEXT: [[SUBF:%[0-9]+]]:gprc = SUBF killed [[PHI]], [[COPY1]]
; AIX64-NEXT: [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
; AIX64-NEXT: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], killed [[SUBF]], %subreg.sub_32
; AIX64-NEXT: [[RLDICL:%[0-9]+]]:g8rc_and_g8rc_nox0 = RLDICL killed [[INSERT_SUBREG]], 0, 32
@@ -384,18 +390,15 @@ define i32 @test4(i32 %inp) {
; AIX64-NEXT: bb.1.for.body:
; AIX64-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; AIX64-NEXT: {{ $}}
+ ; AIX64-NEXT: [[PHI1:%[0-9]+]]:gprc_and_gprc_nor0 = PHI [[ADDI]], %bb.4, %2, %bb.1
+ ; AIX64-NEXT: [[ADDI1:%[0-9]+]]:gprc = ADDI [[PHI1]], -1
; AIX64-NEXT: [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
; AIX64-NEXT: BC killed [[DecreaseCTR8loop]], %bb.1
; AIX64-NEXT: B %bb.2
; AIX64-NEXT: {{ $}}
; AIX64-NEXT: bb.2.return:
- ; AIX64-NEXT: [[LDtoc:%[0-9]+]]:g8rc = LDtoc target-flags(ppc-tlsgdm) @tls_var, $x2 :: (load (s64) from got)
- ; AIX64-NEXT: [[LDtoc1:%[0-9]+]]:g8rc = LDtoc target-flags(ppc-tlsgd) @tls_var, $x2 :: (load (s64) from got)
- ; AIX64-NEXT: [[TLSGDAIX8_:%[0-9]+]]:g8rc = TLSGDAIX8 killed [[LDtoc1]], killed [[LDtoc]]
- ; AIX64-NEXT: [[COPY2:%[0-9]+]]:gprc = COPY [[TLSGDAIX8_]].sub_32
- ; AIX64-NEXT: [[ADD4_:%[0-9]+]]:gprc = ADD4 killed [[COPY2]], [[PHI]]
; AIX64-NEXT: [[DEF1:%[0-9]+]]:g8rc = IMPLICIT_DEF
- ; AIX64-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF1]], killed [[ADD4_]], %subreg.sub_32
+ ; AIX64-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF1]], [[ADDI1]], %subreg.sub_32
; AIX64-NEXT: $x3 = COPY [[INSERT_SUBREG1]]
; AIX64-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
;
@@ -405,6 +408,11 @@ define i32 @test4(i32 %inp) {
; AIX32-NEXT: liveins: $r3
; AIX32-NEXT: {{ $}}
; AIX32-NEXT: [[COPY:%[0-9]+]]:gprc_and_gprc_nor0 = COPY $r3
+ ; AIX32-NEXT: [[LWZtoc:%[0-9]+]]:gprc = LWZtoc target-flags(ppc-tlsgdm) @tls_var, $r2 :: (load (s32) from got)
+ ; AIX32-NEXT: [[LWZtoc1:%[0-9]+]]:gprc = LWZtoc target-flags(ppc-tlsgd) @tls_var, $r2 :: (load (s32) from got)
+ ; AIX32-NEXT: [[TLSGDAIX:%[0-9]+]]:gprc = TLSGDAIX killed [[LWZtoc1]], killed [[LWZtoc]]
+ ; AIX32-NEXT: [[ADD4_:%[0-9]+]]:gprc_and_gprc_nor0 = ADD4 [[COPY]], killed [[TLSGDAIX]]
+ ; AIX32-NEXT: [[ADDI:%[0-9]+]]:gprc = ADDI killed [[ADD4_]], 1
; AIX32-NEXT: [[CMPWI:%[0-9]+]]:crrc = CMPWI [[COPY]], 1
; AIX32-NEXT: [[LI:%[0-9]+]]:gprc_and_gprc_nor0 = LI 1
; AIX32-NEXT: BCC 12, [[CMPWI]], %bb.4
@@ -416,23 +424,21 @@ define i32 @test4(i32 %inp) {
; AIX32-NEXT: successors: %bb.1(0x80000000)
; AIX32-NEXT: {{ $}}
; AIX32-NEXT: [[PHI:%[0-9]+]]:gprc = PHI [[LI]], %bb.3, [[COPY]], %bb.0
- ; AIX32-NEXT: [[SUBF:%[0-9]+]]:gprc_and_gprc_nor0 = SUBF [[PHI]], [[COPY]]
- ; AIX32-NEXT: [[ADDI:%[0-9]+]]:gprc = ADDI killed [[SUBF]], 1
- ; AIX32-NEXT: MTCTRloop killed [[ADDI]], implicit-def dead $ctr
+ ; AIX32-NEXT: [[SUBF:%[0-9]+]]:gprc_and_gprc_nor0 = SUBF killed [[PHI]], [[COPY]]
+ ; AIX32-NEXT: [[ADDI1:%[0-9]+]]:gprc = ADDI killed [[SUBF]], 1
+ ; AIX32-NEXT: MTCTRloop killed [[ADDI1]], implicit-def dead $ctr
; AIX32-NEXT: {{ $}}
; AIX32-NEXT: bb.1.for.body:
; AIX32-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; AIX32-NEXT: {{ $}}
+ ; AIX32-NEXT: [[PHI1:%[0-9]+]]:gprc_and_gprc_nor0 = PHI [[ADDI]], %bb.4, %2, %bb.1
+ ; AIX32-NEXT: [[ADDI2:%[0-9]+]]:gprc = ADDI [[PHI1]], -1
; AIX32-NEXT: [[DecreaseCTRloop:%[0-9]+]]:crbitrc = DecreaseCTRloop 1, implicit-def dead $ctr, implicit $ctr
; AIX32-NEXT: BC killed [[DecreaseCTRloop]], %bb.1
; AIX32-NEXT: B %bb.2
; AIX32-NEXT: {{ $}}
; AIX32-NEXT: bb.2.return:
- ; AIX32-NEXT: [[LWZtoc:%[0-9]+]]:gprc = LWZtoc target-flags(ppc-tlsgdm) @tls_var, $r2 :: (load (s32) from got)
- ; AIX32-NEXT: [[LWZtoc1:%[0-9]+]]:gprc = LWZtoc target-flags(ppc-tlsgd) @tls_var, $r2 :: (load (s32) from got)
- ; AIX32-NEXT: [[TLSGDAIX:%[0-9]+]]:gprc = TLSGDAIX killed [[LWZtoc1]], killed [[LWZtoc]]
- ; AIX32-NEXT: [[ADD4_:%[0-9]+]]:gprc = ADD4 killed [[TLSGDAIX]], [[PHI]]
- ; AIX32-NEXT: $r3 = COPY [[ADD4_]]
+ ; AIX32-NEXT: $r3 = COPY [[ADDI2]]
; AIX32-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
;
; LE64-LABEL: name: test4
@@ -442,10 +448,16 @@ define i32 @test4(i32 %inp) {
; LE64-NEXT: {{ $}}
; LE64-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x3
; LE64-NEXT: [[COPY1:%[0-9]+]]:gprc_and_gprc_nor0 = COPY [[COPY]].sub_32
+ ; LE64-NEXT: [[ADDISgotTprelHA:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDISgotTprelHA $x2, @tls_var
+ ; LE64-NEXT: [[LDgotTprelL:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDgotTprelL @tls_var, killed [[ADDISgotTprelHA]]
+ ; LE64-NEXT: [[ADD8TLS:%[0-9]+]]:g8rc = ADD8TLS killed [[LDgotTprelL]], target-flags(ppc-tls) @tls_var
+ ; LE64-NEXT: [[COPY2:%[0-9]+]]:gprc = COPY [[ADD8TLS]].sub_32
+ ; LE64-NEXT: [[ADD4_:%[0-9]+]]:gprc_and_gprc_nor0 = ADD4 [[COPY1]], killed [[COPY2]]
+ ; LE64-NEXT: [[ADDI:%[0-9]+]]:gprc = ADDI killed [[ADD4_]], 1
; LE64-NEXT: [[CMPWI:%[0-9]+]]:crrc = CMPWI [[COPY1]], 1
; LE64-NEXT: [[LI:%[0-9]+]]:gprc_and_gprc_nor0 = LI 1
; LE64-NEXT: [[ISEL:%[0-9]+]]:gprc = ISEL [[COPY1]], [[LI]], [[CMPWI]].sub_lt
- ; LE64-NEXT: [[SUBF:%[0-9]+]]:gprc = SUBF [[ISEL]], [[COPY1]]
+ ; LE64-NEXT: [[SUBF:%[0-9]+]]:gprc = SUBF killed [[ISEL]], [[COPY1]]
; LE64-NEXT: [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
; LE64-NEXT: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], killed [[SUBF]], %subreg.sub_32
; LE64-NEXT: [[RLDICL:%[0-9]+]]:g8rc_and_g8rc_nox0 = RLDICL killed [[INSERT_SUBREG]], 0, 32
@@ -455,18 +467,15 @@ define i32 @test4(i32 %inp) {
; LE64-NEXT: bb.1.for.body:
; LE64-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; LE64-NEXT: {{ $}}
+ ; LE64-NEXT: [[PHI:%[0-9]+]]:gprc_and_gprc_nor0 = PHI [[ADDI]], %bb.0, %2, %bb.1
+ ; LE64-NEXT: [[ADDI1:%[0-9]+]]:gprc = ADDI [[PHI]], -1
; LE64-NEXT: [[DecreaseCTR8loop:%[0-9]+]]:crbitrc = DecreaseCTR8loop 1, implicit-def dead $ctr8, implicit $ctr8
; LE64-NEXT: BC killed [[DecreaseCTR8loop]], %bb.1
; LE64-NEXT: B %bb.2
; LE64-NEXT: {{ $}}
; LE64-NEXT: bb.2.return:
- ; LE64-NEXT: [[ADDISgotTprelHA:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDISgotTprelHA $x2, @tls_var
- ; LE64-NEXT: [[LDgotTprelL:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDgotTprelL @tls_var, killed [[ADDISgotTprelHA]]
- ; LE64-NEXT: [[ADD8TLS:%[0-9]+]]:g8rc = ADD8TLS killed [[LDgotTprelL]], target-flags(ppc-tls) @tls_var
- ; LE64-NEXT: [[COPY2:%[0-9]+]]:gprc = COPY [[ADD8TLS]].sub_32
- ; LE64-NEXT: [[ADD4_:%[0-9]+]]:gprc = ADD4 killed [[COPY2]], [[ISEL]]
; LE64-NEXT: [[DEF1:%[0-9]+]]:g8rc = IMPLICIT_DEF
- ; LE64-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF1]], killed [[ADD4_]], %subreg.sub_32
+ ; LE64-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF1]], [[ADDI1]], %subreg.sub_32
; LE64-NEXT: $x3 = COPY [[INSERT_SUBREG1]]
; LE64-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
entry:
diff --git a/llvm/test/CodeGen/PowerPC/ctrloops.ll b/llvm/test/CodeGen/PowerPC/ctrloops.ll
index 7cf773644216d..3ca2f20222c06 100644
--- a/llvm/test/CodeGen/PowerPC/ctrloops.ll
+++ b/llvm/test/CodeGen/PowerPC/ctrloops.ll
@@ -91,7 +91,7 @@ for.body: ; preds = %for.body, %entry
return: ; preds = %for.body
ret i32 %val
; CHECK-LABEL: @test4
+; CHECK: __tls_get_addr
; CHECK: mtctr
; CHECK: bdnz
-; CHECK: __tls_get_addr
}
diff --git a/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll b/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
index 9bf619983ee78..a19a47721a41e 100644
--- a/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
+++ b/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
@@ -16,66 +16,63 @@ define void @print_res(ptr %p) nounwind {
; CHECK-NEXT: li 5, 1
; CHECK-NEXT: cmpldi 4, 1
; CHECK-NEXT: iselgt 4, 4, 5
-; CHECK-NEXT: li 5, 0
; CHECK-NEXT: mtctr 4
-; CHECK-NEXT: li 8, -1
+; CHECK-NEXT: li 4, 0
+; CHECK-NEXT: li 5, -1
; CHECK-NEXT: lbz 6, 0(3)
-; CHECK-NEXT: li 4, 1
; CHECK-NEXT: bdz .LBB0_6
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: xori 7, 6, 84
-; CHECK-NEXT: clrldi 6, 8, 32
-; CHECK-NEXT: addi 4, 4, 1
-; CHECK-NEXT: addi 9, 8, -1
+; CHECK-NEXT: clrldi 6, 5, 32
+; CHECK-NEXT: addi 5, 5, -1
; CHECK-NEXT: lbzx 6, 3, 6
; CHECK-NEXT: bdz .LBB0_5
; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: cntlzw 7, 7
-; CHECK-NEXT: addi 4, 4, 1
; CHECK-NEXT: srwi 8, 7, 5
; CHECK-NEXT: xori 7, 6, 84
-; CHECK-NEXT: clrldi 6, 9, 32
-; CHECK-NEXT: addi 9, 9, -1
+; CHECK-NEXT: clrldi 6, 5, 32
+; CHECK-NEXT: addi 5, 5, -1
; CHECK-NEXT: lbzx 6, 3, 6
; CHECK-NEXT: bdz .LBB0_4
-; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_3:
-; CHECK-NEXT: clrldi 11, 9, 32
-; CHECK-NEXT: cntlzw 10, 7
+; CHECK-NEXT: clrldi 10, 5, 32
+; CHECK-NEXT: cntlzw 9, 7
; CHECK-NEXT: xori 7, 6, 84
-; CHECK-NEXT: addi 9, 9, -1
-; CHECK-NEXT: lbzx 6, 3, 11
-; CHECK-NEXT: addi 4, 4, 1
-; CHECK-NEXT: add 5, 5, 8
-; CHECK-NEXT: srwi 8, 10, 5
+; CHECK-NEXT: addi 5, 5, -1
+; CHECK-NEXT: lbzx 6, 3, 10
+; CHECK-NEXT: add 4, 4, 8
+; CHECK-NEXT: srwi 8, 9, 5
; CHECK-NEXT: bdnz .LBB0_3
; CHECK-NEXT: .LBB0_4:
-; CHECK-NEXT: add 5, 5, 8
+; CHECK-NEXT: add 4, 4, 8
; CHECK-NEXT: .LBB0_5:
; CHECK-NEXT: cntlzw 3, 7
; CHECK-NEXT: srwi 3, 3, 5
-; CHECK-NEXT: add 5, 5, 3
+; CHECK-NEXT: add 4, 4, 3
; CHECK-NEXT: .LBB0_6:
; CHECK-NEXT: xori 3, 6, 84
; CHECK-NEXT: mflr 0
; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: srwi 3, 3, 5
-; CHECK-NEXT: add 3, 5, 3
+; CHECK-NEXT: add 3, 4, 3
; CHECK-NEXT: stdu 1, -128(1)
; CHECK-NEXT: clrldi 6, 3, 32
; CHECK-NEXT: addis 3, 2, .LC0 at toc@ha
+; CHECK-NEXT: neg 4, 5
; CHECK-NEXT: li 5, 0
; CHECK-NEXT: std 0, 144(1)
; CHECK-NEXT: ld 3, .LC0 at toc@l(3)
; CHECK-NEXT: std 5, 120(1)
; CHECK-NEXT: li 5, 3
; CHECK-NEXT: clrldi 4, 4, 32
-; CHECK-NEXT: std 4, 104(1)
-; CHECK-NEXT: li 4, 3
; CHECK-NEXT: li 7, 0
; CHECK-NEXT: li 8, 3
; CHECK-NEXT: li 10, 0
; CHECK-NEXT: std 5, 96(1)
+; CHECK-NEXT: std 4, 104(1)
+; CHECK-NEXT: li 4, 3
; CHECK-NEXT: li 5, 0
; CHECK-NEXT: bl printf
; CHECK-NEXT: nop
diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/expander-reused-value-insert-point.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/expander-reused-value-insert-point.ll
index dc5938fbd5871..b32f506ebd7d9 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/X86/expander-reused-value-insert-point.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/expander-reused-value-insert-point.ll
@@ -26,11 +26,9 @@ define void @test(ptr %ioptr, i32 %X, ptr %start, ptr %end) {
; CHECK-NEXT: [[EC0:%.*]] = icmp eq ptr [[ADD_PTR94]], [[END:%.*]]
; CHECK-NEXT: br i1 [[EC0]], label [[FOR_BODY37]], label [[FOR_END_LOOPEXIT:%.*]]
; CHECK: for.end.loopexit:
-; CHECK-NEXT: [[ADD_PTR94_LCSSA:%.*]] = phi ptr [ [[ADD_PTR94]], [[FOR_BODY37]] ]
; CHECK-NEXT: br label [[FOR_END:%.*]]
; CHECK: for.end:
-; CHECK-NEXT: [[P0R_0_LCSSA:%.*]] = phi ptr [ [[ADD_PTR94_LCSSA]], [[FOR_END_LOOPEXIT]] ]
-; CHECK-NEXT: [[EC1:%.*]] = icmp eq ptr [[P0R_0_LCSSA]], [[END]]
+; CHECK-NEXT: [[EC1:%.*]] = icmp eq ptr [[ADD_PTR94]], [[END]]
; CHECK-NEXT: br i1 [[EC1]], label [[FOR_BODY15]], label [[FOR_INC133:%.*]]
; CHECK: for.inc133:
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/normalization-during-scev-expansion.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/normalization-during-scev-expansion.ll
index 3ee0833bc1300..297e2416e5132 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/X86/normalization-during-scev-expansion.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/normalization-during-scev-expansion.ll
@@ -7,39 +7,38 @@ target triple = "x86_64-apple-macos"
declare i1 @cond()
define ptr @test(ptr %dst, i64 %v4, i64 %v5, i64 %v6, i64 %v7) {
-; CHECK-LABEL: define ptr @test
-; CHECK-SAME: (ptr [[DST:%.*]], i64 [[V4:%.*]], i64 [[V5:%.*]], i64 [[V6:%.*]], i64 [[V7:%.*]]) {
+; CHECK-LABEL: define ptr @test(
+; CHECK-SAME: ptr [[DST:%.*]], i64 [[V4:%.*]], i64 [[V5:%.*]], i64 [[V6:%.*]], i64 [[V7:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[V5]], [[V4]]
-; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[TMP0]], 4
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[V7]], [[V6]]
-; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 3
-; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], -8
-; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP5:%.*]] = shl nsw i64 [[V5]], 3
-; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP5]], 8
-; CHECK-NEXT: [[TMP7:%.*]] = shl i64 [[V4]], 4
-; CHECK-NEXT: [[TMP8:%.*]] = add nuw nsw i64 [[TMP7]], 8
-; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[V5]], [[TMP8]]
-; CHECK-NEXT: [[TMP10:%.*]] = shl i64 [[V7]], 3
-; CHECK-NEXT: [[TMP11:%.*]] = shl i64 [[V6]], 3
-; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP10]], [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], -8
-; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP13]]
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[V7]], [[V6]]
+; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[TMP0]], 3
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], -8
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP2]]
+; CHECK-NEXT: [[TMP3:%.*]] = shl nsw i64 [[V5]], 3
+; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], 8
+; CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[V4]], 4
+; CHECK-NEXT: [[TMP6:%.*]] = add nuw nsw i64 [[TMP5]], 8
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[V5]], [[TMP6]]
+; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[V7]], 3
+; CHECK-NEXT: [[TMP9:%.*]] = shl i64 [[V6]], 3
+; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP8]], [[TMP9]]
+; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[TMP10]], -8
+; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP11]]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[LSR_IV4:%.*]] = phi ptr [ [[SCEVGEP5:%.*]], [[LOOP]] ], [ [[SCEVGEP3]], [[ENTRY:%.*]] ]
; CHECK-NEXT: [[LSR_IV:%.*]] = phi ptr [ [[SCEVGEP1:%.*]], [[LOOP]] ], [ [[SCEVGEP]], [[ENTRY]] ]
-; CHECK-NEXT: [[SCEVGEP6:%.*]] = getelementptr i8, ptr [[LSR_IV4]], i64 [[TMP9]]
+; CHECK-NEXT: [[SCEVGEP6:%.*]] = getelementptr i8, ptr [[LSR_IV4]], i64 [[TMP7]]
; CHECK-NEXT: store i64 0, ptr [[SCEVGEP6]], align 8
; CHECK-NEXT: [[C:%.*]] = call i1 @cond()
-; CHECK-NEXT: [[SCEVGEP1]] = getelementptr i8, ptr [[LSR_IV]], i64 [[TMP6]]
-; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[SCEVGEP1]], i64 [[TMP1]]
-; CHECK-NEXT: [[SCEVGEP5]] = getelementptr i8, ptr [[LSR_IV4]], i64 [[TMP6]]
+; CHECK-NEXT: [[SCEVGEP1]] = getelementptr i8, ptr [[LSR_IV]], i64 [[TMP4]]
+; CHECK-NEXT: [[SCEVGEP5]] = getelementptr i8, ptr [[LSR_IV4]], i64 [[TMP4]]
; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
-; CHECK-NEXT: [[RES:%.*]] = phi ptr [ [[SCEVGEP2]], [[LOOP]] ]
-; CHECK-NEXT: ret ptr [[RES]]
+; CHECK-NEXT: [[TMP12:%.*]] = mul i64 [[V5]], [[V4]]
+; CHECK-NEXT: [[TMP13:%.*]] = shl i64 [[TMP12]], 4
+; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[SCEVGEP1]], i64 [[TMP13]]
+; CHECK-NEXT: ret ptr [[SCEVGEP2]]
;
entry:
%mul = mul nsw i64 %v5, %v4
@@ -64,8 +63,8 @@ exit:
}
define i32 @test_pr63678(i1 %c) {
-; CHECK-LABEL: define i32 @test_pr63678
-; CHECK-SAME: (i1 [[C:%.*]]) {
+; CHECK-LABEL: define i32 @test_pr63678(
+; CHECK-SAME: i1 [[C:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP_1_PREHEADER:%.*]]
; CHECK: bb:
diff --git a/llvm/test/Transforms/LoopStrengthReduce/callbr-critical-edge-splitting.ll b/llvm/test/Transforms/LoopStrengthReduce/callbr-critical-edge-splitting.ll
index e7afc96c72d5b..bd4d8ddea70b7 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/callbr-critical-edge-splitting.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/callbr-critical-edge-splitting.ll
@@ -10,7 +10,7 @@ define dso_local i32 @test1() local_unnamed_addr {
; LEGACYPM-NEXT: br label [[FOR_COND:%.*]]
; LEGACYPM: for.cond:
; LEGACYPM-NEXT: callbr void asm sideeffect "", "!i,!i,~{dirflag},~{fpsr},~{flags}"()
-; LEGACYPM-NEXT: to label [[ASM_FALLTHROUGH_I_I:%.*]] [label [[COND_TRUE_I:%.*]], label %for.endsplit]
+; LEGACYPM-NEXT: to label [[ASM_FALLTHROUGH_I_I:%.*]] [label [[COND_TRUE_I:%.*]], label [[FOR_ENDSPLIT:%.*]]]
; LEGACYPM: asm.fallthrough.i.i:
; LEGACYPM-NEXT: unreachable
; LEGACYPM: cond.true.i:
@@ -27,7 +27,7 @@ define dso_local i32 @test1() local_unnamed_addr {
; LEGACYPM: for.endsplit:
; LEGACYPM-NEXT: br label [[FOR_END]]
; LEGACYPM: for.end:
-; LEGACYPM-NEXT: [[PGOCOUNT_PROMOTED24:%.*]] = phi i64 [ [[LSR_IV_NEXT_LCSSA_LCSSA]], [[DO_BODY_I_I_RDRAND_INT_EXIT_I_CRIT_EDGE_FOR_END_CRIT_EDGE]] ], [ undef, [[FOR_ENDSPLIT:%.*]] ]
+; LEGACYPM-NEXT: [[PGOCOUNT_PROMOTED24:%.*]] = phi i64 [ [[LSR_IV_NEXT_LCSSA_LCSSA]], [[DO_BODY_I_I_RDRAND_INT_EXIT_I_CRIT_EDGE_FOR_END_CRIT_EDGE]] ], [ undef, [[FOR_ENDSPLIT]] ]
; LEGACYPM-NEXT: ret i32 undef
;
; NEWPM-LABEL: @test1(
@@ -35,7 +35,7 @@ define dso_local i32 @test1() local_unnamed_addr {
; NEWPM-NEXT: br label [[FOR_COND:%.*]]
; NEWPM: for.cond:
; NEWPM-NEXT: callbr void asm sideeffect "", "!i,!i,~{dirflag},~{fpsr},~{flags}"()
-; NEWPM-NEXT: to label [[ASM_FALLTHROUGH_I_I:%.*]] [label [[COND_TRUE_I:%.*]], label %for.end]
+; NEWPM-NEXT: to label [[ASM_FALLTHROUGH_I_I:%.*]] [label [[COND_TRUE_I:%.*]], label [[FOR_ENDSPLIT:%.*]]]
; NEWPM: asm.fallthrough.i.i:
; NEWPM-NEXT: unreachable
; NEWPM: cond.true.i:
@@ -43,12 +43,16 @@ define dso_local i32 @test1() local_unnamed_addr {
; NEWPM: do.body.i.i.do.body.i.i_crit_edge:
; NEWPM-NEXT: br i1 true, label [[DO_BODY_I_I_RDRAND_INT_EXIT_I_CRIT_EDGE:%.*]], label [[DO_BODY_I_I_DO_BODY_I_I_CRIT_EDGE]]
; NEWPM: do.body.i.i.rdrand_int.exit.i_crit_edge:
-; NEWPM-NEXT: [[TMP0:%.*]] = add i64 1, undef
; NEWPM-NEXT: br i1 true, label [[FOR_END:%.*]], label [[FOR_INC:%.*]]
+; NEWPM: do.body.i.i.rdrand_int.exit.i_crit_edge.for.end_crit_edge:
+; NEWPM-NEXT: [[LSR_IV_NEXT_LCSSA_LCSSA:%.*]] = phi i64 [ undef, [[DO_BODY_I_I_RDRAND_INT_EXIT_I_CRIT_EDGE]] ]
+; NEWPM-NEXT: br label [[FOR_END1:%.*]]
; NEWPM: for.inc:
; NEWPM-NEXT: br label [[FOR_COND]]
+; NEWPM: for.endsplit:
+; NEWPM-NEXT: br label [[FOR_END1]]
; NEWPM: for.end:
-; NEWPM-NEXT: [[PGOCOUNT_PROMOTED24:%.*]] = phi i64 [ undef, [[FOR_COND]] ], [ [[TMP0]], [[DO_BODY_I_I_RDRAND_INT_EXIT_I_CRIT_EDGE]] ]
+; NEWPM-NEXT: [[PGOCOUNT_PROMOTED24:%.*]] = phi i64 [ [[LSR_IV_NEXT_LCSSA_LCSSA]], [[FOR_END]] ], [ undef, [[FOR_ENDSPLIT]] ]
; NEWPM-NEXT: ret i32 undef
;
entry:
diff --git a/llvm/test/Transforms/LoopStrengthReduce/funclet.ll b/llvm/test/Transforms/LoopStrengthReduce/funclet.ll
index da5721a72a906..54fb154479a08 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/funclet.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/funclet.ll
@@ -16,9 +16,9 @@ define void @f() personality ptr @_except_handler3 {
; CHECK-NEXT: br label [[THROW:%.*]]
; CHECK: throw:
; CHECK-NEXT: invoke void @reserve()
-; CHECK-NEXT: to label [[THROW]] unwind label [[PAD:%.*]]
+; CHECK-NEXT: to label [[THROW]] unwind label [[PAD:%.*]]
; CHECK: pad:
-; CHECK-NEXT: [[CS:%.*]] = catchswitch within none [label %unreachable] unwind label [[BLAH2:%.*]]
+; CHECK-NEXT: [[CS:%.*]] = catchswitch within none [label [[UNREACHABLE:%.*]]] unwind label [[BLAH2:%.*]]
; CHECK: unreachable:
; CHECK-NEXT: [[TMP0:%.*]] = catchpad within [[CS]] []
; CHECK-NEXT: unreachable
@@ -75,9 +75,9 @@ define void @g() personality ptr @_except_handler3 {
; CHECK-NEXT: br label [[THROW:%.*]]
; CHECK: throw:
; CHECK-NEXT: invoke void @reserve()
-; CHECK-NEXT: to label [[THROW]] unwind label [[PAD:%.*]]
+; CHECK-NEXT: to label [[THROW]] unwind label [[PAD:%.*]]
; CHECK: pad:
-; CHECK-NEXT: [[CS:%.*]] = catchswitch within none [label [[UNREACHABLE:%.*]], label %blah] unwind to caller
+; CHECK-NEXT: [[CS:%.*]] = catchswitch within none [label [[UNREACHABLE:%.*]], label [[BLAH:%.*]]] unwind to caller
; CHECK: unreachable:
; CHECK-NEXT: [[TMP0:%.*]] = catchpad within [[CS]] []
; CHECK-NEXT: unreachable
@@ -89,7 +89,7 @@ define void @g() personality ptr @_except_handler3 {
; CHECK: leave:
; CHECK-NEXT: ret void
; CHECK: loop_body:
-; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[ITER:%.*]] ], [ 0, [[BLAH:%.*]] ]
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[ITER:%.*]] ], [ 0, [[BLAH]] ]
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i32 [[LSR_IV]], -1
; CHECK-NEXT: [[LSR_IV_NEXT1:%.*]] = inttoptr i32 [[LSR_IV_NEXT]] to ptr
; CHECK-NEXT: [[TMP100:%.*]] = icmp eq ptr [[LSR_IV_NEXT1]], null
@@ -139,9 +139,9 @@ define void @h() personality ptr @_except_handler3 {
; CHECK-NEXT: br label [[THROW:%.*]]
; CHECK: throw:
; CHECK-NEXT: invoke void @reserve()
-; CHECK-NEXT: to label [[THROW]] unwind label [[PAD:%.*]]
+; CHECK-NEXT: to label [[THROW]] unwind label [[PAD:%.*]]
; CHECK: pad:
-; CHECK-NEXT: [[CS:%.*]] = catchswitch within none [label [[UNREACHABLE:%.*]], label %blug] unwind to caller
+; CHECK-NEXT: [[CS:%.*]] = catchswitch within none [label [[UNREACHABLE:%.*]], label [[BLUG:%.*]]] unwind to caller
; CHECK: unreachable:
; CHECK-NEXT: [[TMP0:%.*]] = catchpad within [[CS]] []
; CHECK-NEXT: unreachable
@@ -153,7 +153,7 @@ define void @h() personality ptr @_except_handler3 {
; CHECK: leave:
; CHECK-NEXT: ret void
; CHECK: loop_body:
-; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[ITER:%.*]] ], [ 0, [[BLUG:%.*]] ]
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[ITER:%.*]] ], [ 0, [[BLUG]] ]
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i32 [[LSR_IV]], -1
; CHECK-NEXT: [[LSR_IV_NEXT1:%.*]] = inttoptr i32 [[LSR_IV_NEXT]] to ptr
; CHECK-NEXT: [[TMP100:%.*]] = icmp eq ptr [[LSR_IV_NEXT1]], null
@@ -203,9 +203,9 @@ define void @i() personality ptr @_except_handler3 {
; CHECK-NEXT: br label [[THROW:%.*]]
; CHECK: throw:
; CHECK-NEXT: invoke void @reserve()
-; CHECK-NEXT: to label [[THROW]] unwind label [[CATCHPAD:%.*]]
+; CHECK-NEXT: to label [[THROW]] unwind label [[CATCHPAD:%.*]]
; CHECK: catchpad:
-; CHECK-NEXT: [[CS:%.*]] = catchswitch within none [label %cp_body] unwind label [[CLEANUPPAD:%.*]]
+; CHECK-NEXT: [[CS:%.*]] = catchswitch within none [label [[CP_BODY:%.*]]] unwind label [[CLEANUPPAD:%.*]]
; CHECK: cp_body:
; CHECK-NEXT: [[TMP0:%.*]] = catchpad within [[CS]] []
; CHECK-NEXT: br label [[LOOP_HEAD:%.*]]
@@ -268,21 +268,21 @@ define void @test1(ptr %b, ptr %c) personality ptr @__CxxFrameHandler3 {
; CHECK: for.cond:
; CHECK-NEXT: [[D_0:%.*]] = phi ptr [ [[B:%.*]], [[ENTRY:%.*]] ], [ [[INCDEC_PTR:%.*]], [[FOR_INC:%.*]] ]
; CHECK-NEXT: invoke void @external(ptr [[D_0]])
-; CHECK-NEXT: to label [[FOR_INC]] unwind label [[CATCH_DISPATCH:%.*]]
+; CHECK-NEXT: to label [[FOR_INC]] unwind label [[CATCH_DISPATCH:%.*]]
; CHECK: for.inc:
; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i32, ptr [[D_0]], i32 1
; CHECK-NEXT: br label [[FOR_COND]]
; CHECK: catch.dispatch:
-; CHECK-NEXT: [[CS:%.*]] = catchswitch within none [label %catch] unwind label [[CATCH_DISPATCH_2:%.*]]
+; CHECK-NEXT: [[CS:%.*]] = catchswitch within none [label [[CATCH:%.*]]] unwind label [[CATCH_DISPATCH_2:%.*]]
; CHECK: catch:
; CHECK-NEXT: [[TMP0:%.*]] = catchpad within [[CS]] [ptr null, i32 64, ptr null]
; CHECK-NEXT: catchret from [[TMP0]] to label [[TRY_CONT:%.*]]
; CHECK: try.cont:
; CHECK-NEXT: invoke void @external(ptr [[C:%.*]])
-; CHECK-NEXT: to label [[TRY_CONT_7:%.*]] unwind label [[CATCH_DISPATCH_2]]
+; CHECK-NEXT: to label [[TRY_CONT_7:%.*]] unwind label [[CATCH_DISPATCH_2]]
; CHECK: catch.dispatch.2:
; CHECK-NEXT: [[E_0:%.*]] = phi ptr [ [[C]], [[TRY_CONT]] ], [ [[B]], [[CATCH_DISPATCH]] ]
-; CHECK-NEXT: [[CS2:%.*]] = catchswitch within none [label %catch.4] unwind to caller
+; CHECK-NEXT: [[CS2:%.*]] = catchswitch within none [label [[CATCH_4:%.*]]] unwind to caller
; CHECK: catch.4:
; CHECK-NEXT: [[TMP1:%.*]] = catchpad within [[CS2]] [ptr null, i32 64, ptr null]
; CHECK-NEXT: unreachable
@@ -331,15 +331,14 @@ define i32 @test2() personality ptr @_except_handler3 {
; CHECK: for.body:
; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_INC:%.*]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: invoke void @reserve()
-; CHECK-NEXT: to label [[FOR_INC]] unwind label [[CATCH_DISPATCH:%.*]]
+; CHECK-NEXT: to label [[FOR_INC]] unwind label [[CATCH_DISPATCH:%.*]]
; CHECK: catch.dispatch:
-; CHECK-NEXT: [[TMP18:%.*]] = catchswitch within none [label %catch.handler] unwind to caller
+; CHECK-NEXT: [[TMP18:%.*]] = catchswitch within none [label [[CATCH_HANDLER:%.*]]] unwind to caller
; CHECK: catch.handler:
-; CHECK-NEXT: [[PHI_LCSSA:%.*]] = phi i32 [ [[PHI]], [[CATCH_DISPATCH]] ]
; CHECK-NEXT: [[TMP19:%.*]] = catchpad within [[TMP18]] [ptr null]
; CHECK-NEXT: catchret from [[TMP19]] to label [[DONE:%.*]]
; CHECK: done:
-; CHECK-NEXT: ret i32 [[PHI_LCSSA]]
+; CHECK-NEXT: ret i32 [[PHI]]
; CHECK: for.inc:
; CHECK-NEXT: [[INC]] = add i32 [[PHI]], 1
; CHECK-NEXT: br label [[FOR_BODY]]
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