[llvm-branch-commits] [llvm] 3d76932 - Revert "[AArch64][CodeGen] match (or x (not y)) to generate mov+orn (#190769)"
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llvm-branch-commits at lists.llvm.org
Thu Apr 9 01:53:55 PDT 2026
Author: Shreeyash Pandey
Date: 2026-04-09T14:23:51+05:30
New Revision: 3d76932c87b951c5992746b2e9762e30926204fa
URL: https://github.com/llvm/llvm-project/commit/3d76932c87b951c5992746b2e9762e30926204fa
DIFF: https://github.com/llvm/llvm-project/commit/3d76932c87b951c5992746b2e9762e30926204fa.diff
LOG: Revert "[AArch64][CodeGen] match (or x (not y)) to generate mov+orn (#190769)"
This reverts commit 42629d7a174a62b98835e2e4c738ccdce027590b.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/CodeGen/AArch64/arm64-atomic.ll
llvm/test/CodeGen/AArch64/atomicrmw-O0.ll
llvm/test/CodeGen/AArch64/logical-op-with-not.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index d3c714fcbb564..9f82616a21d0e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3324,10 +3324,6 @@ def : InstAlias<"tst $src1, $src2$sh",
(ANDSXrs XZR, GPR64:$src1,
(logical_shifted_reg64 GPR64:$src2, logical_shift64:$sh)), 2>;
-def : Pat<(or (not GPR32:$Wm), (i32 imm:$x)),
- (ORNWrr (MOVi32imm imm:$x), GPR32:$Wm)>;
-def : Pat<(or (not GPR64:$Xm), (i64 imm:$x)),
- (ORNXrr (MOVi64imm imm:$x), GPR64:$Xm)>;
def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
diff --git a/llvm/test/CodeGen/AArch64/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/arm64-atomic.ll
index 386ce0296519f..739fc8bbcaf07 100644
--- a/llvm/test/CodeGen/AArch64/arm64-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-atomic.ll
@@ -82,10 +82,10 @@ define i64 @val_compare_and_swap_64(ptr %p, i64 %cmp, i64 %new) #0 {
define i32 @fetch_and_nand(ptr %p) #0 {
; CHECK-LABEL: fetch_and_nand:
-; CHECK: mov [[CST_REG:w[0-9]+]], #-8
; CHECK: [[TRYBB:.?LBB[0-9_]+]]:
; CHECK: ldxr w[[DEST_REG:[0-9]+]], [x0]
-; CHECK: orn [[SCRATCH2_REG:w[0-9]+]], [[CST_REG]], w[[DEST_REG]]
+; CHECK: mvn [[TMP_REG:w[0-9]+]], w[[DEST_REG]]
+; CHECK: orr [[SCRATCH2_REG:w[0-9]+]], [[TMP_REG]], #0xfffffff8
; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
; CHECK: cbnz [[SCRATCH_REG]], [[TRYBB]]
diff --git a/llvm/test/CodeGen/AArch64/atomicrmw-O0.ll b/llvm/test/CodeGen/AArch64/atomicrmw-O0.ll
index f7f6a723fd4f6..731274149a24a 100644
--- a/llvm/test/CodeGen/AArch64/atomicrmw-O0.ll
+++ b/llvm/test/CodeGen/AArch64/atomicrmw-O0.ll
@@ -303,8 +303,8 @@ define i8 @test_rmw_nand_8(ptr %dst) {
; NOLSE-NEXT: // Child Loop BB5_2 Depth 2
; NOLSE-NEXT: ldr w9, [sp, #28] // 4-byte Reload
; NOLSE-NEXT: ldr x11, [sp, #16] // 8-byte Reload
-; NOLSE-NEXT: mov w8, #-2 // =0xfffffffe
-; NOLSE-NEXT: orn w12, w8, w9
+; NOLSE-NEXT: mvn w8, w9
+; NOLSE-NEXT: orr w12, w8, #0xfffffffe
; NOLSE-NEXT: .LBB5_2: // %atomicrmw.start
; NOLSE-NEXT: // Parent Loop BB5_1 Depth=1
; NOLSE-NEXT: // => This Inner Loop Header: Depth=2
@@ -339,8 +339,8 @@ define i8 @test_rmw_nand_8(ptr %dst) {
; LSE-NEXT: // =>This Inner Loop Header: Depth=1
; LSE-NEXT: ldr w9, [sp, #28] // 4-byte Reload
; LSE-NEXT: ldr x11, [sp, #16] // 8-byte Reload
-; LSE-NEXT: mov w8, #-2 // =0xfffffffe
-; LSE-NEXT: orn w10, w8, w9
+; LSE-NEXT: mvn w8, w9
+; LSE-NEXT: orr w10, w8, #0xfffffffe
; LSE-NEXT: mov w8, w9
; LSE-NEXT: casalb w8, w10, [x11]
; LSE-NEXT: subs w9, w8, w9, uxtb
@@ -371,8 +371,8 @@ define i16 @test_rmw_nand_16(ptr %dst) {
; NOLSE-NEXT: // Child Loop BB6_2 Depth 2
; NOLSE-NEXT: ldr w9, [sp, #28] // 4-byte Reload
; NOLSE-NEXT: ldr x11, [sp, #16] // 8-byte Reload
-; NOLSE-NEXT: mov w8, #-2 // =0xfffffffe
-; NOLSE-NEXT: orn w12, w8, w9
+; NOLSE-NEXT: mvn w8, w9
+; NOLSE-NEXT: orr w12, w8, #0xfffffffe
; NOLSE-NEXT: .LBB6_2: // %atomicrmw.start
; NOLSE-NEXT: // Parent Loop BB6_1 Depth=1
; NOLSE-NEXT: // => This Inner Loop Header: Depth=2
@@ -407,8 +407,8 @@ define i16 @test_rmw_nand_16(ptr %dst) {
; LSE-NEXT: // =>This Inner Loop Header: Depth=1
; LSE-NEXT: ldr w9, [sp, #28] // 4-byte Reload
; LSE-NEXT: ldr x11, [sp, #16] // 8-byte Reload
-; LSE-NEXT: mov w8, #-2 // =0xfffffffe
-; LSE-NEXT: orn w10, w8, w9
+; LSE-NEXT: mvn w8, w9
+; LSE-NEXT: orr w10, w8, #0xfffffffe
; LSE-NEXT: mov w8, w9
; LSE-NEXT: casalh w8, w10, [x11]
; LSE-NEXT: subs w9, w8, w9, uxth
@@ -439,8 +439,8 @@ define i32 @test_rmw_nand_32(ptr %dst) {
; NOLSE-NEXT: // Child Loop BB7_2 Depth 2
; NOLSE-NEXT: ldr w9, [sp, #28] // 4-byte Reload
; NOLSE-NEXT: ldr x11, [sp, #16] // 8-byte Reload
-; NOLSE-NEXT: mov w8, #-2 // =0xfffffffe
-; NOLSE-NEXT: orn w12, w8, w9
+; NOLSE-NEXT: mvn w8, w9
+; NOLSE-NEXT: orr w12, w8, #0xfffffffe
; NOLSE-NEXT: .LBB7_2: // %atomicrmw.start
; NOLSE-NEXT: // Parent Loop BB7_1 Depth=1
; NOLSE-NEXT: // => This Inner Loop Header: Depth=2
@@ -475,8 +475,8 @@ define i32 @test_rmw_nand_32(ptr %dst) {
; LSE-NEXT: // =>This Inner Loop Header: Depth=1
; LSE-NEXT: ldr w9, [sp, #28] // 4-byte Reload
; LSE-NEXT: ldr x11, [sp, #16] // 8-byte Reload
-; LSE-NEXT: mov w8, #-2 // =0xfffffffe
-; LSE-NEXT: orn w10, w8, w9
+; LSE-NEXT: mvn w8, w9
+; LSE-NEXT: orr w10, w8, #0xfffffffe
; LSE-NEXT: mov w8, w9
; LSE-NEXT: casal w8, w10, [x11]
; LSE-NEXT: subs w9, w8, w9
diff --git a/llvm/test/CodeGen/AArch64/logical-op-with-not.ll b/llvm/test/CodeGen/AArch64/logical-op-with-not.ll
index accc8b43743ff..2f5610a18aa9c 100644
--- a/llvm/test/CodeGen/AArch64/logical-op-with-not.ll
+++ b/llvm/test/CodeGen/AArch64/logical-op-with-not.ll
@@ -17,8 +17,8 @@ define i64 @and_bic(i64 %0, i64 %1) {
define i64 @and_bic2(i32 %0, i64 %1) {
; CHECK-LABEL: and_bic2:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-65281 // =0xffff00ff
-; CHECK-NEXT: orn w8, w8, w0
+; CHECK-NEXT: mvn w8, w0
+; CHECK-NEXT: orr w8, w8, #0xffff00ff
; CHECK-NEXT: and x0, x8, x1
; CHECK-NEXT: ret
%3 = and i32 %0, 65280
@@ -31,8 +31,8 @@ define i64 @and_bic2(i32 %0, i64 %1) {
define i32 @and_bic3(i32 %0, i32 %1) {
; CHECK-LABEL: and_bic3:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-65281 // =0xffff00ff
-; CHECK-NEXT: orn w8, w8, w0
+; CHECK-NEXT: mvn w8, w0
+; CHECK-NEXT: orr w8, w8, #0xffff00ff
; CHECK-NEXT: and w0, w8, w1
; CHECK-NEXT: ret
%3 = and i32 %0, 65280
@@ -56,8 +56,8 @@ define i64 @and_eon(i64 %0, i64 %1) {
define i64 @and_eon2(i32 %0, i64 %1) {
; CHECK-LABEL: and_eon2:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-65281 // =0xffff00ff
-; CHECK-NEXT: orn w8, w8, w0
+; CHECK-NEXT: mvn w8, w0
+; CHECK-NEXT: orr w8, w8, #0xffff00ff
; CHECK-NEXT: eor x0, x8, x1
; CHECK-NEXT: ret
%3 = and i32 %0, 65280
@@ -94,8 +94,8 @@ define i64 @and_orn(i64 %0, i64 %1) {
define i64 @and_orn2(i32 %0, i64 %1) {
; CHECK-LABEL: and_orn2:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-65281 // =0xffff00ff
-; CHECK-NEXT: orn w8, w8, w0
+; CHECK-NEXT: mvn w8, w0
+; CHECK-NEXT: orr w8, w8, #0xffff00ff
; CHECK-NEXT: orr x0, x8, x1
; CHECK-NEXT: ret
%3 = and i32 %0, 65280
@@ -738,27 +738,3 @@ for.body:
%exitcond.not = icmp eq i64 %indvars.iv.next, 256
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
}
-
-; ORN with a constant should use "mov + orn" like BIC does, not "mvn + orr".
-
-define i32 @orn_cst_i32(i32 %c) {
-; CHECK-LABEL: orn_cst_i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #4 // =0x4
-; CHECK-NEXT: orn w0, w8, w0
-; CHECK-NEXT: ret
- %not = xor i32 %c, -1
- %or = or i32 %not, 4
- ret i32 %or
-}
-
-define i64 @orn_cst_i64(i64 %c) {
-; CHECK-LABEL: orn_cst_i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #4 // =0x4
-; CHECK-NEXT: orn x0, x8, x0
-; CHECK-NEXT: ret
- %not = xor i64 %c, -1
- %or = or i64 %not, 4
- ret i64 %or
-}
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