[llvm-branch-commits] [llvm] cf8e6b9 - Revert "[Hexagon][MIR] Serialize HexagonMachineFunctionInfo::StackAlignBaseRe…"
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Apr 8 09:28:11 PDT 2026
Author: Brian Cain
Date: 2026-04-08T11:28:07-05:00
New Revision: cf8e6b9cdcbc25fbb96d6248910d604a4a53ac69
URL: https://github.com/llvm/llvm-project/commit/cf8e6b9cdcbc25fbb96d6248910d604a4a53ac69
DIFF: https://github.com/llvm/llvm-project/commit/cf8e6b9cdcbc25fbb96d6248910d604a4a53ac69.diff
LOG: Revert "[Hexagon][MIR] Serialize HexagonMachineFunctionInfo::StackAlignBaseRe…"
This reverts commit cd66d79be19b6db00500ba4508b3946ef1caec88.
Added:
Modified:
llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp
llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h
llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
llvm/lib/Target/Hexagon/HexagonTargetMachine.h
llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp
index e1444416a020c..539db8f55005a 100644
--- a/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp
@@ -7,9 +7,6 @@
//===----------------------------------------------------------------------===//
#include "HexagonMachineFunctionInfo.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/TargetRegisterInfo.h"
-#include "llvm/Support/raw_ostream.h"
using namespace llvm;
@@ -22,24 +19,3 @@ MachineFunctionInfo *HexagonMachineFunctionInfo::clone(
const {
return DestMF.cloneInfo<HexagonMachineFunctionInfo>(*this);
}
-
-static yaml::StringValue regToString(Register Reg,
- const TargetRegisterInfo &TRI) {
- yaml::StringValue Dest;
- if (Reg.isValid()) {
- raw_string_ostream OS(Dest.Value);
- OS << printReg(Reg, &TRI);
- }
- return Dest;
-}
-
-yaml::HexagonFunctionInfo::HexagonFunctionInfo(
- const llvm::HexagonMachineFunctionInfo &MFI, const TargetRegisterInfo &TRI)
- : StackAlignBaseReg(regToString(MFI.getStackAlignBaseReg(), TRI)) {}
-
-void yaml::HexagonFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
- MappingTraits<HexagonFunctionInfo>::mapping(YamlIO, *this);
-}
-
-void HexagonMachineFunctionInfo::initializeBaseYamlFields(
- const yaml::HexagonFunctionInfo &YamlMFI) {}
diff --git a/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h
index 6349a1a07fc55..c5df02fa3b89c 100644
--- a/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h
@@ -9,16 +9,11 @@
#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
-#include "llvm/CodeGen/MIRYamlMapping.h"
#include "llvm/CodeGen/MachineFunction.h"
#include <map>
namespace llvm {
-namespace yaml {
-struct HexagonFunctionInfo;
-} // end namespace yaml
-
namespace Hexagon {
const unsigned int StartPacket = 0x1;
@@ -53,8 +48,6 @@ class HexagonMachineFunctionInfo : public MachineFunctionInfo {
const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
const override;
- void initializeBaseYamlFields(const yaml::HexagonFunctionInfo &YamlMFI);
-
unsigned getSRetReturnReg() const { return SRetReturnReg; }
void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
@@ -94,28 +87,6 @@ class HexagonMachineFunctionInfo : public MachineFunctionInfo {
Register getStackAlignBaseReg() const { return StackAlignBaseReg; }
};
-namespace yaml {
-
-/// Hexagon-specific MachineFunction properties for YAML serialization.
-struct HexagonFunctionInfo final : public yaml::MachineFunctionInfo {
- StringValue StackAlignBaseReg;
-
- HexagonFunctionInfo() = default;
- HexagonFunctionInfo(const llvm::HexagonMachineFunctionInfo &MFI,
- const TargetRegisterInfo &TRI);
-
- void mappingImpl(yaml::IO &YamlIO) override;
- ~HexagonFunctionInfo() override = default;
-};
-
-template <> struct MappingTraits<HexagonFunctionInfo> {
- static void mapping(IO &YamlIO, HexagonFunctionInfo &MFI) {
- YamlIO.mapOptional("stackAlignBaseReg", MFI.StackAlignBaseReg);
- }
-};
-
-} // end namespace yaml
-
} // end namespace llvm
#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
index a56dfc5f58392..254f1bb021f97 100644
--- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
@@ -242,6 +242,16 @@ bool HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// Add the offset from the instruction.
int RealOffset = Offset + MI.getOperand(FIOp+1).getImm();
+ // If AP is used as the base register, add it to this block's liveins.
+ // AP is defined in the entry block and may be used in other blocks for
+ // stack access. Liveness must be accurate for the verifier.
+ auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
+ Register AP = HMFI.getStackAlignBaseReg();
+ if (AP.isValid() && BP == AP) {
+ if (!MB.isLiveIn(AP))
+ MB.addLiveIn(AP);
+ }
+
unsigned Opc = MI.getOpcode();
switch (Opc) {
case Hexagon::PS_fia:
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
index e42fb0b9866b3..e1af6ec8bb116 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -20,7 +20,6 @@
#include "HexagonTargetTransformInfo.h"
#include "HexagonVectorLoopCarriedReuse.h"
#include "TargetInfo/HexagonTargetInfo.h"
-#include "llvm/CodeGen/MIRParser/MIParser.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/VLIWMachineScheduler.h"
@@ -300,41 +299,6 @@ MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo(
Allocator, F, STI);
}
-yaml::MachineFunctionInfo *
-HexagonTargetMachine::createDefaultFuncInfoYAML() const {
- return new yaml::HexagonFunctionInfo();
-}
-
-yaml::MachineFunctionInfo *
-HexagonTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
- const auto *MFI = MF.getInfo<HexagonMachineFunctionInfo>();
- const auto &TRI = *MF.getSubtarget().getRegisterInfo();
- return new yaml::HexagonFunctionInfo(*MFI, TRI);
-}
-
-bool HexagonTargetMachine::parseMachineFunctionInfo(
- const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
- SMDiagnostic &Error, SMRange &SourceRange) const {
- const auto &YamlMFI = static_cast<const yaml::HexagonFunctionInfo &>(MFI_);
- MachineFunction &MF = PFS.MF;
- HexagonMachineFunctionInfo *MFI = MF.getInfo<HexagonMachineFunctionInfo>();
-
- MFI->initializeBaseYamlFields(YamlMFI);
-
- // Parse StackAlignBaseReg register name
- if (!YamlMFI.StackAlignBaseReg.Value.empty()) {
- Register Reg;
- if (parseNamedRegisterReference(PFS, Reg, YamlMFI.StackAlignBaseReg.Value,
- Error)) {
- SourceRange = YamlMFI.StackAlignBaseReg.SourceRange;
- return true;
- }
- MFI->setStackAlignBaseReg(Reg);
- }
-
- return false;
-}
-
HexagonTargetMachine::~HexagonTargetMachine() = default;
ScheduleDAGInstrs *
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
index 98a21bbba4794..48e0c08c0cab2 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
@@ -47,14 +47,6 @@ class HexagonTargetMachine : public CodeGenTargetMachineImpl {
createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
const TargetSubtargetInfo *STI) const override;
- yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
- yaml::MachineFunctionInfo *
- convertFuncInfoToYAML(const MachineFunction &MF) const override;
- bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
- PerFunctionMIParsingState &PFS,
- SMDiagnostic &Error,
- SMRange &SourceRange) const override;
-
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
return true;
}
diff --git a/llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir b/llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir
index 2a6dbefb77a2a..fefe6e40fbef8 100644
--- a/llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir
+++ b/llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir
@@ -5,8 +5,6 @@
# Verify that PS_aligna is placed AFTER all CSR spills.
#
# CHECK-LABEL: name: test_aligna_expansion
-# CHECK: machineFunctionInfo:
-# CHECK-NEXT: stackAlignBaseReg: '$r16'
# CHECK: S2_allocframe
# CHECK: S2_storerd_io $r30, -8
# CHECK: S2_storerd_io $r30, -16
@@ -17,13 +15,20 @@
# CHECK: PS_aligna
# CHECK-NOT: S2_storerd_io
#
+# Verify that AP (R16) is added to liveins of blocks that use it.
+# CHECK: bb.3:
+# CHECK-NEXT: successors:
+# CHECK-NEXT: liveins: {{.*}}$r16
+#
# SPILL-FUNC-LABEL: name: test_aligna_expansion
-# SPILL-FUNC: machineFunctionInfo:
-# SPILL-FUNC-NEXT: stackAlignBaseReg: '$r16'
# SPILL-FUNC: S2_allocframe
# SPILL-FUNC: SAVE_REGISTERS_CALL_V4
# SPILL-FUNC: PS_aligna
# SPILL-FUNC-NOT: SAVE_REGISTERS_CALL_V4
+#
+# SPILL-FUNC: bb.3:
+# SPILL-FUNC-NEXT: successors:
+# SPILL-FUNC-NEXT: liveins: {{.*}}$r16
--- |
declare void @external_func()
@@ -34,8 +39,6 @@
name: test_aligna_expansion
alignment: 16
tracksRegLiveness: true
-machineFunctionInfo:
- stackAlignBaseReg: '$r16'
frameInfo:
maxAlignment: 128
adjustsStack: true
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