[llvm-branch-commits] [llvm] [AMDGPU] DPP wave reduction for double types - 2 (PR #189391)
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Wed Apr 8 04:55:26 PDT 2026
github-actions[bot] wrote:
<!--PREMERGE ADVISOR COMMENT: Linux-->
# :penguin: Linux x64 Test Results
* 3175 tests passed
* 7 tests skipped
All executed tests passed, but another part of the build **failed**. Click on a failure below to see the details.
<details>
<summary>lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/SIISelLowering.cpp.o</summary>
```
FAILED: lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/SIISelLowering.cpp.o
sccache /opt/llvm/bin/clang++ -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GLIBCXX_USE_CXX11_ABI=1 -D_GNU_SOURCE -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_EXTENSIVE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/AMDGPU -I/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU -I/home/gha/actions-runner/_work/llvm-project/llvm-project/build/include -I/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/include -gmlt -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror -Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion -Wno-pass-failed -Wmisleading-indentation -Wctad-maybe-unsupported -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -std=c++17 -fvisibility=hidden -UNDEBUG -fno-exceptions -funwind-tables -fno-rtti -MD -MT lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/SIISelLowering.cpp.o -MF lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/SIISelLowering.cpp.o.d -o lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/SIISelLowering.cpp.o -c /home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:6387:35: error: no matching function for call to 'ExtractSubRegs'
6387 | auto [Src0Lo, Src0Hi] = ExtractSubRegs(MI, Src0Operand, SrcRegClass);
| ^~~~~~~~~~~~~~
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:5776:1: note: candidate function not viable: requires 5 arguments, but 3 were provided
5776 | ExtractSubRegs(MachineInstr &MI, MachineOperand &Op,
| ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5777 | const TargetRegisterClass *SrcRC, const GCNSubtarget &ST,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5778 | MachineRegisterInfo &MRI) {
| ~~~~~~~~~~~~~~~~~~~~~~~~
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:6388:35: error: no matching function for call to 'ExtractSubRegs'
6388 | auto [Src1Lo, Src1Hi] = ExtractSubRegs(MI, Src1Operand, SrcRegClass);
| ^~~~~~~~~~~~~~
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:5776:1: note: candidate function not viable: requires 5 arguments, but 3 were provided
5776 | ExtractSubRegs(MachineInstr &MI, MachineOperand &Op,
| ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5777 | const TargetRegisterClass *SrcRC, const GCNSubtarget &ST,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5778 | MachineRegisterInfo &MRI) {
| ~~~~~~~~~~~~~~~~~~~~~~~~
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:6431:13: error: no matching function for call to 'ExtractSubRegs'
6431 | ExtractSubRegs(MI, IdentityCopyInstr->getOperand(0), SrcRegClass);
| ^~~~~~~~~~~~~~
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:5776:1: note: candidate function not viable: requires 5 arguments, but 3 were provided
5776 | ExtractSubRegs(MachineInstr &MI, MachineOperand &Op,
| ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5777 | const TargetRegisterClass *SrcRC, const GCNSubtarget &ST,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5778 | MachineRegisterInfo &MRI) {
| ~~~~~~~~~~~~~~~~~~~~~~~~
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:6433:13: error: no matching function for call to 'ExtractSubRegs'
6433 | ExtractSubRegs(MI, MI.getOperand(1), SrcRegClass);
| ^~~~~~~~~~~~~~
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:5776:1: note: candidate function not viable: requires 5 arguments, but 3 were provided
5776 | ExtractSubRegs(MachineInstr &MI, MachineOperand &Op,
| ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5777 | const TargetRegisterClass *SrcRC, const GCNSubtarget &ST,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5778 | MachineRegisterInfo &MRI) {
| ~~~~~~~~~~~~~~~~~~~~~~~~
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:6493:31: error: no matching function for call to 'ExtractSubRegs'
6493 | auto [Op1L, Op1H] = ExtractSubRegs(MI, DPPRowShr8Op, SrcRegClass);
| ^~~~~~~~~~~~~~
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:5776:1: note: candidate function not viable: requires 5 arguments, but 3 were provided
5776 | ExtractSubRegs(MachineInstr &MI, MachineOperand &Op,
| ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5777 | const TargetRegisterClass *SrcRC, const GCNSubtarget &ST,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5778 | MachineRegisterInfo &MRI) {
| ~~~~~~~~~~~~~~~~~~~~~~~~
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:6572:17: error: no matching function for call to 'ExtractSubRegs'
6572 | ExtractSubRegs(MI, RowBcast15Op, SrcRegClass);
| ^~~~~~~~~~~~~~
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:5776:1: note: candidate function not viable: requires 5 arguments, but 3 were provided
5776 | ExtractSubRegs(MachineInstr &MI, MachineOperand &Op,
| ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5777 | const TargetRegisterClass *SrcRC, const GCNSubtarget &ST,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5778 | MachineRegisterInfo &MRI) {
| ~~~~~~~~~~~~~~~~~~~~~~~~
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:6620:29: error: no matching function for call to 'ExtractSubRegs'
6620 | auto [Op1L, Op1H] = ExtractSubRegs(MI, FinalDPPResultOperand, SrcRC);
| ^~~~~~~~~~~~~~
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp:5776:1: note: candidate function not viable: requires 5 arguments, but 3 were provided
5776 | ExtractSubRegs(MachineInstr &MI, MachineOperand &Op,
| ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5777 | const TargetRegisterClass *SrcRC, const GCNSubtarget &ST,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
5778 | MachineRegisterInfo &MRI) {
| ~~~~~~~~~~~~~~~~~~~~~~~~
7 errors generated.
```
</details>
If these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the `infrastructure` label.
https://github.com/llvm/llvm-project/pull/189391
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