[llvm-branch-commits] [llvm] c55c1c1 - [TargetLowering] Speculative fix for a non-determinism issue between different compilers. (#190219)

[Cullen Rhodes via llvm-branch-commits]

Author: Craig Topper
Date: 2026-04-06T18:47:01Z
New Revision: c55c1c1140e10a693685ece7917cacec192c83fe

URL: https://github.com/llvm/llvm-project/commit/c55c1c1140e10a693685ece7917cacec192c83fe
DIFF: https://github.com/llvm/llvm-project/commit/c55c1c1140e10a693685ece7917cacec192c83fe.diff

LOG: [TargetLowering] Speculative fix for a non-determinism issue between different compilers. (#190219)

The evaluation order of function arguments is unspecified by the C++
standard. We had two getNode calls as function arguments which causes
the nodes to be created in a different order depending on the compiler
used. This patch moves them to their own variables to ensure they are
called in the same order on all compilers.

Possible fix for #190148.

(cherry picked from commit e2e5db840109e9a5d5bb190fcae350161a6e5481)

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index ee489f9fc74f9..b218b91c19cbb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -11239,10 +11239,10 @@ void TargetLowering::forceExpandMultiply(SelectionDAG &DAG, const SDLoc &dl,
   // If HiLHS and HiRHS are set, multiply them by the opposite low part and add
   // the products to Hi.
   if (HiLHS) {
+    SDValue RHLL = DAG.getNode(ISD::MUL, dl, VT, HiRHS, LHS);
+    SDValue RLLH = DAG.getNode(ISD::MUL, dl, VT, RHS, HiLHS);
     Hi = DAG.getNode(ISD::ADD, dl, VT, Hi,
-                     DAG.getNode(ISD::ADD, dl, VT,
-                                 DAG.getNode(ISD::MUL, dl, VT, HiRHS, LHS),
-                                 DAG.getNode(ISD::MUL, dl, VT, RHS, HiLHS)));
+                     DAG.getNode(ISD::ADD, dl, VT, RHLL, RLLH));
   }
 }