[llvm-branch-commits] [llvm] [DAGCombiner][GlobalISel] Extend allMulUsesCanBeContracted with FMA/FMAD pattern (PR #188117)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Apr 3 08:57:18 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-selectiondag
@llvm/pr-subscribers-backend-amdgpu
Author: Adel Ejjeh (adelejjeh)
<details>
<summary>Changes</summary>
Supersedes #<!-- -->169735 (PR 5/5). Split into a stack of 5 PRs per reviewer request.
---
Add FMA/FMAD recognition to `allMulUsesCanBeContracted()`: when a multiply is used as an operand of an FMA/FMAD, the guard checks whether the FMA's consumer enables chain reassociation that can eliminate the multiply. Two sub-patterns are recognized:
1. **Direct chain reassociation** (`fmul -> fma -> {fadd, fsub}`): Contractable only if the consumer `fadd`/`fsub` has the `reassoc` flag. Chain reassociation transforms `fadd(fma(a, b, fmul(c, d)), e)` into `fma(a, b, fma(c, d, e))`, eliminating the multiply. Without `reassoc`, the basic `fadd -> fma` fold fires instead, re-computing the multiply and causing duplication.
2. **FPEXT chain reassociation** (`fmul -> fpext -> fma -> {fadd, fsub}` and `fmul -> fma -> fpext -> {fadd, fsub}`): Contractable without `reassoc` because the aggressive fpext folds (inside `if (Aggressive)`) handle these patterns directly.
Changes:
- **DAGCombiner.cpp**: Add `ISD::FMA`/`ISD::FMAD` case to `allMulUsesCanBeContracted()`. FMA/FMAD handler iterates FMA users; accepts if any user is `FP_EXTEND`, or if it is `FADD`/`FSUB` with `hasAllowReassociation()`. FPEXT -> FMA/FMAD handler iterates FMA users; accepts `FADD`/`FSUB` without `reassoc` check. Guards added to 8 fold sites in `visitFADDForFMACombine` and `visitFSUBForFMACombine`.
- **CombinerHelper.cpp**: Add `G_FMA`/`G_FMAD` case to `allMulUsesCanBeContracted()` with equivalent logic using `FmReassoc`. Guards added to 4 fold sites in `matchCombineFAddFpExtFMulToFMadOrFMAAggressive`.
### Test Changes
#### `fma-multiple-uses-contraction.ll`
The final FMA/FMAD chain section is activated: all remaining `P0-` prefixed baseline checks are replaced with real-prefix CHECK lines. The `--allow-unused-prefixes` flag is removed from all RUN lines since all check prefixes are now actively used.
- `fma_chain_fadd_no_reassoc`: Demonstrates the guard correctly blocking contraction when `reassoc` is absent (both SDAG and GISel show shared `v_mul` without duplication).
- `fma_chain_fadd_reassoc`: Demonstrates chain reassociation firing when `reassoc nsz` is present (no `v_mul`, multiply eliminated via FMA chain).
#### Other lit tests
- `dagcombine-fma-crash.ll` (`main`): CHECK lines revert to pre-stack (upstream) behavior. The fmul→FMA chain is now recognized as contractable, restoring the contraction that was temporarily blocked by PR 2/5.
- `dagcombine-fma-fmad.ll` (`_amdgpu_ps_main`): CHECK lines revert to pre-stack (upstream) behavior for the same reason.
---
_This PR was split from the original_ #<!-- -->169735 _with the assistance of_ [_Claude Code_](https://claude.ai/code)_._
---
Patch is 117.22 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/188117.diff
5 Files Affected:
- (modified) llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp (+57-1)
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+55-1)
- (modified) llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll (+10-12)
- (modified) llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll (+80-89)
- (modified) llvm/test/CodeGen/AMDGPU/fma-multiple-uses-contraction.ll (+706-822)
``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 75ead4c775c6c..45c446eba41dc 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -6321,7 +6321,10 @@ static bool hasMoreUses(const MachineInstr &MI0, const MachineInstr &MI1,
/// - fmul --> fneg --> fsub: Contraction through fneg
/// - fmul --> fneg --> fpext --> fsub: FNEG then FPEXT folds if foldable
/// - fmul --> fpext --> {fadd, fsub}: FPEXT folds if foldable
+/// - fmul --> fpext --> {fma, fmad} --> {fadd, fsub}: FPEXT chain reassoc
/// - fmul --> fpext --> fneg --> fsub: FPEXT then FNEG to FSUB
+/// - fmul --> {fma, fmad} --> {fadd, fsub} (reassoc): Direct chain reassoc
+/// - fmul --> {fma, fmad} --> fpext --> {fadd, fsub}: FPEXT outer chain
bool CombinerHelper::allMulUsesCanBeContracted(
const MachineInstr &MI, unsigned PreferredFusedOpcode) const {
const auto &TLI = getTargetLowering();
@@ -6367,7 +6370,8 @@ bool CombinerHelper::allMulUsesCanBeContracted(
continue;
}
- // FP_EXTEND - check if ALL users are FADD, FSUB, or FNEG --> FSUB
+ // FP_EXTEND - check if ALL users are FADD, FSUB, FNEG --> FSUB, or
+ // FMA/FMAD --> {FADD, FSUB}
if (Opcode == TargetOpcode::G_FPEXT) {
Register FPExtReg = UseMI.getOperand(0).getReg();
@@ -6383,6 +6387,26 @@ bool CombinerHelper::allMulUsesCanBeContracted(
ExtUseOpcode == TargetOpcode::G_FSUB) {
continue;
}
+ if (ExtUseOpcode == TargetOpcode::G_FMA ||
+ ExtUseOpcode == TargetOpcode::G_FMAD) {
+ // FPEXT --> FMA/FMAD is only contractable if the FMA/FMAD is
+ // used by FADD or FSUB (chain reassociation can fire to
+ // eliminate the multiply).
+ Register FMAReg = FPExtUseMI.getOperand(0).getReg();
+ bool FMAUsedByAddSub = false;
+ for (const MachineInstr &FMAUseMI :
+ MRI.use_nodbg_instructions(FMAReg)) {
+ unsigned FMAUseOp = FMAUseMI.getOpcode();
+ if (FMAUseOp == TargetOpcode::G_FADD ||
+ FMAUseOp == TargetOpcode::G_FSUB) {
+ FMAUsedByAddSub = true;
+ break;
+ }
+ }
+ if (FMAUsedByAddSub)
+ continue;
+ return false;
+ }
if (ExtUseOpcode == TargetOpcode::G_FNEG) {
// FP_EXTEND --> FNEG --> FSUB
Register FPExtFNegReg = FPExtUseMI.getOperand(0).getReg();
@@ -6398,6 +6422,34 @@ bool CombinerHelper::allMulUsesCanBeContracted(
continue;
}
+ // FMA/FMAD - the multiply is used as an operand of an FMA. This is
+ // contractable only if chain reassociation can fire to eliminate the
+ // multiply. Chain reassociation transforms:
+ // fadd/fsub(fma(a, b, fmul(c, d)), e) -> fma(a, b, fma(c, d, e))
+ // For direct fmul -> fma -> fadd/fsub, this requires the consumer
+ // fadd/fsub to have the reassoc flag. For fmul -> fma -> fpext ->
+ // fadd/fsub, the aggressive fpext folds handle it without reassoc.
+ if (Opcode == TargetOpcode::G_FMA || Opcode == TargetOpcode::G_FMAD) {
+ Register FMAReg = UseMI.getOperand(0).getReg();
+ bool FMAIsContractable = false;
+ for (const MachineInstr &FMAUseMI : MRI.use_nodbg_instructions(FMAReg)) {
+ unsigned FMAUseOp = FMAUseMI.getOpcode();
+ if (FMAUseOp == TargetOpcode::G_FPEXT) {
+ FMAIsContractable = true;
+ break;
+ }
+ if ((FMAUseOp == TargetOpcode::G_FADD ||
+ FMAUseOp == TargetOpcode::G_FSUB) &&
+ FMAUseMI.getFlag(MachineInstr::MIFlag::FmReassoc)) {
+ FMAIsContractable = true;
+ break;
+ }
+ }
+ if (FMAIsContractable)
+ continue;
+ return false;
+ }
+
// Any other use type is not currently recognized as contractable.
return false;
}
@@ -6666,6 +6718,7 @@ bool CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMAAggressive(
mi_match(LHS.MI->getOperand(3).getReg(), MRI,
m_GFPExt(m_MInstr(FMulMI))) &&
isContractableFMul(*FMulMI, AllowFusionGlobally) &&
+ allMulUsesCanBeContracted(*FMulMI, PreferredFusedOpcode) &&
TLI.isFPExtFoldable(MI, PreferredFusedOpcode, DstType,
MRI.getType(FMulMI->getOperand(0).getReg()))) {
MatchInfo = [=](MachineIRBuilder &B) {
@@ -6686,6 +6739,7 @@ bool CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMAAggressive(
FMAMI->getOpcode() == PreferredFusedOpcode) {
MachineInstr *FMulMI = MRI.getVRegDef(FMAMI->getOperand(3).getReg());
if (isContractableFMul(*FMulMI, AllowFusionGlobally) &&
+ allMulUsesCanBeContracted(*FMulMI, PreferredFusedOpcode) &&
TLI.isFPExtFoldable(MI, PreferredFusedOpcode, DstType,
MRI.getType(FMAMI->getOperand(0).getReg()))) {
MatchInfo = [=](MachineIRBuilder &B) {
@@ -6707,6 +6761,7 @@ bool CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMAAggressive(
mi_match(RHS.MI->getOperand(3).getReg(), MRI,
m_GFPExt(m_MInstr(FMulMI))) &&
isContractableFMul(*FMulMI, AllowFusionGlobally) &&
+ allMulUsesCanBeContracted(*FMulMI, PreferredFusedOpcode) &&
TLI.isFPExtFoldable(MI, PreferredFusedOpcode, DstType,
MRI.getType(FMulMI->getOperand(0).getReg()))) {
MatchInfo = [=](MachineIRBuilder &B) {
@@ -6727,6 +6782,7 @@ bool CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMAAggressive(
FMAMI->getOpcode() == PreferredFusedOpcode) {
MachineInstr *FMulMI = MRI.getVRegDef(FMAMI->getOperand(3).getReg());
if (isContractableFMul(*FMulMI, AllowFusionGlobally) &&
+ allMulUsesCanBeContracted(*FMulMI, PreferredFusedOpcode) &&
TLI.isFPExtFoldable(MI, PreferredFusedOpcode, DstType,
MRI.getType(FMAMI->getOperand(0).getReg()))) {
MatchInfo = [=](MachineIRBuilder &B) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6593ff2f3f52b..a8be683e5285d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17690,7 +17690,10 @@ static bool isFusedOp(const MatchContextClass &Matcher, SDValue N) {
/// - fmul --> fneg --> fsub: Contraction through fneg
/// - fmul --> fneg --> fpext --> fsub: FNEG then FPEXT folds if foldable
/// - fmul --> fpext --> {fadd, fsub}: FPEXT folds if foldable
+/// - fmul --> fpext --> {fma, fmad} --> {fadd, fsub}: FPEXT chain reassoc
/// - fmul --> fpext --> fneg --> fsub: FPEXT then FNEG to FSUB
+/// - fmul --> {fma, fmad} --> {fadd, fsub} (reassoc): Direct chain reassoc
+/// - fmul --> {fma, fmad} --> fpext --> {fadd, fsub}: FPEXT outer chain
static bool allMulUsesCanBeContracted(SDValue Mul,
const unsigned PreferredFusedOpcode,
const TargetLowering &TLI,
@@ -17729,7 +17732,8 @@ static bool allMulUsesCanBeContracted(SDValue Mul,
continue; // All FNEG uses are contractable
}
- // FP_EXTEND - check if ALL users are FADD, FSUB, or FNEG --> FSUB
+ // FP_EXTEND - check if ALL users are FADD, FSUB, FNEG --> FSUB, or
+ // FMA/FMAD --> {FADD, FSUB}
if (Opcode == ISD::FP_EXTEND) {
EVT SrcVT = Mul.getValueType();
@@ -17742,6 +17746,22 @@ static bool allMulUsesCanBeContracted(SDValue Mul,
if (ExtUserOp == ISD::FADD || ExtUserOp == ISD::FSUB) {
continue; // FPEXT --> {FADD, FSUB} is contractable
}
+ if (ExtUserOp == ISD::FMA || ExtUserOp == ISD::FMAD) {
+ // FPEXT --> FMA/FMAD is only contractable if the FMA/FMAD is
+ // used by FADD or FSUB (chain reassociation can fire to
+ // eliminate the multiply).
+ bool FMAUsedByAddSub = false;
+ for (const auto *FMAUser : FPExtUser->users()) {
+ unsigned FMAUserOp = FMAUser->getOpcode();
+ if (FMAUserOp == ISD::FADD || FMAUserOp == ISD::FSUB) {
+ FMAUsedByAddSub = true;
+ break;
+ }
+ }
+ if (FMAUsedByAddSub)
+ continue;
+ return false;
+ }
if (ExtUserOp == ISD::FNEG) {
// FP_EXTEND --> FNEG --> FSUB
for (const auto *FPExtFNegUser : FPExtUser->users()) {
@@ -17756,6 +17776,32 @@ static bool allMulUsesCanBeContracted(SDValue Mul,
continue; // All FPEXT uses are contractable
}
+ // FMA/FMAD - the multiply is used as an operand of an FMA. This is
+ // contractable only if chain reassociation can fire to eliminate the
+ // multiply. Chain reassociation transforms:
+ // fadd/fsub(fma(a, b, fmul(c, d)), e) -> fma(a, b, fma(c, d, e))
+ // For direct fmul -> fma -> fadd/fsub, this requires the consumer
+ // fadd/fsub to have the reassoc flag. For fmul -> fma -> fpext ->
+ // fadd/fsub, the aggressive fpext folds handle it without reassoc.
+ if (Opcode == ISD::FMA || Opcode == ISD::FMAD) {
+ bool FMAIsContractable = false;
+ for (const auto *FMAUser : UserNode->users()) {
+ unsigned FMAUserOp = FMAUser->getOpcode();
+ if (FMAUserOp == ISD::FP_EXTEND) {
+ FMAIsContractable = true;
+ break;
+ }
+ if ((FMAUserOp == ISD::FADD || FMAUserOp == ISD::FSUB) &&
+ FMAUser->getFlags().hasAllowReassociation()) {
+ FMAIsContractable = true;
+ break;
+ }
+ }
+ if (FMAIsContractable)
+ continue;
+ return false;
+ }
+
// Any other use type is not currently recognized as contractable.
return false;
}
@@ -17926,6 +17972,7 @@ SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) {
if (matcher.match(N02, ISD::FP_EXTEND)) {
SDValue N020 = N02.getOperand(0);
if (isContractableFMUL(N020) &&
+ allMulUsesCanBeContracted(N020, PreferredFusedOpcode, TLI, DAG) &&
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,
N020.getValueType())) {
return FoldFAddFMAFPExtFMul(N0.getOperand(0), N0.getOperand(1),
@@ -17955,6 +18002,7 @@ SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) {
if (isFusedOp(matcher, N00)) {
SDValue N002 = N00.getOperand(2);
if (isContractableFMUL(N002) &&
+ allMulUsesCanBeContracted(N002, PreferredFusedOpcode, TLI, DAG) &&
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,
N00.getValueType())) {
return FoldFAddFPExtFMAFMul(N00.getOperand(0), N00.getOperand(1),
@@ -17971,6 +18019,7 @@ SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) {
if (N12.getOpcode() == ISD::FP_EXTEND) {
SDValue N120 = N12.getOperand(0);
if (isContractableFMUL(N120) &&
+ allMulUsesCanBeContracted(N120, PreferredFusedOpcode, TLI, DAG) &&
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,
N120.getValueType())) {
return FoldFAddFMAFPExtFMul(N1.getOperand(0), N1.getOperand(1),
@@ -17990,6 +18039,7 @@ SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) {
if (isFusedOp(matcher, N10)) {
SDValue N102 = N10.getOperand(2);
if (isContractableFMUL(N102) &&
+ allMulUsesCanBeContracted(N102, PreferredFusedOpcode, TLI, DAG) &&
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,
N10.getValueType())) {
return FoldFAddFPExtFMAFMul(N10.getOperand(0), N10.getOperand(1),
@@ -18244,6 +18294,7 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) {
if (matcher.match(N02, ISD::FP_EXTEND)) {
SDValue N020 = N02.getOperand(0);
if (isContractableAndReassociableFMUL(N020) &&
+ allMulUsesCanBeContracted(N020, PreferredFusedOpcode, TLI, DAG) &&
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,
N020.getValueType())) {
return matcher.getNode(
@@ -18268,6 +18319,7 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) {
if (isFusedOp(matcher, N00)) {
SDValue N002 = N00.getOperand(2);
if (isContractableAndReassociableFMUL(N002) &&
+ allMulUsesCanBeContracted(N002, PreferredFusedOpcode, TLI, DAG) &&
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,
N00.getValueType())) {
return matcher.getNode(
@@ -18289,6 +18341,7 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) {
matcher.match(N1.getOperand(2), ISD::FP_EXTEND) && N1->hasOneUse()) {
SDValue N120 = N1.getOperand(2).getOperand(0);
if (isContractableAndReassociableFMUL(N120) &&
+ allMulUsesCanBeContracted(N120, PreferredFusedOpcode, TLI, DAG) &&
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,
N120.getValueType())) {
SDValue N1200 = N120.getOperand(0);
@@ -18318,6 +18371,7 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) {
SDValue N101 = CvtSrc.getOperand(1);
SDValue N102 = CvtSrc.getOperand(2);
if (isContractableAndReassociableFMUL(N102) &&
+ allMulUsesCanBeContracted(N102, PreferredFusedOpcode, TLI, DAG) &&
TLI.isFPExtFoldable(DAG, PreferredFusedOpcode, VT,
CvtSrc.getValueType())) {
SDValue N1020 = N102.getOperand(0);
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
index 57070e763e79b..142494a803755 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
@@ -20,24 +20,22 @@ define void @main(float %arg) {
; CHECK-NEXT: bb.1.bb2:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = contract reassoc nofpexcept V_MUL_F32_e64 0, [[S_MOV_B32_]], 0, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 1065353216
- ; CHECK-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = contract reassoc nofpexcept V_ADD_F32_e64 0, [[V_MUL_F32_e64_]], 0, [[S_MOV_B32_2]], 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = contract reassoc nofpexcept V_FMAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[V_ADD_F32_e64_]], 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[V_FMAC_F32_e64_1:%[0-9]+]]:vgpr_32 = contract reassoc nofpexcept V_FMAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[V_MUL_F32_e64_]], 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[V_ADD_F32_e64_1:%[0-9]+]]:vgpr_32 = contract reassoc nofpexcept V_ADD_F32_e64 0, killed [[V_FMAC_F32_e64_1]], 0, [[S_MOV_B32_2]], 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
+ ; CHECK-NEXT: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = contract reassoc nofpexcept V_FMAC_F32_e64 0, [[S_MOV_B32_]], 0, [[S_MOV_B32_]], 0, [[V_MOV_B32_e32_]], 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[V_FMAC_F32_e64_1:%[0-9]+]]:vgpr_32 = contract reassoc nofpexcept V_FMAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[V_FMAC_F32_e64_]], 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = contract reassoc nofpexcept V_ADD_F32_e64 0, [[V_FMAC_F32_e64_1]], 0, [[V_MOV_B32_e32_]], 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.bb11:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, [[V_FMAC_F32_e64_]], %bb.1
- ; CHECK-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, [[V_ADD_F32_e64_1]], %bb.1
- ; CHECK-NEXT: [[PHI2:%[0-9]+]]:sreg_32_xm0_xexec = PHI [[S_MOV_B32_1]], %bb.0, [[S_MOV_B32_3]], %bb.1
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, [[V_FMAC_F32_e64_1]], %bb.1
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, [[V_ADD_F32_e64_]], %bb.1
+ ; CHECK-NEXT: [[PHI2:%[0-9]+]]:sreg_32_xm0_xexec = PHI [[S_MOV_B32_1]], %bb.0, [[S_MOV_B32_2]], %bb.1
; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[PHI2]], implicit $exec
- ; CHECK-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 1
+ ; CHECK-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_CNDMASK_B32_e64_]]
- ; CHECK-NEXT: S_CMP_LG_U32 killed [[COPY1]], killed [[S_MOV_B32_4]], implicit-def $scc
+ ; CHECK-NEXT: S_CMP_LG_U32 killed [[COPY1]], killed [[S_MOV_B32_3]], implicit-def $scc
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
; CHECK-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, killed [[COPY2]], implicit-def dead $scc
; CHECK-NEXT: $vcc_lo = COPY [[S_AND_B32_1]]
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
index e95f19a19d134..8e0e7d2a735f8 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
@@ -17,57 +17,54 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: image_load_mip v4, v[2:4], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D unorm
-; GFX10-NEXT: s_clause 0x2
+; GFX10-NEXT: s_clause 0x3
; GFX10-NEXT: s_buffer_load_dword s24, s[0:3], 0x5c
; GFX10-NEXT: s_buffer_load_dword s25, s[0:3], 0x7c
+; GFX10-NEXT: s_buffer_load_dword s28, s[0:3], 0xc0
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_nop 0
-; GFX10-NEXT: s_buffer_load_dwordx4 s[0:3], s[0:3], 0x40
-; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_clause 0x2
-; GFX10-NEXT: s_buffer_load_dword s26, s[0:3], 0xc0
-; GFX10-NEXT: s_buffer_load_dwordx4 s[4:7], s[0:3], 0x50
-; GFX10-NEXT: s_buffer_load_dwordx4 s[8:11], s[0:3], 0x60
+; GFX10-NEXT: s_buffer_load_dwordx4 s[0:3], s[0:3], 0x70
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_clause 0x3
-; GFX10-NEXT: s_buffer_load_dword s4, s[0:3], 0x2c
-; GFX10-NEXT: s_buffer_load_dwordx4 s[12:15], s[0:3], 0x70
-; GFX10-NEXT: s_buffer_load_dwordx4 s[16:19], s[0:3], 0x20
-; GFX10-NEXT: s_buffer_load_dwordx4 s[20:23], s[0:3], 0x0
-; GFX10-NEXT: v_max_f32_e64 v5, s0, s0 clamp
-; GFX10-NEXT: v_sub_f32_e64 v6, s24, s25
-; GFX10-NEXT: v_mul_f32_e32 v7, s2, v5
-; GFX10-NEXT: s_buffer_load_dwordx4 s[0:3], s[0:3], 0x10
-; GFX10-NEXT: v_fma_f32 v1, v1, v6, s25
+; GFX10-NEXT: v_sub_f32_e64 v5, s24, s25
+; GFX10-NEXT: s_buffer_load_dword s0, s[0:3], 0x2c
+; GFX10-NEXT: v_mul_f32_e32 v2, s2, v2
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: s_clause 0x4
+; GFX10-NEXT: s_buffer_load_dwordx4 s[4:7], s[0:3], 0x40
+; GFX10-NEXT: s_buffer_load_dwordx4 s[8:11], s[0:3], 0x50
+; GFX10-NEXT: s_buffer_load_dwordx4 s[12:15], s[0:3], 0x0
+; GFX10-NEXT: s_buffer_load_dwordx4 s[16:19], s[0:3], 0x60
+; GFX10-NEXT: s_buffer_load_dwordx4 s[20:23], s[0:3], 0x20
+; GFX10-NEXT: v_fma_f32 v1, v1, v5, s25
+; GFX10-NEXT: s_buffer_load_dwordx4 s[24:27], s[0:3], 0x10
+; GFX10-NEXT: v_max_f32_e64 v6, s0, s0 clamp
+; GFX10-NEXT: v_add_f32_e64 v5, s28, -1.0
+; GFX10-NEXT: v_sub_f32_e32 v7, s0, v1
; GFX10-NEXT: s_mov_b32 s0, 0x3c23d70a
-; GFX10-NEXT: v_add_f32_e64 v6, s26, -1.0
-; GFX10-NEXT: v_sub_f32_e32 v8, s6, v7
-; GFX10-NEXT: v_mul_f32_e32 v0, s10, v0
-; GFX10-NEXT: v_sub_f32_e32 v9, s4, v1
-; GFX10-NEXT: v_mul_f32_e32 v2, s14, v2
-; GFX10-NEXT: v_fma_f32 v6, v5, v6, 1.0
-; GFX10-NEXT: v_fmac_f32_e32 v7, v8, v5
-; GFX10-NEXT: v_sub_f32_e32 v8, s18, v0
-; GFX10-NEXT: v_fmac_f32_e32 v1, v5, v9
-; GFX10-NEXT: v_mul_f32_e32 v9, s22, v3
-; GFX10-NEXT: v_mul_f32_e32 v2, v5, v2
-; GFX10-NEXT: v_add_f32_e32 v7, v3, v7
-; GFX10-NEXT: v_fmac_f32_e32 v0, v8, v5
-; GFX10-NEXT: v_sub_f32_e32 v1, v1, v6
-; GFX10-NEXT: v_mul_f32_e32 v8, v9, v5
-; GFX10-NEXT...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/188117
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