[llvm-branch-commits] [llvm] Greedy: Take hints from copy to physical subreg (PR #160467)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/CodeGen/RegAllocGreedy.cpp llvm/lib/CodeGen/RegAllocGreedy.h
``````````

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``````````diff
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 9d3165b79..7414ba32b 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2464,7 +2464,8 @@ void RAGreedy::collectHintInfo(Register Reg, HintsInfo &Out) {
         const TargetRegisterClass *OtherRC = MRI->getRegClass(OtherReg);
         unsigned FullRegCopyCost = OtherRC->getCopyCost();
 
-        const TargetRegisterClass *OtherSubRC = TRI->getSubRegisterClass(OtherRC, OtherSubReg);
+        const TargetRegisterClass *OtherSubRC =
+            TRI->getSubRegisterClass(OtherRC, OtherSubReg);
         unsigned SubRegCopyCost = OtherSubRC->getCopyCost();
 
         BranchProbability Scaling(SubRegCopyCost, FullRegCopyCost);
@@ -2476,11 +2477,9 @@ void RAGreedy::collectHintInfo(Register Reg, HintsInfo &Out) {
 
         BranchProbability Scaling(SubRegCopyCost, FullRegCopyCost);
         Freq *= Scaling;
-
       }
 
-      Out.push_back(HintInfo(Freq, OtherReg,
-                             OtherPhysReg));
+      Out.push_back(HintInfo(Freq, OtherReg, OtherPhysReg));
     }
   }
 }
@@ -2498,7 +2497,6 @@ BlockFrequency RAGreedy::getBrokenHintFreq(const HintsInfo &List,
       continue;
     }
 
-
     if (Info.PhysReg != PhysReg)
       Cost += Info.Freq;
   }
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.h b/llvm/lib/CodeGen/RegAllocGreedy.h
index e0bb26e63..1e711f7db 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.h
+++ b/llvm/lib/CodeGen/RegAllocGreedy.h
@@ -395,13 +395,12 @@ private:
     MCRegister PhysReg;
 
     HintInfo(BlockFrequency Freq, Register Reg, MCRegister PhysReg)
-      : Freq(Freq), Reg(Reg), PhysReg(PhysReg) {}
+        : Freq(Freq), Reg(Reg), PhysReg(PhysReg) {}
 
-    HintInfo(BlockFrequency Freq,
-             Register Reg, unsigned SubReg,
+    HintInfo(BlockFrequency Freq, Register Reg, unsigned SubReg,
              Register HintReg, unsigned HintSubReg)
-      : Freq(Freq), Reg(Reg), SubReg(SubReg),
-      HintReg(HintReg), HintSubReg(HintSubReg) {}
+        : Freq(Freq), Reg(Reg), SubReg(SubReg), HintReg(HintReg),
+          HintSubReg(HintSubReg) {}
   };
   using HintsInfo = SmallVector<HintInfo, 4>;
 

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https://github.com/llvm/llvm-project/pull/160467