[llvm-branch-commits] [llvm] [LV] Mask off possibly aliasing vector lanes (PR #100579)

[Florian Hahn via llvm-branch-commits]

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@@ -479,7 +479,11 @@ class LoopVectorizationPlanner {
   /// Build VPlans for the specified \p UserVF and \p UserIC if they are
   /// non-zero or all applicable candidate VFs otherwise. If vectorization and
   /// interleaving should be avoided up-front, no plans are generated.
-  void plan(ElementCount UserVF, unsigned UserIC);
+  /// DiffChecks is a list of pointer pairs that should be checked for aliasing,
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fhahn wrote:

Memory accesses will be lowered to masked VPWidenLoad/StoreRecipe, so should hopefully be easy to find in the plan

https://github.com/llvm/llvm-project/pull/100579