[llvm-branch-commits] [llvm] CodeGen: Remove PointerLikeRegClass handling from codegen (PR #159883)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Sep 19 16:53:35 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
All uses have been migrated to RegClassByHwMode. This is now
an implementation detail of InstrInfoEmitter for pseudoinstructions.
---
Full diff: https://github.com/llvm/llvm-project/pull/159883.diff
8 Files Affected:
- (modified) llvm/include/llvm/MC/MCInstrDesc.h (+1-12)
- (modified) llvm/include/llvm/Target/Target.td (+13-13)
- (modified) llvm/lib/CodeGen/TargetInstrInfo.cpp (-4)
- (modified) llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp (+1-1)
- (modified) llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp (+1-12)
- (modified) llvm/utils/TableGen/Common/InstructionEncoding.cpp (-3)
- (modified) llvm/utils/TableGen/DAGISelMatcherGen.cpp (-1)
- (modified) llvm/utils/TableGen/InstrInfoEmitter.cpp (+1-5)
``````````diff
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h
index 0a4bd17e20738..fd637f956592b 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -49,8 +49,7 @@ enum OperandConstraint {
/// private, all access should go through the MCOperandInfo accessors.
/// See the accessors for a description of what these are.
enum OperandFlags {
- LookupPtrRegClass = 0,
- LookupRegClassByHwMode,
+ LookupRegClassByHwMode = 0,
Predicate,
OptionalDef,
BranchTarget
@@ -90,9 +89,6 @@ class MCOperandInfo {
/// operand is a register. If LookupRegClassByHwMode is set, then this is an
/// index into a table in TargetInstrInfo or MCInstrInfo which contains the
/// real register class ID.
- ///
- /// If isLookupPtrRegClass is set, then this is an index that is passed to
- /// TargetRegisterInfo::getPointerRegClass(x) to get a dynamic register class.
int16_t RegClass;
/// These are flags from the MCOI::OperandFlags enum.
@@ -104,13 +100,6 @@ class MCOperandInfo {
/// Operand constraints (see OperandConstraint enum).
uint16_t Constraints;
- /// Set if this operand is a pointer value and it requires a callback
- /// to look up its register class.
- // TODO: Deprecated in favor of isLookupRegClassByHwMode
- bool isLookupPtrRegClass() const {
- return Flags & (1 << MCOI::LookupPtrRegClass);
- }
-
/// Set if this operand is a value that requires the current hwmode to look up
/// its register class.
bool isLookupRegClassByHwMode() const {
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 4a759a99d1d25..7cbf131640917 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -918,16 +918,23 @@ def slice;
def encoder;
def decoder;
-/// PointerLikeRegClass - Values that are designed to have pointer width are
-/// derived from this. TableGen treats the register class as having a symbolic
-/// type that it doesn't know, and resolves the actual regclass to use by using
-/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
-///
-/// This is deprecated in favor of RegClassByHwMode.
+/// PointerLikeRegClass - Pseudoinstruction operands that are designed
+/// to have pointer width are derived from this. This should only be
+/// used by StandardPseudoInstruction instructions. No target specific
+/// instruction should use this.
class PointerLikeRegClass<int Kind> {
int RegClassKind = Kind;
}
+/// ptr_rc definition - Mark this operand as being a pointer value
+/// whose register class needs to be defined by the target. Targets
+/// should provide instruction definition overrides which substitute
+/// the uses of this with the backend defined RegisterClass or
+/// RegClassByHwMode to use for pointer virtual registers for a
+/// particular opcode (typically by defining a subsitute instruction
+/// with RemapPointerOperands).
+def ptr_rc : PointerLikeRegClass<0>;
+
/// RegClassByHwMode - Operands that change the register class based
/// on the subtarget are derived from this. TableGen
/// treats the register class as having a symbolic kind that it
@@ -941,13 +948,6 @@ class RegClassByHwMode<list<HwMode> Modes,
list<RegisterClass> Objects = RegClasses;
}
-/// ptr_rc definition - Mark this operand as being a pointer value whose
-/// register class is resolved dynamically via a callback to TargetInstrInfo.
-/// FIXME: We should probably change this to a class which contain a list of
-/// flags. But currently we have but one flag.
-// Deprecated, use RegClassByHwMode instead.
-def ptr_rc : PointerLikeRegClass<0>;
-
/// unknown definition - Mark this operand as being of unknown type, causing
/// it to be resolved by inference in the context it is used.
class unknown_class;
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 5be89b49fb6ba..761e6ed213d95 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -67,10 +67,6 @@ TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
const MCOperandInfo &OpInfo = MCID.operands()[OpNum];
int16_t RegClass = getOpRegClassID(OpInfo);
- // TODO: Remove isLookupPtrRegClass in favor of isLookupRegClassByHwMode
- if (OpInfo.isLookupPtrRegClass())
- return TRI->getPointerRegClass(RegClass);
-
// Instructions like INSERT_SUBREG do not have fixed register classes.
if (RegClass < 0)
return nullptr;
diff --git a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
index 66c770d9ca86b..30c9efe8a0036 100644
--- a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
+++ b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
@@ -120,7 +120,7 @@ Instruction::create(const MCInstrInfo &InstrInfo,
Operand.IsDef = (OpIndex < Description->getNumDefs());
Operand.IsEarlyClobber =
(Description->getOperandConstraint(OpIndex, MCOI::EARLY_CLOBBER) != -1);
- // TODO(gchatelet): Handle isLookupPtrRegClass.
+ // TODO(gchatelet): Handle LookupRegClassByHwMode.
if (OpInfo.RegClass >= 0)
Operand.Tracker = &RATC.getRegisterClass(OpInfo.RegClass);
int TiedToIndex = Description->getOperandConstraint(OpIndex, MCOI::TIED_TO);
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index af75e44f63e48..ea4cc27092e2f 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -1824,10 +1824,6 @@ bool TreePatternNode::UpdateNodeTypeFromInst(unsigned ResNo,
return UpdateNodeType(ResNo, getValueTypeByHwMode(R, T.getHwModes()), TP);
}
- // PointerLikeRegClass has a type that is determined at runtime.
- if (Operand->isSubClassOf("PointerLikeRegClass"))
- return UpdateNodeType(ResNo, MVT::iPTR, TP);
-
// Both RegisterClass and RegisterOperand operands derive their types from a
// register class def.
const Record *RC = nullptr;
@@ -2406,12 +2402,6 @@ static TypeSetByHwMode getImplicitType(const Record *R, unsigned ResNo,
const CodeGenHwModes &CGH = CDP.getTargetInfo().getHwModes();
return TypeSetByHwMode(getValueTypeByHwMode(T, CGH));
}
- if (R->isSubClassOf("PointerLikeRegClass")) {
- assert(ResNo == 0 && "Regclass can only have one result!");
- TypeSetByHwMode VTS(MVT::iPTR);
- TP.getInfer().expandOverloads(VTS);
- return VTS;
- }
if (R->getName() == "node" || R->getName() == "srcvalue" ||
R->getName() == "zero_reg" || R->getName() == "immAllOnesV" ||
@@ -3612,8 +3602,7 @@ void CodeGenDAGPatterns::FindPatternInputsAndOutputs(
if (Val->getDef()->isSubClassOf("RegisterClassLike") ||
Val->getDef()->isSubClassOf("ValueType") ||
- Val->getDef()->isSubClassOf("RegisterOperand") ||
- Val->getDef()->isSubClassOf("PointerLikeRegClass")) {
+ Val->getDef()->isSubClassOf("RegisterOperand")) {
if (Dest->getName().empty())
I.error("set destination must have a name!");
if (!InstResults.insert_or_assign(Dest->getName(), Dest).second)
diff --git a/llvm/utils/TableGen/Common/InstructionEncoding.cpp b/llvm/utils/TableGen/Common/InstructionEncoding.cpp
index c6c006b527b05..0a163fe4a0198 100644
--- a/llvm/utils/TableGen/Common/InstructionEncoding.cpp
+++ b/llvm/utils/TableGen/Common/InstructionEncoding.cpp
@@ -36,9 +36,6 @@ InstructionEncoding::findOperandDecoderMethod(const CodeGenTarget &Target,
Decoder = "Decode" + Record->getName().str() + "RegisterClass";
} else if (Record->isSubClassOf("RegClassByHwMode")) {
Decoder = "Decode" + Record->getName().str() + "RegClassByHwMode";
- } else if (Record->isSubClassOf("PointerLikeRegClass")) {
- Decoder = "DecodePointerLikeRegClass" +
- utostr(Record->getValueAsInt("RegClassKind"));
}
return {Decoder, true};
diff --git a/llvm/utils/TableGen/DAGISelMatcherGen.cpp b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
index d84bfa8d0c92e..7e06ad73ad0b1 100644
--- a/llvm/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
@@ -240,7 +240,6 @@ void MatcherGen::EmitLeafMatchCode(const TreePatternNode &N) {
if ( // Handle register references. Nothing to do here, they always match.
LeafRec->isSubClassOf("RegisterClassLike") ||
LeafRec->isSubClassOf("RegisterOperand") ||
- LeafRec->isSubClassOf("PointerLikeRegClass") ||
LeafRec->isSubClassOf("SubRegIndex") ||
// Place holder for SRCVALUE nodes. Nothing to do here.
LeafRec->getName() == "srcvalue")
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index 84b4e1470183e..59755d1716c73 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -182,12 +182,8 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
// Fill in applicable flags.
Res += "0";
- if (OpR->isSubClassOf("RegClassByHwMode")) {
+ if (OpR->isSubClassOf("RegClassByHwMode"))
Res += "|(1<<MCOI::LookupRegClassByHwMode)";
- } else if (OpR->isSubClassOf("PointerLikeRegClass")) {
- // Ptr value whose register class is resolved via callback.
- Res += "|(1<<MCOI::LookupPtrRegClass)";
- }
// Predicate operands. Check to see if the original unexpanded operand
// was of type PredicateOp.
``````````
</details>
https://github.com/llvm/llvm-project/pull/159883
More information about the llvm-branch-commits
mailing list