[llvm-branch-commits] [llvm] CodeGen: Remove TRI arguments from stack load/store hooks (PR #158240)
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Fri Sep 12 01:27:14 PDT 2025
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``````````bash
git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/include/llvm/CodeGen/TargetInstrInfo.h llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp llvm/lib/CodeGen/InlineSpiller.cpp llvm/lib/CodeGen/RegAllocFast.cpp llvm/lib/CodeGen/RegisterScavenging.cpp llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp llvm/lib/CodeGen/TargetInstrInfo.cpp llvm/lib/Target/AArch64/AArch64FrameLowering.cpp llvm/lib/Target/AArch64/AArch64InstrInfo.cpp llvm/lib/Target/AArch64/AArch64InstrInfo.h llvm/lib/Target/AMDGPU/SIInstrInfo.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.h llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/lib/Target/ARM/ARMBaseInstrInfo.h llvm/lib/Target/ARM/Thumb1InstrInfo.cpp llvm/lib/Target/ARM/Thumb1InstrInfo.h llvm/lib/Target/ARM/Thumb2InstrInfo.cpp llvm/lib/Target/ARM/Thumb2InstrInfo.h llvm/lib/Target/AVR/AVRInstrInfo.cpp llvm/lib/Target/AVR/AVRInstrInfo.h llvm/lib/Target/BPF/BPFInstrInfo.cpp llvm/lib/Target/BPF/BPFInstrInfo.h llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp llvm/lib/Target/Hexagon/HexagonInstrInfo.h llvm/lib/Target/Lanai/LanaiInstrInfo.cpp llvm/lib/Target/Lanai/LanaiInstrInfo.h llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp llvm/lib/Target/LoongArch/LoongArchInstrInfo.h llvm/lib/Target/MSP430/MSP430InstrInfo.cpp llvm/lib/Target/MSP430/MSP430InstrInfo.h llvm/lib/Target/Mips/Mips16InstrInfo.cpp llvm/lib/Target/Mips/Mips16InstrInfo.h llvm/lib/Target/Mips/MipsInstrInfo.h llvm/lib/Target/Mips/MipsSEFrameLowering.cpp llvm/lib/Target/Mips/MipsSEInstrInfo.cpp llvm/lib/Target/Mips/MipsSEInstrInfo.h llvm/lib/Target/PowerPC/PPCFrameLowering.cpp llvm/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/lib/Target/PowerPC/PPCInstrInfo.h llvm/lib/Target/RISCV/RISCVFrameLowering.cpp llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.h llvm/lib/Target/Sparc/SparcInstrInfo.cpp llvm/lib/Target/Sparc/SparcInstrInfo.h llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp llvm/lib/Target/SystemZ/SystemZInstrInfo.h llvm/lib/Target/VE/VEInstrInfo.cpp llvm/lib/Target/VE/VEInstrInfo.h llvm/lib/Target/X86/X86FastPreTileConfig.cpp llvm/lib/Target/X86/X86FrameLowering.cpp llvm/lib/Target/X86/X86InstrInfo.cpp llvm/lib/Target/X86/X86InstrInfo.h llvm/lib/Target/XCore/XCoreFrameLowering.cpp llvm/lib/Target/XCore/XCoreInstrInfo.cpp llvm/lib/Target/XCore/XCoreInstrInfo.h llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp llvm/lib/Target/Xtensa/XtensaInstrInfo.h
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``````````diff
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 1f2a4e01d..748822b37 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -957,170 +957,148 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MFI.getObjectSize(FI), Alignment);
switch (TRI.getSpillSize(*RC)) {
- case 2:
- if (ARM::HPRRegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH))
- .addReg(SrcReg, getKillRegState(isKill))
+ case 2:
+ if (ARM::HPRRegClass.hasSubClassEq(RC)) {
+ BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH))
+ .addReg(SrcReg, getKillRegState(isKill))
+ .addFrameIndex(FI)
+ .addImm(0)
+ .addMemOperand(MMO)
+ .add(predOps(ARMCC::AL));
+ } else
+ llvm_unreachable("Unknown reg class!");
+ break;
+ case 4:
+ if (ARM::GPRRegClass.hasSubClassEq(RC)) {
+ BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12))
+ .addReg(SrcReg, getKillRegState(isKill))
+ .addFrameIndex(FI)
+ .addImm(0)
+ .addMemOperand(MMO)
+ .add(predOps(ARMCC::AL));
+ } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
+ BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS))
+ .addReg(SrcReg, getKillRegState(isKill))
+ .addFrameIndex(FI)
+ .addImm(0)
+ .addMemOperand(MMO)
+ .add(predOps(ARMCC::AL));
+ } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {
+ BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_P0_off))
+ .addReg(SrcReg, getKillRegState(isKill))
+ .addFrameIndex(FI)
+ .addImm(0)
+ .addMemOperand(MMO)
+ .add(predOps(ARMCC::AL));
+ } else if (ARM::cl_FPSCR_NZCVRegClass.hasSubClassEq(RC)) {
+ BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_FPSCR_NZCVQC_off))
+ .addReg(SrcReg, getKillRegState(isKill))
+ .addFrameIndex(FI)
+ .addImm(0)
+ .addMemOperand(MMO)
+ .add(predOps(ARMCC::AL));
+ } else
+ llvm_unreachable("Unknown reg class!");
+ break;
+ case 8:
+ if (ARM::DPRRegClass.hasSubClassEq(RC)) {
+ BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD))
+ .addReg(SrcReg, getKillRegState(isKill))
+ .addFrameIndex(FI)
+ .addImm(0)
+ .addMemOperand(MMO)
+ .add(predOps(ARMCC::AL));
+ } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
+ if (Subtarget.hasV5TEOps()) {
+ MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
+ AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill));
+ AddDReg(MIB, SrcReg, ARM::gsub_1, 0);
+ MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO).add(
+ predOps(ARMCC::AL));
+ } else {
+ // Fallback to STM instruction, which has existed since the dawn of
+ // time.
+ MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA))
+ .addFrameIndex(FI)
+ .addMemOperand(MMO)
+ .add(predOps(ARMCC::AL));
+ AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill));
+ AddDReg(MIB, SrcReg, ARM::gsub_1, 0);
+ }
+ } else
+ llvm_unreachable("Unknown reg class!");
+ break;
+ case 16:
+ if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {
+ // Use aligned spills if the stack can be realigned.
+ if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF)) {
+ BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64))
.addFrameIndex(FI)
- .addImm(0)
- .addMemOperand(MMO)
- .add(predOps(ARMCC::AL));
- } else
- llvm_unreachable("Unknown reg class!");
- break;
- case 4:
- if (ARM::GPRRegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12))
+ .addImm(16)
.addReg(SrcReg, getKillRegState(isKill))
- .addFrameIndex(FI)
- .addImm(0)
.addMemOperand(MMO)
.add(predOps(ARMCC::AL));
- } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS))
+ } else {
+ BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA))
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI)
- .addImm(0)
.addMemOperand(MMO)
.add(predOps(ARMCC::AL));
- } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_P0_off))
- .addReg(SrcReg, getKillRegState(isKill))
+ }
+ } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&
+ Subtarget.hasMVEIntegerOps()) {
+ auto MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::MVE_VSTRWU32));
+ MIB.addReg(SrcReg, getKillRegState(isKill))
+ .addFrameIndex(FI)
+ .addImm(0)
+ .addMemOperand(MMO);
+ addUnpredicatedMveVpredNOp(MIB);
+ } else
+ llvm_unreachable("Unknown reg class!");
+ break;
+ case 24:
+ if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
+ // Use aligned spills if the stack can be realigned.
+ if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) &&
+ Subtarget.hasNEON()) {
+ BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo))
.addFrameIndex(FI)
- .addImm(0)
- .addMemOperand(MMO)
- .add(predOps(ARMCC::AL));
- } else if (ARM::cl_FPSCR_NZCVRegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_FPSCR_NZCVQC_off))
+ .addImm(16)
.addReg(SrcReg, getKillRegState(isKill))
- .addFrameIndex(FI)
- .addImm(0)
.addMemOperand(MMO)
.add(predOps(ARMCC::AL));
- } else
- llvm_unreachable("Unknown reg class!");
- break;
- case 8:
- if (ARM::DPRRegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD))
- .addReg(SrcReg, getKillRegState(isKill))
+ } else {
+ MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA))
+ .addFrameIndex(FI)
+ .add(predOps(ARMCC::AL))
+ .addMemOperand(MMO);
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill));
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0);
+ AddDReg(MIB, SrcReg, ARM::dsub_2, 0);
+ }
+ } else
+ llvm_unreachable("Unknown reg class!");
+ break;
+ case 32:
+ if (ARM::QQPRRegClass.hasSubClassEq(RC) ||
+ ARM::MQQPRRegClass.hasSubClassEq(RC) ||
+ ARM::DQuadRegClass.hasSubClassEq(RC)) {
+ if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) &&
+ Subtarget.hasNEON()) {
+ // FIXME: It's possible to only store part of the QQ register if the
+ // spilled def has a sub-register index.
+ BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo))
.addFrameIndex(FI)
- .addImm(0)
+ .addImm(16)
+ .addReg(SrcReg, getKillRegState(isKill))
.addMemOperand(MMO)
.add(predOps(ARMCC::AL));
- } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
- if (Subtarget.hasV5TEOps()) {
- MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
- AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill));
- AddDReg(MIB, SrcReg, ARM::gsub_1, 0);
- MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
- .add(predOps(ARMCC::AL));
- } else {
- // Fallback to STM instruction, which has existed since the dawn of
- // time.
- MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA))
- .addFrameIndex(FI)
- .addMemOperand(MMO)
- .add(predOps(ARMCC::AL));
- AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill));
- AddDReg(MIB, SrcReg, ARM::gsub_1, 0);
- }
- } else
- llvm_unreachable("Unknown reg class!");
- break;
- case 16:
- if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {
- // Use aligned spills if the stack can be realigned.
- if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF)) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64))
- .addFrameIndex(FI)
- .addImm(16)
- .addReg(SrcReg, getKillRegState(isKill))
- .addMemOperand(MMO)
- .add(predOps(ARMCC::AL));
- } else {
- BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA))
- .addReg(SrcReg, getKillRegState(isKill))
- .addFrameIndex(FI)
- .addMemOperand(MMO)
- .add(predOps(ARMCC::AL));
- }
- } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&
- Subtarget.hasMVEIntegerOps()) {
- auto MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::MVE_VSTRWU32));
- MIB.addReg(SrcReg, getKillRegState(isKill))
- .addFrameIndex(FI)
- .addImm(0)
- .addMemOperand(MMO);
- addUnpredicatedMveVpredNOp(MIB);
- } else
- llvm_unreachable("Unknown reg class!");
- break;
- case 24:
- if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
- // Use aligned spills if the stack can be realigned.
- if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) &&
- Subtarget.hasNEON()) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo))
- .addFrameIndex(FI)
- .addImm(16)
- .addReg(SrcReg, getKillRegState(isKill))
- .addMemOperand(MMO)
- .add(predOps(ARMCC::AL));
- } else {
- MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
- get(ARM::VSTMDIA))
- .addFrameIndex(FI)
- .add(predOps(ARMCC::AL))
- .addMemOperand(MMO);
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill));
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0);
- AddDReg(MIB, SrcReg, ARM::dsub_2, 0);
- }
- } else
- llvm_unreachable("Unknown reg class!");
- break;
- case 32:
- if (ARM::QQPRRegClass.hasSubClassEq(RC) ||
- ARM::MQQPRRegClass.hasSubClassEq(RC) ||
- ARM::DQuadRegClass.hasSubClassEq(RC)) {
- if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) &&
- Subtarget.hasNEON()) {
- // FIXME: It's possible to only store part of the QQ register if the
- // spilled def has a sub-register index.
- BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo))
- .addFrameIndex(FI)
- .addImm(16)
- .addReg(SrcReg, getKillRegState(isKill))
- .addMemOperand(MMO)
- .add(predOps(ARMCC::AL));
- } else if (Subtarget.hasMVEIntegerOps()) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::MQQPRStore))
- .addReg(SrcReg, getKillRegState(isKill))
- .addFrameIndex(FI)
- .addMemOperand(MMO);
- } else {
- MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
- get(ARM::VSTMDIA))
- .addFrameIndex(FI)
- .add(predOps(ARMCC::AL))
- .addMemOperand(MMO);
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill));
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0);
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0);
- AddDReg(MIB, SrcReg, ARM::dsub_3, 0);
- }
- } else
- llvm_unreachable("Unknown reg class!");
- break;
- case 64:
- if (ARM::MQQQQPRRegClass.hasSubClassEq(RC) &&
- Subtarget.hasMVEIntegerOps()) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::MQQQQPRStore))
+ } else if (Subtarget.hasMVEIntegerOps()) {
+ BuildMI(MBB, I, DebugLoc(), get(ARM::MQQPRStore))
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI)
.addMemOperand(MMO);
- } else if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
+ } else {
MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA))
.addFrameIndex(FI)
.add(predOps(ARMCC::AL))
@@ -1128,16 +1106,36 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill));
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0);
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0);
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0);
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0);
- MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0);
- AddDReg(MIB, SrcReg, ARM::dsub_7, 0);
- } else
- llvm_unreachable("Unknown reg class!");
- break;
- default:
+ AddDReg(MIB, SrcReg, ARM::dsub_3, 0);
+ }
+ } else
+ llvm_unreachable("Unknown reg class!");
+ break;
+ case 64:
+ if (ARM::MQQQQPRRegClass.hasSubClassEq(RC) &&
+ Subtarget.hasMVEIntegerOps()) {
+ BuildMI(MBB, I, DebugLoc(), get(ARM::MQQQQPRStore))
+ .addReg(SrcReg, getKillRegState(isKill))
+ .addFrameIndex(FI)
+ .addMemOperand(MMO);
+ } else if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
+ MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA))
+ .addFrameIndex(FI)
+ .add(predOps(ARMCC::AL))
+ .addMemOperand(MMO);
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill));
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0);
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0);
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0);
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0);
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0);
+ MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0);
+ AddDReg(MIB, SrcReg, ARM::dsub_7, 0);
+ } else
llvm_unreachable("Unknown reg class!");
+ break;
+ default:
+ llvm_unreachable("Unknown reg class!");
}
}
``````````
</details>
https://github.com/llvm/llvm-project/pull/158240
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