[llvm-branch-commits] [llvm] CodeGen: Remove TRI argument from getRegClass (PR #158225)

Fri Sep 12 00:26:01 PDT 2025

llvmbot wrote:

<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Matt Arsenault (arsenm)

<details>
<summary>Changes</summary>

TargetInstrInfo now directly holds a reference to TargetRegisterInfo
and does not need TRI passed in anywhere.

---
Full diff: https://github.com/llvm/llvm-project/pull/158225.diff

45 Files Affected:

- (modified) llvm/include/llvm/CodeGen/TargetInstrInfo.h (+2-3) 
- (modified) llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp (+2-2) 
- (modified) llvm/lib/CodeGen/BreakFalseDeps.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp (+2-2) 
- (modified) llvm/lib/CodeGen/GlobalISel/Utils.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/InitUndef.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/MachineInstr.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/MachineLICM.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/MachineVerifier.cpp (+4-7) 
- (modified) llvm/lib/CodeGen/RegisterCoalescer.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/SelectionDAG/FastISel.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (+4-5) 
- (modified) llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/TargetInstrInfo.cpp (+2-3) 
- (modified) llvm/lib/CodeGen/TwoAddressInstructionPass.cpp (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp (+4-6) 
- (modified) llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.cpp (+1-4) 
- (modified) llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp (+6-6) 
- (modified) llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp (+1-1) 
- (modified) llvm/lib/Target/AMDGPU/SIFoldOperands.cpp (+2-2) 
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+5-6) 
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.h (+2-3) 
- (modified) llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp (+2-4) 
- (modified) llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp (+2-3) 
- (modified) llvm/lib/Target/ARM/ARMFrameLowering.cpp (+1-2) 
- (modified) llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (+4-4) 
- (modified) llvm/lib/Target/ARM/MLxExpansionPass.cpp (+1-1) 
- (modified) llvm/lib/Target/ARM/Thumb2InstrInfo.cpp (+1-1) 
- (modified) llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp (+1-1) 
- (modified) llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp (+2-2) 
- (modified) llvm/lib/Target/Hexagon/HexagonLoadStoreWidening.cpp (+2-2) 
- (modified) llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp (+2-2) 
- (modified) llvm/lib/Target/LoongArch/LoongArchDeadRegisterDefinitions.cpp (+1-2) 
- (modified) llvm/lib/Target/Mips/MipsSEInstrInfo.cpp (+2-2) 
- (modified) llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp (+2-2) 
- (modified) llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp (+1-2) 
- (modified) llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp (+2-2) 
- (modified) llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp (+1-2) 
- (modified) llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp (+3-3) 
- (modified) llvm/lib/Target/X86/X86DomainReassignment.cpp (+2-2) 
- (modified) llvm/lib/Target/X86/X86InstrInfo.cpp (+12-14) 
- (modified) llvm/lib/Target/X86/X86InstrInfo.h (+2-3) 
- (modified) llvm/lib/Target/X86/X86OptimizeLEAs.cpp (+1-1) 
- (modified) llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp (+1-1) 

``````````diff

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</details>

https://github.com/llvm/llvm-project/pull/158225