[llvm-branch-commits] [llvm] [AVR] Remove workarounds for instructions using Z register (NFCI) (PR #156361)

[Sergei Barannikov via llvm-branch-commits]

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@@ -1230,7 +1230,9 @@ let Uses = [R1, R0] in {
 
   let Defs = [R31R30] in 
   def SPMZPi : F16<0b1001010111111000, (outs), (ins ZREG:$z), "spm $z+", []>,
-               Requires<[HasSPMX]>;
+               Requires<[HasSPMX]> {
+    bits<0> z;
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s-barannikov wrote:

Those have a custom DecoderMethod, and this field currently only affects the *generated decoders*. If they didn't have a custom DecoderMethod, TableGen would complain about missing operand encoding for "$z" operand.

I think I can remove some custom decoder methods in a follow-up PR.


https://github.com/llvm/llvm-project/pull/156361