[llvm-branch-commits] [llvm] AMDGPU: Handle true16 disassembly of ds_write_b8/b16 (PR #156406)

[Joe Nash via llvm-branch-commits]

================
@@ -4447,76 +4447,76 @@
 # GFX11: ds_store_b128 v255, v[2:5] offset:65535 ; encoding: [0xff,0xff,0x7c,0xdb,0xff,0x02,0x00,0x00]
 0xff,0xff,0x7c,0xdb,0xff,0x02,0x00,0x00
 
-# GFX11: ds_store_b16 v0, v1                     ; encoding: [0x00,0x00,0x7c,0xd8,0x00,0x01,0x00,0x00]
+# GFX11: ds_store_b16 v0, v1.l                   ; encoding: [0x00,0x00,0x7c,0xd8,0x00,0x01,0x00,0x00]
----------------
Sisyph wrote:

Yes I think Jay is right, though the docs here are somewhat misleading. The operand is labeled as a vgpr with 16 bits. However, there is no way to encode the swizzle (ie v0.h) in DS. At least I can't find any reference that these would use the hi bit of the operand field the way vop1/2/C does. 

https://github.com/llvm/llvm-project/pull/156406