[llvm-branch-commits] [llvm] AMDGPU: Fix true16 d16 entry table for DS pseudos (PR #156419)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/156419

This should be trying to use the _gfx9 variants of DS pseudos,
not the base form with m0 uses.

>From 849b10bdde864ad87389594fa063fcb8ea7a25ee Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 2 Sep 2025 16:48:14 +0900
Subject: [PATCH] AMDGPU: Fix true16 d16 entry table for DS pseudos

This should be trying to use the _gfx9 variants of DS pseudos,
not the base form with m0 uses.
---
 llvm/lib/Target/AMDGPU/DSInstructions.td | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 6f9ba8076e11b..d8ef86eae3e16 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -126,11 +126,12 @@ multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
   }
 }
 
-multiclass DS_1A1D_NORET_t16<string opName, RegisterClass rc = VGPR_32> 
+multiclass DS_1A1D_NORET_t16<string opName, RegisterClass rc = VGPR_32>
 : DS_1A1D_NORET_mc<opName, rc> {
   let has_m0_read = 0 in {
     let True16Predicate = UseRealTrue16Insts in {
-      def "_t16" : DS_1A1D_NORET<opName#"_t16", VGPR_16>, True16D16Table<NAME#"_D16_HI", NAME>;
+      def "_t16" : DS_1A1D_NORET<opName#"_t16", VGPR_16>,
+        True16D16Table<NAME#"_D16_HI", NAME#"_gfx9">;
     }
   }
 }