[llvm-branch-commits] [llvm] [AMDGPU] Implement CFI for CSR spills (PR #164724)

[Matt Arsenault via llvm-branch-commits]

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@@ -2244,17 +2244,49 @@ bool SIFrameLowering::allocateScavengingFrameIndexesNearIncomingSP(
   return true;
 }
 
+static bool isLiveIntoMBB(MCRegister Reg, MachineBasicBlock &MBB,
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arsenm wrote:

This shouldn't be here. I'm still unclear on what the rules are for when register aliases will appear in the live in list. This also should account for the LaneMask

https://github.com/llvm/llvm-project/pull/164724