[llvm-branch-commits] [clang] [llvm] [AArch64][llvm] Armv9.7-A: Add support for SVE2p3 DOT and MLA operations (PR #163161)

[via llvm-branch-commits]

================
@@ -0,0 +1,34 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-b16mm 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid element width
+
+bfmmla z0.h, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmmla z0.h, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmmla z0.s, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmmla z0.s, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmmla z0.d, z0.d, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmmla z0.d, z0.d, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.h, p0/m, z7.h
+bfmmla z0.h, z0.h, z0.h
----------------
CarolineConcatto wrote:

I am not sure this is correct, you have a tests in bfmmla.s using movprfx

bfmmla z0.h, z1.h, z2.h
// CHECK-INST: movprfx z0, z7
// CHECK-INST: bfmmla z0.h, z1.h, z2.h
// CHECK-ENCODING: encoding: [0x20,0xe0,0xe2,0x64]
// CHECK-ERROR: instruction requires: sve-b16mm
// CHECK-UNKNOWN: 64e2e020 <unknown>

I think the problem here is that we have Zm as Z0 as well. If you change the problem will go away, no?

Same for the test bellow.

You can also check that class sve_fp_matrix_mla has destructive , so it should accept movprfx

https://github.com/llvm/llvm-project/pull/163161