[llvm-branch-commits] [libunwind] c000f32 - [Mips] Fixed libunwind::Registers_mips_o32::jumpto to allow for load delay (#152942)

Cullen Rhodes via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Mon Oct 13 02:49:19 PDT 2025


Author: Jade Marker
Date: 2025-10-13T09:49:13Z
New Revision: c000f3226bdf469ccf71f3257840493f21ceaead

URL: https://github.com/llvm/llvm-project/commit/c000f3226bdf469ccf71f3257840493f21ceaead
DIFF: https://github.com/llvm/llvm-project/commit/c000f3226bdf469ccf71f3257840493f21ceaead.diff

LOG: [Mips] Fixed libunwind::Registers_mips_o32::jumpto to allow for load delay (#152942)

Fix #152922

MIPS III also has load delay, so
libunwind::Registers_mips_newabi::jumpto() is also fixed.

(cherry picked from commit a3d7c468bdc328f04da720088b2e542ef1f33ffc)

Added: 
    

Modified: 
    libunwind/src/UnwindRegistersRestore.S

Removed: 
    


################################################################################
diff  --git a/libunwind/src/UnwindRegistersRestore.S b/libunwind/src/UnwindRegistersRestore.S
index 5e199188945df..1bcd205be260d 100644
--- a/libunwind/src/UnwindRegistersRestore.S
+++ b/libunwind/src/UnwindRegistersRestore.S
@@ -1044,9 +1044,10 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv)
   lw    $27, (4 * 27)($4)
   lw    $28, (4 * 28)($4)
   lw    $29, (4 * 29)($4)
-  lw    $30, (4 * 30)($4)
   // load new pc into ra
   lw    $31, (4 * 32)($4)
+  // MIPS 1 has load delay slot. Ensure lw $31 and jr are separated by an instruction.
+  lw    $30, (4 * 30)($4)
   // jump to ra, load a0 in the delay slot
   jr    $31
   lw    $4, (4 * 4)($4)
@@ -1082,11 +1083,13 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind21Registers_mips_newabi6jumptoEv)
   ld    $2, (8 * 2)($4)
   ld    $3, (8 * 3)($4)
   // skip a0 for now
-  .irp i,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
+  .irp i,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
     ld $\i, (8 * \i)($4)
   .endr
   // load new pc into ra
   ld    $31, (8 * 32)($4)
+  // MIPS 1 has load delay slot. Ensure lw $31 and jr are separated by an instruction.
+  ld    $30, (8 * 30)($4)
   // jump to ra, load a0 in the delay slot
   jr    $31
   ld    $4, (8 * 4)($4)


        


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