[llvm-branch-commits] [llvm] [AMDGPU][MC] Do not inline lit()/lit64() operands. (PR #162137)
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llvm-branch-commits at lists.llvm.org
Mon Oct 6 12:13:53 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Ivan Kosarev (kosarev)
<details>
<summary>Changes</summary>
For now treat the modifiers synonymous to each other.
The disassembler side is to be addressed separately.
---
Patch is 43.21 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/162137.diff
5 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (+34-51)
- (modified) llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp (+7-1)
- (modified) llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp (+12-3)
- (modified) llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s (+2-1)
- (modified) llvm/test/MC/AMDGPU/literals.s (+380-26)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 22b242e7249b8..34a2cabc38d5b 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -2097,6 +2097,10 @@ bool AMDGPUOperand::isInlinableImm(MVT type) const {
// Only plain immediates are inlinable (e.g. "clamp" attribute is not)
return false;
}
+
+ if (getModifiers().Lit != LitModifier::None)
+ return false;
+
// TODO: We should avoid using host float here. It would be better to
// check the float bit values which is what a few other places do.
// We've had bot failures before due to weird NaN support on mips hosts.
@@ -2341,7 +2345,8 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
- if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),
+ if (Lit == LitModifier::None &&
+ AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),
AsmParser->hasInv2PiInlineImm())) {
Inst.addOperand(MCOperand::createImm(Literal.getZExtValue()));
return;
@@ -2378,14 +2383,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
Val = Hi_32(Val);
}
}
-
- if (Lit != LitModifier::None) {
- Inst.addOperand(
- MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
- } else {
- Inst.addOperand(MCOperand::createImm(Val));
- }
- return;
+ break;
}
// We don't allow fp literals in 64-bit integer instructions. It is
@@ -2397,20 +2395,14 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
if (CanUse64BitLiterals && Lit == LitModifier::None &&
(isInt<32>(Val) || isUInt<32>(Val)))
Lit = LitModifier::Lit64;
-
- if (Lit != LitModifier::None) {
- Inst.addOperand(
- MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
- } else {
- Inst.addOperand(MCOperand::createImm(Val));
- }
- return;
+ break;
case AMDGPU::OPERAND_REG_IMM_BF16:
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
case AMDGPU::OPERAND_REG_IMM_V2BF16:
- if (AsmParser->hasInv2PiInlineImm() && Literal == 0x3fc45f306725feed) {
+ if (Lit == LitModifier::None && AsmParser->hasInv2PiInlineImm() &&
+ Literal == 0x3fc45f306725feed) {
// This is the 1/(2*pi) which is going to be truncated to bf16 with the
// loss of precision. The constant represents ideomatic fp32 value of
// 1/(2*pi) = 0.15915494 since bf16 is in fact fp32 with cleared low 16
@@ -2448,14 +2440,19 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
// We allow precision lost but not overflow or underflow. This should be
// checked earlier in isLiteralImm()
- uint64_t ImmVal = FPLiteral.bitcastToAPInt().getZExtValue();
- Inst.addOperand(MCOperand::createImm(ImmVal));
- return;
+ Val = FPLiteral.bitcastToAPInt().getZExtValue();
+ break;
}
default:
llvm_unreachable("invalid operand size");
}
+ if (Lit != LitModifier::None) {
+ Inst.addOperand(
+ MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
+ } else {
+ Inst.addOperand(MCOperand::createImm(Val));
+ }
return;
}
@@ -2475,12 +2472,12 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
case AMDGPU::OPERAND_REG_IMM_V2INT32:
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
- Inst.addOperand(MCOperand::createImm(Val));
- return;
+ break;
case AMDGPU::OPERAND_REG_IMM_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
- if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
+ if (Lit == LitModifier::None &&
+ AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
Inst.addOperand(MCOperand::createImm(Val));
return;
}
@@ -2491,19 +2488,13 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
// LSBs.
if (!AsmParser->has64BitLiterals() || Lit == LitModifier::Lit)
Val = Lo_32(Val);
-
- if (Lit != LitModifier::None) {
- Inst.addOperand(
- MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
- } else {
- Inst.addOperand(MCOperand::createImm(Val));
- }
- return;
+ break;
case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
- if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
+ if (Lit == LitModifier::None &&
+ AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
Inst.addOperand(MCOperand::createImm(Val));
return;
}
@@ -2526,14 +2517,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
// For FP64 operands lit() specifies the high half of the value.
if (Lit == LitModifier::Lit)
Val = Hi_32(Val);
-
- if (Lit != LitModifier::None) {
- Inst.addOperand(
- MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
- } else {
- Inst.addOperand(MCOperand::createImm(Val));
- }
- return;
+ break;
case AMDGPU::OPERAND_REG_IMM_INT16:
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
@@ -2546,24 +2530,23 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
case AMDGPU::OPERAND_KIMM32:
case AMDGPU::OPERAND_KIMM16:
- Inst.addOperand(MCOperand::createImm(Val));
- return;
+ break;
case AMDGPU::OPERAND_KIMM64:
if ((isInt<32>(Val) || isUInt<32>(Val)) && Lit != LitModifier::Lit64)
Val <<= 32;
-
- if (Lit != LitModifier::None) {
- Inst.addOperand(
- MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
- } else {
- Inst.addOperand(MCOperand::createImm(Val));
- }
- return;
+ break;
default:
llvm_unreachable("invalid operand type");
}
+
+ if (Lit != LitModifier::None) {
+ Inst.addOperand(
+ MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
+ } else {
+ Inst.addOperand(MCOperand::createImm(Val));
+ }
}
void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const {
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 3563caa1331e9..8043201f52439 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -73,7 +73,13 @@ void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
- O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
+ const MCOperand &Op = MI->getOperand(OpNo);
+ if (Op.isExpr()) {
+ MAI.printExpr(O, *Op.getExpr());
+ return;
+ }
+
+ O << formatHex(Op.getImm() & 0xffffffff);
}
void AMDGPUInstPrinter::printFP64ImmOperand(const MCInst *MI, unsigned OpNo,
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index 08a2f9008ad44..ea758bb6a7872 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -270,10 +270,19 @@ std::optional<uint64_t> AMDGPUMCCodeEmitter::getLitEncoding(
const MCInstrDesc &Desc, const MCOperand &MO, unsigned OpNo,
const MCSubtargetInfo &STI, bool HasMandatoryLiteral) const {
const MCOperandInfo &OpInfo = Desc.operands()[OpNo];
- int64_t Imm;
+ int64_t Imm = 0;
if (MO.isExpr()) {
- if (!MO.getExpr()->evaluateAsAbsolute(Imm))
- return AMDGPU::getOperandSize(OpInfo) == 8 ? 254 : 255;
+ if (!MO.getExpr()->evaluateAsAbsolute(Imm) ||
+ AMDGPU::isLitExpr(MO.getExpr())) {
+ if (OpInfo.OperandType == AMDGPU::OPERAND_KIMM16 ||
+ OpInfo.OperandType == AMDGPU::OPERAND_KIMM32 ||
+ OpInfo.OperandType == AMDGPU::OPERAND_KIMM64)
+ return Imm;
+ if (STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
+ AMDGPU::getOperandSize(OpInfo) == 8)
+ return 254;
+ return 255;
+ }
} else {
assert(!MO.isDFPImm());
diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s b/llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s
index 72a7f87cc42c8..73653d0dd0067 100644
--- a/llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s
+++ b/llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s
@@ -62,8 +62,9 @@ s_cselect_b64 s[2:3], s[4:5], 0x10abcdef12345678
s_mov_b64 s[2:3], 0xffffffff01234567
// GFX1250: s_mov_b64 s[2:3], 0xffffffff01234567 ; encoding: [0xfe,0x01,0x82,0xbe,0x67,0x45,0x23,0x01,0xff,0xff,0xff,0xff]
+// TODO: disasm
s_mov_b64 s[2:3], lit64(0x777)
-// GFX1250-ASM: s_mov_b64 s[2:3], lit64(0x777) ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00]
+// GFX1250-ASM: s_mov_b64 s[2:3], lit64(0x777) ; encoding: [0xfe,0x01,0x82,0xbe,0x77,0x07,0x00,0x00,0x00,0x00,0x00,0x00]
// GFX1250-DIS: s_mov_b64 s[2:3], 0x777 ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00]
s_mov_b64 s[2:3], 0x777
diff --git a/llvm/test/MC/AMDGPU/literals.s b/llvm/test/MC/AMDGPU/literals.s
index 90c6369e697f4..ec96816899db5 100644
--- a/llvm/test/MC/AMDGPU/literals.s
+++ b/llvm/test/MC/AMDGPU/literals.s
@@ -5,7 +5,7 @@
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefixes=GFX8PLUS,GFX89,GFX9
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck %s --check-prefixes=GFX8PLUS,GFX11
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck %s --check-prefixes=GFX8PLUS,GFX12
-// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1250 -show-encoding %s | FileCheck %s --check-prefixes=GFX8PLUS,GFX1250
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -show-encoding %s | FileCheck %s --check-prefixes=GFX8PLUS,GFX1250
// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOSICI,NOSI --implicit-check-not=error:
// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOSICI,NOCI --implicit-check-not=error:
@@ -13,7 +13,7 @@
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOGFX8PLUS,NOGFX89,NOGFX9 --implicit-check-not=error:
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOGFX8PLUS,NOGFX11 --implicit-check-not=error:
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOGFX8PLUS,NOGFX12 --implicit-check-not=error:
-// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1250 %s -filetype=null 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOGFX8PLUS,NOGFX1250 --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1250 %s -mattr=+real-true16 -filetype=null 2>&1 | FileCheck %s --check-prefixes=NOGCN,NOGFX8PLUS,NOGFX1250 --implicit-check-not=error:
//---------------------------------------------------------------------------//
// fp literal, expected fp operand
@@ -205,6 +205,118 @@ v_fract_f64 v[0:1], 2.3509886e-70
v_trunc_f32 v0, 2.3509886e-70
// NOGCN: :[[@LINE-1]]:17: error: invalid operand for instruction
+v_fract_f64_e32 v[0:1], 1.0
+// SICI: v_fract_f64_e32 v[0:1], 1.0 ; encoding: [0xf2,0x7c,0x00,0x7e]
+// GFX89: v_fract_f64_e32 v[0:1], 1.0 ; encoding: [0xf2,0x64,0x00,0x7e]
+// GFX11: v_fract_f64_e32 v[0:1], 1.0 ; encoding: [0xf2,0x7c,0x00,0x7e]
+// GFX12: v_fract_f64_e32 v[0:1], 1.0 ; encoding: [0xf2,0x7c,0x00,0x7e]
+// GFX1250: v_fract_f64_e32 v[0:1], 1.0 ; encoding: [0xf2,0x7c,0x00,0x7e]
+
+v_fract_f64_e32 v[0:1], lit(1.0)
+// SICI: v_fract_f64_e32 v[0:1], lit(0x3ff00000) ; encoding: [0xff,0x7c,0x00,0x7e,0x00,0x00,0xf0,0x3f]
+// GFX89: v_fract_f64_e32 v[0:1], lit(0x3ff00000) ; encoding: [0xff,0x64,0x00,0x7e,0x00,0x00,0xf0,0x3f]
+// GFX11: v_fract_f64_e32 v[0:1], lit(0x3ff00000) ; encoding: [0xff,0x7c,0x00,0x7e,0x00,0x00,0xf0,0x3f]
+// GFX12: v_fract_f64_e32 v[0:1], lit(0x3ff00000) ; encoding: [0xff,0x7c,0x00,0x7e,0x00,0x00,0xf0,0x3f]
+// GFX1250: v_fract_f64_e32 v[0:1], lit(0x3ff00000) ; encoding: [0xfe,0x7c,0x00,0x7e,0x00,0x00,0xf0,0x3f,0x00,0x00,0x00,0x00]
+
+v_wmma_i32_16x16x16_iu8 v[8:15], v[0:3], v[4:7], 1.0
+// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+// GFX11: v_wmma_i32_16x16x16_iu8 v[8:15], v[0:3], v[4:7], 1.0 ; encoding: [0x08,0x40,0x44,0xcc,0x00,0x09,0xca,0x1b]
+// NOGFX12: :[[@LINE-4]]:1: error: operands are not valid for this GPU or mode
+// NOGFX1250: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode
+
+v_wmma_i32_16x16x16_iu8 v[8:15], v[0:3], v[4:7], lit(1.0)
+// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+// NOGFX11: :[[@LINE-3]]:54: error: invalid operand for instruction
+// NOGFX12: :[[@LINE-4]]:54: error: invalid operand for instruction
+// NOGFX1250: :[[@LINE-5]]:54: error: invalid operand for instruction
+
+v_cos_f16_e32 v5.l, 1.0
+// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// NOGFX89: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+// GFX11: v_cos_f16_e32 v5.l, 1.0 ; encoding: [0xf2,0xc2,0x0a,0x7e]
+// GFX1250: v_cos_f16_e32 v5.l, 1.0 ; encoding: [0xf2,0xc2,0x0a,0x7e]
+// NOGFX12: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode
+
+v_cos_f16_e32 v5.l, lit(1.0)
+// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// NOGFX89: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
+// GFX11: v_cos_f16_e32 v5.l, lit(0x3c00) ; encoding: [0xff,0xc2,0x0a,0x7e,0x00,0x3c,0x00,0x00]
+// GFX1250: v_cos_f16_e32 v5.l, lit(0x3c00) ; encoding: [0xff,0xc2,0x0a,0x7e,0x00,0x3c,0x00,0x00]
+// NOGFX12: :[[@LINE-5]]:1: error: operands are not valid for this GPU or mode
+
+v_tanh_bf16 v5, 1.0
+// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+// GFX1250: v_tanh_bf16_e32 v5, 1.0 ; encoding: [0xf2,0x94,0x0a,0x7e]
+// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU
+// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU
+
+v_tanh_bf16 v5, lit(1.0)
+// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+// GFX1250: v_tanh_bf16_e32 v5, lit(0x3f80) ; encoding: [0xff,0x94,0x0a,0x7e,0x80,0x3f,0x00,0x00]
+// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU
+// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU
+
+v_trunc_f32_e32 v0, 1.0
+// SICI: v_trunc_f32_e32 v0, 1.0 ; encoding: [0xf2,0x42,0x00,0x7e]
+// GFX89: v_trunc_f32_e32 v0, 1.0 ; encoding: [0xf2,0x38,0x00,0x7e]
+// GFX11: v_trunc_f32_e32 v0, 1.0 ; encoding: [0xf2,0x42,0x00,0x7e]
+// GFX12: v_trunc_f32_e32 v0, 1.0 ; encoding: [0xf2,0x42,0x00,0x7e]
+// GFX1250: v_trunc_f32_e32 v0, 1.0 ; encoding: [0xf2,0x42,0x00,0x7e]
+
+v_trunc_f32_e32 v0, lit(1.0)
+// SICI: v_trunc_f32_e32 v0, lit(0x3f800000) ; encoding: [0xff,0x42,0x00,0x7e,0x00,0x00,0x80,0x3f]
+// GFX89: v_trunc_f32_e32 v0, lit(0x3f800000) ; encoding: [0xff,0x38,0x00,0x7e,0x00,0x00,0x80,0x3f]
+// GFX11: v_trunc_f32_e32 v0, lit(0x3f800000) ; encoding: [0xff,0x42,0x00,0x7e,0x00,0x00,0x80,0x3f]
+// GFX12: v_trunc_f32_e32 v0, lit(0x3f800000) ; encoding: [0xff,0x42,0x00,0x7e,0x00,0x00,0x80,0x3f]
+// GFX1250: v_trunc_f32_e32 v0, lit(0x3f800000) ; encoding: [0xff,0x42,0x00,0x7e,0x00,0x00,0x80,0x3f]
+
+v_dot2_bf16_bf16 v5.l, v1, v2, 1.0
+// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+// GFX11: v_dot2_bf16_bf16 v5.l, v1, v2, 1.0 ; encoding: [0x05,0x00,0x67,0xd6,0x01,0x05,0xca,0x03]
+// NOGFX12: :[[@LINE-4]]:1: error: operands are not valid for this GPU or mode
+// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU
+
+v_dot2_bf16_bf16 v5.l, v1, v2, lit(1.0)
+// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+// GFX11: v_dot2_bf16_bf16 v5.l, v1, v2, lit(0x3f80) ; encoding: [0x05,0x00,0x67,0xd6,0x01,0x05,0xfe,0x03,0x80,0x3f,0x00,0x00]
+// NOGFX12: :[[@LINE-4]]:1: error: operands are not valid for this GPU or mode
+// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU
+
+v_dot2_f32_f16 v5, v1, 1.0, v2
+// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+// GFX11: v_dot2_f32_f16 v5, v1, 1.0, v2 ; encoding: [0x05,0x40,0x13,0xcc,0x01,0xe5,0x09,0x1c]
+// GFX12: v_dot2_f32_f16 v5, v1, 1.0, v2 ; encoding: [0x05,0x40,0x13,0xcc,0x01,0xe5,0x09,0x1c]
+// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU
+
+v_dot2_f32_f16 v5, v1, lit(1.0), v2
+// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+// GFX11: v_dot2_f32_f16 v5, v1, lit(0x3c00), v2 ; encoding: [0x05,0x40,0x13,0xcc,0x01,0xff,0x09,0x1c,0x00,0x3c,0x00,0x00]
+// GFX12: v_dot2_f32_f16 v5, v1, lit(0x3c00), v2 ; encoding: [0x05,0x40,0x13,0xcc,0x01,0xff,0x09,0x1c,0x00,0x3c,0x00,0x00]
+// NOGFX1250: :[[@LINE-5]]:1: error: instruction not supported on this GPU
+
+v_cvt_pk_fp8_f16 v1.l, 1.0
+// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+// GFX1250: v_cvt_pk_fp8_f16 v1.l, 0x3c00 ; encoding: [0x01,0x00,0x72,0xd7,0xff,0x00,0x00,0x00,0x00,0x3c,0x00,0x00]
+// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU
+// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU
+
+v_cvt_pk_fp8_f16 v1.l, lit(1.0)
+// NOSICI: :[[@LINE-1]]:1: error: instruction not supported on this GPU
+// NOGFX89: :[[@LINE-2]]:1: error: instruction not supported on this GPU
+// GFX1250: v_cvt_pk_fp8_f16 v1.l, lit(0x3c00) ; encoding: [0x01,0x00,0x72,0xd7,0xff,0x00,0x00,0x00,0x00,0x3c,0x00,0x00]
+// NOGFX11: :[[@LINE-4]]:1: error: instruction not supported on this GPU
+// NOGFX12: :[[@LINE-5]]:1: error: instruction not supported on this GPU
+
//---------------------------------------------------------------------------//
// fp literal, expected int operand
//---------------------------------------------------------------------------//
@@ -213,6 +325,9 @@ s_mov_b64_e32 s[0:1], 0.5
// GFX8PLUS: s_mov_b64 s[0:1], 0.5 ; encoding: [0xf0,0x01,0x80,0xbe]
// SICI: s_mov_b64 s[0:1], 0.5 ; encoding: [0xf0,0x04,0x80,0xbe]
+s_mov_b64 s[0:1], lit(0.5)
+// NOGCN: :[[@LINE-1]]:23: error: invalid operand for instruction
+
v_and_b32_e32 v0, 0.5, v1
// SICI: v_and_b32_e32 v0, 0.5, v1 ; encoding: [0xf0,0x02,0x00,0x36]
// GFX89: v_and_b32_e32 v0, 0.5, v1 ; encoding: [0xf0,0x02,0x00,0x26]
@@ -347,6 +462,64 @@ s_mov_b64_e32 s[0:1], 2.3509886e-70
v_and_b32_e32 v0, 2.3509886e-70, v1
// NOGCN: :[[@LINE-1]]:19: error: invalid operand for instruction
+v_not_b16 v5.l, 1.0
+// NOSICI: :[[@LINE-1]]:...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/162137
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