[llvm-branch-commits] [llvm] [AMDGPU] Implement CFI for non-kernel functions (PR #164723)

[Matt Arsenault via llvm-branch-commits]

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@@ -283,17 +393,47 @@ class PrologEpilogSGPRSpillBuilder {
           .addReg(SubReg)
           .addImm(Spill[I].Lane)
           .addReg(Spill[I].VGPR, RegState::Undef);
+      if (NeedsFrameMoves && !CFISuperReg)
+          TFI->buildCFIForSGPRToVGPRSpill(MBB, MI, DL, SubReg, Spill[I].VGPR,
+                                          Spill[I].Lane);
     }
+    if (NeedsFrameMoves && CFISuperReg)
+      TFI->buildCFIForSGPRToVGPRSpill(MBB, MI, DL, *CFISuperReg, Spill);
   }
 
   void copyToScratchSGPR(Register DstReg) const {
     BuildMI(MBB, MI, DL, TII->get(AMDGPU::COPY), DstReg)
         .addReg(SuperReg)
         .setMIFlag(MachineInstr::FrameSetup);
+    if (NeedsFrameMoves) {
+      const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(DstReg);
+      ArrayRef<int16_t> DstSplitParts = TRI.getRegSplitParts(RC, EltSize);
+      unsigned DstNumSubRegs = DstSplitParts.empty() ? 1 : DstSplitParts.size();
+      assert(NumSubRegs == DstNumSubRegs);
+      for (unsigned I = 0; I < NumSubRegs; ++I) {
+        Register SrcSubReg =
+            NumSubRegs == 1 ? SuperReg
+                            : Register(TRI.getSubReg(SuperReg, SplitParts[I]));
+        Register DstSubReg =
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arsenm wrote:

```suggestion
        MCRegister DstSubReg =
```

https://github.com/llvm/llvm-project/pull/164723