[llvm-branch-commits] [llvm] AMDGPU: Use RegClassByHwMode to manage GWS operand special case (PR #169373)

[Shilei Tian via llvm-branch-commits]

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@@ -1580,6 +1591,17 @@ foreach size = ["64", "96", "128", "160", "256", "1024" ] in {
   def AVLdSt_#size#_Align2 : AVLdStOperand<!cast<RegisterClassLike>("AV_LdSt_"#size#_Align2)>;
 }
 
+def AV_LdSt_32_Align2_RegMatcher : AsmOperandClass {
+  let Name = "AV_LdSt_32_Align2_RegOp";
+  let RenderMethod = "addRegOperands";
+}
+
+def AV_LdSt_32_Align2_RegOp : RegisterOperand<AV_LdSt_32_Align2> {
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shiltian wrote:

I wonder if I could do something similar to the pseudo register class that I added for downstream support such that I don't need to do a check on register class?

https://github.com/llvm/llvm-project/pull/169373