[llvm-branch-commits] [llvm] [AMDGPU] Implement CFI for CSR spills (PR #164724)
Scott Linder via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Nov 21 12:03:36 PST 2025
https://github.com/slinder1 updated https://github.com/llvm/llvm-project/pull/164724
>From 17e3b5d13cf1f19c19334dcb4cceaea72518cf26 Mon Sep 17 00:00:00 2001
From: Scott Linder <Scott.Linder at amd.com>
Date: Wed, 29 Oct 2025 18:46:12 +0000
Subject: [PATCH 1/3] Use register pair for PC spill
---
llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 20 +
.../CodeGen/AMDGPU/GlobalISel/assert-align.ll | 2 +-
.../GlobalISel/call-outgoing-stack-args.ll | 8 +-
.../CodeGen/AMDGPU/GlobalISel/localizer.ll | 2 +-
.../abi-attribute-hints-undefined-behavior.ll | 2 +-
.../CodeGen/AMDGPU/amdgcn-call-whole-wave.ll | 8 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 5662 ++++++++---------
.../CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll | 44 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll | 1996 +++---
.../CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll | 32 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll | 72 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll | 176 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll | 328 +-
.../amdgpu-simplify-libcall-pow-codegen.ll | 280 +-
...tor-flatscratchinit-undefined-behavior2.ll | 13 +-
llvm/test/CodeGen/AMDGPU/bf16.ll | 166 +-
.../test/CodeGen/AMDGPU/branch-relax-spill.ll | 156 +-
llvm/test/CodeGen/AMDGPU/call-args-inreg.ll | 96 +-
.../CodeGen/AMDGPU/call-argument-types.ll | 40 +-
.../AMDGPU/call-graph-register-usage.ll | 2 +-
.../AMDGPU/call-preserved-registers.ll | 116 +-
.../test/CodeGen/AMDGPU/callee-frame-setup.ll | 106 +-
.../callee-special-input-vgprs-packed.ll | 14 +-
.../AMDGPU/callee-special-input-vgprs.ll | 14 +-
.../AMDGPU/cross-block-use-is-not-abi-copy.ll | 8 +-
llvm/test/CodeGen/AMDGPU/debug-frame.ll | 8 +-
.../AMDGPU/dwarf-multi-register-use-crash.ll | 64 +-
.../dynamic-vgpr-reserve-stack-for-cwsr.ll | 4 +-
.../fix-frame-reg-in-custom-csr-spills.ll | 2 +-
...frame-setup-without-sgpr-to-vgpr-spills.ll | 25 +-
.../CodeGen/AMDGPU/function-args-inreg.ll | 8 +-
.../CodeGen/AMDGPU/gfx-call-non-gfx-func.ll | 144 +-
.../AMDGPU/gfx-callable-argument-types.ll | 1234 ++--
.../gfx-callable-preserved-registers.ll | 72 +-
.../AMDGPU/gfx-callable-return-types.ll | 42 +-
llvm/test/CodeGen/AMDGPU/global-alias.ll | 2 +-
.../identical-subrange-spill-infloop.ll | 92 +-
llvm/test/CodeGen/AMDGPU/indirect-call.ll | 1104 ++--
.../CodeGen/AMDGPU/insert-delay-alu-bug.ll | 2 +-
.../CodeGen/AMDGPU/insert-waitcnts-crash.ll | 12 +-
.../AMDGPU/materialize-frame-index-sgpr.ll | 1634 ++---
.../CodeGen/AMDGPU/mul24-pass-ordering.ll | 20 +-
.../AMDGPU/need-fp-from-vgpr-spills.ll | 6 +-
llvm/test/CodeGen/AMDGPU/nested-calls.ll | 4 +-
.../AMDGPU/no-source-locations-in-prologue.ll | 2 +-
.../AMDGPU/preserve-wwm-copy-dst-reg.ll | 25 +-
llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll | 6 +-
.../AMDGPU/sgpr-spill-overlap-wwm-reserve.mir | 190 +-
.../AMDGPU/sgpr-spills-split-regalloc.ll | 27 +-
.../AMDGPU/shufflevector.v2i64.v8i64.ll | 299 +-
.../si-lower-sgpr-spills-vgpr-lanes-usage.mir | 18 +-
llvm/test/CodeGen/AMDGPU/sibling-call.ll | 222 +-
llvm/test/CodeGen/AMDGPU/stack-realign.ll | 2 +-
.../CodeGen/AMDGPU/stacksave_stackrestore.ll | 10 +-
.../AMDGPU/strictfp_f16_abi_promote.ll | 14 +-
.../CodeGen/AMDGPU/swdev504645-global-fold.ll | 3 +-
.../AMDGPU/tail-call-inreg-arguments.error.ll | 4 +-
...unfold-masked-merge-scalar-variablemask.ll | 38 +-
.../AMDGPU/unstructured-cfg-def-use-issue.ll | 168 +-
.../CodeGen/AMDGPU/vgpr-tuple-allocation.ll | 12 +-
llvm/test/CodeGen/AMDGPU/wave32.ll | 4 +-
.../CodeGen/AMDGPU/whole-wave-functions.ll | 20 +-
.../AMDGPU/whole-wave-register-copy.ll | 2 +-
.../AMDGPU/whole-wave-register-spill.ll | 4 +-
.../test/CodeGen/AMDGPU/wwm-reserved-spill.ll | 8 +-
65 files changed, 7469 insertions(+), 7451 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index 40eeeb8a8630d..057a5e2df8bf7 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -268,11 +268,19 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs(
std::vector<CalleeSavedInfo> CSI;
const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
+ Register RetAddrReg = TRI->getReturnAddressReg(MF);
+ bool SpillRetAddrReg = false;
for (unsigned I = 0; CSRegs[I]; ++I) {
MCRegister Reg = CSRegs[I];
if (SavedRegs.test(Reg)) {
+ if (Reg == TRI->getSubReg(RetAddrReg, AMDGPU::sub0) ||
+ Reg == TRI->getSubReg(RetAddrReg, AMDGPU::sub1)) {
+ SpillRetAddrReg = true;
+ continue;
+ }
+
const TargetRegisterClass *RC =
TRI->getMinimalPhysRegClass(Reg, MVT::i32);
int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC),
@@ -283,6 +291,18 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs(
}
}
+ // Return address uses a register pair. Add the super register to the
+ // CSI list so that it's easier to identify the entire spill and CFI
+ // can be emitted appropriately.
+ if (SpillRetAddrReg) {
+ const TargetRegisterClass *RC =
+ TRI->getMinimalPhysRegClass(RetAddrReg, MVT::i64);
+ int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC),
+ TRI->getSpillAlign(*RC), true);
+ CSI.push_back(CalleeSavedInfo(RetAddrReg, JunkFI));
+ CalleeSavedFIs.push_back(JunkFI);
+ }
+
if (!CSI.empty()) {
for (MachineBasicBlock *SaveBlock : SaveBlocks)
insertCSRSaves(*SaveBlock, CSI, Indexes, LIS);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
index b84b31cd2702c..023398377de94 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
@@ -23,10 +23,10 @@ define ptr addrspace(1) @call_assert_align() {
; CHECK-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: v_mov_b32_e32 v2, 0
+; CHECK-NEXT: v_readlane_b32 s30, v40, 0
; CHECK-NEXT: global_store_dword v[0:1], v2, off
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_readlane_b32 s31, v40, 1
-; CHECK-NEXT: v_readlane_b32 s30, v40, 0
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: v_readlane_b32 s4, v40, 2
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
index 7e6f500181ec6..2c1beb8468576 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
@@ -238,8 +238,8 @@ define void @func_caller_stack() #2 {
; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
+; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
; MUBUF-NEXT: s_mov_b32 s32, s33
; MUBUF-NEXT: v_readlane_b32 s4, v40, 2
; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -277,8 +277,8 @@ define void @func_caller_stack() #2 {
; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_v16i32_v16i32_v4i32 at rel32@hi+12
; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
+; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
; FLATSCR-NEXT: s_mov_b32 s32, s33
; FLATSCR-NEXT: v_readlane_b32 s0, v40, 2
; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1
@@ -363,8 +363,8 @@ define void @func_caller_byval(ptr addrspace(5) %argptr) #2 {
; MUBUF-NEXT: s_waitcnt vmcnt(1)
; MUBUF-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:60
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
+; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
; MUBUF-NEXT: s_mov_b32 s32, s33
; MUBUF-NEXT: v_readlane_b32 s4, v40, 2
; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -414,8 +414,8 @@ define void @func_caller_byval(ptr addrspace(5) %argptr) #2 {
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[0:1], s32 offset:56
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
+; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
; FLATSCR-NEXT: s_mov_b32 s32, s33
; FLATSCR-NEXT: v_readlane_b32 s0, v40, 2
; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
index 72766f47030cc..35591cd602992 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
@@ -244,8 +244,8 @@ define void @sink_null_insert_pt(ptr addrspace(4) %arg0) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], 0
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
index 3194581fa4213..0e24430e7be20 100644
--- a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
+++ b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
@@ -30,8 +30,8 @@ define void @parent_func_missing_inputs() #0 {
; FIXEDABI-NEXT: s_addc_u32 s17, s17, requires_all_inputs at rel32@hi+12
; FIXEDABI-NEXT: v_writelane_b32 v40, s31, 1
; FIXEDABI-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; FIXEDABI-NEXT: v_readlane_b32 s31, v40, 1
; FIXEDABI-NEXT: v_readlane_b32 s30, v40, 0
+; FIXEDABI-NEXT: v_readlane_b32 s31, v40, 1
; FIXEDABI-NEXT: s_mov_b32 s32, s33
; FIXEDABI-NEXT: v_readlane_b32 s4, v40, 2
; FIXEDABI-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll b/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
index 149b0cb4e052d..b6e65c8842904 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
@@ -35,8 +35,8 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr)
; DAGISEL-NEXT: s_clause 0x1
; DAGISEL-NEXT: scratch_load_b32 v41, off, s33
; DAGISEL-NEXT: scratch_load_b32 v40, off, s33 offset:4
-; DAGISEL-NEXT: v_readlane_b32 s31, v42, 1
; DAGISEL-NEXT: v_readlane_b32 s30, v42, 0
+; DAGISEL-NEXT: v_readlane_b32 s31, v42, 1
; DAGISEL-NEXT: s_mov_b32 s32, s33
; DAGISEL-NEXT: v_readlane_b32 s0, v42, 2
; DAGISEL-NEXT: s_or_saveexec_b32 s1, -1
@@ -78,8 +78,8 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr)
; GISEL-NEXT: s_clause 0x1
; GISEL-NEXT: scratch_load_b32 v41, off, s33
; GISEL-NEXT: scratch_load_b32 v40, off, s33 offset:4
-; GISEL-NEXT: v_readlane_b32 s31, v42, 1
; GISEL-NEXT: v_readlane_b32 s30, v42, 0
+; GISEL-NEXT: v_readlane_b32 s31, v42, 1
; GISEL-NEXT: s_mov_b32 s32, s33
; GISEL-NEXT: v_readlane_b32 s0, v42, 2
; GISEL-NEXT: s_or_saveexec_b32 s1, -1
@@ -787,8 +787,8 @@ define amdgpu_gfx void @ret_void(i32 %x) #0 {
; DAGISEL-NEXT: s_wait_alu 0xfffe
; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; DAGISEL-NEXT: v_readlane_b32 s31, v40, 1
; DAGISEL-NEXT: v_readlane_b32 s30, v40, 0
+; DAGISEL-NEXT: v_readlane_b32 s31, v40, 1
; DAGISEL-NEXT: s_mov_b32 s32, s33
; DAGISEL-NEXT: v_readlane_b32 s0, v40, 2
; DAGISEL-NEXT: s_or_saveexec_b32 s1, -1
@@ -822,8 +822,8 @@ define amdgpu_gfx void @ret_void(i32 %x) #0 {
; GISEL-NEXT: s_wait_alu 0xfffe
; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-NEXT: v_readlane_b32 s31, v40, 1
; GISEL-NEXT: v_readlane_b32 s30, v40, 0
+; GISEL-NEXT: v_readlane_b32 s31, v40, 1
; GISEL-NEXT: s_mov_b32 s32, s33
; GISEL-NEXT: v_readlane_b32 s0, v40, 2
; GISEL-NEXT: s_or_saveexec_b32 s1, -1
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index c794168c40075..1e2a46fcefa36 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -7466,42 +7466,42 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_writelane_b32 v20, s30, 0
-; SI-NEXT: v_writelane_b32 v20, s31, 1
-; SI-NEXT: v_writelane_b32 v20, s34, 2
-; SI-NEXT: v_writelane_b32 v20, s35, 3
-; SI-NEXT: v_writelane_b32 v20, s36, 4
-; SI-NEXT: v_writelane_b32 v20, s37, 5
-; SI-NEXT: v_writelane_b32 v20, s38, 6
-; SI-NEXT: v_writelane_b32 v20, s39, 7
-; SI-NEXT: v_writelane_b32 v20, s48, 8
-; SI-NEXT: v_writelane_b32 v20, s49, 9
-; SI-NEXT: v_writelane_b32 v20, s50, 10
-; SI-NEXT: v_writelane_b32 v20, s51, 11
-; SI-NEXT: v_writelane_b32 v20, s52, 12
-; SI-NEXT: v_writelane_b32 v20, s53, 13
-; SI-NEXT: v_writelane_b32 v20, s54, 14
-; SI-NEXT: v_writelane_b32 v20, s55, 15
-; SI-NEXT: v_writelane_b32 v20, s64, 16
-; SI-NEXT: v_writelane_b32 v20, s65, 17
-; SI-NEXT: v_writelane_b32 v20, s66, 18
-; SI-NEXT: v_writelane_b32 v20, s67, 19
-; SI-NEXT: v_writelane_b32 v20, s68, 20
-; SI-NEXT: v_writelane_b32 v20, s69, 21
-; SI-NEXT: v_writelane_b32 v20, s70, 22
-; SI-NEXT: v_writelane_b32 v20, s71, 23
-; SI-NEXT: v_writelane_b32 v20, s80, 24
-; SI-NEXT: v_writelane_b32 v20, s81, 25
-; SI-NEXT: v_writelane_b32 v20, s82, 26
-; SI-NEXT: v_writelane_b32 v20, s83, 27
-; SI-NEXT: v_writelane_b32 v20, s84, 28
-; SI-NEXT: v_writelane_b32 v20, s85, 29
-; SI-NEXT: v_writelane_b32 v20, s86, 30
-; SI-NEXT: v_writelane_b32 v20, s87, 31
-; SI-NEXT: v_writelane_b32 v20, s96, 32
-; SI-NEXT: v_writelane_b32 v20, s97, 33
+; SI-NEXT: v_writelane_b32 v20, s34, 0
+; SI-NEXT: v_writelane_b32 v20, s35, 1
+; SI-NEXT: v_writelane_b32 v20, s36, 2
+; SI-NEXT: v_writelane_b32 v20, s37, 3
+; SI-NEXT: v_writelane_b32 v20, s38, 4
+; SI-NEXT: v_writelane_b32 v20, s39, 5
+; SI-NEXT: v_writelane_b32 v20, s48, 6
+; SI-NEXT: v_writelane_b32 v20, s49, 7
+; SI-NEXT: v_writelane_b32 v20, s50, 8
+; SI-NEXT: v_writelane_b32 v20, s51, 9
+; SI-NEXT: v_writelane_b32 v20, s52, 10
+; SI-NEXT: v_writelane_b32 v20, s53, 11
+; SI-NEXT: v_writelane_b32 v20, s54, 12
+; SI-NEXT: v_writelane_b32 v20, s55, 13
+; SI-NEXT: v_writelane_b32 v20, s64, 14
+; SI-NEXT: v_writelane_b32 v20, s65, 15
+; SI-NEXT: v_writelane_b32 v20, s66, 16
+; SI-NEXT: v_writelane_b32 v20, s67, 17
+; SI-NEXT: v_writelane_b32 v20, s68, 18
+; SI-NEXT: v_writelane_b32 v20, s69, 19
+; SI-NEXT: v_writelane_b32 v20, s70, 20
+; SI-NEXT: v_writelane_b32 v20, s71, 21
+; SI-NEXT: v_writelane_b32 v20, s80, 22
+; SI-NEXT: v_writelane_b32 v20, s81, 23
+; SI-NEXT: v_writelane_b32 v20, s82, 24
+; SI-NEXT: v_writelane_b32 v20, s83, 25
+; SI-NEXT: v_writelane_b32 v20, s84, 26
+; SI-NEXT: v_writelane_b32 v20, s85, 27
+; SI-NEXT: v_writelane_b32 v20, s86, 28
+; SI-NEXT: v_writelane_b32 v20, s87, 29
+; SI-NEXT: v_writelane_b32 v20, s96, 30
+; SI-NEXT: v_writelane_b32 v20, s97, 31
+; SI-NEXT: v_writelane_b32 v20, s98, 32
+; SI-NEXT: v_writelane_b32 v20, s99, 33
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_writelane_b32 v20, s98, 34
+; SI-NEXT: v_writelane_b32 v20, s30, 34
; SI-NEXT: v_readfirstlane_b32 s44, v1
; SI-NEXT: v_readfirstlane_b32 s45, v2
; SI-NEXT: v_readfirstlane_b32 s42, v3
@@ -7521,7 +7521,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v17
; SI-NEXT: s_and_b64 s[46:47], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v18
-; SI-NEXT: v_writelane_b32 v20, s99, 35
+; SI-NEXT: v_writelane_b32 v20, s31, 35
; SI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB13_4
@@ -8391,6 +8391,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v20, 34
; SI-NEXT: v_readlane_b32 s19, v22, 11
; SI-NEXT: v_readlane_b32 s17, v22, 17
; SI-NEXT: v_readlane_b32 s15, v22, 23
@@ -8398,42 +8399,41 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: v_readlane_b32 s11, v22, 35
; SI-NEXT: v_readlane_b32 s9, v22, 41
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s99, v20, 35
-; SI-NEXT: v_readlane_b32 s98, v20, 34
-; SI-NEXT: v_readlane_b32 s97, v20, 33
-; SI-NEXT: v_readlane_b32 s96, v20, 32
-; SI-NEXT: v_readlane_b32 s87, v20, 31
-; SI-NEXT: v_readlane_b32 s86, v20, 30
-; SI-NEXT: v_readlane_b32 s85, v20, 29
-; SI-NEXT: v_readlane_b32 s84, v20, 28
-; SI-NEXT: v_readlane_b32 s83, v20, 27
-; SI-NEXT: v_readlane_b32 s82, v20, 26
-; SI-NEXT: v_readlane_b32 s81, v20, 25
-; SI-NEXT: v_readlane_b32 s80, v20, 24
-; SI-NEXT: v_readlane_b32 s71, v20, 23
-; SI-NEXT: v_readlane_b32 s70, v20, 22
-; SI-NEXT: v_readlane_b32 s69, v20, 21
-; SI-NEXT: v_readlane_b32 s68, v20, 20
-; SI-NEXT: v_readlane_b32 s67, v20, 19
-; SI-NEXT: v_readlane_b32 s66, v20, 18
-; SI-NEXT: v_readlane_b32 s65, v20, 17
-; SI-NEXT: v_readlane_b32 s64, v20, 16
-; SI-NEXT: v_readlane_b32 s55, v20, 15
-; SI-NEXT: v_readlane_b32 s54, v20, 14
-; SI-NEXT: v_readlane_b32 s53, v20, 13
-; SI-NEXT: v_readlane_b32 s52, v20, 12
-; SI-NEXT: v_readlane_b32 s51, v20, 11
-; SI-NEXT: v_readlane_b32 s50, v20, 10
-; SI-NEXT: v_readlane_b32 s49, v20, 9
-; SI-NEXT: v_readlane_b32 s48, v20, 8
-; SI-NEXT: v_readlane_b32 s39, v20, 7
-; SI-NEXT: v_readlane_b32 s38, v20, 6
-; SI-NEXT: v_readlane_b32 s37, v20, 5
-; SI-NEXT: v_readlane_b32 s36, v20, 4
-; SI-NEXT: v_readlane_b32 s35, v20, 3
-; SI-NEXT: v_readlane_b32 s34, v20, 2
-; SI-NEXT: v_readlane_b32 s31, v20, 1
-; SI-NEXT: v_readlane_b32 s30, v20, 0
+; SI-NEXT: v_readlane_b32 s31, v20, 35
+; SI-NEXT: v_readlane_b32 s99, v20, 33
+; SI-NEXT: v_readlane_b32 s98, v20, 32
+; SI-NEXT: v_readlane_b32 s97, v20, 31
+; SI-NEXT: v_readlane_b32 s96, v20, 30
+; SI-NEXT: v_readlane_b32 s87, v20, 29
+; SI-NEXT: v_readlane_b32 s86, v20, 28
+; SI-NEXT: v_readlane_b32 s85, v20, 27
+; SI-NEXT: v_readlane_b32 s84, v20, 26
+; SI-NEXT: v_readlane_b32 s83, v20, 25
+; SI-NEXT: v_readlane_b32 s82, v20, 24
+; SI-NEXT: v_readlane_b32 s81, v20, 23
+; SI-NEXT: v_readlane_b32 s80, v20, 22
+; SI-NEXT: v_readlane_b32 s71, v20, 21
+; SI-NEXT: v_readlane_b32 s70, v20, 20
+; SI-NEXT: v_readlane_b32 s69, v20, 19
+; SI-NEXT: v_readlane_b32 s68, v20, 18
+; SI-NEXT: v_readlane_b32 s67, v20, 17
+; SI-NEXT: v_readlane_b32 s66, v20, 16
+; SI-NEXT: v_readlane_b32 s65, v20, 15
+; SI-NEXT: v_readlane_b32 s64, v20, 14
+; SI-NEXT: v_readlane_b32 s55, v20, 13
+; SI-NEXT: v_readlane_b32 s54, v20, 12
+; SI-NEXT: v_readlane_b32 s53, v20, 11
+; SI-NEXT: v_readlane_b32 s52, v20, 10
+; SI-NEXT: v_readlane_b32 s51, v20, 9
+; SI-NEXT: v_readlane_b32 s50, v20, 8
+; SI-NEXT: v_readlane_b32 s49, v20, 7
+; SI-NEXT: v_readlane_b32 s48, v20, 6
+; SI-NEXT: v_readlane_b32 s39, v20, 5
+; SI-NEXT: v_readlane_b32 s38, v20, 4
+; SI-NEXT: v_readlane_b32 s37, v20, 3
+; SI-NEXT: v_readlane_b32 s36, v20, 2
+; SI-NEXT: v_readlane_b32 s35, v20, 1
+; SI-NEXT: v_readlane_b32 s34, v20, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -8630,38 +8630,38 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v20, s30, 0
-; VI-NEXT: v_writelane_b32 v20, s31, 1
-; VI-NEXT: v_writelane_b32 v20, s34, 2
-; VI-NEXT: v_writelane_b32 v20, s35, 3
-; VI-NEXT: v_writelane_b32 v20, s36, 4
-; VI-NEXT: v_writelane_b32 v20, s37, 5
-; VI-NEXT: v_writelane_b32 v20, s38, 6
-; VI-NEXT: v_writelane_b32 v20, s39, 7
-; VI-NEXT: v_writelane_b32 v20, s48, 8
-; VI-NEXT: v_writelane_b32 v20, s49, 9
-; VI-NEXT: v_writelane_b32 v20, s50, 10
-; VI-NEXT: v_writelane_b32 v20, s51, 11
-; VI-NEXT: v_writelane_b32 v20, s52, 12
-; VI-NEXT: v_writelane_b32 v20, s53, 13
-; VI-NEXT: v_writelane_b32 v20, s54, 14
-; VI-NEXT: v_writelane_b32 v20, s55, 15
-; VI-NEXT: v_writelane_b32 v20, s64, 16
-; VI-NEXT: v_writelane_b32 v20, s65, 17
-; VI-NEXT: v_writelane_b32 v20, s66, 18
-; VI-NEXT: v_writelane_b32 v20, s67, 19
-; VI-NEXT: v_writelane_b32 v20, s68, 20
-; VI-NEXT: v_writelane_b32 v20, s69, 21
-; VI-NEXT: v_writelane_b32 v20, s70, 22
-; VI-NEXT: v_writelane_b32 v20, s71, 23
-; VI-NEXT: v_writelane_b32 v20, s80, 24
-; VI-NEXT: v_writelane_b32 v20, s81, 25
-; VI-NEXT: v_writelane_b32 v20, s82, 26
-; VI-NEXT: v_writelane_b32 v20, s83, 27
-; VI-NEXT: v_writelane_b32 v20, s84, 28
-; VI-NEXT: v_writelane_b32 v20, s85, 29
+; VI-NEXT: v_writelane_b32 v20, s34, 0
+; VI-NEXT: v_writelane_b32 v20, s35, 1
+; VI-NEXT: v_writelane_b32 v20, s36, 2
+; VI-NEXT: v_writelane_b32 v20, s37, 3
+; VI-NEXT: v_writelane_b32 v20, s38, 4
+; VI-NEXT: v_writelane_b32 v20, s39, 5
+; VI-NEXT: v_writelane_b32 v20, s48, 6
+; VI-NEXT: v_writelane_b32 v20, s49, 7
+; VI-NEXT: v_writelane_b32 v20, s50, 8
+; VI-NEXT: v_writelane_b32 v20, s51, 9
+; VI-NEXT: v_writelane_b32 v20, s52, 10
+; VI-NEXT: v_writelane_b32 v20, s53, 11
+; VI-NEXT: v_writelane_b32 v20, s54, 12
+; VI-NEXT: v_writelane_b32 v20, s55, 13
+; VI-NEXT: v_writelane_b32 v20, s64, 14
+; VI-NEXT: v_writelane_b32 v20, s65, 15
+; VI-NEXT: v_writelane_b32 v20, s66, 16
+; VI-NEXT: v_writelane_b32 v20, s67, 17
+; VI-NEXT: v_writelane_b32 v20, s68, 18
+; VI-NEXT: v_writelane_b32 v20, s69, 19
+; VI-NEXT: v_writelane_b32 v20, s70, 20
+; VI-NEXT: v_writelane_b32 v20, s71, 21
+; VI-NEXT: v_writelane_b32 v20, s80, 22
+; VI-NEXT: v_writelane_b32 v20, s81, 23
+; VI-NEXT: v_writelane_b32 v20, s82, 24
+; VI-NEXT: v_writelane_b32 v20, s83, 25
+; VI-NEXT: v_writelane_b32 v20, s84, 26
+; VI-NEXT: v_writelane_b32 v20, s85, 27
+; VI-NEXT: v_writelane_b32 v20, s86, 28
+; VI-NEXT: v_writelane_b32 v20, s87, 29
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; VI-NEXT: v_writelane_b32 v20, s86, 30
+; VI-NEXT: v_writelane_b32 v20, s30, 30
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: v_readfirstlane_b32 s45, v2
; VI-NEXT: v_readfirstlane_b32 s42, v3
@@ -8681,7 +8681,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s4, v17
; VI-NEXT: s_and_b64 s[46:47], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v18
-; VI-NEXT: v_writelane_b32 v20, s87, 31
+; VI-NEXT: v_writelane_b32 v20, s31, 31
; VI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; VI-NEXT: s_cbranch_scc0 .LBB13_4
; VI-NEXT: ; %bb.1: ; %cmp.false
@@ -9470,43 +9470,43 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
; VI-NEXT: v_mov_b32_e32 v1, s4
+; VI-NEXT: v_readlane_b32 s30, v20, 30
; VI-NEXT: v_readlane_b32 s15, v21, 1
; VI-NEXT: v_readlane_b32 s13, v21, 3
; VI-NEXT: v_readlane_b32 s11, v21, 5
; VI-NEXT: v_readlane_b32 s9, v21, 7
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT: v_readlane_b32 s87, v20, 31
-; VI-NEXT: v_readlane_b32 s86, v20, 30
-; VI-NEXT: v_readlane_b32 s85, v20, 29
-; VI-NEXT: v_readlane_b32 s84, v20, 28
-; VI-NEXT: v_readlane_b32 s83, v20, 27
-; VI-NEXT: v_readlane_b32 s82, v20, 26
-; VI-NEXT: v_readlane_b32 s81, v20, 25
-; VI-NEXT: v_readlane_b32 s80, v20, 24
-; VI-NEXT: v_readlane_b32 s71, v20, 23
-; VI-NEXT: v_readlane_b32 s70, v20, 22
-; VI-NEXT: v_readlane_b32 s69, v20, 21
-; VI-NEXT: v_readlane_b32 s68, v20, 20
-; VI-NEXT: v_readlane_b32 s67, v20, 19
-; VI-NEXT: v_readlane_b32 s66, v20, 18
-; VI-NEXT: v_readlane_b32 s65, v20, 17
-; VI-NEXT: v_readlane_b32 s64, v20, 16
-; VI-NEXT: v_readlane_b32 s55, v20, 15
-; VI-NEXT: v_readlane_b32 s54, v20, 14
-; VI-NEXT: v_readlane_b32 s53, v20, 13
-; VI-NEXT: v_readlane_b32 s52, v20, 12
-; VI-NEXT: v_readlane_b32 s51, v20, 11
-; VI-NEXT: v_readlane_b32 s50, v20, 10
-; VI-NEXT: v_readlane_b32 s49, v20, 9
-; VI-NEXT: v_readlane_b32 s48, v20, 8
-; VI-NEXT: v_readlane_b32 s39, v20, 7
-; VI-NEXT: v_readlane_b32 s38, v20, 6
-; VI-NEXT: v_readlane_b32 s37, v20, 5
-; VI-NEXT: v_readlane_b32 s36, v20, 4
-; VI-NEXT: v_readlane_b32 s35, v20, 3
-; VI-NEXT: v_readlane_b32 s34, v20, 2
-; VI-NEXT: v_readlane_b32 s31, v20, 1
-; VI-NEXT: v_readlane_b32 s30, v20, 0
+; VI-NEXT: v_readlane_b32 s31, v20, 31
+; VI-NEXT: v_readlane_b32 s87, v20, 29
+; VI-NEXT: v_readlane_b32 s86, v20, 28
+; VI-NEXT: v_readlane_b32 s85, v20, 27
+; VI-NEXT: v_readlane_b32 s84, v20, 26
+; VI-NEXT: v_readlane_b32 s83, v20, 25
+; VI-NEXT: v_readlane_b32 s82, v20, 24
+; VI-NEXT: v_readlane_b32 s81, v20, 23
+; VI-NEXT: v_readlane_b32 s80, v20, 22
+; VI-NEXT: v_readlane_b32 s71, v20, 21
+; VI-NEXT: v_readlane_b32 s70, v20, 20
+; VI-NEXT: v_readlane_b32 s69, v20, 19
+; VI-NEXT: v_readlane_b32 s68, v20, 18
+; VI-NEXT: v_readlane_b32 s67, v20, 17
+; VI-NEXT: v_readlane_b32 s66, v20, 16
+; VI-NEXT: v_readlane_b32 s65, v20, 15
+; VI-NEXT: v_readlane_b32 s64, v20, 14
+; VI-NEXT: v_readlane_b32 s55, v20, 13
+; VI-NEXT: v_readlane_b32 s54, v20, 12
+; VI-NEXT: v_readlane_b32 s53, v20, 11
+; VI-NEXT: v_readlane_b32 s52, v20, 10
+; VI-NEXT: v_readlane_b32 s51, v20, 9
+; VI-NEXT: v_readlane_b32 s50, v20, 8
+; VI-NEXT: v_readlane_b32 s49, v20, 7
+; VI-NEXT: v_readlane_b32 s48, v20, 6
+; VI-NEXT: v_readlane_b32 s39, v20, 5
+; VI-NEXT: v_readlane_b32 s38, v20, 4
+; VI-NEXT: v_readlane_b32 s37, v20, 3
+; VI-NEXT: v_readlane_b32 s36, v20, 2
+; VI-NEXT: v_readlane_b32 s35, v20, 1
+; VI-NEXT: v_readlane_b32 s34, v20, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -9679,42 +9679,42 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v20, s30, 0
-; GFX9-NEXT: v_writelane_b32 v20, s31, 1
-; GFX9-NEXT: v_writelane_b32 v20, s34, 2
-; GFX9-NEXT: v_writelane_b32 v20, s35, 3
-; GFX9-NEXT: v_writelane_b32 v20, s36, 4
-; GFX9-NEXT: v_writelane_b32 v20, s37, 5
-; GFX9-NEXT: v_writelane_b32 v20, s38, 6
-; GFX9-NEXT: v_writelane_b32 v20, s39, 7
-; GFX9-NEXT: v_writelane_b32 v20, s48, 8
-; GFX9-NEXT: v_writelane_b32 v20, s49, 9
-; GFX9-NEXT: v_writelane_b32 v20, s50, 10
-; GFX9-NEXT: v_writelane_b32 v20, s51, 11
-; GFX9-NEXT: v_writelane_b32 v20, s52, 12
-; GFX9-NEXT: v_writelane_b32 v20, s53, 13
-; GFX9-NEXT: v_writelane_b32 v20, s54, 14
-; GFX9-NEXT: v_writelane_b32 v20, s55, 15
-; GFX9-NEXT: v_writelane_b32 v20, s64, 16
-; GFX9-NEXT: v_writelane_b32 v20, s65, 17
-; GFX9-NEXT: v_writelane_b32 v20, s66, 18
-; GFX9-NEXT: v_writelane_b32 v20, s67, 19
-; GFX9-NEXT: v_writelane_b32 v20, s68, 20
-; GFX9-NEXT: v_writelane_b32 v20, s69, 21
-; GFX9-NEXT: v_writelane_b32 v20, s70, 22
-; GFX9-NEXT: v_writelane_b32 v20, s71, 23
-; GFX9-NEXT: v_writelane_b32 v20, s80, 24
-; GFX9-NEXT: v_writelane_b32 v20, s81, 25
-; GFX9-NEXT: v_writelane_b32 v20, s82, 26
-; GFX9-NEXT: v_writelane_b32 v20, s83, 27
-; GFX9-NEXT: v_writelane_b32 v20, s84, 28
-; GFX9-NEXT: v_writelane_b32 v20, s85, 29
-; GFX9-NEXT: v_writelane_b32 v20, s86, 30
-; GFX9-NEXT: v_writelane_b32 v20, s87, 31
-; GFX9-NEXT: v_writelane_b32 v20, s96, 32
-; GFX9-NEXT: v_writelane_b32 v20, s97, 33
+; GFX9-NEXT: v_writelane_b32 v20, s34, 0
+; GFX9-NEXT: v_writelane_b32 v20, s35, 1
+; GFX9-NEXT: v_writelane_b32 v20, s36, 2
+; GFX9-NEXT: v_writelane_b32 v20, s37, 3
+; GFX9-NEXT: v_writelane_b32 v20, s38, 4
+; GFX9-NEXT: v_writelane_b32 v20, s39, 5
+; GFX9-NEXT: v_writelane_b32 v20, s48, 6
+; GFX9-NEXT: v_writelane_b32 v20, s49, 7
+; GFX9-NEXT: v_writelane_b32 v20, s50, 8
+; GFX9-NEXT: v_writelane_b32 v20, s51, 9
+; GFX9-NEXT: v_writelane_b32 v20, s52, 10
+; GFX9-NEXT: v_writelane_b32 v20, s53, 11
+; GFX9-NEXT: v_writelane_b32 v20, s54, 12
+; GFX9-NEXT: v_writelane_b32 v20, s55, 13
+; GFX9-NEXT: v_writelane_b32 v20, s64, 14
+; GFX9-NEXT: v_writelane_b32 v20, s65, 15
+; GFX9-NEXT: v_writelane_b32 v20, s66, 16
+; GFX9-NEXT: v_writelane_b32 v20, s67, 17
+; GFX9-NEXT: v_writelane_b32 v20, s68, 18
+; GFX9-NEXT: v_writelane_b32 v20, s69, 19
+; GFX9-NEXT: v_writelane_b32 v20, s70, 20
+; GFX9-NEXT: v_writelane_b32 v20, s71, 21
+; GFX9-NEXT: v_writelane_b32 v20, s80, 22
+; GFX9-NEXT: v_writelane_b32 v20, s81, 23
+; GFX9-NEXT: v_writelane_b32 v20, s82, 24
+; GFX9-NEXT: v_writelane_b32 v20, s83, 25
+; GFX9-NEXT: v_writelane_b32 v20, s84, 26
+; GFX9-NEXT: v_writelane_b32 v20, s85, 27
+; GFX9-NEXT: v_writelane_b32 v20, s86, 28
+; GFX9-NEXT: v_writelane_b32 v20, s87, 29
+; GFX9-NEXT: v_writelane_b32 v20, s96, 30
+; GFX9-NEXT: v_writelane_b32 v20, s97, 31
+; GFX9-NEXT: v_writelane_b32 v20, s98, 32
+; GFX9-NEXT: v_writelane_b32 v20, s99, 33
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; GFX9-NEXT: v_writelane_b32 v20, s98, 34
+; GFX9-NEXT: v_writelane_b32 v20, s30, 34
; GFX9-NEXT: v_readfirstlane_b32 s44, v1
; GFX9-NEXT: v_readfirstlane_b32 s45, v2
; GFX9-NEXT: v_readfirstlane_b32 s42, v3
@@ -9734,7 +9734,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s4, v17
; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v18
-; GFX9-NEXT: v_writelane_b32 v20, s99, 35
+; GFX9-NEXT: v_writelane_b32 v20, s31, 35
; GFX9-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; GFX9-NEXT: s_cbranch_scc0 .LBB13_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
@@ -10468,44 +10468,44 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: s_or_b32 s4, s4, s5
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_readlane_b32 s30, v20, 34
; GFX9-NEXT: v_readlane_b32 s9, v21, 1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
-; GFX9-NEXT: v_readlane_b32 s99, v20, 35
-; GFX9-NEXT: v_readlane_b32 s98, v20, 34
-; GFX9-NEXT: v_readlane_b32 s97, v20, 33
-; GFX9-NEXT: v_readlane_b32 s96, v20, 32
-; GFX9-NEXT: v_readlane_b32 s87, v20, 31
-; GFX9-NEXT: v_readlane_b32 s86, v20, 30
-; GFX9-NEXT: v_readlane_b32 s85, v20, 29
-; GFX9-NEXT: v_readlane_b32 s84, v20, 28
-; GFX9-NEXT: v_readlane_b32 s83, v20, 27
-; GFX9-NEXT: v_readlane_b32 s82, v20, 26
-; GFX9-NEXT: v_readlane_b32 s81, v20, 25
-; GFX9-NEXT: v_readlane_b32 s80, v20, 24
-; GFX9-NEXT: v_readlane_b32 s71, v20, 23
-; GFX9-NEXT: v_readlane_b32 s70, v20, 22
-; GFX9-NEXT: v_readlane_b32 s69, v20, 21
-; GFX9-NEXT: v_readlane_b32 s68, v20, 20
-; GFX9-NEXT: v_readlane_b32 s67, v20, 19
-; GFX9-NEXT: v_readlane_b32 s66, v20, 18
-; GFX9-NEXT: v_readlane_b32 s65, v20, 17
-; GFX9-NEXT: v_readlane_b32 s64, v20, 16
-; GFX9-NEXT: v_readlane_b32 s55, v20, 15
-; GFX9-NEXT: v_readlane_b32 s54, v20, 14
-; GFX9-NEXT: v_readlane_b32 s53, v20, 13
-; GFX9-NEXT: v_readlane_b32 s52, v20, 12
-; GFX9-NEXT: v_readlane_b32 s51, v20, 11
-; GFX9-NEXT: v_readlane_b32 s50, v20, 10
-; GFX9-NEXT: v_readlane_b32 s49, v20, 9
-; GFX9-NEXT: v_readlane_b32 s48, v20, 8
-; GFX9-NEXT: v_readlane_b32 s39, v20, 7
-; GFX9-NEXT: v_readlane_b32 s38, v20, 6
-; GFX9-NEXT: v_readlane_b32 s37, v20, 5
-; GFX9-NEXT: v_readlane_b32 s36, v20, 4
-; GFX9-NEXT: v_readlane_b32 s35, v20, 3
-; GFX9-NEXT: v_readlane_b32 s34, v20, 2
-; GFX9-NEXT: v_readlane_b32 s31, v20, 1
-; GFX9-NEXT: v_readlane_b32 s30, v20, 0
+; GFX9-NEXT: v_readlane_b32 s31, v20, 35
+; GFX9-NEXT: v_readlane_b32 s99, v20, 33
+; GFX9-NEXT: v_readlane_b32 s98, v20, 32
+; GFX9-NEXT: v_readlane_b32 s97, v20, 31
+; GFX9-NEXT: v_readlane_b32 s96, v20, 30
+; GFX9-NEXT: v_readlane_b32 s87, v20, 29
+; GFX9-NEXT: v_readlane_b32 s86, v20, 28
+; GFX9-NEXT: v_readlane_b32 s85, v20, 27
+; GFX9-NEXT: v_readlane_b32 s84, v20, 26
+; GFX9-NEXT: v_readlane_b32 s83, v20, 25
+; GFX9-NEXT: v_readlane_b32 s82, v20, 24
+; GFX9-NEXT: v_readlane_b32 s81, v20, 23
+; GFX9-NEXT: v_readlane_b32 s80, v20, 22
+; GFX9-NEXT: v_readlane_b32 s71, v20, 21
+; GFX9-NEXT: v_readlane_b32 s70, v20, 20
+; GFX9-NEXT: v_readlane_b32 s69, v20, 19
+; GFX9-NEXT: v_readlane_b32 s68, v20, 18
+; GFX9-NEXT: v_readlane_b32 s67, v20, 17
+; GFX9-NEXT: v_readlane_b32 s66, v20, 16
+; GFX9-NEXT: v_readlane_b32 s65, v20, 15
+; GFX9-NEXT: v_readlane_b32 s64, v20, 14
+; GFX9-NEXT: v_readlane_b32 s55, v20, 13
+; GFX9-NEXT: v_readlane_b32 s54, v20, 12
+; GFX9-NEXT: v_readlane_b32 s53, v20, 11
+; GFX9-NEXT: v_readlane_b32 s52, v20, 10
+; GFX9-NEXT: v_readlane_b32 s51, v20, 9
+; GFX9-NEXT: v_readlane_b32 s50, v20, 8
+; GFX9-NEXT: v_readlane_b32 s49, v20, 7
+; GFX9-NEXT: v_readlane_b32 s48, v20, 6
+; GFX9-NEXT: v_readlane_b32 s39, v20, 5
+; GFX9-NEXT: v_readlane_b32 s38, v20, 4
+; GFX9-NEXT: v_readlane_b32 s37, v20, 3
+; GFX9-NEXT: v_readlane_b32 s36, v20, 2
+; GFX9-NEXT: v_readlane_b32 s35, v20, 1
+; GFX9-NEXT: v_readlane_b32 s34, v20, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -10672,66 +10672,66 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: scratch_store_b32 off, v18, s32 offset:8
; GFX11-NEXT: scratch_store_b32 off, v19, s32 offset:12
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v16, s30, 0
-; GFX11-NEXT: v_writelane_b32 v17, s96, 0
+; GFX11-NEXT: v_writelane_b32 v16, s34, 0
+; GFX11-NEXT: v_writelane_b32 v17, s98, 0
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
; GFX11-NEXT: v_readfirstlane_b32 s40, v1
; GFX11-NEXT: v_readfirstlane_b32 s41, v2
-; GFX11-NEXT: v_writelane_b32 v16, s31, 1
-; GFX11-NEXT: v_writelane_b32 v17, s97, 1
+; GFX11-NEXT: v_writelane_b32 v16, s35, 1
+; GFX11-NEXT: v_writelane_b32 v17, s99, 1
; GFX11-NEXT: v_readfirstlane_b32 s14, v3
; GFX11-NEXT: v_readfirstlane_b32 s15, v4
; GFX11-NEXT: v_readfirstlane_b32 s12, v5
-; GFX11-NEXT: v_writelane_b32 v16, s34, 2
-; GFX11-NEXT: v_writelane_b32 v17, s98, 2
+; GFX11-NEXT: v_writelane_b32 v16, s36, 2
+; GFX11-NEXT: v_writelane_b32 v17, s100, 2
; GFX11-NEXT: v_readfirstlane_b32 s13, v6
; GFX11-NEXT: v_readfirstlane_b32 s10, v7
; GFX11-NEXT: v_readfirstlane_b32 s11, v8
-; GFX11-NEXT: v_writelane_b32 v16, s35, 3
-; GFX11-NEXT: v_writelane_b32 v17, s99, 3
+; GFX11-NEXT: v_writelane_b32 v16, s37, 3
+; GFX11-NEXT: v_writelane_b32 v17, s101, 3
; GFX11-NEXT: v_readfirstlane_b32 s8, v9
; GFX11-NEXT: v_readfirstlane_b32 s9, v10
; GFX11-NEXT: v_readfirstlane_b32 s6, v11
-; GFX11-NEXT: v_writelane_b32 v16, s36, 4
-; GFX11-NEXT: v_writelane_b32 v17, s100, 4
+; GFX11-NEXT: v_writelane_b32 v16, s38, 4
+; GFX11-NEXT: v_writelane_b32 v17, s102, 4
; GFX11-NEXT: v_readfirstlane_b32 s7, v12
; GFX11-NEXT: v_readfirstlane_b32 s4, v13
; GFX11-NEXT: v_readfirstlane_b32 s5, v14
-; GFX11-NEXT: v_writelane_b32 v16, s37, 5
-; GFX11-NEXT: v_writelane_b32 v17, s101, 5
+; GFX11-NEXT: v_writelane_b32 v16, s39, 5
+; GFX11-NEXT: v_writelane_b32 v17, s103, 5
; GFX11-NEXT: s_mov_b32 s101, 0
; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
; GFX11-NEXT: ; implicit-def: $vgpr19 : SGPR spill to VGPR lane
; GFX11-NEXT: ; implicit-def: $vgpr18 : SGPR spill to VGPR lane
-; GFX11-NEXT: v_writelane_b32 v16, s38, 6
-; GFX11-NEXT: v_writelane_b32 v17, s102, 6
-; GFX11-NEXT: v_writelane_b32 v16, s39, 7
-; GFX11-NEXT: v_writelane_b32 v17, s103, 7
-; GFX11-NEXT: v_writelane_b32 v16, s48, 8
-; GFX11-NEXT: v_writelane_b32 v17, s104, 8
-; GFX11-NEXT: v_writelane_b32 v16, s49, 9
-; GFX11-NEXT: v_writelane_b32 v16, s50, 10
-; GFX11-NEXT: v_writelane_b32 v16, s51, 11
-; GFX11-NEXT: v_writelane_b32 v16, s52, 12
-; GFX11-NEXT: v_writelane_b32 v16, s53, 13
-; GFX11-NEXT: v_writelane_b32 v16, s54, 14
-; GFX11-NEXT: v_writelane_b32 v16, s55, 15
-; GFX11-NEXT: v_writelane_b32 v16, s64, 16
-; GFX11-NEXT: v_writelane_b32 v16, s65, 17
-; GFX11-NEXT: v_writelane_b32 v16, s66, 18
-; GFX11-NEXT: v_writelane_b32 v16, s67, 19
-; GFX11-NEXT: v_writelane_b32 v16, s68, 20
-; GFX11-NEXT: v_writelane_b32 v16, s69, 21
-; GFX11-NEXT: v_writelane_b32 v16, s70, 22
-; GFX11-NEXT: v_writelane_b32 v16, s71, 23
-; GFX11-NEXT: v_writelane_b32 v16, s80, 24
-; GFX11-NEXT: v_writelane_b32 v16, s81, 25
-; GFX11-NEXT: v_writelane_b32 v16, s82, 26
-; GFX11-NEXT: v_writelane_b32 v16, s83, 27
-; GFX11-NEXT: v_writelane_b32 v16, s84, 28
-; GFX11-NEXT: v_writelane_b32 v16, s85, 29
-; GFX11-NEXT: v_writelane_b32 v16, s86, 30
-; GFX11-NEXT: v_writelane_b32 v16, s87, 31
+; GFX11-NEXT: v_writelane_b32 v16, s48, 6
+; GFX11-NEXT: v_writelane_b32 v17, s104, 6
+; GFX11-NEXT: v_writelane_b32 v16, s49, 7
+; GFX11-NEXT: v_writelane_b32 v17, s30, 7
+; GFX11-NEXT: v_writelane_b32 v16, s50, 8
+; GFX11-NEXT: v_writelane_b32 v17, s31, 8
+; GFX11-NEXT: v_writelane_b32 v16, s51, 9
+; GFX11-NEXT: v_writelane_b32 v16, s52, 10
+; GFX11-NEXT: v_writelane_b32 v16, s53, 11
+; GFX11-NEXT: v_writelane_b32 v16, s54, 12
+; GFX11-NEXT: v_writelane_b32 v16, s55, 13
+; GFX11-NEXT: v_writelane_b32 v16, s64, 14
+; GFX11-NEXT: v_writelane_b32 v16, s65, 15
+; GFX11-NEXT: v_writelane_b32 v16, s66, 16
+; GFX11-NEXT: v_writelane_b32 v16, s67, 17
+; GFX11-NEXT: v_writelane_b32 v16, s68, 18
+; GFX11-NEXT: v_writelane_b32 v16, s69, 19
+; GFX11-NEXT: v_writelane_b32 v16, s70, 20
+; GFX11-NEXT: v_writelane_b32 v16, s71, 21
+; GFX11-NEXT: v_writelane_b32 v16, s80, 22
+; GFX11-NEXT: v_writelane_b32 v16, s81, 23
+; GFX11-NEXT: v_writelane_b32 v16, s82, 24
+; GFX11-NEXT: v_writelane_b32 v16, s83, 25
+; GFX11-NEXT: v_writelane_b32 v16, s84, 26
+; GFX11-NEXT: v_writelane_b32 v16, s85, 27
+; GFX11-NEXT: v_writelane_b32 v16, s86, 28
+; GFX11-NEXT: v_writelane_b32 v16, s87, 29
+; GFX11-NEXT: v_writelane_b32 v16, s96, 30
+; GFX11-NEXT: v_writelane_b32 v16, s97, 31
; GFX11-NEXT: s_cbranch_scc0 .LBB13_2
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s43, s25, 8
@@ -11258,9 +11258,9 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: s_and_b32 s1, s1, 0xffff
; GFX11-NEXT: v_readlane_b32 s17, v19, 29
; GFX11-NEXT: s_and_b32 s16, s16, 0xff
-; GFX11-NEXT: v_readlane_b32 s100, v17, 4
+; GFX11-NEXT: v_readlane_b32 s30, v17, 7
; GFX11-NEXT: s_and_b32 s2, s2, 0xff
-; GFX11-NEXT: v_readlane_b32 s99, v17, 3
+; GFX11-NEXT: v_readlane_b32 s31, v17, 8
; GFX11-NEXT: s_or_b32 s2, s2, s3
; GFX11-NEXT: s_and_b32 s3, s18, 0xff
; GFX11-NEXT: s_lshl_b32 s2, s2, 16
@@ -11294,7 +11294,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: s_or_b32 s16, s16, s17
; GFX11-NEXT: v_readlane_b32 s17, v19, 21
; GFX11-NEXT: s_lshl_b32 s16, s16, 16
-; GFX11-NEXT: v_readlane_b32 s98, v17, 2
+; GFX11-NEXT: v_readlane_b32 s100, v17, 2
; GFX11-NEXT: s_or_b32 s3, s3, s16
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3
@@ -11314,12 +11314,12 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: s_or_b32 s0, s0, s1
; GFX11-NEXT: s_and_b32 s1, s21, 0xff
; GFX11-NEXT: s_lshl_b32 s2, s2, 8
-; GFX11-NEXT: v_readlane_b32 s86, v16, 30
+; GFX11-NEXT: v_readlane_b32 s99, v17, 1
; GFX11-NEXT: s_or_b32 s1, s1, s2
; GFX11-NEXT: v_readlane_b32 s2, v19, 25
; GFX11-NEXT: s_and_b32 s1, s1, 0xffff
-; GFX11-NEXT: v_readlane_b32 s31, v16, 1
-; GFX11-NEXT: v_readlane_b32 s30, v16, 0
+; GFX11-NEXT: v_readlane_b32 s98, v17, 0
+; GFX11-NEXT: v_readlane_b32 s86, v16, 28
; GFX11-NEXT: s_and_b32 s2, s2, 0xff
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s2, s2, s3
@@ -11356,9 +11356,9 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: s_lshl_b32 s3, s88, 8
; GFX11-NEXT: s_and_b32 s16, s69, 0xff
; GFX11-NEXT: s_and_b32 s18, s72, 0xff
-; GFX11-NEXT: v_readlane_b32 s97, v17, 1
+; GFX11-NEXT: v_readlane_b32 s97, v16, 31
; GFX11-NEXT: s_and_b32 s2, s2, 0xff
-; GFX11-NEXT: v_readlane_b32 s69, v16, 21
+; GFX11-NEXT: v_readlane_b32 s69, v16, 19
; GFX11-NEXT: s_or_b32 s1, s2, s3
; GFX11-NEXT: v_readlane_b32 s3, v19, 16
; GFX11-NEXT: s_and_b32 s2, s25, 0xff
@@ -11565,39 +11565,39 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:80
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:96
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:112
-; GFX11-NEXT: v_readlane_b32 s104, v17, 8
-; GFX11-NEXT: v_readlane_b32 s103, v17, 7
-; GFX11-NEXT: v_readlane_b32 s102, v17, 6
-; GFX11-NEXT: v_readlane_b32 s101, v17, 5
-; GFX11-NEXT: v_readlane_b32 s96, v17, 0
-; GFX11-NEXT: v_readlane_b32 s87, v16, 31
-; GFX11-NEXT: v_readlane_b32 s85, v16, 29
-; GFX11-NEXT: v_readlane_b32 s84, v16, 28
-; GFX11-NEXT: v_readlane_b32 s83, v16, 27
-; GFX11-NEXT: v_readlane_b32 s82, v16, 26
-; GFX11-NEXT: v_readlane_b32 s81, v16, 25
-; GFX11-NEXT: v_readlane_b32 s80, v16, 24
-; GFX11-NEXT: v_readlane_b32 s71, v16, 23
-; GFX11-NEXT: v_readlane_b32 s70, v16, 22
-; GFX11-NEXT: v_readlane_b32 s68, v16, 20
-; GFX11-NEXT: v_readlane_b32 s67, v16, 19
-; GFX11-NEXT: v_readlane_b32 s66, v16, 18
-; GFX11-NEXT: v_readlane_b32 s65, v16, 17
-; GFX11-NEXT: v_readlane_b32 s64, v16, 16
-; GFX11-NEXT: v_readlane_b32 s55, v16, 15
-; GFX11-NEXT: v_readlane_b32 s54, v16, 14
-; GFX11-NEXT: v_readlane_b32 s53, v16, 13
-; GFX11-NEXT: v_readlane_b32 s52, v16, 12
-; GFX11-NEXT: v_readlane_b32 s51, v16, 11
-; GFX11-NEXT: v_readlane_b32 s50, v16, 10
-; GFX11-NEXT: v_readlane_b32 s49, v16, 9
-; GFX11-NEXT: v_readlane_b32 s48, v16, 8
-; GFX11-NEXT: v_readlane_b32 s39, v16, 7
-; GFX11-NEXT: v_readlane_b32 s38, v16, 6
-; GFX11-NEXT: v_readlane_b32 s37, v16, 5
-; GFX11-NEXT: v_readlane_b32 s36, v16, 4
-; GFX11-NEXT: v_readlane_b32 s35, v16, 3
-; GFX11-NEXT: v_readlane_b32 s34, v16, 2
+; GFX11-NEXT: v_readlane_b32 s104, v17, 6
+; GFX11-NEXT: v_readlane_b32 s103, v17, 5
+; GFX11-NEXT: v_readlane_b32 s102, v17, 4
+; GFX11-NEXT: v_readlane_b32 s101, v17, 3
+; GFX11-NEXT: v_readlane_b32 s96, v16, 30
+; GFX11-NEXT: v_readlane_b32 s87, v16, 29
+; GFX11-NEXT: v_readlane_b32 s85, v16, 27
+; GFX11-NEXT: v_readlane_b32 s84, v16, 26
+; GFX11-NEXT: v_readlane_b32 s83, v16, 25
+; GFX11-NEXT: v_readlane_b32 s82, v16, 24
+; GFX11-NEXT: v_readlane_b32 s81, v16, 23
+; GFX11-NEXT: v_readlane_b32 s80, v16, 22
+; GFX11-NEXT: v_readlane_b32 s71, v16, 21
+; GFX11-NEXT: v_readlane_b32 s70, v16, 20
+; GFX11-NEXT: v_readlane_b32 s68, v16, 18
+; GFX11-NEXT: v_readlane_b32 s67, v16, 17
+; GFX11-NEXT: v_readlane_b32 s66, v16, 16
+; GFX11-NEXT: v_readlane_b32 s65, v16, 15
+; GFX11-NEXT: v_readlane_b32 s64, v16, 14
+; GFX11-NEXT: v_readlane_b32 s55, v16, 13
+; GFX11-NEXT: v_readlane_b32 s54, v16, 12
+; GFX11-NEXT: v_readlane_b32 s53, v16, 11
+; GFX11-NEXT: v_readlane_b32 s52, v16, 10
+; GFX11-NEXT: v_readlane_b32 s51, v16, 9
+; GFX11-NEXT: v_readlane_b32 s50, v16, 8
+; GFX11-NEXT: v_readlane_b32 s49, v16, 7
+; GFX11-NEXT: v_readlane_b32 s48, v16, 6
+; GFX11-NEXT: v_readlane_b32 s39, v16, 5
+; GFX11-NEXT: v_readlane_b32 s38, v16, 4
+; GFX11-NEXT: v_readlane_b32 s37, v16, 3
+; GFX11-NEXT: v_readlane_b32 s36, v16, 2
+; GFX11-NEXT: v_readlane_b32 s35, v16, 1
+; GFX11-NEXT: v_readlane_b32 s34, v16, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_load_b32 v16, off, s32
@@ -23488,43 +23488,42 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_writelane_b32 v20, s30, 0
-; SI-NEXT: v_writelane_b32 v20, s31, 1
-; SI-NEXT: v_writelane_b32 v20, s34, 2
-; SI-NEXT: v_writelane_b32 v20, s35, 3
-; SI-NEXT: v_writelane_b32 v20, s36, 4
-; SI-NEXT: v_writelane_b32 v20, s37, 5
-; SI-NEXT: v_writelane_b32 v20, s38, 6
-; SI-NEXT: v_writelane_b32 v20, s39, 7
-; SI-NEXT: v_writelane_b32 v20, s48, 8
-; SI-NEXT: v_writelane_b32 v20, s49, 9
-; SI-NEXT: v_writelane_b32 v20, s50, 10
-; SI-NEXT: v_writelane_b32 v20, s51, 11
-; SI-NEXT: v_writelane_b32 v20, s52, 12
-; SI-NEXT: v_writelane_b32 v20, s53, 13
-; SI-NEXT: v_writelane_b32 v20, s54, 14
-; SI-NEXT: v_writelane_b32 v20, s55, 15
-; SI-NEXT: v_writelane_b32 v20, s64, 16
-; SI-NEXT: v_writelane_b32 v20, s65, 17
-; SI-NEXT: v_writelane_b32 v20, s66, 18
-; SI-NEXT: v_writelane_b32 v20, s67, 19
-; SI-NEXT: v_writelane_b32 v20, s68, 20
-; SI-NEXT: v_writelane_b32 v20, s69, 21
-; SI-NEXT: v_writelane_b32 v20, s70, 22
-; SI-NEXT: v_writelane_b32 v20, s71, 23
-; SI-NEXT: v_writelane_b32 v20, s80, 24
-; SI-NEXT: v_writelane_b32 v20, s81, 25
-; SI-NEXT: v_writelane_b32 v20, s82, 26
-; SI-NEXT: v_writelane_b32 v20, s83, 27
-; SI-NEXT: v_writelane_b32 v20, s84, 28
-; SI-NEXT: v_writelane_b32 v20, s85, 29
-; SI-NEXT: v_writelane_b32 v20, s86, 30
-; SI-NEXT: v_writelane_b32 v20, s87, 31
-; SI-NEXT: v_writelane_b32 v20, s96, 32
-; SI-NEXT: v_writelane_b32 v20, s97, 33
-; SI-NEXT: v_writelane_b32 v20, s98, 34
+; SI-NEXT: v_writelane_b32 v20, s34, 0
+; SI-NEXT: v_writelane_b32 v20, s35, 1
+; SI-NEXT: v_writelane_b32 v20, s36, 2
+; SI-NEXT: v_writelane_b32 v20, s37, 3
+; SI-NEXT: v_writelane_b32 v20, s38, 4
+; SI-NEXT: v_writelane_b32 v20, s39, 5
+; SI-NEXT: v_writelane_b32 v20, s48, 6
+; SI-NEXT: v_writelane_b32 v20, s49, 7
+; SI-NEXT: v_writelane_b32 v20, s50, 8
+; SI-NEXT: v_writelane_b32 v20, s51, 9
+; SI-NEXT: v_writelane_b32 v20, s52, 10
+; SI-NEXT: v_writelane_b32 v20, s53, 11
+; SI-NEXT: v_writelane_b32 v20, s54, 12
+; SI-NEXT: v_writelane_b32 v20, s55, 13
+; SI-NEXT: v_writelane_b32 v20, s64, 14
+; SI-NEXT: v_writelane_b32 v20, s65, 15
+; SI-NEXT: v_writelane_b32 v20, s66, 16
+; SI-NEXT: v_writelane_b32 v20, s67, 17
+; SI-NEXT: v_writelane_b32 v20, s68, 18
+; SI-NEXT: v_writelane_b32 v20, s69, 19
+; SI-NEXT: v_writelane_b32 v20, s70, 20
+; SI-NEXT: v_writelane_b32 v20, s71, 21
+; SI-NEXT: v_writelane_b32 v20, s80, 22
+; SI-NEXT: v_writelane_b32 v20, s81, 23
+; SI-NEXT: v_writelane_b32 v20, s82, 24
+; SI-NEXT: v_writelane_b32 v20, s83, 25
+; SI-NEXT: v_writelane_b32 v20, s84, 26
+; SI-NEXT: v_writelane_b32 v20, s85, 27
+; SI-NEXT: v_writelane_b32 v20, s86, 28
+; SI-NEXT: v_writelane_b32 v20, s87, 29
+; SI-NEXT: v_writelane_b32 v20, s96, 30
+; SI-NEXT: v_writelane_b32 v20, s97, 31
+; SI-NEXT: v_writelane_b32 v20, s98, 32
+; SI-NEXT: v_writelane_b32 v20, s99, 33
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_writelane_b32 v20, s99, 35
+; SI-NEXT: v_writelane_b32 v20, s30, 34
; SI-NEXT: v_readfirstlane_b32 s70, v1
; SI-NEXT: v_readfirstlane_b32 s71, v2
; SI-NEXT: v_readfirstlane_b32 s80, v3
@@ -23544,6 +23543,7 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a
; SI-NEXT: v_readfirstlane_b32 s8, v17
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v18
+; SI-NEXT: v_writelane_b32 v20, s31, 35
; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB17_2
; SI-NEXT: ; %bb.1: ; %cmp.false
@@ -24044,43 +24044,43 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
+; SI-NEXT: v_readlane_b32 s30, v20, 34
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s99, v20, 35
-; SI-NEXT: v_readlane_b32 s98, v20, 34
-; SI-NEXT: v_readlane_b32 s97, v20, 33
-; SI-NEXT: v_readlane_b32 s96, v20, 32
-; SI-NEXT: v_readlane_b32 s87, v20, 31
-; SI-NEXT: v_readlane_b32 s86, v20, 30
-; SI-NEXT: v_readlane_b32 s85, v20, 29
-; SI-NEXT: v_readlane_b32 s84, v20, 28
-; SI-NEXT: v_readlane_b32 s83, v20, 27
-; SI-NEXT: v_readlane_b32 s82, v20, 26
-; SI-NEXT: v_readlane_b32 s81, v20, 25
-; SI-NEXT: v_readlane_b32 s80, v20, 24
-; SI-NEXT: v_readlane_b32 s71, v20, 23
-; SI-NEXT: v_readlane_b32 s70, v20, 22
-; SI-NEXT: v_readlane_b32 s69, v20, 21
-; SI-NEXT: v_readlane_b32 s68, v20, 20
-; SI-NEXT: v_readlane_b32 s67, v20, 19
-; SI-NEXT: v_readlane_b32 s66, v20, 18
-; SI-NEXT: v_readlane_b32 s65, v20, 17
-; SI-NEXT: v_readlane_b32 s64, v20, 16
-; SI-NEXT: v_readlane_b32 s55, v20, 15
-; SI-NEXT: v_readlane_b32 s54, v20, 14
-; SI-NEXT: v_readlane_b32 s53, v20, 13
-; SI-NEXT: v_readlane_b32 s52, v20, 12
-; SI-NEXT: v_readlane_b32 s51, v20, 11
-; SI-NEXT: v_readlane_b32 s50, v20, 10
-; SI-NEXT: v_readlane_b32 s49, v20, 9
-; SI-NEXT: v_readlane_b32 s48, v20, 8
-; SI-NEXT: v_readlane_b32 s39, v20, 7
-; SI-NEXT: v_readlane_b32 s38, v20, 6
-; SI-NEXT: v_readlane_b32 s37, v20, 5
-; SI-NEXT: v_readlane_b32 s36, v20, 4
-; SI-NEXT: v_readlane_b32 s35, v20, 3
-; SI-NEXT: v_readlane_b32 s34, v20, 2
-; SI-NEXT: v_readlane_b32 s31, v20, 1
-; SI-NEXT: v_readlane_b32 s30, v20, 0
+; SI-NEXT: v_readlane_b32 s31, v20, 35
+; SI-NEXT: v_readlane_b32 s99, v20, 33
+; SI-NEXT: v_readlane_b32 s98, v20, 32
+; SI-NEXT: v_readlane_b32 s97, v20, 31
+; SI-NEXT: v_readlane_b32 s96, v20, 30
+; SI-NEXT: v_readlane_b32 s87, v20, 29
+; SI-NEXT: v_readlane_b32 s86, v20, 28
+; SI-NEXT: v_readlane_b32 s85, v20, 27
+; SI-NEXT: v_readlane_b32 s84, v20, 26
+; SI-NEXT: v_readlane_b32 s83, v20, 25
+; SI-NEXT: v_readlane_b32 s82, v20, 24
+; SI-NEXT: v_readlane_b32 s81, v20, 23
+; SI-NEXT: v_readlane_b32 s80, v20, 22
+; SI-NEXT: v_readlane_b32 s71, v20, 21
+; SI-NEXT: v_readlane_b32 s70, v20, 20
+; SI-NEXT: v_readlane_b32 s69, v20, 19
+; SI-NEXT: v_readlane_b32 s68, v20, 18
+; SI-NEXT: v_readlane_b32 s67, v20, 17
+; SI-NEXT: v_readlane_b32 s66, v20, 16
+; SI-NEXT: v_readlane_b32 s65, v20, 15
+; SI-NEXT: v_readlane_b32 s64, v20, 14
+; SI-NEXT: v_readlane_b32 s55, v20, 13
+; SI-NEXT: v_readlane_b32 s54, v20, 12
+; SI-NEXT: v_readlane_b32 s53, v20, 11
+; SI-NEXT: v_readlane_b32 s52, v20, 10
+; SI-NEXT: v_readlane_b32 s51, v20, 9
+; SI-NEXT: v_readlane_b32 s50, v20, 8
+; SI-NEXT: v_readlane_b32 s49, v20, 7
+; SI-NEXT: v_readlane_b32 s48, v20, 6
+; SI-NEXT: v_readlane_b32 s39, v20, 5
+; SI-NEXT: v_readlane_b32 s38, v20, 4
+; SI-NEXT: v_readlane_b32 s37, v20, 3
+; SI-NEXT: v_readlane_b32 s36, v20, 2
+; SI-NEXT: v_readlane_b32 s35, v20, 1
+; SI-NEXT: v_readlane_b32 s34, v20, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -32002,11 +32002,11 @@ define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v63, s30, 0
-; SI-NEXT: v_writelane_b32 v63, s31, 1
-; SI-NEXT: v_writelane_b32 v63, s34, 2
+; SI-NEXT: v_writelane_b32 v63, s34, 0
+; SI-NEXT: v_writelane_b32 v63, s35, 1
+; SI-NEXT: v_writelane_b32 v63, s30, 2
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_writelane_b32 v63, s35, 3
+; SI-NEXT: v_writelane_b32 v63, s31, 3
; SI-NEXT: v_readfirstlane_b32 s47, v1
; SI-NEXT: v_readfirstlane_b32 s46, v2
; SI-NEXT: v_readfirstlane_b32 s45, v3
@@ -32282,15 +32282,15 @@ define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v61, v61
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NEXT: v_readlane_b32 s35, v63, 3
+; SI-NEXT: v_readlane_b32 s30, v63, 2
; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v61
; SI-NEXT: v_or_b32_e32 v2, v2, v61
; SI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v2, v59
-; SI-NEXT: v_readlane_b32 s34, v63, 2
-; SI-NEXT: v_readlane_b32 s31, v63, 1
-; SI-NEXT: v_readlane_b32 s30, v63, 0
+; SI-NEXT: v_readlane_b32 s31, v63, 3
+; SI-NEXT: v_readlane_b32 s35, v63, 1
+; SI-NEXT: v_readlane_b32 s34, v63, 0
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
@@ -35564,28 +35564,28 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v20, s30, 0
-; SI-NEXT: v_writelane_b32 v20, s31, 1
-; SI-NEXT: v_writelane_b32 v20, s34, 2
-; SI-NEXT: v_writelane_b32 v20, s35, 3
-; SI-NEXT: v_writelane_b32 v20, s36, 4
-; SI-NEXT: v_writelane_b32 v20, s37, 5
-; SI-NEXT: v_writelane_b32 v20, s38, 6
-; SI-NEXT: v_writelane_b32 v20, s39, 7
-; SI-NEXT: v_writelane_b32 v20, s48, 8
-; SI-NEXT: v_writelane_b32 v20, s49, 9
-; SI-NEXT: v_writelane_b32 v20, s50, 10
-; SI-NEXT: v_writelane_b32 v20, s51, 11
-; SI-NEXT: v_writelane_b32 v20, s52, 12
-; SI-NEXT: v_writelane_b32 v20, s53, 13
-; SI-NEXT: v_writelane_b32 v20, s54, 14
-; SI-NEXT: v_writelane_b32 v20, s55, 15
-; SI-NEXT: v_writelane_b32 v20, s64, 16
-; SI-NEXT: v_writelane_b32 v20, s65, 17
-; SI-NEXT: v_writelane_b32 v20, s66, 18
-; SI-NEXT: v_writelane_b32 v20, s67, 19
+; SI-NEXT: v_writelane_b32 v20, s34, 0
+; SI-NEXT: v_writelane_b32 v20, s35, 1
+; SI-NEXT: v_writelane_b32 v20, s36, 2
+; SI-NEXT: v_writelane_b32 v20, s37, 3
+; SI-NEXT: v_writelane_b32 v20, s38, 4
+; SI-NEXT: v_writelane_b32 v20, s39, 5
+; SI-NEXT: v_writelane_b32 v20, s48, 6
+; SI-NEXT: v_writelane_b32 v20, s49, 7
+; SI-NEXT: v_writelane_b32 v20, s50, 8
+; SI-NEXT: v_writelane_b32 v20, s51, 9
+; SI-NEXT: v_writelane_b32 v20, s52, 10
+; SI-NEXT: v_writelane_b32 v20, s53, 11
+; SI-NEXT: v_writelane_b32 v20, s54, 12
+; SI-NEXT: v_writelane_b32 v20, s55, 13
+; SI-NEXT: v_writelane_b32 v20, s64, 14
+; SI-NEXT: v_writelane_b32 v20, s65, 15
+; SI-NEXT: v_writelane_b32 v20, s66, 16
+; SI-NEXT: v_writelane_b32 v20, s67, 17
+; SI-NEXT: v_writelane_b32 v20, s68, 18
+; SI-NEXT: v_writelane_b32 v20, s69, 19
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_writelane_b32 v20, s68, 20
+; SI-NEXT: v_writelane_b32 v20, s30, 20
; SI-NEXT: v_readfirstlane_b32 s44, v1
; SI-NEXT: v_readfirstlane_b32 s45, v2
; SI-NEXT: v_readfirstlane_b32 s42, v3
@@ -35605,7 +35605,7 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v17
; SI-NEXT: s_and_b64 s[46:47], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v18
-; SI-NEXT: v_writelane_b32 v20, s69, 21
+; SI-NEXT: v_writelane_b32 v20, s31, 21
; SI-NEXT: s_cbranch_scc0 .LBB25_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s38, s5, 16
@@ -35924,29 +35924,29 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v20, 20
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s69, v20, 21
-; SI-NEXT: v_readlane_b32 s68, v20, 20
-; SI-NEXT: v_readlane_b32 s67, v20, 19
-; SI-NEXT: v_readlane_b32 s66, v20, 18
-; SI-NEXT: v_readlane_b32 s65, v20, 17
-; SI-NEXT: v_readlane_b32 s64, v20, 16
-; SI-NEXT: v_readlane_b32 s55, v20, 15
-; SI-NEXT: v_readlane_b32 s54, v20, 14
-; SI-NEXT: v_readlane_b32 s53, v20, 13
-; SI-NEXT: v_readlane_b32 s52, v20, 12
-; SI-NEXT: v_readlane_b32 s51, v20, 11
-; SI-NEXT: v_readlane_b32 s50, v20, 10
-; SI-NEXT: v_readlane_b32 s49, v20, 9
-; SI-NEXT: v_readlane_b32 s48, v20, 8
-; SI-NEXT: v_readlane_b32 s39, v20, 7
-; SI-NEXT: v_readlane_b32 s38, v20, 6
-; SI-NEXT: v_readlane_b32 s37, v20, 5
-; SI-NEXT: v_readlane_b32 s36, v20, 4
-; SI-NEXT: v_readlane_b32 s35, v20, 3
-; SI-NEXT: v_readlane_b32 s34, v20, 2
-; SI-NEXT: v_readlane_b32 s31, v20, 1
-; SI-NEXT: v_readlane_b32 s30, v20, 0
+; SI-NEXT: v_readlane_b32 s31, v20, 21
+; SI-NEXT: v_readlane_b32 s69, v20, 19
+; SI-NEXT: v_readlane_b32 s68, v20, 18
+; SI-NEXT: v_readlane_b32 s67, v20, 17
+; SI-NEXT: v_readlane_b32 s66, v20, 16
+; SI-NEXT: v_readlane_b32 s65, v20, 15
+; SI-NEXT: v_readlane_b32 s64, v20, 14
+; SI-NEXT: v_readlane_b32 s55, v20, 13
+; SI-NEXT: v_readlane_b32 s54, v20, 12
+; SI-NEXT: v_readlane_b32 s53, v20, 11
+; SI-NEXT: v_readlane_b32 s52, v20, 10
+; SI-NEXT: v_readlane_b32 s51, v20, 9
+; SI-NEXT: v_readlane_b32 s50, v20, 8
+; SI-NEXT: v_readlane_b32 s49, v20, 7
+; SI-NEXT: v_readlane_b32 s48, v20, 6
+; SI-NEXT: v_readlane_b32 s39, v20, 5
+; SI-NEXT: v_readlane_b32 s38, v20, 4
+; SI-NEXT: v_readlane_b32 s37, v20, 3
+; SI-NEXT: v_readlane_b32 s36, v20, 2
+; SI-NEXT: v_readlane_b32 s35, v20, 1
+; SI-NEXT: v_readlane_b32 s34, v20, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
@@ -44360,43 +44360,43 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_writelane_b32 v63, s30, 0
-; SI-NEXT: v_writelane_b32 v63, s31, 1
-; SI-NEXT: v_writelane_b32 v63, s34, 2
-; SI-NEXT: v_writelane_b32 v63, s35, 3
-; SI-NEXT: v_writelane_b32 v63, s36, 4
-; SI-NEXT: v_writelane_b32 v63, s37, 5
-; SI-NEXT: v_writelane_b32 v63, s38, 6
-; SI-NEXT: v_writelane_b32 v63, s39, 7
-; SI-NEXT: v_writelane_b32 v63, s48, 8
-; SI-NEXT: v_writelane_b32 v63, s49, 9
-; SI-NEXT: v_writelane_b32 v63, s50, 10
-; SI-NEXT: v_writelane_b32 v63, s51, 11
-; SI-NEXT: v_writelane_b32 v63, s52, 12
-; SI-NEXT: v_writelane_b32 v63, s53, 13
-; SI-NEXT: v_writelane_b32 v63, s54, 14
-; SI-NEXT: v_writelane_b32 v63, s55, 15
-; SI-NEXT: v_writelane_b32 v63, s64, 16
-; SI-NEXT: v_writelane_b32 v63, s65, 17
-; SI-NEXT: v_writelane_b32 v63, s66, 18
-; SI-NEXT: v_writelane_b32 v63, s67, 19
-; SI-NEXT: v_writelane_b32 v63, s68, 20
-; SI-NEXT: v_writelane_b32 v63, s69, 21
-; SI-NEXT: v_writelane_b32 v63, s70, 22
-; SI-NEXT: v_writelane_b32 v63, s71, 23
-; SI-NEXT: v_writelane_b32 v63, s80, 24
-; SI-NEXT: v_writelane_b32 v63, s81, 25
-; SI-NEXT: v_writelane_b32 v63, s82, 26
-; SI-NEXT: v_writelane_b32 v63, s83, 27
-; SI-NEXT: v_writelane_b32 v63, s84, 28
-; SI-NEXT: v_writelane_b32 v63, s85, 29
-; SI-NEXT: v_writelane_b32 v63, s86, 30
-; SI-NEXT: v_writelane_b32 v63, s87, 31
-; SI-NEXT: v_writelane_b32 v63, s96, 32
-; SI-NEXT: v_writelane_b32 v63, s97, 33
-; SI-NEXT: v_writelane_b32 v63, s98, 34
+; SI-NEXT: v_writelane_b32 v63, s34, 0
+; SI-NEXT: v_writelane_b32 v63, s35, 1
+; SI-NEXT: v_writelane_b32 v63, s36, 2
+; SI-NEXT: v_writelane_b32 v63, s37, 3
+; SI-NEXT: v_writelane_b32 v63, s38, 4
+; SI-NEXT: v_writelane_b32 v63, s39, 5
+; SI-NEXT: v_writelane_b32 v63, s48, 6
+; SI-NEXT: v_writelane_b32 v63, s49, 7
+; SI-NEXT: v_writelane_b32 v63, s50, 8
+; SI-NEXT: v_writelane_b32 v63, s51, 9
+; SI-NEXT: v_writelane_b32 v63, s52, 10
+; SI-NEXT: v_writelane_b32 v63, s53, 11
+; SI-NEXT: v_writelane_b32 v63, s54, 12
+; SI-NEXT: v_writelane_b32 v63, s55, 13
+; SI-NEXT: v_writelane_b32 v63, s64, 14
+; SI-NEXT: v_writelane_b32 v63, s65, 15
+; SI-NEXT: v_writelane_b32 v63, s66, 16
+; SI-NEXT: v_writelane_b32 v63, s67, 17
+; SI-NEXT: v_writelane_b32 v63, s68, 18
+; SI-NEXT: v_writelane_b32 v63, s69, 19
+; SI-NEXT: v_writelane_b32 v63, s70, 20
+; SI-NEXT: v_writelane_b32 v63, s71, 21
+; SI-NEXT: v_writelane_b32 v63, s80, 22
+; SI-NEXT: v_writelane_b32 v63, s81, 23
+; SI-NEXT: v_writelane_b32 v63, s82, 24
+; SI-NEXT: v_writelane_b32 v63, s83, 25
+; SI-NEXT: v_writelane_b32 v63, s84, 26
+; SI-NEXT: v_writelane_b32 v63, s85, 27
+; SI-NEXT: v_writelane_b32 v63, s86, 28
+; SI-NEXT: v_writelane_b32 v63, s87, 29
+; SI-NEXT: v_writelane_b32 v63, s96, 30
+; SI-NEXT: v_writelane_b32 v63, s97, 31
+; SI-NEXT: v_writelane_b32 v63, s98, 32
+; SI-NEXT: v_writelane_b32 v63, s99, 33
+; SI-NEXT: v_writelane_b32 v63, s30, 34
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_writelane_b32 v63, s99, 35
+; SI-NEXT: v_writelane_b32 v63, s31, 35
; SI-NEXT: v_readfirstlane_b32 s44, v1
; SI-NEXT: v_readfirstlane_b32 s45, v2
; SI-NEXT: v_readfirstlane_b32 s42, v3
@@ -45563,42 +45563,42 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_readlane_b32 s99, v63, 35
-; SI-NEXT: v_readlane_b32 s98, v63, 34
-; SI-NEXT: v_readlane_b32 s97, v63, 33
-; SI-NEXT: v_readlane_b32 s96, v63, 32
-; SI-NEXT: v_readlane_b32 s87, v63, 31
-; SI-NEXT: v_readlane_b32 s86, v63, 30
-; SI-NEXT: v_readlane_b32 s85, v63, 29
-; SI-NEXT: v_readlane_b32 s84, v63, 28
-; SI-NEXT: v_readlane_b32 s83, v63, 27
-; SI-NEXT: v_readlane_b32 s82, v63, 26
-; SI-NEXT: v_readlane_b32 s81, v63, 25
-; SI-NEXT: v_readlane_b32 s80, v63, 24
-; SI-NEXT: v_readlane_b32 s71, v63, 23
-; SI-NEXT: v_readlane_b32 s70, v63, 22
-; SI-NEXT: v_readlane_b32 s69, v63, 21
-; SI-NEXT: v_readlane_b32 s68, v63, 20
-; SI-NEXT: v_readlane_b32 s67, v63, 19
-; SI-NEXT: v_readlane_b32 s66, v63, 18
-; SI-NEXT: v_readlane_b32 s65, v63, 17
-; SI-NEXT: v_readlane_b32 s64, v63, 16
-; SI-NEXT: v_readlane_b32 s55, v63, 15
-; SI-NEXT: v_readlane_b32 s54, v63, 14
-; SI-NEXT: v_readlane_b32 s53, v63, 13
-; SI-NEXT: v_readlane_b32 s52, v63, 12
-; SI-NEXT: v_readlane_b32 s51, v63, 11
-; SI-NEXT: v_readlane_b32 s50, v63, 10
-; SI-NEXT: v_readlane_b32 s49, v63, 9
-; SI-NEXT: v_readlane_b32 s48, v63, 8
-; SI-NEXT: v_readlane_b32 s39, v63, 7
-; SI-NEXT: v_readlane_b32 s38, v63, 6
-; SI-NEXT: v_readlane_b32 s37, v63, 5
-; SI-NEXT: v_readlane_b32 s36, v63, 4
-; SI-NEXT: v_readlane_b32 s35, v63, 3
-; SI-NEXT: v_readlane_b32 s34, v63, 2
-; SI-NEXT: v_readlane_b32 s31, v63, 1
-; SI-NEXT: v_readlane_b32 s30, v63, 0
+; SI-NEXT: v_readlane_b32 s30, v63, 34
+; SI-NEXT: v_readlane_b32 s31, v63, 35
+; SI-NEXT: v_readlane_b32 s99, v63, 33
+; SI-NEXT: v_readlane_b32 s98, v63, 32
+; SI-NEXT: v_readlane_b32 s97, v63, 31
+; SI-NEXT: v_readlane_b32 s96, v63, 30
+; SI-NEXT: v_readlane_b32 s87, v63, 29
+; SI-NEXT: v_readlane_b32 s86, v63, 28
+; SI-NEXT: v_readlane_b32 s85, v63, 27
+; SI-NEXT: v_readlane_b32 s84, v63, 26
+; SI-NEXT: v_readlane_b32 s83, v63, 25
+; SI-NEXT: v_readlane_b32 s82, v63, 24
+; SI-NEXT: v_readlane_b32 s81, v63, 23
+; SI-NEXT: v_readlane_b32 s80, v63, 22
+; SI-NEXT: v_readlane_b32 s71, v63, 21
+; SI-NEXT: v_readlane_b32 s70, v63, 20
+; SI-NEXT: v_readlane_b32 s69, v63, 19
+; SI-NEXT: v_readlane_b32 s68, v63, 18
+; SI-NEXT: v_readlane_b32 s67, v63, 17
+; SI-NEXT: v_readlane_b32 s66, v63, 16
+; SI-NEXT: v_readlane_b32 s65, v63, 15
+; SI-NEXT: v_readlane_b32 s64, v63, 14
+; SI-NEXT: v_readlane_b32 s55, v63, 13
+; SI-NEXT: v_readlane_b32 s54, v63, 12
+; SI-NEXT: v_readlane_b32 s53, v63, 11
+; SI-NEXT: v_readlane_b32 s52, v63, 10
+; SI-NEXT: v_readlane_b32 s51, v63, 9
+; SI-NEXT: v_readlane_b32 s50, v63, 8
+; SI-NEXT: v_readlane_b32 s49, v63, 7
+; SI-NEXT: v_readlane_b32 s48, v63, 6
+; SI-NEXT: v_readlane_b32 s39, v63, 5
+; SI-NEXT: v_readlane_b32 s38, v63, 4
+; SI-NEXT: v_readlane_b32 s37, v63, 3
+; SI-NEXT: v_readlane_b32 s36, v63, 2
+; SI-NEXT: v_readlane_b32 s35, v63, 1
+; SI-NEXT: v_readlane_b32 s34, v63, 0
; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v22
; SI-NEXT: v_and_b32_e32 v22, 0xff, v52
@@ -46098,39 +46098,39 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v63, s30, 0
-; VI-NEXT: v_writelane_b32 v63, s31, 1
-; VI-NEXT: v_writelane_b32 v63, s34, 2
-; VI-NEXT: v_writelane_b32 v63, s35, 3
-; VI-NEXT: v_writelane_b32 v63, s36, 4
-; VI-NEXT: v_writelane_b32 v63, s37, 5
-; VI-NEXT: v_writelane_b32 v63, s38, 6
-; VI-NEXT: v_writelane_b32 v63, s39, 7
-; VI-NEXT: v_writelane_b32 v63, s48, 8
-; VI-NEXT: v_writelane_b32 v63, s49, 9
-; VI-NEXT: v_writelane_b32 v63, s50, 10
-; VI-NEXT: v_writelane_b32 v63, s51, 11
-; VI-NEXT: v_writelane_b32 v63, s52, 12
-; VI-NEXT: v_writelane_b32 v63, s53, 13
-; VI-NEXT: v_writelane_b32 v63, s54, 14
-; VI-NEXT: v_writelane_b32 v63, s55, 15
-; VI-NEXT: v_writelane_b32 v63, s64, 16
-; VI-NEXT: v_writelane_b32 v63, s65, 17
-; VI-NEXT: v_writelane_b32 v63, s66, 18
-; VI-NEXT: v_writelane_b32 v63, s67, 19
-; VI-NEXT: v_writelane_b32 v63, s68, 20
-; VI-NEXT: v_writelane_b32 v63, s69, 21
-; VI-NEXT: v_writelane_b32 v63, s70, 22
-; VI-NEXT: v_writelane_b32 v63, s71, 23
-; VI-NEXT: v_writelane_b32 v63, s80, 24
-; VI-NEXT: v_writelane_b32 v63, s81, 25
-; VI-NEXT: v_writelane_b32 v63, s82, 26
-; VI-NEXT: v_writelane_b32 v63, s83, 27
-; VI-NEXT: v_writelane_b32 v63, s84, 28
-; VI-NEXT: v_writelane_b32 v63, s85, 29
-; VI-NEXT: v_writelane_b32 v63, s86, 30
+; VI-NEXT: v_writelane_b32 v63, s34, 0
+; VI-NEXT: v_writelane_b32 v63, s35, 1
+; VI-NEXT: v_writelane_b32 v63, s36, 2
+; VI-NEXT: v_writelane_b32 v63, s37, 3
+; VI-NEXT: v_writelane_b32 v63, s38, 4
+; VI-NEXT: v_writelane_b32 v63, s39, 5
+; VI-NEXT: v_writelane_b32 v63, s48, 6
+; VI-NEXT: v_writelane_b32 v63, s49, 7
+; VI-NEXT: v_writelane_b32 v63, s50, 8
+; VI-NEXT: v_writelane_b32 v63, s51, 9
+; VI-NEXT: v_writelane_b32 v63, s52, 10
+; VI-NEXT: v_writelane_b32 v63, s53, 11
+; VI-NEXT: v_writelane_b32 v63, s54, 12
+; VI-NEXT: v_writelane_b32 v63, s55, 13
+; VI-NEXT: v_writelane_b32 v63, s64, 14
+; VI-NEXT: v_writelane_b32 v63, s65, 15
+; VI-NEXT: v_writelane_b32 v63, s66, 16
+; VI-NEXT: v_writelane_b32 v63, s67, 17
+; VI-NEXT: v_writelane_b32 v63, s68, 18
+; VI-NEXT: v_writelane_b32 v63, s69, 19
+; VI-NEXT: v_writelane_b32 v63, s70, 20
+; VI-NEXT: v_writelane_b32 v63, s71, 21
+; VI-NEXT: v_writelane_b32 v63, s80, 22
+; VI-NEXT: v_writelane_b32 v63, s81, 23
+; VI-NEXT: v_writelane_b32 v63, s82, 24
+; VI-NEXT: v_writelane_b32 v63, s83, 25
+; VI-NEXT: v_writelane_b32 v63, s84, 26
+; VI-NEXT: v_writelane_b32 v63, s85, 27
+; VI-NEXT: v_writelane_b32 v63, s86, 28
+; VI-NEXT: v_writelane_b32 v63, s87, 29
+; VI-NEXT: v_writelane_b32 v63, s30, 30
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; VI-NEXT: v_writelane_b32 v63, s87, 31
+; VI-NEXT: v_writelane_b32 v63, s31, 31
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: v_readfirstlane_b32 s45, v2
; VI-NEXT: v_readfirstlane_b32 s42, v3
@@ -47018,38 +47018,38 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: v_lshlrev_b32_e32 v23, 8, v50
; VI-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 8, v36
-; VI-NEXT: v_readlane_b32 s87, v63, 31
-; VI-NEXT: v_readlane_b32 s86, v63, 30
-; VI-NEXT: v_readlane_b32 s85, v63, 29
-; VI-NEXT: v_readlane_b32 s84, v63, 28
-; VI-NEXT: v_readlane_b32 s83, v63, 27
-; VI-NEXT: v_readlane_b32 s82, v63, 26
-; VI-NEXT: v_readlane_b32 s81, v63, 25
-; VI-NEXT: v_readlane_b32 s80, v63, 24
-; VI-NEXT: v_readlane_b32 s71, v63, 23
-; VI-NEXT: v_readlane_b32 s70, v63, 22
-; VI-NEXT: v_readlane_b32 s69, v63, 21
-; VI-NEXT: v_readlane_b32 s68, v63, 20
-; VI-NEXT: v_readlane_b32 s67, v63, 19
-; VI-NEXT: v_readlane_b32 s66, v63, 18
-; VI-NEXT: v_readlane_b32 s65, v63, 17
-; VI-NEXT: v_readlane_b32 s64, v63, 16
-; VI-NEXT: v_readlane_b32 s55, v63, 15
-; VI-NEXT: v_readlane_b32 s54, v63, 14
-; VI-NEXT: v_readlane_b32 s53, v63, 13
-; VI-NEXT: v_readlane_b32 s52, v63, 12
-; VI-NEXT: v_readlane_b32 s51, v63, 11
-; VI-NEXT: v_readlane_b32 s50, v63, 10
-; VI-NEXT: v_readlane_b32 s49, v63, 9
-; VI-NEXT: v_readlane_b32 s48, v63, 8
-; VI-NEXT: v_readlane_b32 s39, v63, 7
-; VI-NEXT: v_readlane_b32 s38, v63, 6
-; VI-NEXT: v_readlane_b32 s37, v63, 5
-; VI-NEXT: v_readlane_b32 s36, v63, 4
-; VI-NEXT: v_readlane_b32 s35, v63, 3
-; VI-NEXT: v_readlane_b32 s34, v63, 2
-; VI-NEXT: v_readlane_b32 s31, v63, 1
-; VI-NEXT: v_readlane_b32 s30, v63, 0
+; VI-NEXT: v_readlane_b32 s30, v63, 30
+; VI-NEXT: v_readlane_b32 s31, v63, 31
+; VI-NEXT: v_readlane_b32 s87, v63, 29
+; VI-NEXT: v_readlane_b32 s86, v63, 28
+; VI-NEXT: v_readlane_b32 s85, v63, 27
+; VI-NEXT: v_readlane_b32 s84, v63, 26
+; VI-NEXT: v_readlane_b32 s83, v63, 25
+; VI-NEXT: v_readlane_b32 s82, v63, 24
+; VI-NEXT: v_readlane_b32 s81, v63, 23
+; VI-NEXT: v_readlane_b32 s80, v63, 22
+; VI-NEXT: v_readlane_b32 s71, v63, 21
+; VI-NEXT: v_readlane_b32 s70, v63, 20
+; VI-NEXT: v_readlane_b32 s69, v63, 19
+; VI-NEXT: v_readlane_b32 s68, v63, 18
+; VI-NEXT: v_readlane_b32 s67, v63, 17
+; VI-NEXT: v_readlane_b32 s66, v63, 16
+; VI-NEXT: v_readlane_b32 s65, v63, 15
+; VI-NEXT: v_readlane_b32 s64, v63, 14
+; VI-NEXT: v_readlane_b32 s55, v63, 13
+; VI-NEXT: v_readlane_b32 s54, v63, 12
+; VI-NEXT: v_readlane_b32 s53, v63, 11
+; VI-NEXT: v_readlane_b32 s52, v63, 10
+; VI-NEXT: v_readlane_b32 s51, v63, 9
+; VI-NEXT: v_readlane_b32 s50, v63, 8
+; VI-NEXT: v_readlane_b32 s49, v63, 7
+; VI-NEXT: v_readlane_b32 s48, v63, 6
+; VI-NEXT: v_readlane_b32 s39, v63, 5
+; VI-NEXT: v_readlane_b32 s38, v63, 4
+; VI-NEXT: v_readlane_b32 s37, v63, 3
+; VI-NEXT: v_readlane_b32 s36, v63, 2
+; VI-NEXT: v_readlane_b32 s35, v63, 1
+; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_or_b32_sdwa v24, v25, v24 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
@@ -47369,43 +47369,43 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v63, s30, 0
-; GFX9-NEXT: v_writelane_b32 v63, s31, 1
-; GFX9-NEXT: v_writelane_b32 v63, s34, 2
-; GFX9-NEXT: v_writelane_b32 v63, s35, 3
-; GFX9-NEXT: v_writelane_b32 v63, s36, 4
-; GFX9-NEXT: v_writelane_b32 v63, s37, 5
-; GFX9-NEXT: v_writelane_b32 v63, s38, 6
-; GFX9-NEXT: v_writelane_b32 v63, s39, 7
-; GFX9-NEXT: v_writelane_b32 v63, s48, 8
-; GFX9-NEXT: v_writelane_b32 v63, s49, 9
-; GFX9-NEXT: v_writelane_b32 v63, s50, 10
-; GFX9-NEXT: v_writelane_b32 v63, s51, 11
-; GFX9-NEXT: v_writelane_b32 v63, s52, 12
-; GFX9-NEXT: v_writelane_b32 v63, s53, 13
-; GFX9-NEXT: v_writelane_b32 v63, s54, 14
-; GFX9-NEXT: v_writelane_b32 v63, s55, 15
-; GFX9-NEXT: v_writelane_b32 v63, s64, 16
-; GFX9-NEXT: v_writelane_b32 v63, s65, 17
-; GFX9-NEXT: v_writelane_b32 v63, s66, 18
-; GFX9-NEXT: v_writelane_b32 v63, s67, 19
-; GFX9-NEXT: v_writelane_b32 v63, s68, 20
-; GFX9-NEXT: v_writelane_b32 v63, s69, 21
-; GFX9-NEXT: v_writelane_b32 v63, s70, 22
-; GFX9-NEXT: v_writelane_b32 v63, s71, 23
-; GFX9-NEXT: v_writelane_b32 v63, s80, 24
-; GFX9-NEXT: v_writelane_b32 v63, s81, 25
-; GFX9-NEXT: v_writelane_b32 v63, s82, 26
-; GFX9-NEXT: v_writelane_b32 v63, s83, 27
-; GFX9-NEXT: v_writelane_b32 v63, s84, 28
-; GFX9-NEXT: v_writelane_b32 v63, s85, 29
-; GFX9-NEXT: v_writelane_b32 v63, s86, 30
-; GFX9-NEXT: v_writelane_b32 v63, s87, 31
-; GFX9-NEXT: v_writelane_b32 v63, s96, 32
-; GFX9-NEXT: v_writelane_b32 v63, s97, 33
-; GFX9-NEXT: v_writelane_b32 v63, s98, 34
+; GFX9-NEXT: v_writelane_b32 v63, s34, 0
+; GFX9-NEXT: v_writelane_b32 v63, s35, 1
+; GFX9-NEXT: v_writelane_b32 v63, s36, 2
+; GFX9-NEXT: v_writelane_b32 v63, s37, 3
+; GFX9-NEXT: v_writelane_b32 v63, s38, 4
+; GFX9-NEXT: v_writelane_b32 v63, s39, 5
+; GFX9-NEXT: v_writelane_b32 v63, s48, 6
+; GFX9-NEXT: v_writelane_b32 v63, s49, 7
+; GFX9-NEXT: v_writelane_b32 v63, s50, 8
+; GFX9-NEXT: v_writelane_b32 v63, s51, 9
+; GFX9-NEXT: v_writelane_b32 v63, s52, 10
+; GFX9-NEXT: v_writelane_b32 v63, s53, 11
+; GFX9-NEXT: v_writelane_b32 v63, s54, 12
+; GFX9-NEXT: v_writelane_b32 v63, s55, 13
+; GFX9-NEXT: v_writelane_b32 v63, s64, 14
+; GFX9-NEXT: v_writelane_b32 v63, s65, 15
+; GFX9-NEXT: v_writelane_b32 v63, s66, 16
+; GFX9-NEXT: v_writelane_b32 v63, s67, 17
+; GFX9-NEXT: v_writelane_b32 v63, s68, 18
+; GFX9-NEXT: v_writelane_b32 v63, s69, 19
+; GFX9-NEXT: v_writelane_b32 v63, s70, 20
+; GFX9-NEXT: v_writelane_b32 v63, s71, 21
+; GFX9-NEXT: v_writelane_b32 v63, s80, 22
+; GFX9-NEXT: v_writelane_b32 v63, s81, 23
+; GFX9-NEXT: v_writelane_b32 v63, s82, 24
+; GFX9-NEXT: v_writelane_b32 v63, s83, 25
+; GFX9-NEXT: v_writelane_b32 v63, s84, 26
+; GFX9-NEXT: v_writelane_b32 v63, s85, 27
+; GFX9-NEXT: v_writelane_b32 v63, s86, 28
+; GFX9-NEXT: v_writelane_b32 v63, s87, 29
+; GFX9-NEXT: v_writelane_b32 v63, s96, 30
+; GFX9-NEXT: v_writelane_b32 v63, s97, 31
+; GFX9-NEXT: v_writelane_b32 v63, s98, 32
+; GFX9-NEXT: v_writelane_b32 v63, s99, 33
+; GFX9-NEXT: v_writelane_b32 v63, s30, 34
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; GFX9-NEXT: v_writelane_b32 v63, s99, 35
+; GFX9-NEXT: v_writelane_b32 v63, s31, 35
; GFX9-NEXT: v_readfirstlane_b32 s44, v1
; GFX9-NEXT: v_readfirstlane_b32 s45, v2
; GFX9-NEXT: v_readfirstlane_b32 s42, v3
@@ -48291,42 +48291,42 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 8, v49
-; GFX9-NEXT: v_readlane_b32 s99, v63, 35
-; GFX9-NEXT: v_readlane_b32 s98, v63, 34
-; GFX9-NEXT: v_readlane_b32 s97, v63, 33
-; GFX9-NEXT: v_readlane_b32 s96, v63, 32
-; GFX9-NEXT: v_readlane_b32 s87, v63, 31
-; GFX9-NEXT: v_readlane_b32 s86, v63, 30
-; GFX9-NEXT: v_readlane_b32 s85, v63, 29
-; GFX9-NEXT: v_readlane_b32 s84, v63, 28
-; GFX9-NEXT: v_readlane_b32 s83, v63, 27
-; GFX9-NEXT: v_readlane_b32 s82, v63, 26
-; GFX9-NEXT: v_readlane_b32 s81, v63, 25
-; GFX9-NEXT: v_readlane_b32 s80, v63, 24
-; GFX9-NEXT: v_readlane_b32 s71, v63, 23
-; GFX9-NEXT: v_readlane_b32 s70, v63, 22
-; GFX9-NEXT: v_readlane_b32 s69, v63, 21
-; GFX9-NEXT: v_readlane_b32 s68, v63, 20
-; GFX9-NEXT: v_readlane_b32 s67, v63, 19
-; GFX9-NEXT: v_readlane_b32 s66, v63, 18
-; GFX9-NEXT: v_readlane_b32 s65, v63, 17
-; GFX9-NEXT: v_readlane_b32 s64, v63, 16
-; GFX9-NEXT: v_readlane_b32 s55, v63, 15
-; GFX9-NEXT: v_readlane_b32 s54, v63, 14
-; GFX9-NEXT: v_readlane_b32 s53, v63, 13
-; GFX9-NEXT: v_readlane_b32 s52, v63, 12
-; GFX9-NEXT: v_readlane_b32 s51, v63, 11
-; GFX9-NEXT: v_readlane_b32 s50, v63, 10
-; GFX9-NEXT: v_readlane_b32 s49, v63, 9
-; GFX9-NEXT: v_readlane_b32 s48, v63, 8
-; GFX9-NEXT: v_readlane_b32 s39, v63, 7
-; GFX9-NEXT: v_readlane_b32 s38, v63, 6
-; GFX9-NEXT: v_readlane_b32 s37, v63, 5
-; GFX9-NEXT: v_readlane_b32 s36, v63, 4
-; GFX9-NEXT: v_readlane_b32 s35, v63, 3
-; GFX9-NEXT: v_readlane_b32 s34, v63, 2
-; GFX9-NEXT: v_readlane_b32 s31, v63, 1
-; GFX9-NEXT: v_readlane_b32 s30, v63, 0
+; GFX9-NEXT: v_readlane_b32 s30, v63, 34
+; GFX9-NEXT: v_readlane_b32 s31, v63, 35
+; GFX9-NEXT: v_readlane_b32 s99, v63, 33
+; GFX9-NEXT: v_readlane_b32 s98, v63, 32
+; GFX9-NEXT: v_readlane_b32 s97, v63, 31
+; GFX9-NEXT: v_readlane_b32 s96, v63, 30
+; GFX9-NEXT: v_readlane_b32 s87, v63, 29
+; GFX9-NEXT: v_readlane_b32 s86, v63, 28
+; GFX9-NEXT: v_readlane_b32 s85, v63, 27
+; GFX9-NEXT: v_readlane_b32 s84, v63, 26
+; GFX9-NEXT: v_readlane_b32 s83, v63, 25
+; GFX9-NEXT: v_readlane_b32 s82, v63, 24
+; GFX9-NEXT: v_readlane_b32 s81, v63, 23
+; GFX9-NEXT: v_readlane_b32 s80, v63, 22
+; GFX9-NEXT: v_readlane_b32 s71, v63, 21
+; GFX9-NEXT: v_readlane_b32 s70, v63, 20
+; GFX9-NEXT: v_readlane_b32 s69, v63, 19
+; GFX9-NEXT: v_readlane_b32 s68, v63, 18
+; GFX9-NEXT: v_readlane_b32 s67, v63, 17
+; GFX9-NEXT: v_readlane_b32 s66, v63, 16
+; GFX9-NEXT: v_readlane_b32 s65, v63, 15
+; GFX9-NEXT: v_readlane_b32 s64, v63, 14
+; GFX9-NEXT: v_readlane_b32 s55, v63, 13
+; GFX9-NEXT: v_readlane_b32 s54, v63, 12
+; GFX9-NEXT: v_readlane_b32 s53, v63, 11
+; GFX9-NEXT: v_readlane_b32 s52, v63, 10
+; GFX9-NEXT: v_readlane_b32 s51, v63, 9
+; GFX9-NEXT: v_readlane_b32 s50, v63, 8
+; GFX9-NEXT: v_readlane_b32 s49, v63, 7
+; GFX9-NEXT: v_readlane_b32 s48, v63, 6
+; GFX9-NEXT: v_readlane_b32 s39, v63, 5
+; GFX9-NEXT: v_readlane_b32 s38, v63, 4
+; GFX9-NEXT: v_readlane_b32 s37, v63, 3
+; GFX9-NEXT: v_readlane_b32 s36, v63, 2
+; GFX9-NEXT: v_readlane_b32 s35, v63, 1
+; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v15, v35, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
@@ -48652,33 +48652,33 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v75, s30, 0
-; GFX11-NEXT: v_writelane_b32 v76, s96, 0
+; GFX11-NEXT: v_writelane_b32 v75, s34, 0
+; GFX11-NEXT: v_writelane_b32 v76, s98, 0
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
; GFX11-NEXT: v_readfirstlane_b32 s40, v1
; GFX11-NEXT: v_readfirstlane_b32 s41, v2
-; GFX11-NEXT: v_writelane_b32 v75, s31, 1
-; GFX11-NEXT: v_writelane_b32 v76, s97, 1
+; GFX11-NEXT: v_writelane_b32 v75, s35, 1
+; GFX11-NEXT: v_writelane_b32 v76, s99, 1
; GFX11-NEXT: v_readfirstlane_b32 s14, v3
; GFX11-NEXT: v_readfirstlane_b32 s15, v4
; GFX11-NEXT: v_readfirstlane_b32 s4, v5
-; GFX11-NEXT: v_writelane_b32 v75, s34, 2
-; GFX11-NEXT: v_writelane_b32 v76, s98, 2
+; GFX11-NEXT: v_writelane_b32 v75, s36, 2
+; GFX11-NEXT: v_writelane_b32 v76, s100, 2
; GFX11-NEXT: v_readfirstlane_b32 s5, v6
; GFX11-NEXT: v_readfirstlane_b32 s6, v7
; GFX11-NEXT: v_readfirstlane_b32 s7, v8
-; GFX11-NEXT: v_writelane_b32 v75, s35, 3
-; GFX11-NEXT: v_writelane_b32 v76, s99, 3
+; GFX11-NEXT: v_writelane_b32 v75, s37, 3
+; GFX11-NEXT: v_writelane_b32 v76, s101, 3
; GFX11-NEXT: v_readfirstlane_b32 s8, v9
; GFX11-NEXT: v_readfirstlane_b32 s9, v10
; GFX11-NEXT: v_readfirstlane_b32 s10, v11
-; GFX11-NEXT: v_writelane_b32 v75, s36, 4
-; GFX11-NEXT: v_writelane_b32 v76, s100, 4
+; GFX11-NEXT: v_writelane_b32 v75, s38, 4
+; GFX11-NEXT: v_writelane_b32 v76, s102, 4
; GFX11-NEXT: v_readfirstlane_b32 s11, v12
; GFX11-NEXT: v_readfirstlane_b32 s12, v13
; GFX11-NEXT: v_readfirstlane_b32 s13, v14
-; GFX11-NEXT: v_writelane_b32 v75, s37, 5
-; GFX11-NEXT: v_writelane_b32 v76, s101, 5
+; GFX11-NEXT: v_writelane_b32 v75, s39, 5
+; GFX11-NEXT: v_writelane_b32 v76, s103, 5
; GFX11-NEXT: s_mov_b32 vcc_hi, 0
; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
; GFX11-NEXT: s_clause 0x12
@@ -48701,37 +48701,37 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:8
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:4
; GFX11-NEXT: scratch_store_b32 off, v74, s32
-; GFX11-NEXT: v_writelane_b32 v75, s38, 6
-; GFX11-NEXT: v_writelane_b32 v76, s102, 6
+; GFX11-NEXT: v_writelane_b32 v75, s48, 6
+; GFX11-NEXT: v_writelane_b32 v76, s104, 6
; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane
; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane
-; GFX11-NEXT: v_writelane_b32 v75, s39, 7
-; GFX11-NEXT: v_writelane_b32 v76, s103, 7
-; GFX11-NEXT: v_writelane_b32 v75, s48, 8
-; GFX11-NEXT: v_writelane_b32 v76, s104, 8
-; GFX11-NEXT: v_writelane_b32 v75, s49, 9
-; GFX11-NEXT: v_writelane_b32 v75, s50, 10
-; GFX11-NEXT: v_writelane_b32 v75, s51, 11
-; GFX11-NEXT: v_writelane_b32 v75, s52, 12
-; GFX11-NEXT: v_writelane_b32 v75, s53, 13
-; GFX11-NEXT: v_writelane_b32 v75, s54, 14
-; GFX11-NEXT: v_writelane_b32 v75, s55, 15
-; GFX11-NEXT: v_writelane_b32 v75, s64, 16
-; GFX11-NEXT: v_writelane_b32 v75, s65, 17
-; GFX11-NEXT: v_writelane_b32 v75, s66, 18
-; GFX11-NEXT: v_writelane_b32 v75, s67, 19
-; GFX11-NEXT: v_writelane_b32 v75, s68, 20
-; GFX11-NEXT: v_writelane_b32 v75, s69, 21
-; GFX11-NEXT: v_writelane_b32 v75, s70, 22
-; GFX11-NEXT: v_writelane_b32 v75, s71, 23
-; GFX11-NEXT: v_writelane_b32 v75, s80, 24
-; GFX11-NEXT: v_writelane_b32 v75, s81, 25
-; GFX11-NEXT: v_writelane_b32 v75, s82, 26
-; GFX11-NEXT: v_writelane_b32 v75, s83, 27
-; GFX11-NEXT: v_writelane_b32 v75, s84, 28
-; GFX11-NEXT: v_writelane_b32 v75, s85, 29
-; GFX11-NEXT: v_writelane_b32 v75, s86, 30
-; GFX11-NEXT: v_writelane_b32 v75, s87, 31
+; GFX11-NEXT: v_writelane_b32 v75, s49, 7
+; GFX11-NEXT: v_writelane_b32 v76, s30, 7
+; GFX11-NEXT: v_writelane_b32 v75, s50, 8
+; GFX11-NEXT: v_writelane_b32 v76, s31, 8
+; GFX11-NEXT: v_writelane_b32 v75, s51, 9
+; GFX11-NEXT: v_writelane_b32 v75, s52, 10
+; GFX11-NEXT: v_writelane_b32 v75, s53, 11
+; GFX11-NEXT: v_writelane_b32 v75, s54, 12
+; GFX11-NEXT: v_writelane_b32 v75, s55, 13
+; GFX11-NEXT: v_writelane_b32 v75, s64, 14
+; GFX11-NEXT: v_writelane_b32 v75, s65, 15
+; GFX11-NEXT: v_writelane_b32 v75, s66, 16
+; GFX11-NEXT: v_writelane_b32 v75, s67, 17
+; GFX11-NEXT: v_writelane_b32 v75, s68, 18
+; GFX11-NEXT: v_writelane_b32 v75, s69, 19
+; GFX11-NEXT: v_writelane_b32 v75, s70, 20
+; GFX11-NEXT: v_writelane_b32 v75, s71, 21
+; GFX11-NEXT: v_writelane_b32 v75, s80, 22
+; GFX11-NEXT: v_writelane_b32 v75, s81, 23
+; GFX11-NEXT: v_writelane_b32 v75, s82, 24
+; GFX11-NEXT: v_writelane_b32 v75, s83, 25
+; GFX11-NEXT: v_writelane_b32 v75, s84, 26
+; GFX11-NEXT: v_writelane_b32 v75, s85, 27
+; GFX11-NEXT: v_writelane_b32 v75, s86, 28
+; GFX11-NEXT: v_writelane_b32 v75, s87, 29
+; GFX11-NEXT: v_writelane_b32 v75, s96, 30
+; GFX11-NEXT: v_writelane_b32 v75, s97, 31
; GFX11-NEXT: s_cbranch_scc0 .LBB37_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s13, 24
@@ -49621,47 +49621,47 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:64
; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:68
; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:72
-; GFX11-NEXT: v_readlane_b32 s104, v76, 8
-; GFX11-NEXT: v_readlane_b32 s103, v76, 7
-; GFX11-NEXT: v_readlane_b32 s102, v76, 6
-; GFX11-NEXT: v_readlane_b32 s101, v76, 5
-; GFX11-NEXT: v_readlane_b32 s100, v76, 4
-; GFX11-NEXT: v_readlane_b32 s99, v76, 3
-; GFX11-NEXT: v_readlane_b32 s98, v76, 2
-; GFX11-NEXT: v_readlane_b32 s97, v76, 1
-; GFX11-NEXT: v_readlane_b32 s96, v76, 0
-; GFX11-NEXT: v_readlane_b32 s87, v75, 31
-; GFX11-NEXT: v_readlane_b32 s86, v75, 30
-; GFX11-NEXT: v_readlane_b32 s85, v75, 29
-; GFX11-NEXT: v_readlane_b32 s84, v75, 28
-; GFX11-NEXT: v_readlane_b32 s83, v75, 27
-; GFX11-NEXT: v_readlane_b32 s82, v75, 26
-; GFX11-NEXT: v_readlane_b32 s81, v75, 25
-; GFX11-NEXT: v_readlane_b32 s80, v75, 24
-; GFX11-NEXT: v_readlane_b32 s71, v75, 23
-; GFX11-NEXT: v_readlane_b32 s70, v75, 22
-; GFX11-NEXT: v_readlane_b32 s69, v75, 21
-; GFX11-NEXT: v_readlane_b32 s68, v75, 20
-; GFX11-NEXT: v_readlane_b32 s67, v75, 19
-; GFX11-NEXT: v_readlane_b32 s66, v75, 18
-; GFX11-NEXT: v_readlane_b32 s65, v75, 17
-; GFX11-NEXT: v_readlane_b32 s64, v75, 16
-; GFX11-NEXT: v_readlane_b32 s55, v75, 15
-; GFX11-NEXT: v_readlane_b32 s54, v75, 14
-; GFX11-NEXT: v_readlane_b32 s53, v75, 13
-; GFX11-NEXT: v_readlane_b32 s52, v75, 12
-; GFX11-NEXT: v_readlane_b32 s51, v75, 11
-; GFX11-NEXT: v_readlane_b32 s50, v75, 10
-; GFX11-NEXT: v_readlane_b32 s49, v75, 9
-; GFX11-NEXT: v_readlane_b32 s48, v75, 8
-; GFX11-NEXT: v_readlane_b32 s39, v75, 7
-; GFX11-NEXT: v_readlane_b32 s38, v75, 6
-; GFX11-NEXT: v_readlane_b32 s37, v75, 5
-; GFX11-NEXT: v_readlane_b32 s36, v75, 4
-; GFX11-NEXT: v_readlane_b32 s35, v75, 3
-; GFX11-NEXT: v_readlane_b32 s34, v75, 2
-; GFX11-NEXT: v_readlane_b32 s31, v75, 1
-; GFX11-NEXT: v_readlane_b32 s30, v75, 0
+; GFX11-NEXT: v_readlane_b32 s30, v76, 7
+; GFX11-NEXT: v_readlane_b32 s31, v76, 8
+; GFX11-NEXT: v_readlane_b32 s104, v76, 6
+; GFX11-NEXT: v_readlane_b32 s103, v76, 5
+; GFX11-NEXT: v_readlane_b32 s102, v76, 4
+; GFX11-NEXT: v_readlane_b32 s101, v76, 3
+; GFX11-NEXT: v_readlane_b32 s100, v76, 2
+; GFX11-NEXT: v_readlane_b32 s99, v76, 1
+; GFX11-NEXT: v_readlane_b32 s98, v76, 0
+; GFX11-NEXT: v_readlane_b32 s97, v75, 31
+; GFX11-NEXT: v_readlane_b32 s96, v75, 30
+; GFX11-NEXT: v_readlane_b32 s87, v75, 29
+; GFX11-NEXT: v_readlane_b32 s86, v75, 28
+; GFX11-NEXT: v_readlane_b32 s85, v75, 27
+; GFX11-NEXT: v_readlane_b32 s84, v75, 26
+; GFX11-NEXT: v_readlane_b32 s83, v75, 25
+; GFX11-NEXT: v_readlane_b32 s82, v75, 24
+; GFX11-NEXT: v_readlane_b32 s81, v75, 23
+; GFX11-NEXT: v_readlane_b32 s80, v75, 22
+; GFX11-NEXT: v_readlane_b32 s71, v75, 21
+; GFX11-NEXT: v_readlane_b32 s70, v75, 20
+; GFX11-NEXT: v_readlane_b32 s69, v75, 19
+; GFX11-NEXT: v_readlane_b32 s68, v75, 18
+; GFX11-NEXT: v_readlane_b32 s67, v75, 17
+; GFX11-NEXT: v_readlane_b32 s66, v75, 16
+; GFX11-NEXT: v_readlane_b32 s65, v75, 15
+; GFX11-NEXT: v_readlane_b32 s64, v75, 14
+; GFX11-NEXT: v_readlane_b32 s55, v75, 13
+; GFX11-NEXT: v_readlane_b32 s54, v75, 12
+; GFX11-NEXT: v_readlane_b32 s53, v75, 11
+; GFX11-NEXT: v_readlane_b32 s52, v75, 10
+; GFX11-NEXT: v_readlane_b32 s51, v75, 9
+; GFX11-NEXT: v_readlane_b32 s50, v75, 8
+; GFX11-NEXT: v_readlane_b32 s49, v75, 7
+; GFX11-NEXT: v_readlane_b32 s48, v75, 6
+; GFX11-NEXT: v_readlane_b32 s39, v75, 5
+; GFX11-NEXT: v_readlane_b32 s38, v75, 4
+; GFX11-NEXT: v_readlane_b32 s37, v75, 3
+; GFX11-NEXT: v_readlane_b32 s36, v75, 2
+; GFX11-NEXT: v_readlane_b32 s35, v75, 1
+; GFX11-NEXT: v_readlane_b32 s34, v75, 0
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_load_b32 v75, off, s32 offset:76
@@ -61536,43 +61536,43 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_writelane_b32 v63, s30, 0
-; SI-NEXT: v_writelane_b32 v63, s31, 1
-; SI-NEXT: v_writelane_b32 v63, s34, 2
-; SI-NEXT: v_writelane_b32 v63, s35, 3
-; SI-NEXT: v_writelane_b32 v63, s36, 4
-; SI-NEXT: v_writelane_b32 v63, s37, 5
-; SI-NEXT: v_writelane_b32 v63, s38, 6
-; SI-NEXT: v_writelane_b32 v63, s39, 7
-; SI-NEXT: v_writelane_b32 v63, s48, 8
-; SI-NEXT: v_writelane_b32 v63, s49, 9
-; SI-NEXT: v_writelane_b32 v63, s50, 10
-; SI-NEXT: v_writelane_b32 v63, s51, 11
-; SI-NEXT: v_writelane_b32 v63, s52, 12
-; SI-NEXT: v_writelane_b32 v63, s53, 13
-; SI-NEXT: v_writelane_b32 v63, s54, 14
-; SI-NEXT: v_writelane_b32 v63, s55, 15
-; SI-NEXT: v_writelane_b32 v63, s64, 16
-; SI-NEXT: v_writelane_b32 v63, s65, 17
-; SI-NEXT: v_writelane_b32 v63, s66, 18
-; SI-NEXT: v_writelane_b32 v63, s67, 19
-; SI-NEXT: v_writelane_b32 v63, s68, 20
-; SI-NEXT: v_writelane_b32 v63, s69, 21
-; SI-NEXT: v_writelane_b32 v63, s70, 22
-; SI-NEXT: v_writelane_b32 v63, s71, 23
-; SI-NEXT: v_writelane_b32 v63, s80, 24
-; SI-NEXT: v_writelane_b32 v63, s81, 25
-; SI-NEXT: v_writelane_b32 v63, s82, 26
-; SI-NEXT: v_writelane_b32 v63, s83, 27
-; SI-NEXT: v_writelane_b32 v63, s84, 28
-; SI-NEXT: v_writelane_b32 v63, s85, 29
-; SI-NEXT: v_writelane_b32 v63, s86, 30
-; SI-NEXT: v_writelane_b32 v63, s87, 31
-; SI-NEXT: v_writelane_b32 v63, s96, 32
-; SI-NEXT: v_writelane_b32 v63, s97, 33
-; SI-NEXT: v_writelane_b32 v63, s98, 34
+; SI-NEXT: v_writelane_b32 v63, s34, 0
+; SI-NEXT: v_writelane_b32 v63, s35, 1
+; SI-NEXT: v_writelane_b32 v63, s36, 2
+; SI-NEXT: v_writelane_b32 v63, s37, 3
+; SI-NEXT: v_writelane_b32 v63, s38, 4
+; SI-NEXT: v_writelane_b32 v63, s39, 5
+; SI-NEXT: v_writelane_b32 v63, s48, 6
+; SI-NEXT: v_writelane_b32 v63, s49, 7
+; SI-NEXT: v_writelane_b32 v63, s50, 8
+; SI-NEXT: v_writelane_b32 v63, s51, 9
+; SI-NEXT: v_writelane_b32 v63, s52, 10
+; SI-NEXT: v_writelane_b32 v63, s53, 11
+; SI-NEXT: v_writelane_b32 v63, s54, 12
+; SI-NEXT: v_writelane_b32 v63, s55, 13
+; SI-NEXT: v_writelane_b32 v63, s64, 14
+; SI-NEXT: v_writelane_b32 v63, s65, 15
+; SI-NEXT: v_writelane_b32 v63, s66, 16
+; SI-NEXT: v_writelane_b32 v63, s67, 17
+; SI-NEXT: v_writelane_b32 v63, s68, 18
+; SI-NEXT: v_writelane_b32 v63, s69, 19
+; SI-NEXT: v_writelane_b32 v63, s70, 20
+; SI-NEXT: v_writelane_b32 v63, s71, 21
+; SI-NEXT: v_writelane_b32 v63, s80, 22
+; SI-NEXT: v_writelane_b32 v63, s81, 23
+; SI-NEXT: v_writelane_b32 v63, s82, 24
+; SI-NEXT: v_writelane_b32 v63, s83, 25
+; SI-NEXT: v_writelane_b32 v63, s84, 26
+; SI-NEXT: v_writelane_b32 v63, s85, 27
+; SI-NEXT: v_writelane_b32 v63, s86, 28
+; SI-NEXT: v_writelane_b32 v63, s87, 29
+; SI-NEXT: v_writelane_b32 v63, s96, 30
+; SI-NEXT: v_writelane_b32 v63, s97, 31
+; SI-NEXT: v_writelane_b32 v63, s98, 32
+; SI-NEXT: v_writelane_b32 v63, s99, 33
+; SI-NEXT: v_writelane_b32 v63, s30, 34
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_writelane_b32 v63, s99, 35
+; SI-NEXT: v_writelane_b32 v63, s31, 35
; SI-NEXT: v_readfirstlane_b32 s6, v1
; SI-NEXT: v_readfirstlane_b32 s7, v2
; SI-NEXT: v_readfirstlane_b32 s8, v3
@@ -62140,42 +62140,42 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; SI-NEXT: v_readlane_b32 s99, v63, 35
-; SI-NEXT: v_readlane_b32 s98, v63, 34
-; SI-NEXT: v_readlane_b32 s97, v63, 33
-; SI-NEXT: v_readlane_b32 s96, v63, 32
-; SI-NEXT: v_readlane_b32 s87, v63, 31
-; SI-NEXT: v_readlane_b32 s86, v63, 30
-; SI-NEXT: v_readlane_b32 s85, v63, 29
-; SI-NEXT: v_readlane_b32 s84, v63, 28
-; SI-NEXT: v_readlane_b32 s83, v63, 27
-; SI-NEXT: v_readlane_b32 s82, v63, 26
-; SI-NEXT: v_readlane_b32 s81, v63, 25
-; SI-NEXT: v_readlane_b32 s80, v63, 24
-; SI-NEXT: v_readlane_b32 s71, v63, 23
-; SI-NEXT: v_readlane_b32 s70, v63, 22
-; SI-NEXT: v_readlane_b32 s69, v63, 21
-; SI-NEXT: v_readlane_b32 s68, v63, 20
-; SI-NEXT: v_readlane_b32 s67, v63, 19
-; SI-NEXT: v_readlane_b32 s66, v63, 18
-; SI-NEXT: v_readlane_b32 s65, v63, 17
-; SI-NEXT: v_readlane_b32 s64, v63, 16
-; SI-NEXT: v_readlane_b32 s55, v63, 15
-; SI-NEXT: v_readlane_b32 s54, v63, 14
-; SI-NEXT: v_readlane_b32 s53, v63, 13
-; SI-NEXT: v_readlane_b32 s52, v63, 12
-; SI-NEXT: v_readlane_b32 s51, v63, 11
-; SI-NEXT: v_readlane_b32 s50, v63, 10
-; SI-NEXT: v_readlane_b32 s49, v63, 9
-; SI-NEXT: v_readlane_b32 s48, v63, 8
-; SI-NEXT: v_readlane_b32 s39, v63, 7
-; SI-NEXT: v_readlane_b32 s38, v63, 6
-; SI-NEXT: v_readlane_b32 s37, v63, 5
-; SI-NEXT: v_readlane_b32 s36, v63, 4
-; SI-NEXT: v_readlane_b32 s35, v63, 3
-; SI-NEXT: v_readlane_b32 s34, v63, 2
-; SI-NEXT: v_readlane_b32 s31, v63, 1
-; SI-NEXT: v_readlane_b32 s30, v63, 0
+; SI-NEXT: v_readlane_b32 s30, v63, 34
+; SI-NEXT: v_readlane_b32 s31, v63, 35
+; SI-NEXT: v_readlane_b32 s99, v63, 33
+; SI-NEXT: v_readlane_b32 s98, v63, 32
+; SI-NEXT: v_readlane_b32 s97, v63, 31
+; SI-NEXT: v_readlane_b32 s96, v63, 30
+; SI-NEXT: v_readlane_b32 s87, v63, 29
+; SI-NEXT: v_readlane_b32 s86, v63, 28
+; SI-NEXT: v_readlane_b32 s85, v63, 27
+; SI-NEXT: v_readlane_b32 s84, v63, 26
+; SI-NEXT: v_readlane_b32 s83, v63, 25
+; SI-NEXT: v_readlane_b32 s82, v63, 24
+; SI-NEXT: v_readlane_b32 s81, v63, 23
+; SI-NEXT: v_readlane_b32 s80, v63, 22
+; SI-NEXT: v_readlane_b32 s71, v63, 21
+; SI-NEXT: v_readlane_b32 s70, v63, 20
+; SI-NEXT: v_readlane_b32 s69, v63, 19
+; SI-NEXT: v_readlane_b32 s68, v63, 18
+; SI-NEXT: v_readlane_b32 s67, v63, 17
+; SI-NEXT: v_readlane_b32 s66, v63, 16
+; SI-NEXT: v_readlane_b32 s65, v63, 15
+; SI-NEXT: v_readlane_b32 s64, v63, 14
+; SI-NEXT: v_readlane_b32 s55, v63, 13
+; SI-NEXT: v_readlane_b32 s54, v63, 12
+; SI-NEXT: v_readlane_b32 s53, v63, 11
+; SI-NEXT: v_readlane_b32 s52, v63, 10
+; SI-NEXT: v_readlane_b32 s51, v63, 9
+; SI-NEXT: v_readlane_b32 s50, v63, 8
+; SI-NEXT: v_readlane_b32 s49, v63, 7
+; SI-NEXT: v_readlane_b32 s48, v63, 6
+; SI-NEXT: v_readlane_b32 s39, v63, 5
+; SI-NEXT: v_readlane_b32 s38, v63, 4
+; SI-NEXT: v_readlane_b32 s37, v63, 3
+; SI-NEXT: v_readlane_b32 s36, v63, 2
+; SI-NEXT: v_readlane_b32 s35, v63, 1
+; SI-NEXT: v_readlane_b32 s34, v63, 0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -81431,42 +81431,42 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_writelane_b32 v20, s30, 0
-; SI-NEXT: v_writelane_b32 v20, s31, 1
-; SI-NEXT: v_writelane_b32 v20, s34, 2
-; SI-NEXT: v_writelane_b32 v20, s35, 3
-; SI-NEXT: v_writelane_b32 v20, s36, 4
-; SI-NEXT: v_writelane_b32 v20, s37, 5
-; SI-NEXT: v_writelane_b32 v20, s38, 6
-; SI-NEXT: v_writelane_b32 v20, s39, 7
-; SI-NEXT: v_writelane_b32 v20, s48, 8
-; SI-NEXT: v_writelane_b32 v20, s49, 9
-; SI-NEXT: v_writelane_b32 v20, s50, 10
-; SI-NEXT: v_writelane_b32 v20, s51, 11
-; SI-NEXT: v_writelane_b32 v20, s52, 12
-; SI-NEXT: v_writelane_b32 v20, s53, 13
-; SI-NEXT: v_writelane_b32 v20, s54, 14
-; SI-NEXT: v_writelane_b32 v20, s55, 15
-; SI-NEXT: v_writelane_b32 v20, s64, 16
-; SI-NEXT: v_writelane_b32 v20, s65, 17
-; SI-NEXT: v_writelane_b32 v20, s66, 18
-; SI-NEXT: v_writelane_b32 v20, s67, 19
-; SI-NEXT: v_writelane_b32 v20, s68, 20
-; SI-NEXT: v_writelane_b32 v20, s69, 21
-; SI-NEXT: v_writelane_b32 v20, s70, 22
-; SI-NEXT: v_writelane_b32 v20, s71, 23
-; SI-NEXT: v_writelane_b32 v20, s80, 24
-; SI-NEXT: v_writelane_b32 v20, s81, 25
-; SI-NEXT: v_writelane_b32 v20, s82, 26
-; SI-NEXT: v_writelane_b32 v20, s83, 27
-; SI-NEXT: v_writelane_b32 v20, s84, 28
-; SI-NEXT: v_writelane_b32 v20, s85, 29
-; SI-NEXT: v_writelane_b32 v20, s86, 30
-; SI-NEXT: v_writelane_b32 v20, s87, 31
-; SI-NEXT: v_writelane_b32 v20, s96, 32
-; SI-NEXT: v_writelane_b32 v20, s97, 33
+; SI-NEXT: v_writelane_b32 v20, s34, 0
+; SI-NEXT: v_writelane_b32 v20, s35, 1
+; SI-NEXT: v_writelane_b32 v20, s36, 2
+; SI-NEXT: v_writelane_b32 v20, s37, 3
+; SI-NEXT: v_writelane_b32 v20, s38, 4
+; SI-NEXT: v_writelane_b32 v20, s39, 5
+; SI-NEXT: v_writelane_b32 v20, s48, 6
+; SI-NEXT: v_writelane_b32 v20, s49, 7
+; SI-NEXT: v_writelane_b32 v20, s50, 8
+; SI-NEXT: v_writelane_b32 v20, s51, 9
+; SI-NEXT: v_writelane_b32 v20, s52, 10
+; SI-NEXT: v_writelane_b32 v20, s53, 11
+; SI-NEXT: v_writelane_b32 v20, s54, 12
+; SI-NEXT: v_writelane_b32 v20, s55, 13
+; SI-NEXT: v_writelane_b32 v20, s64, 14
+; SI-NEXT: v_writelane_b32 v20, s65, 15
+; SI-NEXT: v_writelane_b32 v20, s66, 16
+; SI-NEXT: v_writelane_b32 v20, s67, 17
+; SI-NEXT: v_writelane_b32 v20, s68, 18
+; SI-NEXT: v_writelane_b32 v20, s69, 19
+; SI-NEXT: v_writelane_b32 v20, s70, 20
+; SI-NEXT: v_writelane_b32 v20, s71, 21
+; SI-NEXT: v_writelane_b32 v20, s80, 22
+; SI-NEXT: v_writelane_b32 v20, s81, 23
+; SI-NEXT: v_writelane_b32 v20, s82, 24
+; SI-NEXT: v_writelane_b32 v20, s83, 25
+; SI-NEXT: v_writelane_b32 v20, s84, 26
+; SI-NEXT: v_writelane_b32 v20, s85, 27
+; SI-NEXT: v_writelane_b32 v20, s86, 28
+; SI-NEXT: v_writelane_b32 v20, s87, 29
+; SI-NEXT: v_writelane_b32 v20, s96, 30
+; SI-NEXT: v_writelane_b32 v20, s97, 31
+; SI-NEXT: v_writelane_b32 v20, s98, 32
+; SI-NEXT: v_writelane_b32 v20, s99, 33
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_writelane_b32 v20, s98, 34
+; SI-NEXT: v_writelane_b32 v20, s30, 34
; SI-NEXT: v_readfirstlane_b32 s44, v1
; SI-NEXT: v_readfirstlane_b32 s45, v2
; SI-NEXT: v_readfirstlane_b32 s42, v3
@@ -81486,7 +81486,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v17
; SI-NEXT: s_and_b64 s[46:47], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v18
-; SI-NEXT: v_writelane_b32 v20, s99, 35
+; SI-NEXT: v_writelane_b32 v20, s31, 35
; SI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB57_4
@@ -82356,6 +82356,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v20, 34
; SI-NEXT: v_readlane_b32 s19, v22, 11
; SI-NEXT: v_readlane_b32 s17, v22, 17
; SI-NEXT: v_readlane_b32 s15, v22, 23
@@ -82363,42 +82364,41 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: v_readlane_b32 s11, v22, 35
; SI-NEXT: v_readlane_b32 s9, v22, 39
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s99, v20, 35
-; SI-NEXT: v_readlane_b32 s98, v20, 34
-; SI-NEXT: v_readlane_b32 s97, v20, 33
-; SI-NEXT: v_readlane_b32 s96, v20, 32
-; SI-NEXT: v_readlane_b32 s87, v20, 31
-; SI-NEXT: v_readlane_b32 s86, v20, 30
-; SI-NEXT: v_readlane_b32 s85, v20, 29
-; SI-NEXT: v_readlane_b32 s84, v20, 28
-; SI-NEXT: v_readlane_b32 s83, v20, 27
-; SI-NEXT: v_readlane_b32 s82, v20, 26
-; SI-NEXT: v_readlane_b32 s81, v20, 25
-; SI-NEXT: v_readlane_b32 s80, v20, 24
-; SI-NEXT: v_readlane_b32 s71, v20, 23
-; SI-NEXT: v_readlane_b32 s70, v20, 22
-; SI-NEXT: v_readlane_b32 s69, v20, 21
-; SI-NEXT: v_readlane_b32 s68, v20, 20
-; SI-NEXT: v_readlane_b32 s67, v20, 19
-; SI-NEXT: v_readlane_b32 s66, v20, 18
-; SI-NEXT: v_readlane_b32 s65, v20, 17
-; SI-NEXT: v_readlane_b32 s64, v20, 16
-; SI-NEXT: v_readlane_b32 s55, v20, 15
-; SI-NEXT: v_readlane_b32 s54, v20, 14
-; SI-NEXT: v_readlane_b32 s53, v20, 13
-; SI-NEXT: v_readlane_b32 s52, v20, 12
-; SI-NEXT: v_readlane_b32 s51, v20, 11
-; SI-NEXT: v_readlane_b32 s50, v20, 10
-; SI-NEXT: v_readlane_b32 s49, v20, 9
-; SI-NEXT: v_readlane_b32 s48, v20, 8
-; SI-NEXT: v_readlane_b32 s39, v20, 7
-; SI-NEXT: v_readlane_b32 s38, v20, 6
-; SI-NEXT: v_readlane_b32 s37, v20, 5
-; SI-NEXT: v_readlane_b32 s36, v20, 4
-; SI-NEXT: v_readlane_b32 s35, v20, 3
-; SI-NEXT: v_readlane_b32 s34, v20, 2
-; SI-NEXT: v_readlane_b32 s31, v20, 1
-; SI-NEXT: v_readlane_b32 s30, v20, 0
+; SI-NEXT: v_readlane_b32 s31, v20, 35
+; SI-NEXT: v_readlane_b32 s99, v20, 33
+; SI-NEXT: v_readlane_b32 s98, v20, 32
+; SI-NEXT: v_readlane_b32 s97, v20, 31
+; SI-NEXT: v_readlane_b32 s96, v20, 30
+; SI-NEXT: v_readlane_b32 s87, v20, 29
+; SI-NEXT: v_readlane_b32 s86, v20, 28
+; SI-NEXT: v_readlane_b32 s85, v20, 27
+; SI-NEXT: v_readlane_b32 s84, v20, 26
+; SI-NEXT: v_readlane_b32 s83, v20, 25
+; SI-NEXT: v_readlane_b32 s82, v20, 24
+; SI-NEXT: v_readlane_b32 s81, v20, 23
+; SI-NEXT: v_readlane_b32 s80, v20, 22
+; SI-NEXT: v_readlane_b32 s71, v20, 21
+; SI-NEXT: v_readlane_b32 s70, v20, 20
+; SI-NEXT: v_readlane_b32 s69, v20, 19
+; SI-NEXT: v_readlane_b32 s68, v20, 18
+; SI-NEXT: v_readlane_b32 s67, v20, 17
+; SI-NEXT: v_readlane_b32 s66, v20, 16
+; SI-NEXT: v_readlane_b32 s65, v20, 15
+; SI-NEXT: v_readlane_b32 s64, v20, 14
+; SI-NEXT: v_readlane_b32 s55, v20, 13
+; SI-NEXT: v_readlane_b32 s54, v20, 12
+; SI-NEXT: v_readlane_b32 s53, v20, 11
+; SI-NEXT: v_readlane_b32 s52, v20, 10
+; SI-NEXT: v_readlane_b32 s51, v20, 9
+; SI-NEXT: v_readlane_b32 s50, v20, 8
+; SI-NEXT: v_readlane_b32 s49, v20, 7
+; SI-NEXT: v_readlane_b32 s48, v20, 6
+; SI-NEXT: v_readlane_b32 s39, v20, 5
+; SI-NEXT: v_readlane_b32 s38, v20, 4
+; SI-NEXT: v_readlane_b32 s37, v20, 3
+; SI-NEXT: v_readlane_b32 s36, v20, 2
+; SI-NEXT: v_readlane_b32 s35, v20, 1
+; SI-NEXT: v_readlane_b32 s34, v20, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -82595,38 +82595,38 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v20, s30, 0
-; VI-NEXT: v_writelane_b32 v20, s31, 1
-; VI-NEXT: v_writelane_b32 v20, s34, 2
-; VI-NEXT: v_writelane_b32 v20, s35, 3
-; VI-NEXT: v_writelane_b32 v20, s36, 4
-; VI-NEXT: v_writelane_b32 v20, s37, 5
-; VI-NEXT: v_writelane_b32 v20, s38, 6
-; VI-NEXT: v_writelane_b32 v20, s39, 7
-; VI-NEXT: v_writelane_b32 v20, s48, 8
-; VI-NEXT: v_writelane_b32 v20, s49, 9
-; VI-NEXT: v_writelane_b32 v20, s50, 10
-; VI-NEXT: v_writelane_b32 v20, s51, 11
-; VI-NEXT: v_writelane_b32 v20, s52, 12
-; VI-NEXT: v_writelane_b32 v20, s53, 13
-; VI-NEXT: v_writelane_b32 v20, s54, 14
-; VI-NEXT: v_writelane_b32 v20, s55, 15
-; VI-NEXT: v_writelane_b32 v20, s64, 16
-; VI-NEXT: v_writelane_b32 v20, s65, 17
-; VI-NEXT: v_writelane_b32 v20, s66, 18
-; VI-NEXT: v_writelane_b32 v20, s67, 19
-; VI-NEXT: v_writelane_b32 v20, s68, 20
-; VI-NEXT: v_writelane_b32 v20, s69, 21
-; VI-NEXT: v_writelane_b32 v20, s70, 22
-; VI-NEXT: v_writelane_b32 v20, s71, 23
-; VI-NEXT: v_writelane_b32 v20, s80, 24
-; VI-NEXT: v_writelane_b32 v20, s81, 25
-; VI-NEXT: v_writelane_b32 v20, s82, 26
-; VI-NEXT: v_writelane_b32 v20, s83, 27
-; VI-NEXT: v_writelane_b32 v20, s84, 28
-; VI-NEXT: v_writelane_b32 v20, s85, 29
+; VI-NEXT: v_writelane_b32 v20, s34, 0
+; VI-NEXT: v_writelane_b32 v20, s35, 1
+; VI-NEXT: v_writelane_b32 v20, s36, 2
+; VI-NEXT: v_writelane_b32 v20, s37, 3
+; VI-NEXT: v_writelane_b32 v20, s38, 4
+; VI-NEXT: v_writelane_b32 v20, s39, 5
+; VI-NEXT: v_writelane_b32 v20, s48, 6
+; VI-NEXT: v_writelane_b32 v20, s49, 7
+; VI-NEXT: v_writelane_b32 v20, s50, 8
+; VI-NEXT: v_writelane_b32 v20, s51, 9
+; VI-NEXT: v_writelane_b32 v20, s52, 10
+; VI-NEXT: v_writelane_b32 v20, s53, 11
+; VI-NEXT: v_writelane_b32 v20, s54, 12
+; VI-NEXT: v_writelane_b32 v20, s55, 13
+; VI-NEXT: v_writelane_b32 v20, s64, 14
+; VI-NEXT: v_writelane_b32 v20, s65, 15
+; VI-NEXT: v_writelane_b32 v20, s66, 16
+; VI-NEXT: v_writelane_b32 v20, s67, 17
+; VI-NEXT: v_writelane_b32 v20, s68, 18
+; VI-NEXT: v_writelane_b32 v20, s69, 19
+; VI-NEXT: v_writelane_b32 v20, s70, 20
+; VI-NEXT: v_writelane_b32 v20, s71, 21
+; VI-NEXT: v_writelane_b32 v20, s80, 22
+; VI-NEXT: v_writelane_b32 v20, s81, 23
+; VI-NEXT: v_writelane_b32 v20, s82, 24
+; VI-NEXT: v_writelane_b32 v20, s83, 25
+; VI-NEXT: v_writelane_b32 v20, s84, 26
+; VI-NEXT: v_writelane_b32 v20, s85, 27
+; VI-NEXT: v_writelane_b32 v20, s86, 28
+; VI-NEXT: v_writelane_b32 v20, s87, 29
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; VI-NEXT: v_writelane_b32 v20, s86, 30
+; VI-NEXT: v_writelane_b32 v20, s30, 30
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: v_readfirstlane_b32 s45, v2
; VI-NEXT: v_readfirstlane_b32 s42, v3
@@ -82646,7 +82646,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s4, v17
; VI-NEXT: s_and_b64 s[46:47], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v18
-; VI-NEXT: v_writelane_b32 v20, s87, 31
+; VI-NEXT: v_writelane_b32 v20, s31, 31
; VI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; VI-NEXT: s_cbranch_scc0 .LBB57_4
; VI-NEXT: ; %bb.1: ; %cmp.false
@@ -83435,43 +83435,43 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
; VI-NEXT: v_mov_b32_e32 v1, s4
+; VI-NEXT: v_readlane_b32 s30, v20, 30
; VI-NEXT: v_readlane_b32 s15, v21, 1
; VI-NEXT: v_readlane_b32 s13, v21, 3
; VI-NEXT: v_readlane_b32 s11, v21, 5
; VI-NEXT: v_readlane_b32 s9, v21, 7
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT: v_readlane_b32 s87, v20, 31
-; VI-NEXT: v_readlane_b32 s86, v20, 30
-; VI-NEXT: v_readlane_b32 s85, v20, 29
-; VI-NEXT: v_readlane_b32 s84, v20, 28
-; VI-NEXT: v_readlane_b32 s83, v20, 27
-; VI-NEXT: v_readlane_b32 s82, v20, 26
-; VI-NEXT: v_readlane_b32 s81, v20, 25
-; VI-NEXT: v_readlane_b32 s80, v20, 24
-; VI-NEXT: v_readlane_b32 s71, v20, 23
-; VI-NEXT: v_readlane_b32 s70, v20, 22
-; VI-NEXT: v_readlane_b32 s69, v20, 21
-; VI-NEXT: v_readlane_b32 s68, v20, 20
-; VI-NEXT: v_readlane_b32 s67, v20, 19
-; VI-NEXT: v_readlane_b32 s66, v20, 18
-; VI-NEXT: v_readlane_b32 s65, v20, 17
-; VI-NEXT: v_readlane_b32 s64, v20, 16
-; VI-NEXT: v_readlane_b32 s55, v20, 15
-; VI-NEXT: v_readlane_b32 s54, v20, 14
-; VI-NEXT: v_readlane_b32 s53, v20, 13
-; VI-NEXT: v_readlane_b32 s52, v20, 12
-; VI-NEXT: v_readlane_b32 s51, v20, 11
-; VI-NEXT: v_readlane_b32 s50, v20, 10
-; VI-NEXT: v_readlane_b32 s49, v20, 9
-; VI-NEXT: v_readlane_b32 s48, v20, 8
-; VI-NEXT: v_readlane_b32 s39, v20, 7
-; VI-NEXT: v_readlane_b32 s38, v20, 6
-; VI-NEXT: v_readlane_b32 s37, v20, 5
-; VI-NEXT: v_readlane_b32 s36, v20, 4
-; VI-NEXT: v_readlane_b32 s35, v20, 3
-; VI-NEXT: v_readlane_b32 s34, v20, 2
-; VI-NEXT: v_readlane_b32 s31, v20, 1
-; VI-NEXT: v_readlane_b32 s30, v20, 0
+; VI-NEXT: v_readlane_b32 s31, v20, 31
+; VI-NEXT: v_readlane_b32 s87, v20, 29
+; VI-NEXT: v_readlane_b32 s86, v20, 28
+; VI-NEXT: v_readlane_b32 s85, v20, 27
+; VI-NEXT: v_readlane_b32 s84, v20, 26
+; VI-NEXT: v_readlane_b32 s83, v20, 25
+; VI-NEXT: v_readlane_b32 s82, v20, 24
+; VI-NEXT: v_readlane_b32 s81, v20, 23
+; VI-NEXT: v_readlane_b32 s80, v20, 22
+; VI-NEXT: v_readlane_b32 s71, v20, 21
+; VI-NEXT: v_readlane_b32 s70, v20, 20
+; VI-NEXT: v_readlane_b32 s69, v20, 19
+; VI-NEXT: v_readlane_b32 s68, v20, 18
+; VI-NEXT: v_readlane_b32 s67, v20, 17
+; VI-NEXT: v_readlane_b32 s66, v20, 16
+; VI-NEXT: v_readlane_b32 s65, v20, 15
+; VI-NEXT: v_readlane_b32 s64, v20, 14
+; VI-NEXT: v_readlane_b32 s55, v20, 13
+; VI-NEXT: v_readlane_b32 s54, v20, 12
+; VI-NEXT: v_readlane_b32 s53, v20, 11
+; VI-NEXT: v_readlane_b32 s52, v20, 10
+; VI-NEXT: v_readlane_b32 s51, v20, 9
+; VI-NEXT: v_readlane_b32 s50, v20, 8
+; VI-NEXT: v_readlane_b32 s49, v20, 7
+; VI-NEXT: v_readlane_b32 s48, v20, 6
+; VI-NEXT: v_readlane_b32 s39, v20, 5
+; VI-NEXT: v_readlane_b32 s38, v20, 4
+; VI-NEXT: v_readlane_b32 s37, v20, 3
+; VI-NEXT: v_readlane_b32 s36, v20, 2
+; VI-NEXT: v_readlane_b32 s35, v20, 1
+; VI-NEXT: v_readlane_b32 s34, v20, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -83644,42 +83644,42 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v20, s30, 0
-; GFX9-NEXT: v_writelane_b32 v20, s31, 1
-; GFX9-NEXT: v_writelane_b32 v20, s34, 2
-; GFX9-NEXT: v_writelane_b32 v20, s35, 3
-; GFX9-NEXT: v_writelane_b32 v20, s36, 4
-; GFX9-NEXT: v_writelane_b32 v20, s37, 5
-; GFX9-NEXT: v_writelane_b32 v20, s38, 6
-; GFX9-NEXT: v_writelane_b32 v20, s39, 7
-; GFX9-NEXT: v_writelane_b32 v20, s48, 8
-; GFX9-NEXT: v_writelane_b32 v20, s49, 9
-; GFX9-NEXT: v_writelane_b32 v20, s50, 10
-; GFX9-NEXT: v_writelane_b32 v20, s51, 11
-; GFX9-NEXT: v_writelane_b32 v20, s52, 12
-; GFX9-NEXT: v_writelane_b32 v20, s53, 13
-; GFX9-NEXT: v_writelane_b32 v20, s54, 14
-; GFX9-NEXT: v_writelane_b32 v20, s55, 15
-; GFX9-NEXT: v_writelane_b32 v20, s64, 16
-; GFX9-NEXT: v_writelane_b32 v20, s65, 17
-; GFX9-NEXT: v_writelane_b32 v20, s66, 18
-; GFX9-NEXT: v_writelane_b32 v20, s67, 19
-; GFX9-NEXT: v_writelane_b32 v20, s68, 20
-; GFX9-NEXT: v_writelane_b32 v20, s69, 21
-; GFX9-NEXT: v_writelane_b32 v20, s70, 22
-; GFX9-NEXT: v_writelane_b32 v20, s71, 23
-; GFX9-NEXT: v_writelane_b32 v20, s80, 24
-; GFX9-NEXT: v_writelane_b32 v20, s81, 25
-; GFX9-NEXT: v_writelane_b32 v20, s82, 26
-; GFX9-NEXT: v_writelane_b32 v20, s83, 27
-; GFX9-NEXT: v_writelane_b32 v20, s84, 28
-; GFX9-NEXT: v_writelane_b32 v20, s85, 29
-; GFX9-NEXT: v_writelane_b32 v20, s86, 30
-; GFX9-NEXT: v_writelane_b32 v20, s87, 31
-; GFX9-NEXT: v_writelane_b32 v20, s96, 32
-; GFX9-NEXT: v_writelane_b32 v20, s97, 33
+; GFX9-NEXT: v_writelane_b32 v20, s34, 0
+; GFX9-NEXT: v_writelane_b32 v20, s35, 1
+; GFX9-NEXT: v_writelane_b32 v20, s36, 2
+; GFX9-NEXT: v_writelane_b32 v20, s37, 3
+; GFX9-NEXT: v_writelane_b32 v20, s38, 4
+; GFX9-NEXT: v_writelane_b32 v20, s39, 5
+; GFX9-NEXT: v_writelane_b32 v20, s48, 6
+; GFX9-NEXT: v_writelane_b32 v20, s49, 7
+; GFX9-NEXT: v_writelane_b32 v20, s50, 8
+; GFX9-NEXT: v_writelane_b32 v20, s51, 9
+; GFX9-NEXT: v_writelane_b32 v20, s52, 10
+; GFX9-NEXT: v_writelane_b32 v20, s53, 11
+; GFX9-NEXT: v_writelane_b32 v20, s54, 12
+; GFX9-NEXT: v_writelane_b32 v20, s55, 13
+; GFX9-NEXT: v_writelane_b32 v20, s64, 14
+; GFX9-NEXT: v_writelane_b32 v20, s65, 15
+; GFX9-NEXT: v_writelane_b32 v20, s66, 16
+; GFX9-NEXT: v_writelane_b32 v20, s67, 17
+; GFX9-NEXT: v_writelane_b32 v20, s68, 18
+; GFX9-NEXT: v_writelane_b32 v20, s69, 19
+; GFX9-NEXT: v_writelane_b32 v20, s70, 20
+; GFX9-NEXT: v_writelane_b32 v20, s71, 21
+; GFX9-NEXT: v_writelane_b32 v20, s80, 22
+; GFX9-NEXT: v_writelane_b32 v20, s81, 23
+; GFX9-NEXT: v_writelane_b32 v20, s82, 24
+; GFX9-NEXT: v_writelane_b32 v20, s83, 25
+; GFX9-NEXT: v_writelane_b32 v20, s84, 26
+; GFX9-NEXT: v_writelane_b32 v20, s85, 27
+; GFX9-NEXT: v_writelane_b32 v20, s86, 28
+; GFX9-NEXT: v_writelane_b32 v20, s87, 29
+; GFX9-NEXT: v_writelane_b32 v20, s96, 30
+; GFX9-NEXT: v_writelane_b32 v20, s97, 31
+; GFX9-NEXT: v_writelane_b32 v20, s98, 32
+; GFX9-NEXT: v_writelane_b32 v20, s99, 33
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; GFX9-NEXT: v_writelane_b32 v20, s98, 34
+; GFX9-NEXT: v_writelane_b32 v20, s30, 34
; GFX9-NEXT: v_readfirstlane_b32 s44, v1
; GFX9-NEXT: v_readfirstlane_b32 s45, v2
; GFX9-NEXT: v_readfirstlane_b32 s42, v3
@@ -83699,7 +83699,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s4, v17
; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v18
-; GFX9-NEXT: v_writelane_b32 v20, s99, 35
+; GFX9-NEXT: v_writelane_b32 v20, s31, 35
; GFX9-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; GFX9-NEXT: s_cbranch_scc0 .LBB57_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
@@ -84433,44 +84433,44 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: s_or_b32 s4, s4, s5
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_readlane_b32 s30, v20, 34
; GFX9-NEXT: v_readlane_b32 s9, v21, 1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
-; GFX9-NEXT: v_readlane_b32 s99, v20, 35
-; GFX9-NEXT: v_readlane_b32 s98, v20, 34
-; GFX9-NEXT: v_readlane_b32 s97, v20, 33
-; GFX9-NEXT: v_readlane_b32 s96, v20, 32
-; GFX9-NEXT: v_readlane_b32 s87, v20, 31
-; GFX9-NEXT: v_readlane_b32 s86, v20, 30
-; GFX9-NEXT: v_readlane_b32 s85, v20, 29
-; GFX9-NEXT: v_readlane_b32 s84, v20, 28
-; GFX9-NEXT: v_readlane_b32 s83, v20, 27
-; GFX9-NEXT: v_readlane_b32 s82, v20, 26
-; GFX9-NEXT: v_readlane_b32 s81, v20, 25
-; GFX9-NEXT: v_readlane_b32 s80, v20, 24
-; GFX9-NEXT: v_readlane_b32 s71, v20, 23
-; GFX9-NEXT: v_readlane_b32 s70, v20, 22
-; GFX9-NEXT: v_readlane_b32 s69, v20, 21
-; GFX9-NEXT: v_readlane_b32 s68, v20, 20
-; GFX9-NEXT: v_readlane_b32 s67, v20, 19
-; GFX9-NEXT: v_readlane_b32 s66, v20, 18
-; GFX9-NEXT: v_readlane_b32 s65, v20, 17
-; GFX9-NEXT: v_readlane_b32 s64, v20, 16
-; GFX9-NEXT: v_readlane_b32 s55, v20, 15
-; GFX9-NEXT: v_readlane_b32 s54, v20, 14
-; GFX9-NEXT: v_readlane_b32 s53, v20, 13
-; GFX9-NEXT: v_readlane_b32 s52, v20, 12
-; GFX9-NEXT: v_readlane_b32 s51, v20, 11
-; GFX9-NEXT: v_readlane_b32 s50, v20, 10
-; GFX9-NEXT: v_readlane_b32 s49, v20, 9
-; GFX9-NEXT: v_readlane_b32 s48, v20, 8
-; GFX9-NEXT: v_readlane_b32 s39, v20, 7
-; GFX9-NEXT: v_readlane_b32 s38, v20, 6
-; GFX9-NEXT: v_readlane_b32 s37, v20, 5
-; GFX9-NEXT: v_readlane_b32 s36, v20, 4
-; GFX9-NEXT: v_readlane_b32 s35, v20, 3
-; GFX9-NEXT: v_readlane_b32 s34, v20, 2
-; GFX9-NEXT: v_readlane_b32 s31, v20, 1
-; GFX9-NEXT: v_readlane_b32 s30, v20, 0
+; GFX9-NEXT: v_readlane_b32 s31, v20, 35
+; GFX9-NEXT: v_readlane_b32 s99, v20, 33
+; GFX9-NEXT: v_readlane_b32 s98, v20, 32
+; GFX9-NEXT: v_readlane_b32 s97, v20, 31
+; GFX9-NEXT: v_readlane_b32 s96, v20, 30
+; GFX9-NEXT: v_readlane_b32 s87, v20, 29
+; GFX9-NEXT: v_readlane_b32 s86, v20, 28
+; GFX9-NEXT: v_readlane_b32 s85, v20, 27
+; GFX9-NEXT: v_readlane_b32 s84, v20, 26
+; GFX9-NEXT: v_readlane_b32 s83, v20, 25
+; GFX9-NEXT: v_readlane_b32 s82, v20, 24
+; GFX9-NEXT: v_readlane_b32 s81, v20, 23
+; GFX9-NEXT: v_readlane_b32 s80, v20, 22
+; GFX9-NEXT: v_readlane_b32 s71, v20, 21
+; GFX9-NEXT: v_readlane_b32 s70, v20, 20
+; GFX9-NEXT: v_readlane_b32 s69, v20, 19
+; GFX9-NEXT: v_readlane_b32 s68, v20, 18
+; GFX9-NEXT: v_readlane_b32 s67, v20, 17
+; GFX9-NEXT: v_readlane_b32 s66, v20, 16
+; GFX9-NEXT: v_readlane_b32 s65, v20, 15
+; GFX9-NEXT: v_readlane_b32 s64, v20, 14
+; GFX9-NEXT: v_readlane_b32 s55, v20, 13
+; GFX9-NEXT: v_readlane_b32 s54, v20, 12
+; GFX9-NEXT: v_readlane_b32 s53, v20, 11
+; GFX9-NEXT: v_readlane_b32 s52, v20, 10
+; GFX9-NEXT: v_readlane_b32 s51, v20, 9
+; GFX9-NEXT: v_readlane_b32 s50, v20, 8
+; GFX9-NEXT: v_readlane_b32 s49, v20, 7
+; GFX9-NEXT: v_readlane_b32 s48, v20, 6
+; GFX9-NEXT: v_readlane_b32 s39, v20, 5
+; GFX9-NEXT: v_readlane_b32 s38, v20, 4
+; GFX9-NEXT: v_readlane_b32 s37, v20, 3
+; GFX9-NEXT: v_readlane_b32 s36, v20, 2
+; GFX9-NEXT: v_readlane_b32 s35, v20, 1
+; GFX9-NEXT: v_readlane_b32 s34, v20, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -84637,66 +84637,66 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: scratch_store_b32 off, v18, s32 offset:8
; GFX11-NEXT: scratch_store_b32 off, v19, s32 offset:12
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v16, s30, 0
-; GFX11-NEXT: v_writelane_b32 v17, s96, 0
+; GFX11-NEXT: v_writelane_b32 v16, s34, 0
+; GFX11-NEXT: v_writelane_b32 v17, s98, 0
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
; GFX11-NEXT: v_readfirstlane_b32 s40, v1
; GFX11-NEXT: v_readfirstlane_b32 s41, v2
-; GFX11-NEXT: v_writelane_b32 v16, s31, 1
-; GFX11-NEXT: v_writelane_b32 v17, s97, 1
+; GFX11-NEXT: v_writelane_b32 v16, s35, 1
+; GFX11-NEXT: v_writelane_b32 v17, s99, 1
; GFX11-NEXT: v_readfirstlane_b32 s14, v3
; GFX11-NEXT: v_readfirstlane_b32 s15, v4
; GFX11-NEXT: v_readfirstlane_b32 s12, v5
-; GFX11-NEXT: v_writelane_b32 v16, s34, 2
-; GFX11-NEXT: v_writelane_b32 v17, s98, 2
+; GFX11-NEXT: v_writelane_b32 v16, s36, 2
+; GFX11-NEXT: v_writelane_b32 v17, s100, 2
; GFX11-NEXT: v_readfirstlane_b32 s13, v6
; GFX11-NEXT: v_readfirstlane_b32 s10, v7
; GFX11-NEXT: v_readfirstlane_b32 s11, v8
-; GFX11-NEXT: v_writelane_b32 v16, s35, 3
-; GFX11-NEXT: v_writelane_b32 v17, s99, 3
+; GFX11-NEXT: v_writelane_b32 v16, s37, 3
+; GFX11-NEXT: v_writelane_b32 v17, s101, 3
; GFX11-NEXT: v_readfirstlane_b32 s8, v9
; GFX11-NEXT: v_readfirstlane_b32 s9, v10
; GFX11-NEXT: v_readfirstlane_b32 s6, v11
-; GFX11-NEXT: v_writelane_b32 v16, s36, 4
-; GFX11-NEXT: v_writelane_b32 v17, s100, 4
+; GFX11-NEXT: v_writelane_b32 v16, s38, 4
+; GFX11-NEXT: v_writelane_b32 v17, s102, 4
; GFX11-NEXT: v_readfirstlane_b32 s7, v12
; GFX11-NEXT: v_readfirstlane_b32 s4, v13
; GFX11-NEXT: v_readfirstlane_b32 s5, v14
-; GFX11-NEXT: v_writelane_b32 v16, s37, 5
-; GFX11-NEXT: v_writelane_b32 v17, s101, 5
+; GFX11-NEXT: v_writelane_b32 v16, s39, 5
+; GFX11-NEXT: v_writelane_b32 v17, s103, 5
; GFX11-NEXT: s_mov_b32 s101, 0
; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
; GFX11-NEXT: ; implicit-def: $vgpr19 : SGPR spill to VGPR lane
; GFX11-NEXT: ; implicit-def: $vgpr18 : SGPR spill to VGPR lane
-; GFX11-NEXT: v_writelane_b32 v16, s38, 6
-; GFX11-NEXT: v_writelane_b32 v17, s102, 6
-; GFX11-NEXT: v_writelane_b32 v16, s39, 7
-; GFX11-NEXT: v_writelane_b32 v17, s103, 7
-; GFX11-NEXT: v_writelane_b32 v16, s48, 8
-; GFX11-NEXT: v_writelane_b32 v17, s104, 8
-; GFX11-NEXT: v_writelane_b32 v16, s49, 9
-; GFX11-NEXT: v_writelane_b32 v16, s50, 10
-; GFX11-NEXT: v_writelane_b32 v16, s51, 11
-; GFX11-NEXT: v_writelane_b32 v16, s52, 12
-; GFX11-NEXT: v_writelane_b32 v16, s53, 13
-; GFX11-NEXT: v_writelane_b32 v16, s54, 14
-; GFX11-NEXT: v_writelane_b32 v16, s55, 15
-; GFX11-NEXT: v_writelane_b32 v16, s64, 16
-; GFX11-NEXT: v_writelane_b32 v16, s65, 17
-; GFX11-NEXT: v_writelane_b32 v16, s66, 18
-; GFX11-NEXT: v_writelane_b32 v16, s67, 19
-; GFX11-NEXT: v_writelane_b32 v16, s68, 20
-; GFX11-NEXT: v_writelane_b32 v16, s69, 21
-; GFX11-NEXT: v_writelane_b32 v16, s70, 22
-; GFX11-NEXT: v_writelane_b32 v16, s71, 23
-; GFX11-NEXT: v_writelane_b32 v16, s80, 24
-; GFX11-NEXT: v_writelane_b32 v16, s81, 25
-; GFX11-NEXT: v_writelane_b32 v16, s82, 26
-; GFX11-NEXT: v_writelane_b32 v16, s83, 27
-; GFX11-NEXT: v_writelane_b32 v16, s84, 28
-; GFX11-NEXT: v_writelane_b32 v16, s85, 29
-; GFX11-NEXT: v_writelane_b32 v16, s86, 30
-; GFX11-NEXT: v_writelane_b32 v16, s87, 31
+; GFX11-NEXT: v_writelane_b32 v16, s48, 6
+; GFX11-NEXT: v_writelane_b32 v17, s104, 6
+; GFX11-NEXT: v_writelane_b32 v16, s49, 7
+; GFX11-NEXT: v_writelane_b32 v17, s30, 7
+; GFX11-NEXT: v_writelane_b32 v16, s50, 8
+; GFX11-NEXT: v_writelane_b32 v17, s31, 8
+; GFX11-NEXT: v_writelane_b32 v16, s51, 9
+; GFX11-NEXT: v_writelane_b32 v16, s52, 10
+; GFX11-NEXT: v_writelane_b32 v16, s53, 11
+; GFX11-NEXT: v_writelane_b32 v16, s54, 12
+; GFX11-NEXT: v_writelane_b32 v16, s55, 13
+; GFX11-NEXT: v_writelane_b32 v16, s64, 14
+; GFX11-NEXT: v_writelane_b32 v16, s65, 15
+; GFX11-NEXT: v_writelane_b32 v16, s66, 16
+; GFX11-NEXT: v_writelane_b32 v16, s67, 17
+; GFX11-NEXT: v_writelane_b32 v16, s68, 18
+; GFX11-NEXT: v_writelane_b32 v16, s69, 19
+; GFX11-NEXT: v_writelane_b32 v16, s70, 20
+; GFX11-NEXT: v_writelane_b32 v16, s71, 21
+; GFX11-NEXT: v_writelane_b32 v16, s80, 22
+; GFX11-NEXT: v_writelane_b32 v16, s81, 23
+; GFX11-NEXT: v_writelane_b32 v16, s82, 24
+; GFX11-NEXT: v_writelane_b32 v16, s83, 25
+; GFX11-NEXT: v_writelane_b32 v16, s84, 26
+; GFX11-NEXT: v_writelane_b32 v16, s85, 27
+; GFX11-NEXT: v_writelane_b32 v16, s86, 28
+; GFX11-NEXT: v_writelane_b32 v16, s87, 29
+; GFX11-NEXT: v_writelane_b32 v16, s96, 30
+; GFX11-NEXT: v_writelane_b32 v16, s97, 31
; GFX11-NEXT: s_cbranch_scc0 .LBB57_2
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s43, s25, 8
@@ -85225,9 +85225,9 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: s_and_b32 s1, s1, 0xffff
; GFX11-NEXT: v_readlane_b32 s17, v19, 29
; GFX11-NEXT: s_and_b32 s16, s16, 0xff
-; GFX11-NEXT: v_readlane_b32 s100, v17, 4
+; GFX11-NEXT: v_readlane_b32 s30, v17, 7
; GFX11-NEXT: s_and_b32 s2, s2, 0xff
-; GFX11-NEXT: v_readlane_b32 s99, v17, 3
+; GFX11-NEXT: v_readlane_b32 s31, v17, 8
; GFX11-NEXT: s_or_b32 s2, s2, s3
; GFX11-NEXT: s_and_b32 s3, s18, 0xff
; GFX11-NEXT: s_lshl_b32 s2, s2, 16
@@ -85261,7 +85261,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: s_or_b32 s16, s16, s17
; GFX11-NEXT: v_readlane_b32 s17, v19, 21
; GFX11-NEXT: s_lshl_b32 s16, s16, 16
-; GFX11-NEXT: v_readlane_b32 s98, v17, 2
+; GFX11-NEXT: v_readlane_b32 s100, v17, 2
; GFX11-NEXT: s_or_b32 s3, s3, s16
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3
@@ -85281,12 +85281,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: s_or_b32 s0, s0, s1
; GFX11-NEXT: s_and_b32 s1, s21, 0xff
; GFX11-NEXT: s_lshl_b32 s2, s2, 8
-; GFX11-NEXT: v_readlane_b32 s86, v16, 30
+; GFX11-NEXT: v_readlane_b32 s99, v17, 1
; GFX11-NEXT: s_or_b32 s1, s1, s2
; GFX11-NEXT: v_readlane_b32 s2, v19, 25
; GFX11-NEXT: s_and_b32 s1, s1, 0xffff
-; GFX11-NEXT: v_readlane_b32 s31, v16, 1
-; GFX11-NEXT: v_readlane_b32 s30, v16, 0
+; GFX11-NEXT: v_readlane_b32 s98, v17, 0
+; GFX11-NEXT: v_readlane_b32 s86, v16, 28
; GFX11-NEXT: s_and_b32 s2, s2, 0xff
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s2, s2, s3
@@ -85323,9 +85323,9 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: s_lshl_b32 s3, s88, 8
; GFX11-NEXT: s_and_b32 s16, s69, 0xff
; GFX11-NEXT: s_and_b32 s18, s72, 0xff
-; GFX11-NEXT: v_readlane_b32 s97, v17, 1
+; GFX11-NEXT: v_readlane_b32 s97, v16, 31
; GFX11-NEXT: s_and_b32 s2, s2, 0xff
-; GFX11-NEXT: v_readlane_b32 s69, v16, 21
+; GFX11-NEXT: v_readlane_b32 s69, v16, 19
; GFX11-NEXT: s_or_b32 s1, s2, s3
; GFX11-NEXT: v_readlane_b32 s3, v19, 16
; GFX11-NEXT: s_and_b32 s2, s25, 0xff
@@ -85532,39 +85532,39 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:80
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:96
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:112
-; GFX11-NEXT: v_readlane_b32 s104, v17, 8
-; GFX11-NEXT: v_readlane_b32 s103, v17, 7
-; GFX11-NEXT: v_readlane_b32 s102, v17, 6
-; GFX11-NEXT: v_readlane_b32 s101, v17, 5
-; GFX11-NEXT: v_readlane_b32 s96, v17, 0
-; GFX11-NEXT: v_readlane_b32 s87, v16, 31
-; GFX11-NEXT: v_readlane_b32 s85, v16, 29
-; GFX11-NEXT: v_readlane_b32 s84, v16, 28
-; GFX11-NEXT: v_readlane_b32 s83, v16, 27
-; GFX11-NEXT: v_readlane_b32 s82, v16, 26
-; GFX11-NEXT: v_readlane_b32 s81, v16, 25
-; GFX11-NEXT: v_readlane_b32 s80, v16, 24
-; GFX11-NEXT: v_readlane_b32 s71, v16, 23
-; GFX11-NEXT: v_readlane_b32 s70, v16, 22
-; GFX11-NEXT: v_readlane_b32 s68, v16, 20
-; GFX11-NEXT: v_readlane_b32 s67, v16, 19
-; GFX11-NEXT: v_readlane_b32 s66, v16, 18
-; GFX11-NEXT: v_readlane_b32 s65, v16, 17
-; GFX11-NEXT: v_readlane_b32 s64, v16, 16
-; GFX11-NEXT: v_readlane_b32 s55, v16, 15
-; GFX11-NEXT: v_readlane_b32 s54, v16, 14
-; GFX11-NEXT: v_readlane_b32 s53, v16, 13
-; GFX11-NEXT: v_readlane_b32 s52, v16, 12
-; GFX11-NEXT: v_readlane_b32 s51, v16, 11
-; GFX11-NEXT: v_readlane_b32 s50, v16, 10
-; GFX11-NEXT: v_readlane_b32 s49, v16, 9
-; GFX11-NEXT: v_readlane_b32 s48, v16, 8
-; GFX11-NEXT: v_readlane_b32 s39, v16, 7
-; GFX11-NEXT: v_readlane_b32 s38, v16, 6
-; GFX11-NEXT: v_readlane_b32 s37, v16, 5
-; GFX11-NEXT: v_readlane_b32 s36, v16, 4
-; GFX11-NEXT: v_readlane_b32 s35, v16, 3
-; GFX11-NEXT: v_readlane_b32 s34, v16, 2
+; GFX11-NEXT: v_readlane_b32 s104, v17, 6
+; GFX11-NEXT: v_readlane_b32 s103, v17, 5
+; GFX11-NEXT: v_readlane_b32 s102, v17, 4
+; GFX11-NEXT: v_readlane_b32 s101, v17, 3
+; GFX11-NEXT: v_readlane_b32 s96, v16, 30
+; GFX11-NEXT: v_readlane_b32 s87, v16, 29
+; GFX11-NEXT: v_readlane_b32 s85, v16, 27
+; GFX11-NEXT: v_readlane_b32 s84, v16, 26
+; GFX11-NEXT: v_readlane_b32 s83, v16, 25
+; GFX11-NEXT: v_readlane_b32 s82, v16, 24
+; GFX11-NEXT: v_readlane_b32 s81, v16, 23
+; GFX11-NEXT: v_readlane_b32 s80, v16, 22
+; GFX11-NEXT: v_readlane_b32 s71, v16, 21
+; GFX11-NEXT: v_readlane_b32 s70, v16, 20
+; GFX11-NEXT: v_readlane_b32 s68, v16, 18
+; GFX11-NEXT: v_readlane_b32 s67, v16, 17
+; GFX11-NEXT: v_readlane_b32 s66, v16, 16
+; GFX11-NEXT: v_readlane_b32 s65, v16, 15
+; GFX11-NEXT: v_readlane_b32 s64, v16, 14
+; GFX11-NEXT: v_readlane_b32 s55, v16, 13
+; GFX11-NEXT: v_readlane_b32 s54, v16, 12
+; GFX11-NEXT: v_readlane_b32 s53, v16, 11
+; GFX11-NEXT: v_readlane_b32 s52, v16, 10
+; GFX11-NEXT: v_readlane_b32 s51, v16, 9
+; GFX11-NEXT: v_readlane_b32 s50, v16, 8
+; GFX11-NEXT: v_readlane_b32 s49, v16, 7
+; GFX11-NEXT: v_readlane_b32 s48, v16, 6
+; GFX11-NEXT: v_readlane_b32 s39, v16, 5
+; GFX11-NEXT: v_readlane_b32 s38, v16, 4
+; GFX11-NEXT: v_readlane_b32 s37, v16, 3
+; GFX11-NEXT: v_readlane_b32 s36, v16, 2
+; GFX11-NEXT: v_readlane_b32 s35, v16, 1
+; GFX11-NEXT: v_readlane_b32 s34, v16, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_load_b32 v16, off, s32
@@ -97464,43 +97464,42 @@ define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_writelane_b32 v20, s30, 0
-; SI-NEXT: v_writelane_b32 v20, s31, 1
-; SI-NEXT: v_writelane_b32 v20, s34, 2
-; SI-NEXT: v_writelane_b32 v20, s35, 3
-; SI-NEXT: v_writelane_b32 v20, s36, 4
-; SI-NEXT: v_writelane_b32 v20, s37, 5
-; SI-NEXT: v_writelane_b32 v20, s38, 6
-; SI-NEXT: v_writelane_b32 v20, s39, 7
-; SI-NEXT: v_writelane_b32 v20, s48, 8
-; SI-NEXT: v_writelane_b32 v20, s49, 9
-; SI-NEXT: v_writelane_b32 v20, s50, 10
-; SI-NEXT: v_writelane_b32 v20, s51, 11
-; SI-NEXT: v_writelane_b32 v20, s52, 12
-; SI-NEXT: v_writelane_b32 v20, s53, 13
-; SI-NEXT: v_writelane_b32 v20, s54, 14
-; SI-NEXT: v_writelane_b32 v20, s55, 15
-; SI-NEXT: v_writelane_b32 v20, s64, 16
-; SI-NEXT: v_writelane_b32 v20, s65, 17
-; SI-NEXT: v_writelane_b32 v20, s66, 18
-; SI-NEXT: v_writelane_b32 v20, s67, 19
-; SI-NEXT: v_writelane_b32 v20, s68, 20
-; SI-NEXT: v_writelane_b32 v20, s69, 21
-; SI-NEXT: v_writelane_b32 v20, s70, 22
-; SI-NEXT: v_writelane_b32 v20, s71, 23
-; SI-NEXT: v_writelane_b32 v20, s80, 24
-; SI-NEXT: v_writelane_b32 v20, s81, 25
-; SI-NEXT: v_writelane_b32 v20, s82, 26
-; SI-NEXT: v_writelane_b32 v20, s83, 27
-; SI-NEXT: v_writelane_b32 v20, s84, 28
-; SI-NEXT: v_writelane_b32 v20, s85, 29
-; SI-NEXT: v_writelane_b32 v20, s86, 30
-; SI-NEXT: v_writelane_b32 v20, s87, 31
-; SI-NEXT: v_writelane_b32 v20, s96, 32
-; SI-NEXT: v_writelane_b32 v20, s97, 33
-; SI-NEXT: v_writelane_b32 v20, s98, 34
+; SI-NEXT: v_writelane_b32 v20, s34, 0
+; SI-NEXT: v_writelane_b32 v20, s35, 1
+; SI-NEXT: v_writelane_b32 v20, s36, 2
+; SI-NEXT: v_writelane_b32 v20, s37, 3
+; SI-NEXT: v_writelane_b32 v20, s38, 4
+; SI-NEXT: v_writelane_b32 v20, s39, 5
+; SI-NEXT: v_writelane_b32 v20, s48, 6
+; SI-NEXT: v_writelane_b32 v20, s49, 7
+; SI-NEXT: v_writelane_b32 v20, s50, 8
+; SI-NEXT: v_writelane_b32 v20, s51, 9
+; SI-NEXT: v_writelane_b32 v20, s52, 10
+; SI-NEXT: v_writelane_b32 v20, s53, 11
+; SI-NEXT: v_writelane_b32 v20, s54, 12
+; SI-NEXT: v_writelane_b32 v20, s55, 13
+; SI-NEXT: v_writelane_b32 v20, s64, 14
+; SI-NEXT: v_writelane_b32 v20, s65, 15
+; SI-NEXT: v_writelane_b32 v20, s66, 16
+; SI-NEXT: v_writelane_b32 v20, s67, 17
+; SI-NEXT: v_writelane_b32 v20, s68, 18
+; SI-NEXT: v_writelane_b32 v20, s69, 19
+; SI-NEXT: v_writelane_b32 v20, s70, 20
+; SI-NEXT: v_writelane_b32 v20, s71, 21
+; SI-NEXT: v_writelane_b32 v20, s80, 22
+; SI-NEXT: v_writelane_b32 v20, s81, 23
+; SI-NEXT: v_writelane_b32 v20, s82, 24
+; SI-NEXT: v_writelane_b32 v20, s83, 25
+; SI-NEXT: v_writelane_b32 v20, s84, 26
+; SI-NEXT: v_writelane_b32 v20, s85, 27
+; SI-NEXT: v_writelane_b32 v20, s86, 28
+; SI-NEXT: v_writelane_b32 v20, s87, 29
+; SI-NEXT: v_writelane_b32 v20, s96, 30
+; SI-NEXT: v_writelane_b32 v20, s97, 31
+; SI-NEXT: v_writelane_b32 v20, s98, 32
+; SI-NEXT: v_writelane_b32 v20, s99, 33
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_writelane_b32 v20, s99, 35
+; SI-NEXT: v_writelane_b32 v20, s30, 34
; SI-NEXT: v_readfirstlane_b32 s70, v1
; SI-NEXT: v_readfirstlane_b32 s71, v2
; SI-NEXT: v_readfirstlane_b32 s80, v3
@@ -97520,6 +97519,7 @@ define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a
; SI-NEXT: v_readfirstlane_b32 s8, v17
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v18
+; SI-NEXT: v_writelane_b32 v20, s31, 35
; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB61_4
; SI-NEXT: ; %bb.1: ; %cmp.false
@@ -97921,43 +97921,43 @@ define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
+; SI-NEXT: v_readlane_b32 s30, v20, 34
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s99, v20, 35
-; SI-NEXT: v_readlane_b32 s98, v20, 34
-; SI-NEXT: v_readlane_b32 s97, v20, 33
-; SI-NEXT: v_readlane_b32 s96, v20, 32
-; SI-NEXT: v_readlane_b32 s87, v20, 31
-; SI-NEXT: v_readlane_b32 s86, v20, 30
-; SI-NEXT: v_readlane_b32 s85, v20, 29
-; SI-NEXT: v_readlane_b32 s84, v20, 28
-; SI-NEXT: v_readlane_b32 s83, v20, 27
-; SI-NEXT: v_readlane_b32 s82, v20, 26
-; SI-NEXT: v_readlane_b32 s81, v20, 25
-; SI-NEXT: v_readlane_b32 s80, v20, 24
-; SI-NEXT: v_readlane_b32 s71, v20, 23
-; SI-NEXT: v_readlane_b32 s70, v20, 22
-; SI-NEXT: v_readlane_b32 s69, v20, 21
-; SI-NEXT: v_readlane_b32 s68, v20, 20
-; SI-NEXT: v_readlane_b32 s67, v20, 19
-; SI-NEXT: v_readlane_b32 s66, v20, 18
-; SI-NEXT: v_readlane_b32 s65, v20, 17
-; SI-NEXT: v_readlane_b32 s64, v20, 16
-; SI-NEXT: v_readlane_b32 s55, v20, 15
-; SI-NEXT: v_readlane_b32 s54, v20, 14
-; SI-NEXT: v_readlane_b32 s53, v20, 13
-; SI-NEXT: v_readlane_b32 s52, v20, 12
-; SI-NEXT: v_readlane_b32 s51, v20, 11
-; SI-NEXT: v_readlane_b32 s50, v20, 10
-; SI-NEXT: v_readlane_b32 s49, v20, 9
-; SI-NEXT: v_readlane_b32 s48, v20, 8
-; SI-NEXT: v_readlane_b32 s39, v20, 7
-; SI-NEXT: v_readlane_b32 s38, v20, 6
-; SI-NEXT: v_readlane_b32 s37, v20, 5
-; SI-NEXT: v_readlane_b32 s36, v20, 4
-; SI-NEXT: v_readlane_b32 s35, v20, 3
-; SI-NEXT: v_readlane_b32 s34, v20, 2
-; SI-NEXT: v_readlane_b32 s31, v20, 1
-; SI-NEXT: v_readlane_b32 s30, v20, 0
+; SI-NEXT: v_readlane_b32 s31, v20, 35
+; SI-NEXT: v_readlane_b32 s99, v20, 33
+; SI-NEXT: v_readlane_b32 s98, v20, 32
+; SI-NEXT: v_readlane_b32 s97, v20, 31
+; SI-NEXT: v_readlane_b32 s96, v20, 30
+; SI-NEXT: v_readlane_b32 s87, v20, 29
+; SI-NEXT: v_readlane_b32 s86, v20, 28
+; SI-NEXT: v_readlane_b32 s85, v20, 27
+; SI-NEXT: v_readlane_b32 s84, v20, 26
+; SI-NEXT: v_readlane_b32 s83, v20, 25
+; SI-NEXT: v_readlane_b32 s82, v20, 24
+; SI-NEXT: v_readlane_b32 s81, v20, 23
+; SI-NEXT: v_readlane_b32 s80, v20, 22
+; SI-NEXT: v_readlane_b32 s71, v20, 21
+; SI-NEXT: v_readlane_b32 s70, v20, 20
+; SI-NEXT: v_readlane_b32 s69, v20, 19
+; SI-NEXT: v_readlane_b32 s68, v20, 18
+; SI-NEXT: v_readlane_b32 s67, v20, 17
+; SI-NEXT: v_readlane_b32 s66, v20, 16
+; SI-NEXT: v_readlane_b32 s65, v20, 15
+; SI-NEXT: v_readlane_b32 s64, v20, 14
+; SI-NEXT: v_readlane_b32 s55, v20, 13
+; SI-NEXT: v_readlane_b32 s54, v20, 12
+; SI-NEXT: v_readlane_b32 s53, v20, 11
+; SI-NEXT: v_readlane_b32 s52, v20, 10
+; SI-NEXT: v_readlane_b32 s51, v20, 9
+; SI-NEXT: v_readlane_b32 s50, v20, 8
+; SI-NEXT: v_readlane_b32 s49, v20, 7
+; SI-NEXT: v_readlane_b32 s48, v20, 6
+; SI-NEXT: v_readlane_b32 s39, v20, 5
+; SI-NEXT: v_readlane_b32 s38, v20, 4
+; SI-NEXT: v_readlane_b32 s37, v20, 3
+; SI-NEXT: v_readlane_b32 s36, v20, 2
+; SI-NEXT: v_readlane_b32 s35, v20, 1
+; SI-NEXT: v_readlane_b32 s34, v20, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -105962,11 +105962,11 @@ define inreg <64 x half> @bitcast_v16i64_to_v64f16_scalar(<16 x i64> inreg %a, i
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v63, s30, 0
-; SI-NEXT: v_writelane_b32 v63, s31, 1
-; SI-NEXT: v_writelane_b32 v63, s34, 2
+; SI-NEXT: v_writelane_b32 v63, s34, 0
+; SI-NEXT: v_writelane_b32 v63, s35, 1
+; SI-NEXT: v_writelane_b32 v63, s30, 2
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_writelane_b32 v63, s35, 3
+; SI-NEXT: v_writelane_b32 v63, s31, 3
; SI-NEXT: v_readfirstlane_b32 s46, v1
; SI-NEXT: v_readfirstlane_b32 s47, v2
; SI-NEXT: v_readfirstlane_b32 s44, v3
@@ -106242,15 +106242,15 @@ define inreg <64 x half> @bitcast_v16i64_to_v64f16_scalar(<16 x i64> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v61, v61
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NEXT: v_readlane_b32 s35, v63, 3
+; SI-NEXT: v_readlane_b32 s30, v63, 2
; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v61
; SI-NEXT: v_or_b32_e32 v2, v2, v61
; SI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v2, v59
-; SI-NEXT: v_readlane_b32 s34, v63, 2
-; SI-NEXT: v_readlane_b32 s31, v63, 1
-; SI-NEXT: v_readlane_b32 s30, v63, 0
+; SI-NEXT: v_readlane_b32 s31, v63, 3
+; SI-NEXT: v_readlane_b32 s35, v63, 1
+; SI-NEXT: v_readlane_b32 s34, v63, 0
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
@@ -109538,28 +109538,28 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v20, s30, 0
-; SI-NEXT: v_writelane_b32 v20, s31, 1
-; SI-NEXT: v_writelane_b32 v20, s34, 2
-; SI-NEXT: v_writelane_b32 v20, s35, 3
-; SI-NEXT: v_writelane_b32 v20, s36, 4
-; SI-NEXT: v_writelane_b32 v20, s37, 5
-; SI-NEXT: v_writelane_b32 v20, s38, 6
-; SI-NEXT: v_writelane_b32 v20, s39, 7
-; SI-NEXT: v_writelane_b32 v20, s48, 8
-; SI-NEXT: v_writelane_b32 v20, s49, 9
-; SI-NEXT: v_writelane_b32 v20, s50, 10
-; SI-NEXT: v_writelane_b32 v20, s51, 11
-; SI-NEXT: v_writelane_b32 v20, s52, 12
-; SI-NEXT: v_writelane_b32 v20, s53, 13
-; SI-NEXT: v_writelane_b32 v20, s54, 14
-; SI-NEXT: v_writelane_b32 v20, s55, 15
-; SI-NEXT: v_writelane_b32 v20, s64, 16
-; SI-NEXT: v_writelane_b32 v20, s65, 17
-; SI-NEXT: v_writelane_b32 v20, s66, 18
-; SI-NEXT: v_writelane_b32 v20, s67, 19
+; SI-NEXT: v_writelane_b32 v20, s34, 0
+; SI-NEXT: v_writelane_b32 v20, s35, 1
+; SI-NEXT: v_writelane_b32 v20, s36, 2
+; SI-NEXT: v_writelane_b32 v20, s37, 3
+; SI-NEXT: v_writelane_b32 v20, s38, 4
+; SI-NEXT: v_writelane_b32 v20, s39, 5
+; SI-NEXT: v_writelane_b32 v20, s48, 6
+; SI-NEXT: v_writelane_b32 v20, s49, 7
+; SI-NEXT: v_writelane_b32 v20, s50, 8
+; SI-NEXT: v_writelane_b32 v20, s51, 9
+; SI-NEXT: v_writelane_b32 v20, s52, 10
+; SI-NEXT: v_writelane_b32 v20, s53, 11
+; SI-NEXT: v_writelane_b32 v20, s54, 12
+; SI-NEXT: v_writelane_b32 v20, s55, 13
+; SI-NEXT: v_writelane_b32 v20, s64, 14
+; SI-NEXT: v_writelane_b32 v20, s65, 15
+; SI-NEXT: v_writelane_b32 v20, s66, 16
+; SI-NEXT: v_writelane_b32 v20, s67, 17
+; SI-NEXT: v_writelane_b32 v20, s68, 18
+; SI-NEXT: v_writelane_b32 v20, s69, 19
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_writelane_b32 v20, s68, 20
+; SI-NEXT: v_writelane_b32 v20, s30, 20
; SI-NEXT: v_readfirstlane_b32 s44, v1
; SI-NEXT: v_readfirstlane_b32 s45, v2
; SI-NEXT: v_readfirstlane_b32 s42, v3
@@ -109579,7 +109579,7 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v17
; SI-NEXT: s_and_b64 s[46:47], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v18
-; SI-NEXT: v_writelane_b32 v20, s69, 21
+; SI-NEXT: v_writelane_b32 v20, s31, 21
; SI-NEXT: s_cbranch_scc0 .LBB69_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s38, s5, 16
@@ -109898,29 +109898,29 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v20, 20
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s69, v20, 21
-; SI-NEXT: v_readlane_b32 s68, v20, 20
-; SI-NEXT: v_readlane_b32 s67, v20, 19
-; SI-NEXT: v_readlane_b32 s66, v20, 18
-; SI-NEXT: v_readlane_b32 s65, v20, 17
-; SI-NEXT: v_readlane_b32 s64, v20, 16
-; SI-NEXT: v_readlane_b32 s55, v20, 15
-; SI-NEXT: v_readlane_b32 s54, v20, 14
-; SI-NEXT: v_readlane_b32 s53, v20, 13
-; SI-NEXT: v_readlane_b32 s52, v20, 12
-; SI-NEXT: v_readlane_b32 s51, v20, 11
-; SI-NEXT: v_readlane_b32 s50, v20, 10
-; SI-NEXT: v_readlane_b32 s49, v20, 9
-; SI-NEXT: v_readlane_b32 s48, v20, 8
-; SI-NEXT: v_readlane_b32 s39, v20, 7
-; SI-NEXT: v_readlane_b32 s38, v20, 6
-; SI-NEXT: v_readlane_b32 s37, v20, 5
-; SI-NEXT: v_readlane_b32 s36, v20, 4
-; SI-NEXT: v_readlane_b32 s35, v20, 3
-; SI-NEXT: v_readlane_b32 s34, v20, 2
-; SI-NEXT: v_readlane_b32 s31, v20, 1
-; SI-NEXT: v_readlane_b32 s30, v20, 0
+; SI-NEXT: v_readlane_b32 s31, v20, 21
+; SI-NEXT: v_readlane_b32 s69, v20, 19
+; SI-NEXT: v_readlane_b32 s68, v20, 18
+; SI-NEXT: v_readlane_b32 s67, v20, 17
+; SI-NEXT: v_readlane_b32 s66, v20, 16
+; SI-NEXT: v_readlane_b32 s65, v20, 15
+; SI-NEXT: v_readlane_b32 s64, v20, 14
+; SI-NEXT: v_readlane_b32 s55, v20, 13
+; SI-NEXT: v_readlane_b32 s54, v20, 12
+; SI-NEXT: v_readlane_b32 s53, v20, 11
+; SI-NEXT: v_readlane_b32 s52, v20, 10
+; SI-NEXT: v_readlane_b32 s51, v20, 9
+; SI-NEXT: v_readlane_b32 s50, v20, 8
+; SI-NEXT: v_readlane_b32 s49, v20, 7
+; SI-NEXT: v_readlane_b32 s48, v20, 6
+; SI-NEXT: v_readlane_b32 s39, v20, 5
+; SI-NEXT: v_readlane_b32 s38, v20, 4
+; SI-NEXT: v_readlane_b32 s37, v20, 3
+; SI-NEXT: v_readlane_b32 s36, v20, 2
+; SI-NEXT: v_readlane_b32 s35, v20, 1
+; SI-NEXT: v_readlane_b32 s34, v20, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
@@ -116322,43 +116322,43 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_writelane_b32 v63, s30, 0
-; SI-NEXT: v_writelane_b32 v63, s31, 1
-; SI-NEXT: v_writelane_b32 v63, s34, 2
-; SI-NEXT: v_writelane_b32 v63, s35, 3
-; SI-NEXT: v_writelane_b32 v63, s36, 4
-; SI-NEXT: v_writelane_b32 v63, s37, 5
-; SI-NEXT: v_writelane_b32 v63, s38, 6
-; SI-NEXT: v_writelane_b32 v63, s39, 7
-; SI-NEXT: v_writelane_b32 v63, s48, 8
-; SI-NEXT: v_writelane_b32 v63, s49, 9
-; SI-NEXT: v_writelane_b32 v63, s50, 10
-; SI-NEXT: v_writelane_b32 v63, s51, 11
-; SI-NEXT: v_writelane_b32 v63, s52, 12
-; SI-NEXT: v_writelane_b32 v63, s53, 13
-; SI-NEXT: v_writelane_b32 v63, s54, 14
-; SI-NEXT: v_writelane_b32 v63, s55, 15
-; SI-NEXT: v_writelane_b32 v63, s64, 16
-; SI-NEXT: v_writelane_b32 v63, s65, 17
-; SI-NEXT: v_writelane_b32 v63, s66, 18
-; SI-NEXT: v_writelane_b32 v63, s67, 19
-; SI-NEXT: v_writelane_b32 v63, s68, 20
-; SI-NEXT: v_writelane_b32 v63, s69, 21
-; SI-NEXT: v_writelane_b32 v63, s70, 22
-; SI-NEXT: v_writelane_b32 v63, s71, 23
-; SI-NEXT: v_writelane_b32 v63, s80, 24
-; SI-NEXT: v_writelane_b32 v63, s81, 25
-; SI-NEXT: v_writelane_b32 v63, s82, 26
-; SI-NEXT: v_writelane_b32 v63, s83, 27
-; SI-NEXT: v_writelane_b32 v63, s84, 28
-; SI-NEXT: v_writelane_b32 v63, s85, 29
-; SI-NEXT: v_writelane_b32 v63, s86, 30
-; SI-NEXT: v_writelane_b32 v63, s87, 31
-; SI-NEXT: v_writelane_b32 v63, s96, 32
-; SI-NEXT: v_writelane_b32 v63, s97, 33
-; SI-NEXT: v_writelane_b32 v63, s98, 34
+; SI-NEXT: v_writelane_b32 v63, s34, 0
+; SI-NEXT: v_writelane_b32 v63, s35, 1
+; SI-NEXT: v_writelane_b32 v63, s36, 2
+; SI-NEXT: v_writelane_b32 v63, s37, 3
+; SI-NEXT: v_writelane_b32 v63, s38, 4
+; SI-NEXT: v_writelane_b32 v63, s39, 5
+; SI-NEXT: v_writelane_b32 v63, s48, 6
+; SI-NEXT: v_writelane_b32 v63, s49, 7
+; SI-NEXT: v_writelane_b32 v63, s50, 8
+; SI-NEXT: v_writelane_b32 v63, s51, 9
+; SI-NEXT: v_writelane_b32 v63, s52, 10
+; SI-NEXT: v_writelane_b32 v63, s53, 11
+; SI-NEXT: v_writelane_b32 v63, s54, 12
+; SI-NEXT: v_writelane_b32 v63, s55, 13
+; SI-NEXT: v_writelane_b32 v63, s64, 14
+; SI-NEXT: v_writelane_b32 v63, s65, 15
+; SI-NEXT: v_writelane_b32 v63, s66, 16
+; SI-NEXT: v_writelane_b32 v63, s67, 17
+; SI-NEXT: v_writelane_b32 v63, s68, 18
+; SI-NEXT: v_writelane_b32 v63, s69, 19
+; SI-NEXT: v_writelane_b32 v63, s70, 20
+; SI-NEXT: v_writelane_b32 v63, s71, 21
+; SI-NEXT: v_writelane_b32 v63, s80, 22
+; SI-NEXT: v_writelane_b32 v63, s81, 23
+; SI-NEXT: v_writelane_b32 v63, s82, 24
+; SI-NEXT: v_writelane_b32 v63, s83, 25
+; SI-NEXT: v_writelane_b32 v63, s84, 26
+; SI-NEXT: v_writelane_b32 v63, s85, 27
+; SI-NEXT: v_writelane_b32 v63, s86, 28
+; SI-NEXT: v_writelane_b32 v63, s87, 29
+; SI-NEXT: v_writelane_b32 v63, s96, 30
+; SI-NEXT: v_writelane_b32 v63, s97, 31
+; SI-NEXT: v_writelane_b32 v63, s98, 32
+; SI-NEXT: v_writelane_b32 v63, s99, 33
+; SI-NEXT: v_writelane_b32 v63, s30, 34
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_writelane_b32 v63, s99, 35
+; SI-NEXT: v_writelane_b32 v63, s31, 35
; SI-NEXT: v_readfirstlane_b32 s4, v1
; SI-NEXT: v_readfirstlane_b32 s5, v2
; SI-NEXT: v_readfirstlane_b32 s6, v3
@@ -117476,42 +117476,42 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_readlane_b32 s99, v63, 35
-; SI-NEXT: v_readlane_b32 s98, v63, 34
-; SI-NEXT: v_readlane_b32 s97, v63, 33
-; SI-NEXT: v_readlane_b32 s96, v63, 32
-; SI-NEXT: v_readlane_b32 s87, v63, 31
-; SI-NEXT: v_readlane_b32 s86, v63, 30
-; SI-NEXT: v_readlane_b32 s85, v63, 29
-; SI-NEXT: v_readlane_b32 s84, v63, 28
-; SI-NEXT: v_readlane_b32 s83, v63, 27
-; SI-NEXT: v_readlane_b32 s82, v63, 26
-; SI-NEXT: v_readlane_b32 s81, v63, 25
-; SI-NEXT: v_readlane_b32 s80, v63, 24
-; SI-NEXT: v_readlane_b32 s71, v63, 23
-; SI-NEXT: v_readlane_b32 s70, v63, 22
-; SI-NEXT: v_readlane_b32 s69, v63, 21
-; SI-NEXT: v_readlane_b32 s68, v63, 20
-; SI-NEXT: v_readlane_b32 s67, v63, 19
-; SI-NEXT: v_readlane_b32 s66, v63, 18
-; SI-NEXT: v_readlane_b32 s65, v63, 17
-; SI-NEXT: v_readlane_b32 s64, v63, 16
-; SI-NEXT: v_readlane_b32 s55, v63, 15
-; SI-NEXT: v_readlane_b32 s54, v63, 14
-; SI-NEXT: v_readlane_b32 s53, v63, 13
-; SI-NEXT: v_readlane_b32 s52, v63, 12
-; SI-NEXT: v_readlane_b32 s51, v63, 11
-; SI-NEXT: v_readlane_b32 s50, v63, 10
-; SI-NEXT: v_readlane_b32 s49, v63, 9
-; SI-NEXT: v_readlane_b32 s48, v63, 8
-; SI-NEXT: v_readlane_b32 s39, v63, 7
-; SI-NEXT: v_readlane_b32 s38, v63, 6
-; SI-NEXT: v_readlane_b32 s37, v63, 5
-; SI-NEXT: v_readlane_b32 s36, v63, 4
-; SI-NEXT: v_readlane_b32 s35, v63, 3
-; SI-NEXT: v_readlane_b32 s34, v63, 2
-; SI-NEXT: v_readlane_b32 s31, v63, 1
-; SI-NEXT: v_readlane_b32 s30, v63, 0
+; SI-NEXT: v_readlane_b32 s30, v63, 34
+; SI-NEXT: v_readlane_b32 s31, v63, 35
+; SI-NEXT: v_readlane_b32 s99, v63, 33
+; SI-NEXT: v_readlane_b32 s98, v63, 32
+; SI-NEXT: v_readlane_b32 s97, v63, 31
+; SI-NEXT: v_readlane_b32 s96, v63, 30
+; SI-NEXT: v_readlane_b32 s87, v63, 29
+; SI-NEXT: v_readlane_b32 s86, v63, 28
+; SI-NEXT: v_readlane_b32 s85, v63, 27
+; SI-NEXT: v_readlane_b32 s84, v63, 26
+; SI-NEXT: v_readlane_b32 s83, v63, 25
+; SI-NEXT: v_readlane_b32 s82, v63, 24
+; SI-NEXT: v_readlane_b32 s81, v63, 23
+; SI-NEXT: v_readlane_b32 s80, v63, 22
+; SI-NEXT: v_readlane_b32 s71, v63, 21
+; SI-NEXT: v_readlane_b32 s70, v63, 20
+; SI-NEXT: v_readlane_b32 s69, v63, 19
+; SI-NEXT: v_readlane_b32 s68, v63, 18
+; SI-NEXT: v_readlane_b32 s67, v63, 17
+; SI-NEXT: v_readlane_b32 s66, v63, 16
+; SI-NEXT: v_readlane_b32 s65, v63, 15
+; SI-NEXT: v_readlane_b32 s64, v63, 14
+; SI-NEXT: v_readlane_b32 s55, v63, 13
+; SI-NEXT: v_readlane_b32 s54, v63, 12
+; SI-NEXT: v_readlane_b32 s53, v63, 11
+; SI-NEXT: v_readlane_b32 s52, v63, 10
+; SI-NEXT: v_readlane_b32 s51, v63, 9
+; SI-NEXT: v_readlane_b32 s50, v63, 8
+; SI-NEXT: v_readlane_b32 s49, v63, 7
+; SI-NEXT: v_readlane_b32 s48, v63, 6
+; SI-NEXT: v_readlane_b32 s39, v63, 5
+; SI-NEXT: v_readlane_b32 s38, v63, 4
+; SI-NEXT: v_readlane_b32 s37, v63, 3
+; SI-NEXT: v_readlane_b32 s36, v63, 2
+; SI-NEXT: v_readlane_b32 s35, v63, 1
+; SI-NEXT: v_readlane_b32 s34, v63, 0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
@@ -118039,39 +118039,39 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v63, s30, 0
-; VI-NEXT: v_writelane_b32 v63, s31, 1
-; VI-NEXT: v_writelane_b32 v63, s34, 2
-; VI-NEXT: v_writelane_b32 v63, s35, 3
-; VI-NEXT: v_writelane_b32 v63, s36, 4
-; VI-NEXT: v_writelane_b32 v63, s37, 5
-; VI-NEXT: v_writelane_b32 v63, s38, 6
-; VI-NEXT: v_writelane_b32 v63, s39, 7
-; VI-NEXT: v_writelane_b32 v63, s48, 8
-; VI-NEXT: v_writelane_b32 v63, s49, 9
-; VI-NEXT: v_writelane_b32 v63, s50, 10
-; VI-NEXT: v_writelane_b32 v63, s51, 11
-; VI-NEXT: v_writelane_b32 v63, s52, 12
-; VI-NEXT: v_writelane_b32 v63, s53, 13
-; VI-NEXT: v_writelane_b32 v63, s54, 14
-; VI-NEXT: v_writelane_b32 v63, s55, 15
-; VI-NEXT: v_writelane_b32 v63, s64, 16
-; VI-NEXT: v_writelane_b32 v63, s65, 17
-; VI-NEXT: v_writelane_b32 v63, s66, 18
-; VI-NEXT: v_writelane_b32 v63, s67, 19
-; VI-NEXT: v_writelane_b32 v63, s68, 20
-; VI-NEXT: v_writelane_b32 v63, s69, 21
-; VI-NEXT: v_writelane_b32 v63, s70, 22
-; VI-NEXT: v_writelane_b32 v63, s71, 23
-; VI-NEXT: v_writelane_b32 v63, s80, 24
-; VI-NEXT: v_writelane_b32 v63, s81, 25
-; VI-NEXT: v_writelane_b32 v63, s82, 26
-; VI-NEXT: v_writelane_b32 v63, s83, 27
-; VI-NEXT: v_writelane_b32 v63, s84, 28
-; VI-NEXT: v_writelane_b32 v63, s85, 29
-; VI-NEXT: v_writelane_b32 v63, s86, 30
+; VI-NEXT: v_writelane_b32 v63, s34, 0
+; VI-NEXT: v_writelane_b32 v63, s35, 1
+; VI-NEXT: v_writelane_b32 v63, s36, 2
+; VI-NEXT: v_writelane_b32 v63, s37, 3
+; VI-NEXT: v_writelane_b32 v63, s38, 4
+; VI-NEXT: v_writelane_b32 v63, s39, 5
+; VI-NEXT: v_writelane_b32 v63, s48, 6
+; VI-NEXT: v_writelane_b32 v63, s49, 7
+; VI-NEXT: v_writelane_b32 v63, s50, 8
+; VI-NEXT: v_writelane_b32 v63, s51, 9
+; VI-NEXT: v_writelane_b32 v63, s52, 10
+; VI-NEXT: v_writelane_b32 v63, s53, 11
+; VI-NEXT: v_writelane_b32 v63, s54, 12
+; VI-NEXT: v_writelane_b32 v63, s55, 13
+; VI-NEXT: v_writelane_b32 v63, s64, 14
+; VI-NEXT: v_writelane_b32 v63, s65, 15
+; VI-NEXT: v_writelane_b32 v63, s66, 16
+; VI-NEXT: v_writelane_b32 v63, s67, 17
+; VI-NEXT: v_writelane_b32 v63, s68, 18
+; VI-NEXT: v_writelane_b32 v63, s69, 19
+; VI-NEXT: v_writelane_b32 v63, s70, 20
+; VI-NEXT: v_writelane_b32 v63, s71, 21
+; VI-NEXT: v_writelane_b32 v63, s80, 22
+; VI-NEXT: v_writelane_b32 v63, s81, 23
+; VI-NEXT: v_writelane_b32 v63, s82, 24
+; VI-NEXT: v_writelane_b32 v63, s83, 25
+; VI-NEXT: v_writelane_b32 v63, s84, 26
+; VI-NEXT: v_writelane_b32 v63, s85, 27
+; VI-NEXT: v_writelane_b32 v63, s86, 28
+; VI-NEXT: v_writelane_b32 v63, s87, 29
+; VI-NEXT: v_writelane_b32 v63, s30, 30
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; VI-NEXT: v_writelane_b32 v63, s87, 31
+; VI-NEXT: v_writelane_b32 v63, s31, 31
; VI-NEXT: v_readfirstlane_b32 s6, v1
; VI-NEXT: v_readfirstlane_b32 s7, v2
; VI-NEXT: v_readfirstlane_b32 s8, v3
@@ -118901,38 +118901,38 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
; VI-NEXT: v_or_b32_sdwa v32, v32, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_readlane_b32 s87, v63, 31
-; VI-NEXT: v_readlane_b32 s86, v63, 30
-; VI-NEXT: v_readlane_b32 s85, v63, 29
-; VI-NEXT: v_readlane_b32 s84, v63, 28
-; VI-NEXT: v_readlane_b32 s83, v63, 27
-; VI-NEXT: v_readlane_b32 s82, v63, 26
-; VI-NEXT: v_readlane_b32 s81, v63, 25
-; VI-NEXT: v_readlane_b32 s80, v63, 24
-; VI-NEXT: v_readlane_b32 s71, v63, 23
-; VI-NEXT: v_readlane_b32 s70, v63, 22
-; VI-NEXT: v_readlane_b32 s69, v63, 21
-; VI-NEXT: v_readlane_b32 s68, v63, 20
-; VI-NEXT: v_readlane_b32 s67, v63, 19
-; VI-NEXT: v_readlane_b32 s66, v63, 18
-; VI-NEXT: v_readlane_b32 s65, v63, 17
-; VI-NEXT: v_readlane_b32 s64, v63, 16
-; VI-NEXT: v_readlane_b32 s55, v63, 15
-; VI-NEXT: v_readlane_b32 s54, v63, 14
-; VI-NEXT: v_readlane_b32 s53, v63, 13
-; VI-NEXT: v_readlane_b32 s52, v63, 12
-; VI-NEXT: v_readlane_b32 s51, v63, 11
-; VI-NEXT: v_readlane_b32 s50, v63, 10
-; VI-NEXT: v_readlane_b32 s49, v63, 9
-; VI-NEXT: v_readlane_b32 s48, v63, 8
-; VI-NEXT: v_readlane_b32 s39, v63, 7
-; VI-NEXT: v_readlane_b32 s38, v63, 6
-; VI-NEXT: v_readlane_b32 s37, v63, 5
-; VI-NEXT: v_readlane_b32 s36, v63, 4
-; VI-NEXT: v_readlane_b32 s35, v63, 3
-; VI-NEXT: v_readlane_b32 s34, v63, 2
-; VI-NEXT: v_readlane_b32 s31, v63, 1
-; VI-NEXT: v_readlane_b32 s30, v63, 0
+; VI-NEXT: v_readlane_b32 s30, v63, 30
+; VI-NEXT: v_readlane_b32 s31, v63, 31
+; VI-NEXT: v_readlane_b32 s87, v63, 29
+; VI-NEXT: v_readlane_b32 s86, v63, 28
+; VI-NEXT: v_readlane_b32 s85, v63, 27
+; VI-NEXT: v_readlane_b32 s84, v63, 26
+; VI-NEXT: v_readlane_b32 s83, v63, 25
+; VI-NEXT: v_readlane_b32 s82, v63, 24
+; VI-NEXT: v_readlane_b32 s81, v63, 23
+; VI-NEXT: v_readlane_b32 s80, v63, 22
+; VI-NEXT: v_readlane_b32 s71, v63, 21
+; VI-NEXT: v_readlane_b32 s70, v63, 20
+; VI-NEXT: v_readlane_b32 s69, v63, 19
+; VI-NEXT: v_readlane_b32 s68, v63, 18
+; VI-NEXT: v_readlane_b32 s67, v63, 17
+; VI-NEXT: v_readlane_b32 s66, v63, 16
+; VI-NEXT: v_readlane_b32 s65, v63, 15
+; VI-NEXT: v_readlane_b32 s64, v63, 14
+; VI-NEXT: v_readlane_b32 s55, v63, 13
+; VI-NEXT: v_readlane_b32 s54, v63, 12
+; VI-NEXT: v_readlane_b32 s53, v63, 11
+; VI-NEXT: v_readlane_b32 s52, v63, 10
+; VI-NEXT: v_readlane_b32 s51, v63, 9
+; VI-NEXT: v_readlane_b32 s50, v63, 8
+; VI-NEXT: v_readlane_b32 s49, v63, 7
+; VI-NEXT: v_readlane_b32 s48, v63, 6
+; VI-NEXT: v_readlane_b32 s39, v63, 5
+; VI-NEXT: v_readlane_b32 s38, v63, 4
+; VI-NEXT: v_readlane_b32 s37, v63, 3
+; VI-NEXT: v_readlane_b32 s36, v63, 2
+; VI-NEXT: v_readlane_b32 s35, v63, 1
+; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_lshlrev_b32_e32 v34, 8, v42
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -119323,43 +119323,43 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v63, s30, 0
-; GFX9-NEXT: v_writelane_b32 v63, s31, 1
-; GFX9-NEXT: v_writelane_b32 v63, s34, 2
-; GFX9-NEXT: v_writelane_b32 v63, s35, 3
-; GFX9-NEXT: v_writelane_b32 v63, s36, 4
-; GFX9-NEXT: v_writelane_b32 v63, s37, 5
-; GFX9-NEXT: v_writelane_b32 v63, s38, 6
-; GFX9-NEXT: v_writelane_b32 v63, s39, 7
-; GFX9-NEXT: v_writelane_b32 v63, s48, 8
-; GFX9-NEXT: v_writelane_b32 v63, s49, 9
-; GFX9-NEXT: v_writelane_b32 v63, s50, 10
-; GFX9-NEXT: v_writelane_b32 v63, s51, 11
-; GFX9-NEXT: v_writelane_b32 v63, s52, 12
-; GFX9-NEXT: v_writelane_b32 v63, s53, 13
-; GFX9-NEXT: v_writelane_b32 v63, s54, 14
-; GFX9-NEXT: v_writelane_b32 v63, s55, 15
-; GFX9-NEXT: v_writelane_b32 v63, s64, 16
-; GFX9-NEXT: v_writelane_b32 v63, s65, 17
-; GFX9-NEXT: v_writelane_b32 v63, s66, 18
-; GFX9-NEXT: v_writelane_b32 v63, s67, 19
-; GFX9-NEXT: v_writelane_b32 v63, s68, 20
-; GFX9-NEXT: v_writelane_b32 v63, s69, 21
-; GFX9-NEXT: v_writelane_b32 v63, s70, 22
-; GFX9-NEXT: v_writelane_b32 v63, s71, 23
-; GFX9-NEXT: v_writelane_b32 v63, s80, 24
-; GFX9-NEXT: v_writelane_b32 v63, s81, 25
-; GFX9-NEXT: v_writelane_b32 v63, s82, 26
-; GFX9-NEXT: v_writelane_b32 v63, s83, 27
-; GFX9-NEXT: v_writelane_b32 v63, s84, 28
-; GFX9-NEXT: v_writelane_b32 v63, s85, 29
-; GFX9-NEXT: v_writelane_b32 v63, s86, 30
-; GFX9-NEXT: v_writelane_b32 v63, s87, 31
-; GFX9-NEXT: v_writelane_b32 v63, s96, 32
-; GFX9-NEXT: v_writelane_b32 v63, s97, 33
-; GFX9-NEXT: v_writelane_b32 v63, s98, 34
+; GFX9-NEXT: v_writelane_b32 v63, s34, 0
+; GFX9-NEXT: v_writelane_b32 v63, s35, 1
+; GFX9-NEXT: v_writelane_b32 v63, s36, 2
+; GFX9-NEXT: v_writelane_b32 v63, s37, 3
+; GFX9-NEXT: v_writelane_b32 v63, s38, 4
+; GFX9-NEXT: v_writelane_b32 v63, s39, 5
+; GFX9-NEXT: v_writelane_b32 v63, s48, 6
+; GFX9-NEXT: v_writelane_b32 v63, s49, 7
+; GFX9-NEXT: v_writelane_b32 v63, s50, 8
+; GFX9-NEXT: v_writelane_b32 v63, s51, 9
+; GFX9-NEXT: v_writelane_b32 v63, s52, 10
+; GFX9-NEXT: v_writelane_b32 v63, s53, 11
+; GFX9-NEXT: v_writelane_b32 v63, s54, 12
+; GFX9-NEXT: v_writelane_b32 v63, s55, 13
+; GFX9-NEXT: v_writelane_b32 v63, s64, 14
+; GFX9-NEXT: v_writelane_b32 v63, s65, 15
+; GFX9-NEXT: v_writelane_b32 v63, s66, 16
+; GFX9-NEXT: v_writelane_b32 v63, s67, 17
+; GFX9-NEXT: v_writelane_b32 v63, s68, 18
+; GFX9-NEXT: v_writelane_b32 v63, s69, 19
+; GFX9-NEXT: v_writelane_b32 v63, s70, 20
+; GFX9-NEXT: v_writelane_b32 v63, s71, 21
+; GFX9-NEXT: v_writelane_b32 v63, s80, 22
+; GFX9-NEXT: v_writelane_b32 v63, s81, 23
+; GFX9-NEXT: v_writelane_b32 v63, s82, 24
+; GFX9-NEXT: v_writelane_b32 v63, s83, 25
+; GFX9-NEXT: v_writelane_b32 v63, s84, 26
+; GFX9-NEXT: v_writelane_b32 v63, s85, 27
+; GFX9-NEXT: v_writelane_b32 v63, s86, 28
+; GFX9-NEXT: v_writelane_b32 v63, s87, 29
+; GFX9-NEXT: v_writelane_b32 v63, s96, 30
+; GFX9-NEXT: v_writelane_b32 v63, s97, 31
+; GFX9-NEXT: v_writelane_b32 v63, s98, 32
+; GFX9-NEXT: v_writelane_b32 v63, s99, 33
+; GFX9-NEXT: v_writelane_b32 v63, s30, 34
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; GFX9-NEXT: v_writelane_b32 v63, s99, 35
+; GFX9-NEXT: v_writelane_b32 v63, s31, 35
; GFX9-NEXT: v_readfirstlane_b32 s6, v1
; GFX9-NEXT: v_readfirstlane_b32 s7, v2
; GFX9-NEXT: v_readfirstlane_b32 s8, v3
@@ -120215,42 +120215,42 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: v_or_b32_sdwa v18, v38, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v38, 8, v41
; GFX9-NEXT: v_or_b32_sdwa v35, v35, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_readlane_b32 s99, v63, 35
-; GFX9-NEXT: v_readlane_b32 s98, v63, 34
-; GFX9-NEXT: v_readlane_b32 s97, v63, 33
-; GFX9-NEXT: v_readlane_b32 s96, v63, 32
-; GFX9-NEXT: v_readlane_b32 s87, v63, 31
-; GFX9-NEXT: v_readlane_b32 s86, v63, 30
-; GFX9-NEXT: v_readlane_b32 s85, v63, 29
-; GFX9-NEXT: v_readlane_b32 s84, v63, 28
-; GFX9-NEXT: v_readlane_b32 s83, v63, 27
-; GFX9-NEXT: v_readlane_b32 s82, v63, 26
-; GFX9-NEXT: v_readlane_b32 s81, v63, 25
-; GFX9-NEXT: v_readlane_b32 s80, v63, 24
-; GFX9-NEXT: v_readlane_b32 s71, v63, 23
-; GFX9-NEXT: v_readlane_b32 s70, v63, 22
-; GFX9-NEXT: v_readlane_b32 s69, v63, 21
-; GFX9-NEXT: v_readlane_b32 s68, v63, 20
-; GFX9-NEXT: v_readlane_b32 s67, v63, 19
-; GFX9-NEXT: v_readlane_b32 s66, v63, 18
-; GFX9-NEXT: v_readlane_b32 s65, v63, 17
-; GFX9-NEXT: v_readlane_b32 s64, v63, 16
-; GFX9-NEXT: v_readlane_b32 s55, v63, 15
-; GFX9-NEXT: v_readlane_b32 s54, v63, 14
-; GFX9-NEXT: v_readlane_b32 s53, v63, 13
-; GFX9-NEXT: v_readlane_b32 s52, v63, 12
-; GFX9-NEXT: v_readlane_b32 s51, v63, 11
-; GFX9-NEXT: v_readlane_b32 s50, v63, 10
-; GFX9-NEXT: v_readlane_b32 s49, v63, 9
-; GFX9-NEXT: v_readlane_b32 s48, v63, 8
-; GFX9-NEXT: v_readlane_b32 s39, v63, 7
-; GFX9-NEXT: v_readlane_b32 s38, v63, 6
-; GFX9-NEXT: v_readlane_b32 s37, v63, 5
-; GFX9-NEXT: v_readlane_b32 s36, v63, 4
-; GFX9-NEXT: v_readlane_b32 s35, v63, 3
-; GFX9-NEXT: v_readlane_b32 s34, v63, 2
-; GFX9-NEXT: v_readlane_b32 s31, v63, 1
-; GFX9-NEXT: v_readlane_b32 s30, v63, 0
+; GFX9-NEXT: v_readlane_b32 s30, v63, 34
+; GFX9-NEXT: v_readlane_b32 s31, v63, 35
+; GFX9-NEXT: v_readlane_b32 s99, v63, 33
+; GFX9-NEXT: v_readlane_b32 s98, v63, 32
+; GFX9-NEXT: v_readlane_b32 s97, v63, 31
+; GFX9-NEXT: v_readlane_b32 s96, v63, 30
+; GFX9-NEXT: v_readlane_b32 s87, v63, 29
+; GFX9-NEXT: v_readlane_b32 s86, v63, 28
+; GFX9-NEXT: v_readlane_b32 s85, v63, 27
+; GFX9-NEXT: v_readlane_b32 s84, v63, 26
+; GFX9-NEXT: v_readlane_b32 s83, v63, 25
+; GFX9-NEXT: v_readlane_b32 s82, v63, 24
+; GFX9-NEXT: v_readlane_b32 s81, v63, 23
+; GFX9-NEXT: v_readlane_b32 s80, v63, 22
+; GFX9-NEXT: v_readlane_b32 s71, v63, 21
+; GFX9-NEXT: v_readlane_b32 s70, v63, 20
+; GFX9-NEXT: v_readlane_b32 s69, v63, 19
+; GFX9-NEXT: v_readlane_b32 s68, v63, 18
+; GFX9-NEXT: v_readlane_b32 s67, v63, 17
+; GFX9-NEXT: v_readlane_b32 s66, v63, 16
+; GFX9-NEXT: v_readlane_b32 s65, v63, 15
+; GFX9-NEXT: v_readlane_b32 s64, v63, 14
+; GFX9-NEXT: v_readlane_b32 s55, v63, 13
+; GFX9-NEXT: v_readlane_b32 s54, v63, 12
+; GFX9-NEXT: v_readlane_b32 s53, v63, 11
+; GFX9-NEXT: v_readlane_b32 s52, v63, 10
+; GFX9-NEXT: v_readlane_b32 s51, v63, 9
+; GFX9-NEXT: v_readlane_b32 s50, v63, 8
+; GFX9-NEXT: v_readlane_b32 s49, v63, 7
+; GFX9-NEXT: v_readlane_b32 s48, v63, 6
+; GFX9-NEXT: v_readlane_b32 s39, v63, 5
+; GFX9-NEXT: v_readlane_b32 s38, v63, 4
+; GFX9-NEXT: v_readlane_b32 s37, v63, 3
+; GFX9-NEXT: v_readlane_b32 s36, v63, 2
+; GFX9-NEXT: v_readlane_b32 s35, v63, 1
+; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b32_e32 v36, 8, v36
@@ -120605,33 +120605,33 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88
; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:92
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v76, s30, 0
-; GFX11-NEXT: v_writelane_b32 v77, s96, 0
+; GFX11-NEXT: v_writelane_b32 v76, s34, 0
+; GFX11-NEXT: v_writelane_b32 v77, s98, 0
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
; GFX11-NEXT: v_readfirstlane_b32 s4, v1
; GFX11-NEXT: v_readfirstlane_b32 s5, v2
-; GFX11-NEXT: v_writelane_b32 v76, s31, 1
-; GFX11-NEXT: v_writelane_b32 v77, s97, 1
+; GFX11-NEXT: v_writelane_b32 v76, s35, 1
+; GFX11-NEXT: v_writelane_b32 v77, s99, 1
; GFX11-NEXT: v_readfirstlane_b32 s6, v3
; GFX11-NEXT: v_readfirstlane_b32 s7, v4
; GFX11-NEXT: v_readfirstlane_b32 s8, v5
-; GFX11-NEXT: v_writelane_b32 v76, s34, 2
-; GFX11-NEXT: v_writelane_b32 v77, s98, 2
+; GFX11-NEXT: v_writelane_b32 v76, s36, 2
+; GFX11-NEXT: v_writelane_b32 v77, s100, 2
; GFX11-NEXT: v_readfirstlane_b32 s9, v6
; GFX11-NEXT: v_readfirstlane_b32 s10, v7
; GFX11-NEXT: v_readfirstlane_b32 s11, v8
-; GFX11-NEXT: v_writelane_b32 v76, s35, 3
-; GFX11-NEXT: v_writelane_b32 v77, s99, 3
+; GFX11-NEXT: v_writelane_b32 v76, s37, 3
+; GFX11-NEXT: v_writelane_b32 v77, s101, 3
; GFX11-NEXT: v_readfirstlane_b32 s12, v9
; GFX11-NEXT: v_readfirstlane_b32 s13, v10
; GFX11-NEXT: v_readfirstlane_b32 s14, v11
-; GFX11-NEXT: v_writelane_b32 v76, s36, 4
-; GFX11-NEXT: v_writelane_b32 v77, s100, 4
+; GFX11-NEXT: v_writelane_b32 v76, s38, 4
+; GFX11-NEXT: v_writelane_b32 v77, s102, 4
; GFX11-NEXT: v_readfirstlane_b32 s15, v12
; GFX11-NEXT: v_readfirstlane_b32 s40, v13
; GFX11-NEXT: v_readfirstlane_b32 s41, v14
-; GFX11-NEXT: v_writelane_b32 v76, s37, 5
-; GFX11-NEXT: v_writelane_b32 v77, s101, 5
+; GFX11-NEXT: v_writelane_b32 v76, s39, 5
+; GFX11-NEXT: v_writelane_b32 v77, s103, 5
; GFX11-NEXT: s_mov_b32 vcc_hi, 0
; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
; GFX11-NEXT: s_clause 0x13
@@ -120655,37 +120655,37 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:8
; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:4
; GFX11-NEXT: scratch_store_b32 off, v75, s32
-; GFX11-NEXT: v_writelane_b32 v76, s38, 6
-; GFX11-NEXT: v_writelane_b32 v77, s102, 6
+; GFX11-NEXT: v_writelane_b32 v76, s48, 6
+; GFX11-NEXT: v_writelane_b32 v77, s104, 6
; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane
; GFX11-NEXT: ; implicit-def: $vgpr79 : SGPR spill to VGPR lane
-; GFX11-NEXT: v_writelane_b32 v76, s39, 7
-; GFX11-NEXT: v_writelane_b32 v77, s103, 7
-; GFX11-NEXT: v_writelane_b32 v76, s48, 8
-; GFX11-NEXT: v_writelane_b32 v77, s104, 8
-; GFX11-NEXT: v_writelane_b32 v76, s49, 9
-; GFX11-NEXT: v_writelane_b32 v76, s50, 10
-; GFX11-NEXT: v_writelane_b32 v76, s51, 11
-; GFX11-NEXT: v_writelane_b32 v76, s52, 12
-; GFX11-NEXT: v_writelane_b32 v76, s53, 13
-; GFX11-NEXT: v_writelane_b32 v76, s54, 14
-; GFX11-NEXT: v_writelane_b32 v76, s55, 15
-; GFX11-NEXT: v_writelane_b32 v76, s64, 16
-; GFX11-NEXT: v_writelane_b32 v76, s65, 17
-; GFX11-NEXT: v_writelane_b32 v76, s66, 18
-; GFX11-NEXT: v_writelane_b32 v76, s67, 19
-; GFX11-NEXT: v_writelane_b32 v76, s68, 20
-; GFX11-NEXT: v_writelane_b32 v76, s69, 21
-; GFX11-NEXT: v_writelane_b32 v76, s70, 22
-; GFX11-NEXT: v_writelane_b32 v76, s71, 23
-; GFX11-NEXT: v_writelane_b32 v76, s80, 24
-; GFX11-NEXT: v_writelane_b32 v76, s81, 25
-; GFX11-NEXT: v_writelane_b32 v76, s82, 26
-; GFX11-NEXT: v_writelane_b32 v76, s83, 27
-; GFX11-NEXT: v_writelane_b32 v76, s84, 28
-; GFX11-NEXT: v_writelane_b32 v76, s85, 29
-; GFX11-NEXT: v_writelane_b32 v76, s86, 30
-; GFX11-NEXT: v_writelane_b32 v76, s87, 31
+; GFX11-NEXT: v_writelane_b32 v76, s49, 7
+; GFX11-NEXT: v_writelane_b32 v77, s30, 7
+; GFX11-NEXT: v_writelane_b32 v76, s50, 8
+; GFX11-NEXT: v_writelane_b32 v77, s31, 8
+; GFX11-NEXT: v_writelane_b32 v76, s51, 9
+; GFX11-NEXT: v_writelane_b32 v76, s52, 10
+; GFX11-NEXT: v_writelane_b32 v76, s53, 11
+; GFX11-NEXT: v_writelane_b32 v76, s54, 12
+; GFX11-NEXT: v_writelane_b32 v76, s55, 13
+; GFX11-NEXT: v_writelane_b32 v76, s64, 14
+; GFX11-NEXT: v_writelane_b32 v76, s65, 15
+; GFX11-NEXT: v_writelane_b32 v76, s66, 16
+; GFX11-NEXT: v_writelane_b32 v76, s67, 17
+; GFX11-NEXT: v_writelane_b32 v76, s68, 18
+; GFX11-NEXT: v_writelane_b32 v76, s69, 19
+; GFX11-NEXT: v_writelane_b32 v76, s70, 20
+; GFX11-NEXT: v_writelane_b32 v76, s71, 21
+; GFX11-NEXT: v_writelane_b32 v76, s80, 22
+; GFX11-NEXT: v_writelane_b32 v76, s81, 23
+; GFX11-NEXT: v_writelane_b32 v76, s82, 24
+; GFX11-NEXT: v_writelane_b32 v76, s83, 25
+; GFX11-NEXT: v_writelane_b32 v76, s84, 26
+; GFX11-NEXT: v_writelane_b32 v76, s85, 27
+; GFX11-NEXT: v_writelane_b32 v76, s86, 28
+; GFX11-NEXT: v_writelane_b32 v76, s87, 29
+; GFX11-NEXT: v_writelane_b32 v76, s96, 30
+; GFX11-NEXT: v_writelane_b32 v76, s97, 31
; GFX11-NEXT: s_cbranch_scc0 .LBB73_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s13, 16
@@ -121563,47 +121563,47 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:68
; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:72
; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:76
-; GFX11-NEXT: v_readlane_b32 s104, v77, 8
-; GFX11-NEXT: v_readlane_b32 s103, v77, 7
-; GFX11-NEXT: v_readlane_b32 s102, v77, 6
-; GFX11-NEXT: v_readlane_b32 s101, v77, 5
-; GFX11-NEXT: v_readlane_b32 s100, v77, 4
-; GFX11-NEXT: v_readlane_b32 s99, v77, 3
-; GFX11-NEXT: v_readlane_b32 s98, v77, 2
-; GFX11-NEXT: v_readlane_b32 s97, v77, 1
-; GFX11-NEXT: v_readlane_b32 s96, v77, 0
-; GFX11-NEXT: v_readlane_b32 s87, v76, 31
-; GFX11-NEXT: v_readlane_b32 s86, v76, 30
-; GFX11-NEXT: v_readlane_b32 s85, v76, 29
-; GFX11-NEXT: v_readlane_b32 s84, v76, 28
-; GFX11-NEXT: v_readlane_b32 s83, v76, 27
-; GFX11-NEXT: v_readlane_b32 s82, v76, 26
-; GFX11-NEXT: v_readlane_b32 s81, v76, 25
-; GFX11-NEXT: v_readlane_b32 s80, v76, 24
-; GFX11-NEXT: v_readlane_b32 s71, v76, 23
-; GFX11-NEXT: v_readlane_b32 s70, v76, 22
-; GFX11-NEXT: v_readlane_b32 s69, v76, 21
-; GFX11-NEXT: v_readlane_b32 s68, v76, 20
-; GFX11-NEXT: v_readlane_b32 s67, v76, 19
-; GFX11-NEXT: v_readlane_b32 s66, v76, 18
-; GFX11-NEXT: v_readlane_b32 s65, v76, 17
-; GFX11-NEXT: v_readlane_b32 s64, v76, 16
-; GFX11-NEXT: v_readlane_b32 s55, v76, 15
-; GFX11-NEXT: v_readlane_b32 s54, v76, 14
-; GFX11-NEXT: v_readlane_b32 s53, v76, 13
-; GFX11-NEXT: v_readlane_b32 s52, v76, 12
-; GFX11-NEXT: v_readlane_b32 s51, v76, 11
-; GFX11-NEXT: v_readlane_b32 s50, v76, 10
-; GFX11-NEXT: v_readlane_b32 s49, v76, 9
-; GFX11-NEXT: v_readlane_b32 s48, v76, 8
-; GFX11-NEXT: v_readlane_b32 s39, v76, 7
-; GFX11-NEXT: v_readlane_b32 s38, v76, 6
-; GFX11-NEXT: v_readlane_b32 s37, v76, 5
-; GFX11-NEXT: v_readlane_b32 s36, v76, 4
-; GFX11-NEXT: v_readlane_b32 s35, v76, 3
-; GFX11-NEXT: v_readlane_b32 s34, v76, 2
-; GFX11-NEXT: v_readlane_b32 s31, v76, 1
-; GFX11-NEXT: v_readlane_b32 s30, v76, 0
+; GFX11-NEXT: v_readlane_b32 s30, v77, 7
+; GFX11-NEXT: v_readlane_b32 s31, v77, 8
+; GFX11-NEXT: v_readlane_b32 s104, v77, 6
+; GFX11-NEXT: v_readlane_b32 s103, v77, 5
+; GFX11-NEXT: v_readlane_b32 s102, v77, 4
+; GFX11-NEXT: v_readlane_b32 s101, v77, 3
+; GFX11-NEXT: v_readlane_b32 s100, v77, 2
+; GFX11-NEXT: v_readlane_b32 s99, v77, 1
+; GFX11-NEXT: v_readlane_b32 s98, v77, 0
+; GFX11-NEXT: v_readlane_b32 s97, v76, 31
+; GFX11-NEXT: v_readlane_b32 s96, v76, 30
+; GFX11-NEXT: v_readlane_b32 s87, v76, 29
+; GFX11-NEXT: v_readlane_b32 s86, v76, 28
+; GFX11-NEXT: v_readlane_b32 s85, v76, 27
+; GFX11-NEXT: v_readlane_b32 s84, v76, 26
+; GFX11-NEXT: v_readlane_b32 s83, v76, 25
+; GFX11-NEXT: v_readlane_b32 s82, v76, 24
+; GFX11-NEXT: v_readlane_b32 s81, v76, 23
+; GFX11-NEXT: v_readlane_b32 s80, v76, 22
+; GFX11-NEXT: v_readlane_b32 s71, v76, 21
+; GFX11-NEXT: v_readlane_b32 s70, v76, 20
+; GFX11-NEXT: v_readlane_b32 s69, v76, 19
+; GFX11-NEXT: v_readlane_b32 s68, v76, 18
+; GFX11-NEXT: v_readlane_b32 s67, v76, 17
+; GFX11-NEXT: v_readlane_b32 s66, v76, 16
+; GFX11-NEXT: v_readlane_b32 s65, v76, 15
+; GFX11-NEXT: v_readlane_b32 s64, v76, 14
+; GFX11-NEXT: v_readlane_b32 s55, v76, 13
+; GFX11-NEXT: v_readlane_b32 s54, v76, 12
+; GFX11-NEXT: v_readlane_b32 s53, v76, 11
+; GFX11-NEXT: v_readlane_b32 s52, v76, 10
+; GFX11-NEXT: v_readlane_b32 s51, v76, 9
+; GFX11-NEXT: v_readlane_b32 s50, v76, 8
+; GFX11-NEXT: v_readlane_b32 s49, v76, 7
+; GFX11-NEXT: v_readlane_b32 s48, v76, 6
+; GFX11-NEXT: v_readlane_b32 s39, v76, 5
+; GFX11-NEXT: v_readlane_b32 s38, v76, 4
+; GFX11-NEXT: v_readlane_b32 s37, v76, 3
+; GFX11-NEXT: v_readlane_b32 s36, v76, 2
+; GFX11-NEXT: v_readlane_b32 s35, v76, 1
+; GFX11-NEXT: v_readlane_b32 s34, v76, 0
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_load_b32 v76, off, s32 offset:80
@@ -133411,43 +133411,43 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_writelane_b32 v63, s30, 0
-; SI-NEXT: v_writelane_b32 v63, s31, 1
-; SI-NEXT: v_writelane_b32 v63, s34, 2
-; SI-NEXT: v_writelane_b32 v63, s35, 3
-; SI-NEXT: v_writelane_b32 v63, s36, 4
-; SI-NEXT: v_writelane_b32 v63, s37, 5
-; SI-NEXT: v_writelane_b32 v63, s38, 6
-; SI-NEXT: v_writelane_b32 v63, s39, 7
-; SI-NEXT: v_writelane_b32 v63, s48, 8
-; SI-NEXT: v_writelane_b32 v63, s49, 9
-; SI-NEXT: v_writelane_b32 v63, s50, 10
-; SI-NEXT: v_writelane_b32 v63, s51, 11
-; SI-NEXT: v_writelane_b32 v63, s52, 12
-; SI-NEXT: v_writelane_b32 v63, s53, 13
-; SI-NEXT: v_writelane_b32 v63, s54, 14
-; SI-NEXT: v_writelane_b32 v63, s55, 15
-; SI-NEXT: v_writelane_b32 v63, s64, 16
-; SI-NEXT: v_writelane_b32 v63, s65, 17
-; SI-NEXT: v_writelane_b32 v63, s66, 18
-; SI-NEXT: v_writelane_b32 v63, s67, 19
-; SI-NEXT: v_writelane_b32 v63, s68, 20
-; SI-NEXT: v_writelane_b32 v63, s69, 21
-; SI-NEXT: v_writelane_b32 v63, s70, 22
-; SI-NEXT: v_writelane_b32 v63, s71, 23
-; SI-NEXT: v_writelane_b32 v63, s80, 24
-; SI-NEXT: v_writelane_b32 v63, s81, 25
-; SI-NEXT: v_writelane_b32 v63, s82, 26
-; SI-NEXT: v_writelane_b32 v63, s83, 27
-; SI-NEXT: v_writelane_b32 v63, s84, 28
-; SI-NEXT: v_writelane_b32 v63, s85, 29
-; SI-NEXT: v_writelane_b32 v63, s86, 30
-; SI-NEXT: v_writelane_b32 v63, s87, 31
-; SI-NEXT: v_writelane_b32 v63, s96, 32
-; SI-NEXT: v_writelane_b32 v63, s97, 33
-; SI-NEXT: v_writelane_b32 v63, s98, 34
+; SI-NEXT: v_writelane_b32 v63, s34, 0
+; SI-NEXT: v_writelane_b32 v63, s35, 1
+; SI-NEXT: v_writelane_b32 v63, s36, 2
+; SI-NEXT: v_writelane_b32 v63, s37, 3
+; SI-NEXT: v_writelane_b32 v63, s38, 4
+; SI-NEXT: v_writelane_b32 v63, s39, 5
+; SI-NEXT: v_writelane_b32 v63, s48, 6
+; SI-NEXT: v_writelane_b32 v63, s49, 7
+; SI-NEXT: v_writelane_b32 v63, s50, 8
+; SI-NEXT: v_writelane_b32 v63, s51, 9
+; SI-NEXT: v_writelane_b32 v63, s52, 10
+; SI-NEXT: v_writelane_b32 v63, s53, 11
+; SI-NEXT: v_writelane_b32 v63, s54, 12
+; SI-NEXT: v_writelane_b32 v63, s55, 13
+; SI-NEXT: v_writelane_b32 v63, s64, 14
+; SI-NEXT: v_writelane_b32 v63, s65, 15
+; SI-NEXT: v_writelane_b32 v63, s66, 16
+; SI-NEXT: v_writelane_b32 v63, s67, 17
+; SI-NEXT: v_writelane_b32 v63, s68, 18
+; SI-NEXT: v_writelane_b32 v63, s69, 19
+; SI-NEXT: v_writelane_b32 v63, s70, 20
+; SI-NEXT: v_writelane_b32 v63, s71, 21
+; SI-NEXT: v_writelane_b32 v63, s80, 22
+; SI-NEXT: v_writelane_b32 v63, s81, 23
+; SI-NEXT: v_writelane_b32 v63, s82, 24
+; SI-NEXT: v_writelane_b32 v63, s83, 25
+; SI-NEXT: v_writelane_b32 v63, s84, 26
+; SI-NEXT: v_writelane_b32 v63, s85, 27
+; SI-NEXT: v_writelane_b32 v63, s86, 28
+; SI-NEXT: v_writelane_b32 v63, s87, 29
+; SI-NEXT: v_writelane_b32 v63, s96, 30
+; SI-NEXT: v_writelane_b32 v63, s97, 31
+; SI-NEXT: v_writelane_b32 v63, s98, 32
+; SI-NEXT: v_writelane_b32 v63, s99, 33
+; SI-NEXT: v_writelane_b32 v63, s30, 34
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_writelane_b32 v63, s99, 35
+; SI-NEXT: v_writelane_b32 v63, s31, 35
; SI-NEXT: v_readfirstlane_b32 s44, v1
; SI-NEXT: v_readfirstlane_b32 s45, v2
; SI-NEXT: v_readfirstlane_b32 s42, v3
@@ -133884,42 +133884,42 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_readlane_b32 s99, v63, 35
-; SI-NEXT: v_readlane_b32 s98, v63, 34
-; SI-NEXT: v_readlane_b32 s97, v63, 33
-; SI-NEXT: v_readlane_b32 s96, v63, 32
-; SI-NEXT: v_readlane_b32 s87, v63, 31
-; SI-NEXT: v_readlane_b32 s86, v63, 30
-; SI-NEXT: v_readlane_b32 s85, v63, 29
-; SI-NEXT: v_readlane_b32 s84, v63, 28
-; SI-NEXT: v_readlane_b32 s83, v63, 27
-; SI-NEXT: v_readlane_b32 s82, v63, 26
-; SI-NEXT: v_readlane_b32 s81, v63, 25
-; SI-NEXT: v_readlane_b32 s80, v63, 24
-; SI-NEXT: v_readlane_b32 s71, v63, 23
-; SI-NEXT: v_readlane_b32 s70, v63, 22
-; SI-NEXT: v_readlane_b32 s69, v63, 21
-; SI-NEXT: v_readlane_b32 s68, v63, 20
-; SI-NEXT: v_readlane_b32 s67, v63, 19
-; SI-NEXT: v_readlane_b32 s66, v63, 18
-; SI-NEXT: v_readlane_b32 s65, v63, 17
-; SI-NEXT: v_readlane_b32 s64, v63, 16
-; SI-NEXT: v_readlane_b32 s55, v63, 15
-; SI-NEXT: v_readlane_b32 s54, v63, 14
-; SI-NEXT: v_readlane_b32 s53, v63, 13
-; SI-NEXT: v_readlane_b32 s52, v63, 12
-; SI-NEXT: v_readlane_b32 s51, v63, 11
-; SI-NEXT: v_readlane_b32 s50, v63, 10
-; SI-NEXT: v_readlane_b32 s49, v63, 9
-; SI-NEXT: v_readlane_b32 s48, v63, 8
-; SI-NEXT: v_readlane_b32 s39, v63, 7
-; SI-NEXT: v_readlane_b32 s38, v63, 6
-; SI-NEXT: v_readlane_b32 s37, v63, 5
-; SI-NEXT: v_readlane_b32 s36, v63, 4
-; SI-NEXT: v_readlane_b32 s35, v63, 3
-; SI-NEXT: v_readlane_b32 s34, v63, 2
-; SI-NEXT: v_readlane_b32 s31, v63, 1
-; SI-NEXT: v_readlane_b32 s30, v63, 0
+; SI-NEXT: v_readlane_b32 s30, v63, 34
+; SI-NEXT: v_readlane_b32 s31, v63, 35
+; SI-NEXT: v_readlane_b32 s99, v63, 33
+; SI-NEXT: v_readlane_b32 s98, v63, 32
+; SI-NEXT: v_readlane_b32 s97, v63, 31
+; SI-NEXT: v_readlane_b32 s96, v63, 30
+; SI-NEXT: v_readlane_b32 s87, v63, 29
+; SI-NEXT: v_readlane_b32 s86, v63, 28
+; SI-NEXT: v_readlane_b32 s85, v63, 27
+; SI-NEXT: v_readlane_b32 s84, v63, 26
+; SI-NEXT: v_readlane_b32 s83, v63, 25
+; SI-NEXT: v_readlane_b32 s82, v63, 24
+; SI-NEXT: v_readlane_b32 s81, v63, 23
+; SI-NEXT: v_readlane_b32 s80, v63, 22
+; SI-NEXT: v_readlane_b32 s71, v63, 21
+; SI-NEXT: v_readlane_b32 s70, v63, 20
+; SI-NEXT: v_readlane_b32 s69, v63, 19
+; SI-NEXT: v_readlane_b32 s68, v63, 18
+; SI-NEXT: v_readlane_b32 s67, v63, 17
+; SI-NEXT: v_readlane_b32 s66, v63, 16
+; SI-NEXT: v_readlane_b32 s65, v63, 15
+; SI-NEXT: v_readlane_b32 s64, v63, 14
+; SI-NEXT: v_readlane_b32 s55, v63, 13
+; SI-NEXT: v_readlane_b32 s54, v63, 12
+; SI-NEXT: v_readlane_b32 s53, v63, 11
+; SI-NEXT: v_readlane_b32 s52, v63, 10
+; SI-NEXT: v_readlane_b32 s51, v63, 9
+; SI-NEXT: v_readlane_b32 s50, v63, 8
+; SI-NEXT: v_readlane_b32 s49, v63, 7
+; SI-NEXT: v_readlane_b32 s48, v63, 6
+; SI-NEXT: v_readlane_b32 s39, v63, 5
+; SI-NEXT: v_readlane_b32 s38, v63, 4
+; SI-NEXT: v_readlane_b32 s37, v63, 3
+; SI-NEXT: v_readlane_b32 s36, v63, 2
+; SI-NEXT: v_readlane_b32 s35, v63, 1
+; SI-NEXT: v_readlane_b32 s34, v63, 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
@@ -154035,44 +154035,42 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: v_writelane_b32 v43, s17, 2
; SI-NEXT: v_writelane_b32 v43, s16, 3
; SI-NEXT: s_mov_b32 s60, s24
-; SI-NEXT: v_writelane_b32 v41, s30, 0
-; SI-NEXT: v_writelane_b32 v41, s31, 1
-; SI-NEXT: v_writelane_b32 v41, s34, 2
-; SI-NEXT: v_writelane_b32 v41, s35, 3
-; SI-NEXT: v_writelane_b32 v41, s36, 4
-; SI-NEXT: v_writelane_b32 v41, s37, 5
-; SI-NEXT: v_writelane_b32 v41, s38, 6
-; SI-NEXT: v_writelane_b32 v41, s39, 7
-; SI-NEXT: v_writelane_b32 v41, s48, 8
-; SI-NEXT: v_writelane_b32 v41, s49, 9
-; SI-NEXT: v_writelane_b32 v41, s50, 10
-; SI-NEXT: v_writelane_b32 v41, s51, 11
-; SI-NEXT: v_writelane_b32 v41, s52, 12
-; SI-NEXT: v_writelane_b32 v41, s53, 13
-; SI-NEXT: v_writelane_b32 v41, s54, 14
-; SI-NEXT: v_writelane_b32 v41, s55, 15
-; SI-NEXT: v_writelane_b32 v41, s64, 16
-; SI-NEXT: v_writelane_b32 v41, s65, 17
-; SI-NEXT: v_writelane_b32 v41, s66, 18
-; SI-NEXT: v_writelane_b32 v41, s67, 19
-; SI-NEXT: v_writelane_b32 v41, s68, 20
-; SI-NEXT: v_writelane_b32 v41, s69, 21
-; SI-NEXT: v_writelane_b32 v41, s70, 22
-; SI-NEXT: v_writelane_b32 v41, s71, 23
+; SI-NEXT: v_writelane_b32 v41, s34, 0
+; SI-NEXT: v_writelane_b32 v41, s35, 1
+; SI-NEXT: v_writelane_b32 v41, s36, 2
+; SI-NEXT: v_writelane_b32 v41, s37, 3
+; SI-NEXT: v_writelane_b32 v41, s38, 4
+; SI-NEXT: v_writelane_b32 v41, s39, 5
+; SI-NEXT: v_writelane_b32 v41, s48, 6
+; SI-NEXT: v_writelane_b32 v41, s49, 7
+; SI-NEXT: v_writelane_b32 v41, s50, 8
+; SI-NEXT: v_writelane_b32 v41, s51, 9
+; SI-NEXT: v_writelane_b32 v41, s52, 10
+; SI-NEXT: v_writelane_b32 v41, s53, 11
+; SI-NEXT: v_writelane_b32 v41, s54, 12
+; SI-NEXT: v_writelane_b32 v41, s55, 13
+; SI-NEXT: v_writelane_b32 v41, s64, 14
+; SI-NEXT: v_writelane_b32 v41, s65, 15
+; SI-NEXT: v_writelane_b32 v41, s66, 16
+; SI-NEXT: v_writelane_b32 v41, s67, 17
+; SI-NEXT: v_writelane_b32 v41, s68, 18
+; SI-NEXT: v_writelane_b32 v41, s69, 19
+; SI-NEXT: v_writelane_b32 v41, s70, 20
+; SI-NEXT: v_writelane_b32 v41, s71, 21
; SI-NEXT: s_mov_b32 s77, s28
; SI-NEXT: s_mov_b32 s76, s27
-; SI-NEXT: v_writelane_b32 v41, s80, 24
-; SI-NEXT: v_writelane_b32 v41, s81, 25
-; SI-NEXT: v_writelane_b32 v41, s82, 26
-; SI-NEXT: v_writelane_b32 v41, s83, 27
-; SI-NEXT: v_writelane_b32 v41, s84, 28
-; SI-NEXT: v_writelane_b32 v41, s85, 29
-; SI-NEXT: v_writelane_b32 v41, s86, 30
-; SI-NEXT: v_writelane_b32 v41, s87, 31
-; SI-NEXT: v_writelane_b32 v41, s96, 32
-; SI-NEXT: v_writelane_b32 v41, s97, 33
-; SI-NEXT: v_writelane_b32 v41, s98, 34
-; SI-NEXT: v_writelane_b32 v41, s99, 35
+; SI-NEXT: v_writelane_b32 v41, s80, 22
+; SI-NEXT: v_writelane_b32 v41, s81, 23
+; SI-NEXT: v_writelane_b32 v41, s82, 24
+; SI-NEXT: v_writelane_b32 v41, s83, 25
+; SI-NEXT: v_writelane_b32 v41, s84, 26
+; SI-NEXT: v_writelane_b32 v41, s85, 27
+; SI-NEXT: v_writelane_b32 v41, s86, 28
+; SI-NEXT: v_writelane_b32 v41, s87, 29
+; SI-NEXT: v_writelane_b32 v41, s96, 30
+; SI-NEXT: v_writelane_b32 v41, s97, 31
+; SI-NEXT: v_writelane_b32 v41, s98, 32
+; SI-NEXT: v_writelane_b32 v41, s99, 33
; SI-NEXT: s_mov_b32 s79, s26
; SI-NEXT: v_readfirstlane_b32 s38, v20
; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
@@ -154102,6 +154100,8 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: v_readfirstlane_b32 s88, v4
; SI-NEXT: v_readfirstlane_b32 s89, v3
; SI-NEXT: v_readfirstlane_b32 s90, v9
+; SI-NEXT: v_readfirstlane_b32 s91, v10
+; SI-NEXT: v_readfirstlane_b32 s92, v8
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_readfirstlane_b32 s6, v31
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:300
@@ -154137,11 +154137,11 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s4, v38
; SI-NEXT: v_writelane_b32 v43, s4, 10
-; SI-NEXT: v_readfirstlane_b32 s91, v10
-; SI-NEXT: v_readfirstlane_b32 s92, v8
; SI-NEXT: v_readfirstlane_b32 s93, v7
; SI-NEXT: v_readfirstlane_b32 s94, v13
; SI-NEXT: v_readfirstlane_b32 s95, v14
+; SI-NEXT: v_writelane_b32 v41, s30, 34
+; SI-NEXT: v_writelane_b32 v41, s31, 35
; SI-NEXT: v_readfirstlane_b32 s30, v17
; SI-NEXT: v_readfirstlane_b32 s31, v18
; SI-NEXT: v_readfirstlane_b32 s34, v16
@@ -155626,42 +155626,42 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; SI-NEXT: v_readlane_b32 s99, v41, 35
-; SI-NEXT: v_readlane_b32 s98, v41, 34
-; SI-NEXT: v_readlane_b32 s97, v41, 33
-; SI-NEXT: v_readlane_b32 s96, v41, 32
-; SI-NEXT: v_readlane_b32 s87, v41, 31
-; SI-NEXT: v_readlane_b32 s86, v41, 30
-; SI-NEXT: v_readlane_b32 s85, v41, 29
-; SI-NEXT: v_readlane_b32 s84, v41, 28
-; SI-NEXT: v_readlane_b32 s83, v41, 27
-; SI-NEXT: v_readlane_b32 s82, v41, 26
-; SI-NEXT: v_readlane_b32 s81, v41, 25
-; SI-NEXT: v_readlane_b32 s80, v41, 24
-; SI-NEXT: v_readlane_b32 s71, v41, 23
-; SI-NEXT: v_readlane_b32 s70, v41, 22
-; SI-NEXT: v_readlane_b32 s69, v41, 21
-; SI-NEXT: v_readlane_b32 s68, v41, 20
-; SI-NEXT: v_readlane_b32 s67, v41, 19
-; SI-NEXT: v_readlane_b32 s66, v41, 18
-; SI-NEXT: v_readlane_b32 s65, v41, 17
-; SI-NEXT: v_readlane_b32 s64, v41, 16
-; SI-NEXT: v_readlane_b32 s55, v41, 15
-; SI-NEXT: v_readlane_b32 s54, v41, 14
-; SI-NEXT: v_readlane_b32 s53, v41, 13
-; SI-NEXT: v_readlane_b32 s52, v41, 12
-; SI-NEXT: v_readlane_b32 s51, v41, 11
-; SI-NEXT: v_readlane_b32 s50, v41, 10
-; SI-NEXT: v_readlane_b32 s49, v41, 9
-; SI-NEXT: v_readlane_b32 s48, v41, 8
-; SI-NEXT: v_readlane_b32 s39, v41, 7
-; SI-NEXT: v_readlane_b32 s38, v41, 6
-; SI-NEXT: v_readlane_b32 s37, v41, 5
-; SI-NEXT: v_readlane_b32 s36, v41, 4
-; SI-NEXT: v_readlane_b32 s35, v41, 3
-; SI-NEXT: v_readlane_b32 s34, v41, 2
-; SI-NEXT: v_readlane_b32 s31, v41, 1
-; SI-NEXT: v_readlane_b32 s30, v41, 0
+; SI-NEXT: v_readlane_b32 s30, v41, 34
+; SI-NEXT: v_readlane_b32 s31, v41, 35
+; SI-NEXT: v_readlane_b32 s99, v41, 33
+; SI-NEXT: v_readlane_b32 s98, v41, 32
+; SI-NEXT: v_readlane_b32 s97, v41, 31
+; SI-NEXT: v_readlane_b32 s96, v41, 30
+; SI-NEXT: v_readlane_b32 s87, v41, 29
+; SI-NEXT: v_readlane_b32 s86, v41, 28
+; SI-NEXT: v_readlane_b32 s85, v41, 27
+; SI-NEXT: v_readlane_b32 s84, v41, 26
+; SI-NEXT: v_readlane_b32 s83, v41, 25
+; SI-NEXT: v_readlane_b32 s82, v41, 24
+; SI-NEXT: v_readlane_b32 s81, v41, 23
+; SI-NEXT: v_readlane_b32 s80, v41, 22
+; SI-NEXT: v_readlane_b32 s71, v41, 21
+; SI-NEXT: v_readlane_b32 s70, v41, 20
+; SI-NEXT: v_readlane_b32 s69, v41, 19
+; SI-NEXT: v_readlane_b32 s68, v41, 18
+; SI-NEXT: v_readlane_b32 s67, v41, 17
+; SI-NEXT: v_readlane_b32 s66, v41, 16
+; SI-NEXT: v_readlane_b32 s65, v41, 15
+; SI-NEXT: v_readlane_b32 s64, v41, 14
+; SI-NEXT: v_readlane_b32 s55, v41, 13
+; SI-NEXT: v_readlane_b32 s54, v41, 12
+; SI-NEXT: v_readlane_b32 s53, v41, 11
+; SI-NEXT: v_readlane_b32 s52, v41, 10
+; SI-NEXT: v_readlane_b32 s51, v41, 9
+; SI-NEXT: v_readlane_b32 s50, v41, 8
+; SI-NEXT: v_readlane_b32 s49, v41, 7
+; SI-NEXT: v_readlane_b32 s48, v41, 6
+; SI-NEXT: v_readlane_b32 s39, v41, 5
+; SI-NEXT: v_readlane_b32 s38, v41, 4
+; SI-NEXT: v_readlane_b32 s37, v41, 3
+; SI-NEXT: v_readlane_b32 s36, v41, 2
+; SI-NEXT: v_readlane_b32 s35, v41, 1
+; SI-NEXT: v_readlane_b32 s34, v41, 0
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
@@ -167076,62 +167076,62 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:64
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:76
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:72
-; SI-NEXT: v_writelane_b32 v63, s30, 0
-; SI-NEXT: v_writelane_b32 v63, s31, 1
-; SI-NEXT: v_writelane_b32 v63, s34, 2
-; SI-NEXT: v_writelane_b32 v63, s35, 3
-; SI-NEXT: v_writelane_b32 v63, s36, 4
-; SI-NEXT: v_writelane_b32 v63, s37, 5
-; SI-NEXT: v_writelane_b32 v63, s38, 6
-; SI-NEXT: v_writelane_b32 v63, s39, 7
-; SI-NEXT: v_writelane_b32 v63, s48, 8
-; SI-NEXT: v_writelane_b32 v63, s49, 9
-; SI-NEXT: v_writelane_b32 v63, s50, 10
-; SI-NEXT: v_writelane_b32 v63, s51, 11
-; SI-NEXT: v_writelane_b32 v63, s52, 12
-; SI-NEXT: v_writelane_b32 v63, s53, 13
-; SI-NEXT: v_writelane_b32 v63, s54, 14
-; SI-NEXT: v_writelane_b32 v63, s55, 15
-; SI-NEXT: v_writelane_b32 v63, s64, 16
-; SI-NEXT: v_writelane_b32 v63, s65, 17
-; SI-NEXT: v_writelane_b32 v63, s66, 18
-; SI-NEXT: v_writelane_b32 v63, s67, 19
-; SI-NEXT: v_writelane_b32 v63, s68, 20
-; SI-NEXT: v_writelane_b32 v63, s69, 21
-; SI-NEXT: v_writelane_b32 v63, s70, 22
-; SI-NEXT: v_writelane_b32 v63, s71, 23
-; SI-NEXT: v_writelane_b32 v63, s80, 24
-; SI-NEXT: v_writelane_b32 v63, s81, 25
-; SI-NEXT: v_writelane_b32 v63, s82, 26
-; SI-NEXT: v_writelane_b32 v63, s83, 27
+; SI-NEXT: v_writelane_b32 v63, s34, 0
+; SI-NEXT: v_writelane_b32 v63, s35, 1
+; SI-NEXT: v_writelane_b32 v63, s36, 2
+; SI-NEXT: v_writelane_b32 v63, s37, 3
+; SI-NEXT: v_writelane_b32 v63, s38, 4
+; SI-NEXT: v_writelane_b32 v63, s39, 5
+; SI-NEXT: v_writelane_b32 v63, s48, 6
+; SI-NEXT: v_writelane_b32 v63, s49, 7
+; SI-NEXT: v_writelane_b32 v63, s50, 8
+; SI-NEXT: v_writelane_b32 v63, s51, 9
+; SI-NEXT: v_writelane_b32 v63, s52, 10
+; SI-NEXT: v_writelane_b32 v63, s53, 11
+; SI-NEXT: v_writelane_b32 v63, s54, 12
+; SI-NEXT: v_writelane_b32 v63, s55, 13
+; SI-NEXT: v_writelane_b32 v63, s64, 14
+; SI-NEXT: v_writelane_b32 v63, s65, 15
+; SI-NEXT: v_writelane_b32 v63, s66, 16
+; SI-NEXT: v_writelane_b32 v63, s67, 17
+; SI-NEXT: v_writelane_b32 v63, s68, 18
+; SI-NEXT: v_writelane_b32 v63, s69, 19
+; SI-NEXT: v_writelane_b32 v63, s70, 20
+; SI-NEXT: v_writelane_b32 v63, s71, 21
+; SI-NEXT: v_writelane_b32 v63, s80, 22
+; SI-NEXT: v_writelane_b32 v63, s81, 23
+; SI-NEXT: v_writelane_b32 v63, s82, 24
+; SI-NEXT: v_writelane_b32 v63, s83, 25
+; SI-NEXT: v_writelane_b32 v63, s84, 26
+; SI-NEXT: v_writelane_b32 v63, s85, 27
; SI-NEXT: s_waitcnt expcnt(5)
; SI-NEXT: v_mul_f32_e32 v56, 1.0, v2
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10
-; SI-NEXT: v_writelane_b32 v63, s84, 28
+; SI-NEXT: v_writelane_b32 v63, s86, 28
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v9
-; SI-NEXT: v_writelane_b32 v63, s85, 29
+; SI-NEXT: v_writelane_b32 v63, s87, 29
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v14
-; SI-NEXT: v_writelane_b32 v63, s86, 30
+; SI-NEXT: v_writelane_b32 v63, s96, 30
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15
-; SI-NEXT: v_writelane_b32 v63, s87, 31
+; SI-NEXT: v_writelane_b32 v63, s97, 31
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v18
-; SI-NEXT: v_writelane_b32 v63, s96, 32
+; SI-NEXT: v_writelane_b32 v63, s98, 32
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v26
-; SI-NEXT: v_writelane_b32 v63, s97, 33
+; SI-NEXT: v_writelane_b32 v63, s99, 33
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; SI-NEXT: v_writelane_b32 v63, s98, 34
+; SI-NEXT: v_writelane_b32 v63, s30, 34
; SI-NEXT: v_mov_b32_e32 v46, v21
-; SI-NEXT: v_writelane_b32 v63, s99, 35
+; SI-NEXT: v_writelane_b32 v63, s31, 35
; SI-NEXT: v_mul_f32_e32 v47, 1.0, v1
; SI-NEXT: v_mul_f32_e32 v32, 1.0, v4
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
@@ -168240,24 +168240,23 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: s_lshl_b32 s4, s4, 8
; SI-NEXT: v_readlane_b32 s7, v62, 1
-; SI-NEXT: v_readlane_b32 s99, v63, 35
-; SI-NEXT: v_readlane_b32 s97, v63, 33
-; SI-NEXT: v_readlane_b32 s87, v63, 31
-; SI-NEXT: v_readlane_b32 s85, v63, 29
-; SI-NEXT: v_readlane_b32 s83, v63, 27
-; SI-NEXT: v_readlane_b32 s81, v63, 25
-; SI-NEXT: v_readlane_b32 s71, v63, 23
-; SI-NEXT: v_readlane_b32 s69, v63, 21
-; SI-NEXT: v_readlane_b32 s67, v63, 19
-; SI-NEXT: v_readlane_b32 s65, v63, 17
-; SI-NEXT: v_readlane_b32 s55, v63, 15
-; SI-NEXT: v_readlane_b32 s53, v63, 13
-; SI-NEXT: v_readlane_b32 s51, v63, 11
-; SI-NEXT: v_readlane_b32 s49, v63, 9
-; SI-NEXT: v_readlane_b32 s39, v63, 7
-; SI-NEXT: v_readlane_b32 s37, v63, 5
-; SI-NEXT: v_readlane_b32 s35, v63, 3
-; SI-NEXT: v_readlane_b32 s31, v63, 1
+; SI-NEXT: v_readlane_b32 s99, v63, 33
+; SI-NEXT: v_readlane_b32 s97, v63, 31
+; SI-NEXT: v_readlane_b32 s87, v63, 29
+; SI-NEXT: v_readlane_b32 s85, v63, 27
+; SI-NEXT: v_readlane_b32 s83, v63, 25
+; SI-NEXT: v_readlane_b32 s81, v63, 23
+; SI-NEXT: v_readlane_b32 s71, v63, 21
+; SI-NEXT: v_readlane_b32 s69, v63, 19
+; SI-NEXT: v_readlane_b32 s67, v63, 17
+; SI-NEXT: v_readlane_b32 s65, v63, 15
+; SI-NEXT: v_readlane_b32 s55, v63, 13
+; SI-NEXT: v_readlane_b32 s53, v63, 11
+; SI-NEXT: v_readlane_b32 s51, v63, 9
+; SI-NEXT: v_readlane_b32 s49, v63, 7
+; SI-NEXT: v_readlane_b32 s39, v63, 5
+; SI-NEXT: v_readlane_b32 s37, v63, 3
+; SI-NEXT: v_readlane_b32 s35, v63, 1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_or_b32_e32 v1, s5, v1
@@ -168467,7 +168466,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_lshl_b32 s5, s34, 8
; SI-NEXT: s_lshl_b32 s6, s90, 24
-; SI-NEXT: v_readlane_b32 s34, v63, 2
+; SI-NEXT: v_readlane_b32 s34, v63, 0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
@@ -168498,8 +168497,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_lshl_b32 s5, s38, 8
; SI-NEXT: s_lshl_b32 s6, s30, 24
-; SI-NEXT: v_readlane_b32 s38, v63, 6
-; SI-NEXT: v_readlane_b32 s30, v63, 0
+; SI-NEXT: v_readlane_b32 s30, v63, 34
+; SI-NEXT: v_readlane_b32 s31, v63, 35
+; SI-NEXT: v_readlane_b32 s38, v63, 4
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
@@ -168527,9 +168527,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: s_lshl_b32 s5, s52, 8
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; SI-NEXT: s_lshl_b32 s6, s48, 24
-; SI-NEXT: v_readlane_b32 s52, v63, 12
-; SI-NEXT: v_readlane_b32 s48, v63, 8
-; SI-NEXT: v_readlane_b32 s36, v63, 4
+; SI-NEXT: v_readlane_b32 s52, v63, 10
+; SI-NEXT: v_readlane_b32 s48, v63, 6
+; SI-NEXT: v_readlane_b32 s36, v63, 2
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; SI-NEXT: v_or_b32_e32 v1, v1, v3
@@ -168562,9 +168562,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; SI-NEXT: s_lshl_b32 s5, s68, 8
; SI-NEXT: s_lshl_b32 s6, s54, 24
-; SI-NEXT: v_readlane_b32 s68, v63, 20
-; SI-NEXT: v_readlane_b32 s54, v63, 14
-; SI-NEXT: v_readlane_b32 s50, v63, 10
+; SI-NEXT: v_readlane_b32 s68, v63, 18
+; SI-NEXT: v_readlane_b32 s54, v63, 12
+; SI-NEXT: v_readlane_b32 s50, v63, 8
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; SI-NEXT: v_or_b32_e32 v1, v1, v3
@@ -168599,9 +168599,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_lshl_b32 s5, s82, 8
; SI-NEXT: s_lshl_b32 s6, s66, 24
-; SI-NEXT: v_readlane_b32 s82, v63, 26
-; SI-NEXT: v_readlane_b32 s66, v63, 18
-; SI-NEXT: v_readlane_b32 s64, v63, 16
+; SI-NEXT: v_readlane_b32 s82, v63, 24
+; SI-NEXT: v_readlane_b32 s66, v63, 16
+; SI-NEXT: v_readlane_b32 s64, v63, 14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
@@ -168629,9 +168629,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; SI-NEXT: s_lshl_b32 s5, s96, 8
; SI-NEXT: s_lshl_b32 s6, s80, 24
-; SI-NEXT: v_readlane_b32 s96, v63, 32
-; SI-NEXT: v_readlane_b32 s80, v63, 24
-; SI-NEXT: v_readlane_b32 s70, v63, 22
+; SI-NEXT: v_readlane_b32 s96, v63, 30
+; SI-NEXT: v_readlane_b32 s80, v63, 22
+; SI-NEXT: v_readlane_b32 s70, v63, 20
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
@@ -168663,8 +168663,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: v_and_b32_e32 v1, 0xff, v46
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; SI-NEXT: s_lshl_b32 s5, s86, 24
-; SI-NEXT: v_readlane_b32 s86, v63, 30
-; SI-NEXT: v_readlane_b32 s84, v63, 28
+; SI-NEXT: v_readlane_b32 s86, v63, 28
+; SI-NEXT: v_readlane_b32 s84, v63, 26
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
@@ -168696,7 +168696,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xff, v38
-; SI-NEXT: v_readlane_b32 s98, v63, 34
+; SI-NEXT: v_readlane_b32 s98, v63, 32
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
@@ -168736,39 +168736,39 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v63, s30, 0
-; VI-NEXT: v_writelane_b32 v63, s31, 1
-; VI-NEXT: v_writelane_b32 v63, s34, 2
-; VI-NEXT: v_writelane_b32 v63, s35, 3
-; VI-NEXT: v_writelane_b32 v63, s36, 4
-; VI-NEXT: v_writelane_b32 v63, s37, 5
-; VI-NEXT: v_writelane_b32 v63, s38, 6
-; VI-NEXT: v_writelane_b32 v63, s39, 7
-; VI-NEXT: v_writelane_b32 v63, s48, 8
-; VI-NEXT: v_writelane_b32 v63, s49, 9
-; VI-NEXT: v_writelane_b32 v63, s50, 10
-; VI-NEXT: v_writelane_b32 v63, s51, 11
-; VI-NEXT: v_writelane_b32 v63, s52, 12
-; VI-NEXT: v_writelane_b32 v63, s53, 13
-; VI-NEXT: v_writelane_b32 v63, s54, 14
-; VI-NEXT: v_writelane_b32 v63, s55, 15
-; VI-NEXT: v_writelane_b32 v63, s64, 16
-; VI-NEXT: v_writelane_b32 v63, s65, 17
-; VI-NEXT: v_writelane_b32 v63, s66, 18
-; VI-NEXT: v_writelane_b32 v63, s67, 19
-; VI-NEXT: v_writelane_b32 v63, s68, 20
-; VI-NEXT: v_writelane_b32 v63, s69, 21
-; VI-NEXT: v_writelane_b32 v63, s70, 22
-; VI-NEXT: v_writelane_b32 v63, s71, 23
-; VI-NEXT: v_writelane_b32 v63, s80, 24
-; VI-NEXT: v_writelane_b32 v63, s81, 25
-; VI-NEXT: v_writelane_b32 v63, s82, 26
-; VI-NEXT: v_writelane_b32 v63, s83, 27
-; VI-NEXT: v_writelane_b32 v63, s84, 28
-; VI-NEXT: v_writelane_b32 v63, s85, 29
-; VI-NEXT: v_writelane_b32 v63, s86, 30
+; VI-NEXT: v_writelane_b32 v63, s34, 0
+; VI-NEXT: v_writelane_b32 v63, s35, 1
+; VI-NEXT: v_writelane_b32 v63, s36, 2
+; VI-NEXT: v_writelane_b32 v63, s37, 3
+; VI-NEXT: v_writelane_b32 v63, s38, 4
+; VI-NEXT: v_writelane_b32 v63, s39, 5
+; VI-NEXT: v_writelane_b32 v63, s48, 6
+; VI-NEXT: v_writelane_b32 v63, s49, 7
+; VI-NEXT: v_writelane_b32 v63, s50, 8
+; VI-NEXT: v_writelane_b32 v63, s51, 9
+; VI-NEXT: v_writelane_b32 v63, s52, 10
+; VI-NEXT: v_writelane_b32 v63, s53, 11
+; VI-NEXT: v_writelane_b32 v63, s54, 12
+; VI-NEXT: v_writelane_b32 v63, s55, 13
+; VI-NEXT: v_writelane_b32 v63, s64, 14
+; VI-NEXT: v_writelane_b32 v63, s65, 15
+; VI-NEXT: v_writelane_b32 v63, s66, 16
+; VI-NEXT: v_writelane_b32 v63, s67, 17
+; VI-NEXT: v_writelane_b32 v63, s68, 18
+; VI-NEXT: v_writelane_b32 v63, s69, 19
+; VI-NEXT: v_writelane_b32 v63, s70, 20
+; VI-NEXT: v_writelane_b32 v63, s71, 21
+; VI-NEXT: v_writelane_b32 v63, s80, 22
+; VI-NEXT: v_writelane_b32 v63, s81, 23
+; VI-NEXT: v_writelane_b32 v63, s82, 24
+; VI-NEXT: v_writelane_b32 v63, s83, 25
+; VI-NEXT: v_writelane_b32 v63, s84, 26
+; VI-NEXT: v_writelane_b32 v63, s85, 27
+; VI-NEXT: v_writelane_b32 v63, s86, 28
+; VI-NEXT: v_writelane_b32 v63, s87, 29
+; VI-NEXT: v_writelane_b32 v63, s30, 30
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; VI-NEXT: v_writelane_b32 v63, s87, 31
+; VI-NEXT: v_writelane_b32 v63, s31, 31
; VI-NEXT: v_readfirstlane_b32 s44, v3
; VI-NEXT: v_readfirstlane_b32 s45, v4
; VI-NEXT: v_readfirstlane_b32 s42, v5
@@ -170160,38 +170160,38 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_lshlrev_b32_e32 v36, 8, v33
; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
; VI-NEXT: v_or_b32_sdwa v17, v17, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_readlane_b32 s87, v63, 31
-; VI-NEXT: v_readlane_b32 s86, v63, 30
-; VI-NEXT: v_readlane_b32 s85, v63, 29
-; VI-NEXT: v_readlane_b32 s84, v63, 28
-; VI-NEXT: v_readlane_b32 s83, v63, 27
-; VI-NEXT: v_readlane_b32 s82, v63, 26
-; VI-NEXT: v_readlane_b32 s81, v63, 25
-; VI-NEXT: v_readlane_b32 s80, v63, 24
-; VI-NEXT: v_readlane_b32 s71, v63, 23
-; VI-NEXT: v_readlane_b32 s70, v63, 22
-; VI-NEXT: v_readlane_b32 s69, v63, 21
-; VI-NEXT: v_readlane_b32 s68, v63, 20
-; VI-NEXT: v_readlane_b32 s67, v63, 19
-; VI-NEXT: v_readlane_b32 s66, v63, 18
-; VI-NEXT: v_readlane_b32 s65, v63, 17
-; VI-NEXT: v_readlane_b32 s64, v63, 16
-; VI-NEXT: v_readlane_b32 s55, v63, 15
-; VI-NEXT: v_readlane_b32 s54, v63, 14
-; VI-NEXT: v_readlane_b32 s53, v63, 13
-; VI-NEXT: v_readlane_b32 s52, v63, 12
-; VI-NEXT: v_readlane_b32 s51, v63, 11
-; VI-NEXT: v_readlane_b32 s50, v63, 10
-; VI-NEXT: v_readlane_b32 s49, v63, 9
-; VI-NEXT: v_readlane_b32 s48, v63, 8
-; VI-NEXT: v_readlane_b32 s39, v63, 7
-; VI-NEXT: v_readlane_b32 s38, v63, 6
-; VI-NEXT: v_readlane_b32 s37, v63, 5
-; VI-NEXT: v_readlane_b32 s36, v63, 4
-; VI-NEXT: v_readlane_b32 s35, v63, 3
-; VI-NEXT: v_readlane_b32 s34, v63, 2
-; VI-NEXT: v_readlane_b32 s31, v63, 1
-; VI-NEXT: v_readlane_b32 s30, v63, 0
+; VI-NEXT: v_readlane_b32 s30, v63, 30
+; VI-NEXT: v_readlane_b32 s31, v63, 31
+; VI-NEXT: v_readlane_b32 s87, v63, 29
+; VI-NEXT: v_readlane_b32 s86, v63, 28
+; VI-NEXT: v_readlane_b32 s85, v63, 27
+; VI-NEXT: v_readlane_b32 s84, v63, 26
+; VI-NEXT: v_readlane_b32 s83, v63, 25
+; VI-NEXT: v_readlane_b32 s82, v63, 24
+; VI-NEXT: v_readlane_b32 s81, v63, 23
+; VI-NEXT: v_readlane_b32 s80, v63, 22
+; VI-NEXT: v_readlane_b32 s71, v63, 21
+; VI-NEXT: v_readlane_b32 s70, v63, 20
+; VI-NEXT: v_readlane_b32 s69, v63, 19
+; VI-NEXT: v_readlane_b32 s68, v63, 18
+; VI-NEXT: v_readlane_b32 s67, v63, 17
+; VI-NEXT: v_readlane_b32 s66, v63, 16
+; VI-NEXT: v_readlane_b32 s65, v63, 15
+; VI-NEXT: v_readlane_b32 s64, v63, 14
+; VI-NEXT: v_readlane_b32 s55, v63, 13
+; VI-NEXT: v_readlane_b32 s54, v63, 12
+; VI-NEXT: v_readlane_b32 s53, v63, 11
+; VI-NEXT: v_readlane_b32 s52, v63, 10
+; VI-NEXT: v_readlane_b32 s51, v63, 9
+; VI-NEXT: v_readlane_b32 s50, v63, 8
+; VI-NEXT: v_readlane_b32 s49, v63, 7
+; VI-NEXT: v_readlane_b32 s48, v63, 6
+; VI-NEXT: v_readlane_b32 s39, v63, 5
+; VI-NEXT: v_readlane_b32 s38, v63, 4
+; VI-NEXT: v_readlane_b32 s37, v63, 3
+; VI-NEXT: v_readlane_b32 s36, v63, 2
+; VI-NEXT: v_readlane_b32 s35, v63, 1
+; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshlrev_b32_e32 v36, 8, v33
; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
@@ -170590,43 +170590,43 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v63, s30, 0
-; GFX9-NEXT: v_writelane_b32 v63, s31, 1
-; GFX9-NEXT: v_writelane_b32 v63, s34, 2
-; GFX9-NEXT: v_writelane_b32 v63, s35, 3
-; GFX9-NEXT: v_writelane_b32 v63, s36, 4
-; GFX9-NEXT: v_writelane_b32 v63, s37, 5
-; GFX9-NEXT: v_writelane_b32 v63, s38, 6
-; GFX9-NEXT: v_writelane_b32 v63, s39, 7
-; GFX9-NEXT: v_writelane_b32 v63, s48, 8
-; GFX9-NEXT: v_writelane_b32 v63, s49, 9
-; GFX9-NEXT: v_writelane_b32 v63, s50, 10
-; GFX9-NEXT: v_writelane_b32 v63, s51, 11
-; GFX9-NEXT: v_writelane_b32 v63, s52, 12
-; GFX9-NEXT: v_writelane_b32 v63, s53, 13
-; GFX9-NEXT: v_writelane_b32 v63, s54, 14
-; GFX9-NEXT: v_writelane_b32 v63, s55, 15
-; GFX9-NEXT: v_writelane_b32 v63, s64, 16
-; GFX9-NEXT: v_writelane_b32 v63, s65, 17
-; GFX9-NEXT: v_writelane_b32 v63, s66, 18
-; GFX9-NEXT: v_writelane_b32 v63, s67, 19
-; GFX9-NEXT: v_writelane_b32 v63, s68, 20
-; GFX9-NEXT: v_writelane_b32 v63, s69, 21
-; GFX9-NEXT: v_writelane_b32 v63, s70, 22
-; GFX9-NEXT: v_writelane_b32 v63, s71, 23
-; GFX9-NEXT: v_writelane_b32 v63, s80, 24
-; GFX9-NEXT: v_writelane_b32 v63, s81, 25
-; GFX9-NEXT: v_writelane_b32 v63, s82, 26
-; GFX9-NEXT: v_writelane_b32 v63, s83, 27
-; GFX9-NEXT: v_writelane_b32 v63, s84, 28
-; GFX9-NEXT: v_writelane_b32 v63, s85, 29
-; GFX9-NEXT: v_writelane_b32 v63, s86, 30
-; GFX9-NEXT: v_writelane_b32 v63, s87, 31
-; GFX9-NEXT: v_writelane_b32 v63, s96, 32
-; GFX9-NEXT: v_writelane_b32 v63, s97, 33
-; GFX9-NEXT: v_writelane_b32 v63, s98, 34
+; GFX9-NEXT: v_writelane_b32 v63, s34, 0
+; GFX9-NEXT: v_writelane_b32 v63, s35, 1
+; GFX9-NEXT: v_writelane_b32 v63, s36, 2
+; GFX9-NEXT: v_writelane_b32 v63, s37, 3
+; GFX9-NEXT: v_writelane_b32 v63, s38, 4
+; GFX9-NEXT: v_writelane_b32 v63, s39, 5
+; GFX9-NEXT: v_writelane_b32 v63, s48, 6
+; GFX9-NEXT: v_writelane_b32 v63, s49, 7
+; GFX9-NEXT: v_writelane_b32 v63, s50, 8
+; GFX9-NEXT: v_writelane_b32 v63, s51, 9
+; GFX9-NEXT: v_writelane_b32 v63, s52, 10
+; GFX9-NEXT: v_writelane_b32 v63, s53, 11
+; GFX9-NEXT: v_writelane_b32 v63, s54, 12
+; GFX9-NEXT: v_writelane_b32 v63, s55, 13
+; GFX9-NEXT: v_writelane_b32 v63, s64, 14
+; GFX9-NEXT: v_writelane_b32 v63, s65, 15
+; GFX9-NEXT: v_writelane_b32 v63, s66, 16
+; GFX9-NEXT: v_writelane_b32 v63, s67, 17
+; GFX9-NEXT: v_writelane_b32 v63, s68, 18
+; GFX9-NEXT: v_writelane_b32 v63, s69, 19
+; GFX9-NEXT: v_writelane_b32 v63, s70, 20
+; GFX9-NEXT: v_writelane_b32 v63, s71, 21
+; GFX9-NEXT: v_writelane_b32 v63, s80, 22
+; GFX9-NEXT: v_writelane_b32 v63, s81, 23
+; GFX9-NEXT: v_writelane_b32 v63, s82, 24
+; GFX9-NEXT: v_writelane_b32 v63, s83, 25
+; GFX9-NEXT: v_writelane_b32 v63, s84, 26
+; GFX9-NEXT: v_writelane_b32 v63, s85, 27
+; GFX9-NEXT: v_writelane_b32 v63, s86, 28
+; GFX9-NEXT: v_writelane_b32 v63, s87, 29
+; GFX9-NEXT: v_writelane_b32 v63, s96, 30
+; GFX9-NEXT: v_writelane_b32 v63, s97, 31
+; GFX9-NEXT: v_writelane_b32 v63, s98, 32
+; GFX9-NEXT: v_writelane_b32 v63, s99, 33
+; GFX9-NEXT: v_writelane_b32 v63, s30, 34
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; GFX9-NEXT: v_writelane_b32 v63, s99, 35
+; GFX9-NEXT: v_writelane_b32 v63, s31, 35
; GFX9-NEXT: v_readfirstlane_b32 s76, v3
; GFX9-NEXT: v_readfirstlane_b32 s77, v4
; GFX9-NEXT: v_readfirstlane_b32 s74, v5
@@ -172043,42 +172043,42 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_or_b32_sdwa v2, v44, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v1, v26, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_readlane_b32 s99, v63, 35
-; GFX9-NEXT: v_readlane_b32 s98, v63, 34
-; GFX9-NEXT: v_readlane_b32 s97, v63, 33
-; GFX9-NEXT: v_readlane_b32 s96, v63, 32
-; GFX9-NEXT: v_readlane_b32 s87, v63, 31
-; GFX9-NEXT: v_readlane_b32 s86, v63, 30
-; GFX9-NEXT: v_readlane_b32 s85, v63, 29
-; GFX9-NEXT: v_readlane_b32 s84, v63, 28
-; GFX9-NEXT: v_readlane_b32 s83, v63, 27
-; GFX9-NEXT: v_readlane_b32 s82, v63, 26
-; GFX9-NEXT: v_readlane_b32 s81, v63, 25
-; GFX9-NEXT: v_readlane_b32 s80, v63, 24
-; GFX9-NEXT: v_readlane_b32 s71, v63, 23
-; GFX9-NEXT: v_readlane_b32 s70, v63, 22
-; GFX9-NEXT: v_readlane_b32 s69, v63, 21
-; GFX9-NEXT: v_readlane_b32 s68, v63, 20
-; GFX9-NEXT: v_readlane_b32 s67, v63, 19
-; GFX9-NEXT: v_readlane_b32 s66, v63, 18
-; GFX9-NEXT: v_readlane_b32 s65, v63, 17
-; GFX9-NEXT: v_readlane_b32 s64, v63, 16
-; GFX9-NEXT: v_readlane_b32 s55, v63, 15
-; GFX9-NEXT: v_readlane_b32 s54, v63, 14
-; GFX9-NEXT: v_readlane_b32 s53, v63, 13
-; GFX9-NEXT: v_readlane_b32 s52, v63, 12
-; GFX9-NEXT: v_readlane_b32 s51, v63, 11
-; GFX9-NEXT: v_readlane_b32 s50, v63, 10
-; GFX9-NEXT: v_readlane_b32 s49, v63, 9
-; GFX9-NEXT: v_readlane_b32 s48, v63, 8
-; GFX9-NEXT: v_readlane_b32 s39, v63, 7
-; GFX9-NEXT: v_readlane_b32 s38, v63, 6
-; GFX9-NEXT: v_readlane_b32 s37, v63, 5
-; GFX9-NEXT: v_readlane_b32 s36, v63, 4
-; GFX9-NEXT: v_readlane_b32 s35, v63, 3
-; GFX9-NEXT: v_readlane_b32 s34, v63, 2
-; GFX9-NEXT: v_readlane_b32 s31, v63, 1
-; GFX9-NEXT: v_readlane_b32 s30, v63, 0
+; GFX9-NEXT: v_readlane_b32 s30, v63, 34
+; GFX9-NEXT: v_readlane_b32 s31, v63, 35
+; GFX9-NEXT: v_readlane_b32 s99, v63, 33
+; GFX9-NEXT: v_readlane_b32 s98, v63, 32
+; GFX9-NEXT: v_readlane_b32 s97, v63, 31
+; GFX9-NEXT: v_readlane_b32 s96, v63, 30
+; GFX9-NEXT: v_readlane_b32 s87, v63, 29
+; GFX9-NEXT: v_readlane_b32 s86, v63, 28
+; GFX9-NEXT: v_readlane_b32 s85, v63, 27
+; GFX9-NEXT: v_readlane_b32 s84, v63, 26
+; GFX9-NEXT: v_readlane_b32 s83, v63, 25
+; GFX9-NEXT: v_readlane_b32 s82, v63, 24
+; GFX9-NEXT: v_readlane_b32 s81, v63, 23
+; GFX9-NEXT: v_readlane_b32 s80, v63, 22
+; GFX9-NEXT: v_readlane_b32 s71, v63, 21
+; GFX9-NEXT: v_readlane_b32 s70, v63, 20
+; GFX9-NEXT: v_readlane_b32 s69, v63, 19
+; GFX9-NEXT: v_readlane_b32 s68, v63, 18
+; GFX9-NEXT: v_readlane_b32 s67, v63, 17
+; GFX9-NEXT: v_readlane_b32 s66, v63, 16
+; GFX9-NEXT: v_readlane_b32 s65, v63, 15
+; GFX9-NEXT: v_readlane_b32 s64, v63, 14
+; GFX9-NEXT: v_readlane_b32 s55, v63, 13
+; GFX9-NEXT: v_readlane_b32 s54, v63, 12
+; GFX9-NEXT: v_readlane_b32 s53, v63, 11
+; GFX9-NEXT: v_readlane_b32 s52, v63, 10
+; GFX9-NEXT: v_readlane_b32 s51, v63, 9
+; GFX9-NEXT: v_readlane_b32 s50, v63, 8
+; GFX9-NEXT: v_readlane_b32 s49, v63, 7
+; GFX9-NEXT: v_readlane_b32 s48, v63, 6
+; GFX9-NEXT: v_readlane_b32 s39, v63, 5
+; GFX9-NEXT: v_readlane_b32 s38, v63, 4
+; GFX9-NEXT: v_readlane_b32 s37, v63, 3
+; GFX9-NEXT: v_readlane_b32 s36, v63, 2
+; GFX9-NEXT: v_readlane_b32 s35, v63, 1
+; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_or_b32_sdwa v7, v30, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v7, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
@@ -172200,66 +172200,66 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:12
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s96, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s34, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s98, 0
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v2
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s97, 1
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s35, 1
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s99, 1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v3
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v4
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v5
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s34, 2
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s98, 2
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s36, 2
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s100, 2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v6
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v7
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v8
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s35, 3
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s99, 3
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s37, 3
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s101, 3
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v9
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v10
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v11
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s36, 4
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s100, 4
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s38, 4
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s102, 4
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v12
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v13
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v14
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s37, 5
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s101, 5
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s39, 5
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s103, 5
; GFX11-TRUE16-NEXT: s_mov_b32 vcc_hi, 0
; GFX11-TRUE16-NEXT: s_and_b32 s4, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s38, 6
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s102, 6
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s39, 7
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s103, 7
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s48, 8
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s104, 8
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s49, 9
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s50, 10
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s51, 11
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s52, 12
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s53, 13
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s54, 14
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s55, 15
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s64, 16
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s65, 17
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s66, 18
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s67, 19
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s68, 20
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s69, 21
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s70, 22
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s71, 23
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s80, 24
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s81, 25
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s82, 26
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s83, 27
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s84, 28
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s85, 29
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s86, 30
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s87, 31
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s48, 6
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s104, 6
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s49, 7
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s30, 7
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s50, 8
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s31, 8
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s51, 9
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s52, 10
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s53, 11
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s54, 12
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s55, 13
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s64, 14
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s65, 15
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s66, 16
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s67, 17
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s68, 18
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s69, 19
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s70, 20
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s71, 21
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s80, 22
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s81, 23
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s82, 24
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s83, 25
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s84, 26
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s85, 27
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s86, 28
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s87, 29
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s96, 30
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s97, 31
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB91_3
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s27, 24
@@ -173691,6 +173691,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v8, v9
+; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v41, 7
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v16, v19
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v18, v1
@@ -173702,47 +173703,46 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[4:7], off offset:80
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[11:14], off offset:96
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[15:18], off offset:112
-; GFX11-TRUE16-NEXT: v_readlane_b32 s104, v41, 8
-; GFX11-TRUE16-NEXT: v_readlane_b32 s103, v41, 7
-; GFX11-TRUE16-NEXT: v_readlane_b32 s102, v41, 6
-; GFX11-TRUE16-NEXT: v_readlane_b32 s101, v41, 5
-; GFX11-TRUE16-NEXT: v_readlane_b32 s100, v41, 4
-; GFX11-TRUE16-NEXT: v_readlane_b32 s99, v41, 3
-; GFX11-TRUE16-NEXT: v_readlane_b32 s98, v41, 2
-; GFX11-TRUE16-NEXT: v_readlane_b32 s97, v41, 1
-; GFX11-TRUE16-NEXT: v_readlane_b32 s96, v41, 0
-; GFX11-TRUE16-NEXT: v_readlane_b32 s87, v40, 31
-; GFX11-TRUE16-NEXT: v_readlane_b32 s86, v40, 30
-; GFX11-TRUE16-NEXT: v_readlane_b32 s85, v40, 29
-; GFX11-TRUE16-NEXT: v_readlane_b32 s84, v40, 28
-; GFX11-TRUE16-NEXT: v_readlane_b32 s83, v40, 27
-; GFX11-TRUE16-NEXT: v_readlane_b32 s82, v40, 26
-; GFX11-TRUE16-NEXT: v_readlane_b32 s81, v40, 25
-; GFX11-TRUE16-NEXT: v_readlane_b32 s80, v40, 24
-; GFX11-TRUE16-NEXT: v_readlane_b32 s71, v40, 23
-; GFX11-TRUE16-NEXT: v_readlane_b32 s70, v40, 22
-; GFX11-TRUE16-NEXT: v_readlane_b32 s69, v40, 21
-; GFX11-TRUE16-NEXT: v_readlane_b32 s68, v40, 20
-; GFX11-TRUE16-NEXT: v_readlane_b32 s67, v40, 19
-; GFX11-TRUE16-NEXT: v_readlane_b32 s66, v40, 18
-; GFX11-TRUE16-NEXT: v_readlane_b32 s65, v40, 17
-; GFX11-TRUE16-NEXT: v_readlane_b32 s64, v40, 16
-; GFX11-TRUE16-NEXT: v_readlane_b32 s55, v40, 15
-; GFX11-TRUE16-NEXT: v_readlane_b32 s54, v40, 14
-; GFX11-TRUE16-NEXT: v_readlane_b32 s53, v40, 13
-; GFX11-TRUE16-NEXT: v_readlane_b32 s52, v40, 12
-; GFX11-TRUE16-NEXT: v_readlane_b32 s51, v40, 11
-; GFX11-TRUE16-NEXT: v_readlane_b32 s50, v40, 10
-; GFX11-TRUE16-NEXT: v_readlane_b32 s49, v40, 9
-; GFX11-TRUE16-NEXT: v_readlane_b32 s48, v40, 8
-; GFX11-TRUE16-NEXT: v_readlane_b32 s39, v40, 7
-; GFX11-TRUE16-NEXT: v_readlane_b32 s38, v40, 6
-; GFX11-TRUE16-NEXT: v_readlane_b32 s37, v40, 5
-; GFX11-TRUE16-NEXT: v_readlane_b32 s36, v40, 4
-; GFX11-TRUE16-NEXT: v_readlane_b32 s35, v40, 3
-; GFX11-TRUE16-NEXT: v_readlane_b32 s34, v40, 2
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
-; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v41, 8
+; GFX11-TRUE16-NEXT: v_readlane_b32 s104, v41, 6
+; GFX11-TRUE16-NEXT: v_readlane_b32 s103, v41, 5
+; GFX11-TRUE16-NEXT: v_readlane_b32 s102, v41, 4
+; GFX11-TRUE16-NEXT: v_readlane_b32 s101, v41, 3
+; GFX11-TRUE16-NEXT: v_readlane_b32 s100, v41, 2
+; GFX11-TRUE16-NEXT: v_readlane_b32 s99, v41, 1
+; GFX11-TRUE16-NEXT: v_readlane_b32 s98, v41, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s97, v40, 31
+; GFX11-TRUE16-NEXT: v_readlane_b32 s96, v40, 30
+; GFX11-TRUE16-NEXT: v_readlane_b32 s87, v40, 29
+; GFX11-TRUE16-NEXT: v_readlane_b32 s86, v40, 28
+; GFX11-TRUE16-NEXT: v_readlane_b32 s85, v40, 27
+; GFX11-TRUE16-NEXT: v_readlane_b32 s84, v40, 26
+; GFX11-TRUE16-NEXT: v_readlane_b32 s83, v40, 25
+; GFX11-TRUE16-NEXT: v_readlane_b32 s82, v40, 24
+; GFX11-TRUE16-NEXT: v_readlane_b32 s81, v40, 23
+; GFX11-TRUE16-NEXT: v_readlane_b32 s80, v40, 22
+; GFX11-TRUE16-NEXT: v_readlane_b32 s71, v40, 21
+; GFX11-TRUE16-NEXT: v_readlane_b32 s70, v40, 20
+; GFX11-TRUE16-NEXT: v_readlane_b32 s69, v40, 19
+; GFX11-TRUE16-NEXT: v_readlane_b32 s68, v40, 18
+; GFX11-TRUE16-NEXT: v_readlane_b32 s67, v40, 17
+; GFX11-TRUE16-NEXT: v_readlane_b32 s66, v40, 16
+; GFX11-TRUE16-NEXT: v_readlane_b32 s65, v40, 15
+; GFX11-TRUE16-NEXT: v_readlane_b32 s64, v40, 14
+; GFX11-TRUE16-NEXT: v_readlane_b32 s55, v40, 13
+; GFX11-TRUE16-NEXT: v_readlane_b32 s54, v40, 12
+; GFX11-TRUE16-NEXT: v_readlane_b32 s53, v40, 11
+; GFX11-TRUE16-NEXT: v_readlane_b32 s52, v40, 10
+; GFX11-TRUE16-NEXT: v_readlane_b32 s51, v40, 9
+; GFX11-TRUE16-NEXT: v_readlane_b32 s50, v40, 8
+; GFX11-TRUE16-NEXT: v_readlane_b32 s49, v40, 7
+; GFX11-TRUE16-NEXT: v_readlane_b32 s48, v40, 6
+; GFX11-TRUE16-NEXT: v_readlane_b32 s39, v40, 5
+; GFX11-TRUE16-NEXT: v_readlane_b32 s38, v40, 4
+; GFX11-TRUE16-NEXT: v_readlane_b32 s37, v40, 3
+; GFX11-TRUE16-NEXT: v_readlane_b32 s36, v40, 2
+; GFX11-TRUE16-NEXT: v_readlane_b32 s35, v40, 1
+; GFX11-TRUE16-NEXT: v_readlane_b32 s34, v40, 0
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s0, -1
; GFX11-TRUE16-NEXT: s_clause 0x3
; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32
@@ -173763,66 +173763,66 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:8
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:12
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s96, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s34, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s98, 0
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s72, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v2
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s97, 1
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s35, 1
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s99, 1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s62, v3
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s63, v4
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v5
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s34, 2
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s98, 2
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s36, 2
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s100, 2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v6
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v7
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s59, v8
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s35, 3
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s99, 3
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s37, 3
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s101, 3
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v9
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v10
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v11
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s36, 4
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s100, 4
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s38, 4
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s102, 4
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v12
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v13
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v14
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s37, 5
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s101, 5
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s39, 5
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s103, 5
; GFX11-FAKE16-NEXT: s_mov_b32 vcc_hi, 0
; GFX11-FAKE16-NEXT: s_and_b32 s4, vcc_lo, exec_lo
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s38, 6
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s102, 6
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s39, 7
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s103, 7
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s48, 8
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s104, 8
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s49, 9
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s50, 10
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s51, 11
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s52, 12
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s53, 13
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s54, 14
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s55, 15
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s64, 16
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s65, 17
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s66, 18
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s67, 19
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s68, 20
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s69, 21
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s70, 22
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s71, 23
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s80, 24
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s81, 25
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s82, 26
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s83, 27
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s84, 28
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s85, 29
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s86, 30
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s87, 31
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s48, 6
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s104, 6
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s49, 7
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s30, 7
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s50, 8
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s31, 8
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s51, 9
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s52, 10
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s53, 11
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s54, 12
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s55, 13
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s64, 14
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s65, 15
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s66, 16
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s67, 17
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s68, 18
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s69, 19
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s70, 20
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s71, 21
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s80, 22
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s81, 23
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s82, 24
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s83, 25
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s84, 26
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s85, 27
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s86, 28
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s87, 29
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s96, 30
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s97, 31
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB91_3
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s27, 24
@@ -175261,6 +175261,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v3, v4
+; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v41, 7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v10, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v11, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v17, v19
@@ -175272,47 +175273,46 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[6:9], off offset:80
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:96
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[1:4], off offset:112
-; GFX11-FAKE16-NEXT: v_readlane_b32 s104, v41, 8
-; GFX11-FAKE16-NEXT: v_readlane_b32 s103, v41, 7
-; GFX11-FAKE16-NEXT: v_readlane_b32 s102, v41, 6
-; GFX11-FAKE16-NEXT: v_readlane_b32 s101, v41, 5
-; GFX11-FAKE16-NEXT: v_readlane_b32 s100, v41, 4
-; GFX11-FAKE16-NEXT: v_readlane_b32 s99, v41, 3
-; GFX11-FAKE16-NEXT: v_readlane_b32 s98, v41, 2
-; GFX11-FAKE16-NEXT: v_readlane_b32 s97, v41, 1
-; GFX11-FAKE16-NEXT: v_readlane_b32 s96, v41, 0
-; GFX11-FAKE16-NEXT: v_readlane_b32 s87, v40, 31
-; GFX11-FAKE16-NEXT: v_readlane_b32 s86, v40, 30
-; GFX11-FAKE16-NEXT: v_readlane_b32 s85, v40, 29
-; GFX11-FAKE16-NEXT: v_readlane_b32 s84, v40, 28
-; GFX11-FAKE16-NEXT: v_readlane_b32 s83, v40, 27
-; GFX11-FAKE16-NEXT: v_readlane_b32 s82, v40, 26
-; GFX11-FAKE16-NEXT: v_readlane_b32 s81, v40, 25
-; GFX11-FAKE16-NEXT: v_readlane_b32 s80, v40, 24
-; GFX11-FAKE16-NEXT: v_readlane_b32 s71, v40, 23
-; GFX11-FAKE16-NEXT: v_readlane_b32 s70, v40, 22
-; GFX11-FAKE16-NEXT: v_readlane_b32 s69, v40, 21
-; GFX11-FAKE16-NEXT: v_readlane_b32 s68, v40, 20
-; GFX11-FAKE16-NEXT: v_readlane_b32 s67, v40, 19
-; GFX11-FAKE16-NEXT: v_readlane_b32 s66, v40, 18
-; GFX11-FAKE16-NEXT: v_readlane_b32 s65, v40, 17
-; GFX11-FAKE16-NEXT: v_readlane_b32 s64, v40, 16
-; GFX11-FAKE16-NEXT: v_readlane_b32 s55, v40, 15
-; GFX11-FAKE16-NEXT: v_readlane_b32 s54, v40, 14
-; GFX11-FAKE16-NEXT: v_readlane_b32 s53, v40, 13
-; GFX11-FAKE16-NEXT: v_readlane_b32 s52, v40, 12
-; GFX11-FAKE16-NEXT: v_readlane_b32 s51, v40, 11
-; GFX11-FAKE16-NEXT: v_readlane_b32 s50, v40, 10
-; GFX11-FAKE16-NEXT: v_readlane_b32 s49, v40, 9
-; GFX11-FAKE16-NEXT: v_readlane_b32 s48, v40, 8
-; GFX11-FAKE16-NEXT: v_readlane_b32 s39, v40, 7
-; GFX11-FAKE16-NEXT: v_readlane_b32 s38, v40, 6
-; GFX11-FAKE16-NEXT: v_readlane_b32 s37, v40, 5
-; GFX11-FAKE16-NEXT: v_readlane_b32 s36, v40, 4
-; GFX11-FAKE16-NEXT: v_readlane_b32 s35, v40, 3
-; GFX11-FAKE16-NEXT: v_readlane_b32 s34, v40, 2
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
-; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v41, 8
+; GFX11-FAKE16-NEXT: v_readlane_b32 s104, v41, 6
+; GFX11-FAKE16-NEXT: v_readlane_b32 s103, v41, 5
+; GFX11-FAKE16-NEXT: v_readlane_b32 s102, v41, 4
+; GFX11-FAKE16-NEXT: v_readlane_b32 s101, v41, 3
+; GFX11-FAKE16-NEXT: v_readlane_b32 s100, v41, 2
+; GFX11-FAKE16-NEXT: v_readlane_b32 s99, v41, 1
+; GFX11-FAKE16-NEXT: v_readlane_b32 s98, v41, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s97, v40, 31
+; GFX11-FAKE16-NEXT: v_readlane_b32 s96, v40, 30
+; GFX11-FAKE16-NEXT: v_readlane_b32 s87, v40, 29
+; GFX11-FAKE16-NEXT: v_readlane_b32 s86, v40, 28
+; GFX11-FAKE16-NEXT: v_readlane_b32 s85, v40, 27
+; GFX11-FAKE16-NEXT: v_readlane_b32 s84, v40, 26
+; GFX11-FAKE16-NEXT: v_readlane_b32 s83, v40, 25
+; GFX11-FAKE16-NEXT: v_readlane_b32 s82, v40, 24
+; GFX11-FAKE16-NEXT: v_readlane_b32 s81, v40, 23
+; GFX11-FAKE16-NEXT: v_readlane_b32 s80, v40, 22
+; GFX11-FAKE16-NEXT: v_readlane_b32 s71, v40, 21
+; GFX11-FAKE16-NEXT: v_readlane_b32 s70, v40, 20
+; GFX11-FAKE16-NEXT: v_readlane_b32 s69, v40, 19
+; GFX11-FAKE16-NEXT: v_readlane_b32 s68, v40, 18
+; GFX11-FAKE16-NEXT: v_readlane_b32 s67, v40, 17
+; GFX11-FAKE16-NEXT: v_readlane_b32 s66, v40, 16
+; GFX11-FAKE16-NEXT: v_readlane_b32 s65, v40, 15
+; GFX11-FAKE16-NEXT: v_readlane_b32 s64, v40, 14
+; GFX11-FAKE16-NEXT: v_readlane_b32 s55, v40, 13
+; GFX11-FAKE16-NEXT: v_readlane_b32 s54, v40, 12
+; GFX11-FAKE16-NEXT: v_readlane_b32 s53, v40, 11
+; GFX11-FAKE16-NEXT: v_readlane_b32 s52, v40, 10
+; GFX11-FAKE16-NEXT: v_readlane_b32 s51, v40, 9
+; GFX11-FAKE16-NEXT: v_readlane_b32 s50, v40, 8
+; GFX11-FAKE16-NEXT: v_readlane_b32 s49, v40, 7
+; GFX11-FAKE16-NEXT: v_readlane_b32 s48, v40, 6
+; GFX11-FAKE16-NEXT: v_readlane_b32 s39, v40, 5
+; GFX11-FAKE16-NEXT: v_readlane_b32 s38, v40, 4
+; GFX11-FAKE16-NEXT: v_readlane_b32 s37, v40, 3
+; GFX11-FAKE16-NEXT: v_readlane_b32 s36, v40, 2
+; GFX11-FAKE16-NEXT: v_readlane_b32 s35, v40, 1
+; GFX11-FAKE16-NEXT: v_readlane_b32 s34, v40, 0
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s0, -1
; GFX11-FAKE16-NEXT: s_clause 0x3
; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32
@@ -181743,47 +181743,47 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: v_writelane_b32 v61, s28, 1
; SI-NEXT: v_writelane_b32 v61, s27, 2
; SI-NEXT: s_mov_b32 s61, s21
-; SI-NEXT: v_writelane_b32 v63, s30, 0
-; SI-NEXT: v_writelane_b32 v63, s31, 1
-; SI-NEXT: v_writelane_b32 v63, s34, 2
-; SI-NEXT: v_writelane_b32 v63, s35, 3
-; SI-NEXT: v_writelane_b32 v63, s36, 4
-; SI-NEXT: v_writelane_b32 v63, s37, 5
-; SI-NEXT: v_writelane_b32 v63, s38, 6
-; SI-NEXT: v_writelane_b32 v63, s39, 7
-; SI-NEXT: v_writelane_b32 v63, s48, 8
-; SI-NEXT: v_writelane_b32 v63, s49, 9
-; SI-NEXT: v_writelane_b32 v63, s50, 10
-; SI-NEXT: v_writelane_b32 v63, s51, 11
-; SI-NEXT: v_writelane_b32 v63, s52, 12
-; SI-NEXT: v_writelane_b32 v63, s53, 13
-; SI-NEXT: v_writelane_b32 v63, s54, 14
-; SI-NEXT: v_writelane_b32 v63, s55, 15
-; SI-NEXT: v_writelane_b32 v63, s64, 16
-; SI-NEXT: v_writelane_b32 v63, s65, 17
-; SI-NEXT: v_writelane_b32 v63, s66, 18
-; SI-NEXT: v_writelane_b32 v63, s67, 19
-; SI-NEXT: v_writelane_b32 v63, s68, 20
-; SI-NEXT: v_writelane_b32 v63, s69, 21
-; SI-NEXT: v_writelane_b32 v63, s70, 22
-; SI-NEXT: v_writelane_b32 v63, s71, 23
-; SI-NEXT: v_writelane_b32 v63, s80, 24
-; SI-NEXT: v_writelane_b32 v63, s81, 25
-; SI-NEXT: v_writelane_b32 v63, s82, 26
-; SI-NEXT: v_writelane_b32 v63, s83, 27
-; SI-NEXT: v_writelane_b32 v63, s84, 28
-; SI-NEXT: v_writelane_b32 v63, s85, 29
-; SI-NEXT: v_writelane_b32 v63, s86, 30
-; SI-NEXT: v_writelane_b32 v63, s87, 31
-; SI-NEXT: v_writelane_b32 v63, s96, 32
-; SI-NEXT: v_writelane_b32 v63, s97, 33
+; SI-NEXT: v_writelane_b32 v63, s34, 0
+; SI-NEXT: v_writelane_b32 v63, s35, 1
+; SI-NEXT: v_writelane_b32 v63, s36, 2
+; SI-NEXT: v_writelane_b32 v63, s37, 3
+; SI-NEXT: v_writelane_b32 v63, s38, 4
+; SI-NEXT: v_writelane_b32 v63, s39, 5
+; SI-NEXT: v_writelane_b32 v63, s48, 6
+; SI-NEXT: v_writelane_b32 v63, s49, 7
+; SI-NEXT: v_writelane_b32 v63, s50, 8
+; SI-NEXT: v_writelane_b32 v63, s51, 9
+; SI-NEXT: v_writelane_b32 v63, s52, 10
+; SI-NEXT: v_writelane_b32 v63, s53, 11
+; SI-NEXT: v_writelane_b32 v63, s54, 12
+; SI-NEXT: v_writelane_b32 v63, s55, 13
+; SI-NEXT: v_writelane_b32 v63, s64, 14
+; SI-NEXT: v_writelane_b32 v63, s65, 15
+; SI-NEXT: v_writelane_b32 v63, s66, 16
+; SI-NEXT: v_writelane_b32 v63, s67, 17
+; SI-NEXT: v_writelane_b32 v63, s68, 18
+; SI-NEXT: v_writelane_b32 v63, s69, 19
+; SI-NEXT: v_writelane_b32 v63, s70, 20
+; SI-NEXT: v_writelane_b32 v63, s71, 21
+; SI-NEXT: v_writelane_b32 v63, s80, 22
+; SI-NEXT: v_writelane_b32 v63, s81, 23
+; SI-NEXT: v_writelane_b32 v63, s82, 24
+; SI-NEXT: v_writelane_b32 v63, s83, 25
+; SI-NEXT: v_writelane_b32 v63, s84, 26
+; SI-NEXT: v_writelane_b32 v63, s85, 27
+; SI-NEXT: v_writelane_b32 v63, s86, 28
+; SI-NEXT: v_writelane_b32 v63, s87, 29
+; SI-NEXT: v_writelane_b32 v63, s96, 30
+; SI-NEXT: v_writelane_b32 v63, s97, 31
; SI-NEXT: s_mov_b32 s67, s19
; SI-NEXT: s_mov_b32 s54, s17
+; SI-NEXT: v_writelane_b32 v63, s98, 32
+; SI-NEXT: v_writelane_b32 v63, s99, 33
+; SI-NEXT: v_writelane_b32 v63, s30, 34
+; SI-NEXT: v_writelane_b32 v63, s31, 35
; SI-NEXT: s_mov_b32 s35, s23
; SI-NEXT: s_mov_b32 s39, s26
; SI-NEXT: s_mov_b32 s62, s25
-; SI-NEXT: v_writelane_b32 v63, s98, 34
-; SI-NEXT: v_writelane_b32 v63, s99, 35
; SI-NEXT: v_readfirstlane_b32 s99, v1
; SI-NEXT: v_readfirstlane_b32 s74, v24
; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
@@ -182980,7 +182980,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NEXT: v_readlane_b32 s99, v63, 35
+; SI-NEXT: v_readlane_b32 s30, v63, 34
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen
@@ -182988,41 +182988,41 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_readlane_b32 s98, v63, 34
-; SI-NEXT: v_readlane_b32 s97, v63, 33
-; SI-NEXT: v_readlane_b32 s96, v63, 32
-; SI-NEXT: v_readlane_b32 s87, v63, 31
-; SI-NEXT: v_readlane_b32 s86, v63, 30
-; SI-NEXT: v_readlane_b32 s85, v63, 29
-; SI-NEXT: v_readlane_b32 s84, v63, 28
-; SI-NEXT: v_readlane_b32 s83, v63, 27
-; SI-NEXT: v_readlane_b32 s82, v63, 26
-; SI-NEXT: v_readlane_b32 s81, v63, 25
-; SI-NEXT: v_readlane_b32 s80, v63, 24
-; SI-NEXT: v_readlane_b32 s71, v63, 23
-; SI-NEXT: v_readlane_b32 s70, v63, 22
-; SI-NEXT: v_readlane_b32 s69, v63, 21
-; SI-NEXT: v_readlane_b32 s68, v63, 20
-; SI-NEXT: v_readlane_b32 s67, v63, 19
-; SI-NEXT: v_readlane_b32 s66, v63, 18
-; SI-NEXT: v_readlane_b32 s65, v63, 17
-; SI-NEXT: v_readlane_b32 s64, v63, 16
-; SI-NEXT: v_readlane_b32 s55, v63, 15
-; SI-NEXT: v_readlane_b32 s54, v63, 14
-; SI-NEXT: v_readlane_b32 s53, v63, 13
-; SI-NEXT: v_readlane_b32 s52, v63, 12
-; SI-NEXT: v_readlane_b32 s51, v63, 11
-; SI-NEXT: v_readlane_b32 s50, v63, 10
-; SI-NEXT: v_readlane_b32 s49, v63, 9
-; SI-NEXT: v_readlane_b32 s48, v63, 8
-; SI-NEXT: v_readlane_b32 s39, v63, 7
-; SI-NEXT: v_readlane_b32 s38, v63, 6
-; SI-NEXT: v_readlane_b32 s37, v63, 5
-; SI-NEXT: v_readlane_b32 s36, v63, 4
-; SI-NEXT: v_readlane_b32 s35, v63, 3
-; SI-NEXT: v_readlane_b32 s34, v63, 2
-; SI-NEXT: v_readlane_b32 s31, v63, 1
-; SI-NEXT: v_readlane_b32 s30, v63, 0
+; SI-NEXT: v_readlane_b32 s31, v63, 35
+; SI-NEXT: v_readlane_b32 s99, v63, 33
+; SI-NEXT: v_readlane_b32 s98, v63, 32
+; SI-NEXT: v_readlane_b32 s97, v63, 31
+; SI-NEXT: v_readlane_b32 s96, v63, 30
+; SI-NEXT: v_readlane_b32 s87, v63, 29
+; SI-NEXT: v_readlane_b32 s86, v63, 28
+; SI-NEXT: v_readlane_b32 s85, v63, 27
+; SI-NEXT: v_readlane_b32 s84, v63, 26
+; SI-NEXT: v_readlane_b32 s83, v63, 25
+; SI-NEXT: v_readlane_b32 s82, v63, 24
+; SI-NEXT: v_readlane_b32 s81, v63, 23
+; SI-NEXT: v_readlane_b32 s80, v63, 22
+; SI-NEXT: v_readlane_b32 s71, v63, 21
+; SI-NEXT: v_readlane_b32 s70, v63, 20
+; SI-NEXT: v_readlane_b32 s69, v63, 19
+; SI-NEXT: v_readlane_b32 s68, v63, 18
+; SI-NEXT: v_readlane_b32 s67, v63, 17
+; SI-NEXT: v_readlane_b32 s66, v63, 16
+; SI-NEXT: v_readlane_b32 s65, v63, 15
+; SI-NEXT: v_readlane_b32 s64, v63, 14
+; SI-NEXT: v_readlane_b32 s55, v63, 13
+; SI-NEXT: v_readlane_b32 s54, v63, 12
+; SI-NEXT: v_readlane_b32 s53, v63, 11
+; SI-NEXT: v_readlane_b32 s52, v63, 10
+; SI-NEXT: v_readlane_b32 s51, v63, 9
+; SI-NEXT: v_readlane_b32 s50, v63, 8
+; SI-NEXT: v_readlane_b32 s49, v63, 7
+; SI-NEXT: v_readlane_b32 s48, v63, 6
+; SI-NEXT: v_readlane_b32 s39, v63, 5
+; SI-NEXT: v_readlane_b32 s38, v63, 4
+; SI-NEXT: v_readlane_b32 s37, v63, 3
+; SI-NEXT: v_readlane_b32 s36, v63, 2
+; SI-NEXT: v_readlane_b32 s35, v63, 1
+; SI-NEXT: v_readlane_b32 s34, v63, 0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -192380,58 +192380,58 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:64
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:76
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:72
-; SI-NEXT: v_writelane_b32 v63, s30, 0
-; SI-NEXT: v_writelane_b32 v63, s31, 1
-; SI-NEXT: v_writelane_b32 v63, s34, 2
-; SI-NEXT: v_writelane_b32 v63, s35, 3
-; SI-NEXT: v_writelane_b32 v63, s36, 4
+; SI-NEXT: v_writelane_b32 v63, s34, 0
+; SI-NEXT: v_writelane_b32 v63, s35, 1
+; SI-NEXT: v_writelane_b32 v63, s36, 2
+; SI-NEXT: v_writelane_b32 v63, s37, 3
+; SI-NEXT: v_writelane_b32 v63, s38, 4
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NEXT: v_writelane_b32 v63, s37, 5
-; SI-NEXT: v_writelane_b32 v63, s38, 6
-; SI-NEXT: v_writelane_b32 v63, s39, 7
-; SI-NEXT: v_writelane_b32 v63, s48, 8
+; SI-NEXT: v_writelane_b32 v63, s39, 5
+; SI-NEXT: v_writelane_b32 v63, s48, 6
+; SI-NEXT: v_writelane_b32 v63, s49, 7
+; SI-NEXT: v_writelane_b32 v63, s50, 8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v1, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v7
-; SI-NEXT: v_writelane_b32 v63, s49, 9
-; SI-NEXT: v_writelane_b32 v63, s50, 10
-; SI-NEXT: v_writelane_b32 v63, s51, 11
-; SI-NEXT: v_writelane_b32 v63, s52, 12
+; SI-NEXT: v_writelane_b32 v63, s51, 9
+; SI-NEXT: v_writelane_b32 v63, s52, 10
+; SI-NEXT: v_writelane_b32 v63, s53, 11
+; SI-NEXT: v_writelane_b32 v63, s54, 12
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v3, v9
-; SI-NEXT: v_writelane_b32 v63, s53, 13
-; SI-NEXT: v_writelane_b32 v63, s54, 14
-; SI-NEXT: v_writelane_b32 v63, s55, 15
-; SI-NEXT: v_writelane_b32 v63, s64, 16
+; SI-NEXT: v_writelane_b32 v63, s55, 13
+; SI-NEXT: v_writelane_b32 v63, s64, 14
+; SI-NEXT: v_writelane_b32 v63, s65, 15
+; SI-NEXT: v_writelane_b32 v63, s66, 16
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v3, v26
-; SI-NEXT: v_writelane_b32 v63, s65, 17
-; SI-NEXT: v_writelane_b32 v63, s66, 18
-; SI-NEXT: v_writelane_b32 v63, s67, 19
-; SI-NEXT: v_writelane_b32 v63, s68, 20
+; SI-NEXT: v_writelane_b32 v63, s67, 17
+; SI-NEXT: v_writelane_b32 v63, s68, 18
+; SI-NEXT: v_writelane_b32 v63, s69, 19
+; SI-NEXT: v_writelane_b32 v63, s70, 20
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v3, v25
-; SI-NEXT: v_writelane_b32 v63, s69, 21
-; SI-NEXT: v_writelane_b32 v63, s70, 22
-; SI-NEXT: v_writelane_b32 v63, s71, 23
-; SI-NEXT: v_writelane_b32 v63, s80, 24
+; SI-NEXT: v_writelane_b32 v63, s71, 21
+; SI-NEXT: v_writelane_b32 v63, s80, 22
+; SI-NEXT: v_writelane_b32 v63, s81, 23
+; SI-NEXT: v_writelane_b32 v63, s82, 24
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v3, v30
-; SI-NEXT: v_writelane_b32 v63, s81, 25
-; SI-NEXT: v_writelane_b32 v63, s82, 26
-; SI-NEXT: v_writelane_b32 v63, s83, 27
-; SI-NEXT: v_writelane_b32 v63, s84, 28
+; SI-NEXT: v_writelane_b32 v63, s83, 25
+; SI-NEXT: v_writelane_b32 v63, s84, 26
+; SI-NEXT: v_writelane_b32 v63, s85, 27
+; SI-NEXT: v_writelane_b32 v63, s86, 28
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: v_writelane_b32 v63, s85, 29
-; SI-NEXT: v_writelane_b32 v63, s86, 30
-; SI-NEXT: v_writelane_b32 v63, s87, 31
+; SI-NEXT: v_writelane_b32 v63, s87, 29
+; SI-NEXT: v_writelane_b32 v63, s96, 30
+; SI-NEXT: v_writelane_b32 v63, s97, 31
; SI-NEXT: v_mov_b32_e32 v46, v29
-; SI-NEXT: v_writelane_b32 v63, s96, 32
+; SI-NEXT: v_writelane_b32 v63, s98, 32
; SI-NEXT: v_cvt_f16_f32_e32 v47, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v4
; SI-NEXT: v_cvt_f16_f32_e32 v33, v6
@@ -192502,9 +192502,9 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v39, s26
; SI-NEXT: v_cvt_f16_f32_e32 v35, s29
; SI-NEXT: v_cvt_f16_f32_e32 v20, s28
-; SI-NEXT: v_writelane_b32 v63, s97, 33
-; SI-NEXT: v_writelane_b32 v63, s98, 34
-; SI-NEXT: v_writelane_b32 v63, s99, 35
+; SI-NEXT: v_writelane_b32 v63, s99, 33
+; SI-NEXT: v_writelane_b32 v63, s30, 34
+; SI-NEXT: v_writelane_b32 v63, s31, 35
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
@@ -193994,6 +193994,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: v_readlane_b32 s30, v63, 34
; SI-NEXT: v_readlane_b32 s45, v62, 17
; SI-NEXT: v_readlane_b32 s43, v62, 23
; SI-NEXT: v_readlane_b32 s41, v62, 29
@@ -194001,42 +194002,41 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_readlane_b32 s27, v62, 41
; SI-NEXT: v_readlane_b32 s25, v62, 45
; SI-NEXT: v_readlane_b32 s9, v62, 49
-; SI-NEXT: v_readlane_b32 s99, v63, 35
-; SI-NEXT: v_readlane_b32 s98, v63, 34
-; SI-NEXT: v_readlane_b32 s97, v63, 33
-; SI-NEXT: v_readlane_b32 s96, v63, 32
-; SI-NEXT: v_readlane_b32 s87, v63, 31
-; SI-NEXT: v_readlane_b32 s86, v63, 30
-; SI-NEXT: v_readlane_b32 s85, v63, 29
-; SI-NEXT: v_readlane_b32 s84, v63, 28
-; SI-NEXT: v_readlane_b32 s83, v63, 27
-; SI-NEXT: v_readlane_b32 s82, v63, 26
-; SI-NEXT: v_readlane_b32 s81, v63, 25
-; SI-NEXT: v_readlane_b32 s80, v63, 24
-; SI-NEXT: v_readlane_b32 s71, v63, 23
-; SI-NEXT: v_readlane_b32 s70, v63, 22
-; SI-NEXT: v_readlane_b32 s69, v63, 21
-; SI-NEXT: v_readlane_b32 s68, v63, 20
-; SI-NEXT: v_readlane_b32 s67, v63, 19
-; SI-NEXT: v_readlane_b32 s66, v63, 18
-; SI-NEXT: v_readlane_b32 s65, v63, 17
-; SI-NEXT: v_readlane_b32 s64, v63, 16
-; SI-NEXT: v_readlane_b32 s55, v63, 15
-; SI-NEXT: v_readlane_b32 s54, v63, 14
-; SI-NEXT: v_readlane_b32 s53, v63, 13
-; SI-NEXT: v_readlane_b32 s52, v63, 12
-; SI-NEXT: v_readlane_b32 s51, v63, 11
-; SI-NEXT: v_readlane_b32 s50, v63, 10
-; SI-NEXT: v_readlane_b32 s49, v63, 9
-; SI-NEXT: v_readlane_b32 s48, v63, 8
-; SI-NEXT: v_readlane_b32 s39, v63, 7
-; SI-NEXT: v_readlane_b32 s38, v63, 6
-; SI-NEXT: v_readlane_b32 s37, v63, 5
-; SI-NEXT: v_readlane_b32 s36, v63, 4
-; SI-NEXT: v_readlane_b32 s35, v63, 3
-; SI-NEXT: v_readlane_b32 s34, v63, 2
-; SI-NEXT: v_readlane_b32 s31, v63, 1
-; SI-NEXT: v_readlane_b32 s30, v63, 0
+; SI-NEXT: v_readlane_b32 s31, v63, 35
+; SI-NEXT: v_readlane_b32 s99, v63, 33
+; SI-NEXT: v_readlane_b32 s98, v63, 32
+; SI-NEXT: v_readlane_b32 s97, v63, 31
+; SI-NEXT: v_readlane_b32 s96, v63, 30
+; SI-NEXT: v_readlane_b32 s87, v63, 29
+; SI-NEXT: v_readlane_b32 s86, v63, 28
+; SI-NEXT: v_readlane_b32 s85, v63, 27
+; SI-NEXT: v_readlane_b32 s84, v63, 26
+; SI-NEXT: v_readlane_b32 s83, v63, 25
+; SI-NEXT: v_readlane_b32 s82, v63, 24
+; SI-NEXT: v_readlane_b32 s81, v63, 23
+; SI-NEXT: v_readlane_b32 s80, v63, 22
+; SI-NEXT: v_readlane_b32 s71, v63, 21
+; SI-NEXT: v_readlane_b32 s70, v63, 20
+; SI-NEXT: v_readlane_b32 s69, v63, 19
+; SI-NEXT: v_readlane_b32 s68, v63, 18
+; SI-NEXT: v_readlane_b32 s67, v63, 17
+; SI-NEXT: v_readlane_b32 s66, v63, 16
+; SI-NEXT: v_readlane_b32 s65, v63, 15
+; SI-NEXT: v_readlane_b32 s64, v63, 14
+; SI-NEXT: v_readlane_b32 s55, v63, 13
+; SI-NEXT: v_readlane_b32 s54, v63, 12
+; SI-NEXT: v_readlane_b32 s53, v63, 11
+; SI-NEXT: v_readlane_b32 s52, v63, 10
+; SI-NEXT: v_readlane_b32 s51, v63, 9
+; SI-NEXT: v_readlane_b32 s50, v63, 8
+; SI-NEXT: v_readlane_b32 s49, v63, 7
+; SI-NEXT: v_readlane_b32 s48, v63, 6
+; SI-NEXT: v_readlane_b32 s39, v63, 5
+; SI-NEXT: v_readlane_b32 s38, v63, 4
+; SI-NEXT: v_readlane_b32 s37, v63, 3
+; SI-NEXT: v_readlane_b32 s36, v63, 2
+; SI-NEXT: v_readlane_b32 s35, v63, 1
+; SI-NEXT: v_readlane_b32 s34, v63, 0
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
@@ -194051,39 +194051,39 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v63, s30, 0
-; VI-NEXT: v_writelane_b32 v63, s31, 1
-; VI-NEXT: v_writelane_b32 v63, s34, 2
-; VI-NEXT: v_writelane_b32 v63, s35, 3
-; VI-NEXT: v_writelane_b32 v63, s36, 4
-; VI-NEXT: v_writelane_b32 v63, s37, 5
-; VI-NEXT: v_writelane_b32 v63, s38, 6
-; VI-NEXT: v_writelane_b32 v63, s39, 7
-; VI-NEXT: v_writelane_b32 v63, s48, 8
-; VI-NEXT: v_writelane_b32 v63, s49, 9
-; VI-NEXT: v_writelane_b32 v63, s50, 10
-; VI-NEXT: v_writelane_b32 v63, s51, 11
-; VI-NEXT: v_writelane_b32 v63, s52, 12
-; VI-NEXT: v_writelane_b32 v63, s53, 13
-; VI-NEXT: v_writelane_b32 v63, s54, 14
-; VI-NEXT: v_writelane_b32 v63, s55, 15
-; VI-NEXT: v_writelane_b32 v63, s64, 16
-; VI-NEXT: v_writelane_b32 v63, s65, 17
-; VI-NEXT: v_writelane_b32 v63, s66, 18
-; VI-NEXT: v_writelane_b32 v63, s67, 19
-; VI-NEXT: v_writelane_b32 v63, s68, 20
-; VI-NEXT: v_writelane_b32 v63, s69, 21
-; VI-NEXT: v_writelane_b32 v63, s70, 22
-; VI-NEXT: v_writelane_b32 v63, s71, 23
-; VI-NEXT: v_writelane_b32 v63, s80, 24
-; VI-NEXT: v_writelane_b32 v63, s81, 25
-; VI-NEXT: v_writelane_b32 v63, s82, 26
-; VI-NEXT: v_writelane_b32 v63, s83, 27
-; VI-NEXT: v_writelane_b32 v63, s84, 28
-; VI-NEXT: v_writelane_b32 v63, s85, 29
-; VI-NEXT: v_writelane_b32 v63, s86, 30
+; VI-NEXT: v_writelane_b32 v63, s34, 0
+; VI-NEXT: v_writelane_b32 v63, s35, 1
+; VI-NEXT: v_writelane_b32 v63, s36, 2
+; VI-NEXT: v_writelane_b32 v63, s37, 3
+; VI-NEXT: v_writelane_b32 v63, s38, 4
+; VI-NEXT: v_writelane_b32 v63, s39, 5
+; VI-NEXT: v_writelane_b32 v63, s48, 6
+; VI-NEXT: v_writelane_b32 v63, s49, 7
+; VI-NEXT: v_writelane_b32 v63, s50, 8
+; VI-NEXT: v_writelane_b32 v63, s51, 9
+; VI-NEXT: v_writelane_b32 v63, s52, 10
+; VI-NEXT: v_writelane_b32 v63, s53, 11
+; VI-NEXT: v_writelane_b32 v63, s54, 12
+; VI-NEXT: v_writelane_b32 v63, s55, 13
+; VI-NEXT: v_writelane_b32 v63, s64, 14
+; VI-NEXT: v_writelane_b32 v63, s65, 15
+; VI-NEXT: v_writelane_b32 v63, s66, 16
+; VI-NEXT: v_writelane_b32 v63, s67, 17
+; VI-NEXT: v_writelane_b32 v63, s68, 18
+; VI-NEXT: v_writelane_b32 v63, s69, 19
+; VI-NEXT: v_writelane_b32 v63, s70, 20
+; VI-NEXT: v_writelane_b32 v63, s71, 21
+; VI-NEXT: v_writelane_b32 v63, s80, 22
+; VI-NEXT: v_writelane_b32 v63, s81, 23
+; VI-NEXT: v_writelane_b32 v63, s82, 24
+; VI-NEXT: v_writelane_b32 v63, s83, 25
+; VI-NEXT: v_writelane_b32 v63, s84, 26
+; VI-NEXT: v_writelane_b32 v63, s85, 27
+; VI-NEXT: v_writelane_b32 v63, s86, 28
+; VI-NEXT: v_writelane_b32 v63, s87, 29
+; VI-NEXT: v_writelane_b32 v63, s30, 30
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; VI-NEXT: v_writelane_b32 v63, s87, 31
+; VI-NEXT: v_writelane_b32 v63, s31, 31
; VI-NEXT: v_readfirstlane_b32 s44, v3
; VI-NEXT: v_readfirstlane_b32 s45, v4
; VI-NEXT: v_readfirstlane_b32 s42, v5
@@ -194998,38 +194998,38 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; VI-NEXT: v_or_b32_sdwa v1, v61, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_readlane_b32 s87, v63, 31
-; VI-NEXT: v_readlane_b32 s86, v63, 30
-; VI-NEXT: v_readlane_b32 s85, v63, 29
-; VI-NEXT: v_readlane_b32 s84, v63, 28
-; VI-NEXT: v_readlane_b32 s83, v63, 27
-; VI-NEXT: v_readlane_b32 s82, v63, 26
-; VI-NEXT: v_readlane_b32 s81, v63, 25
-; VI-NEXT: v_readlane_b32 s80, v63, 24
-; VI-NEXT: v_readlane_b32 s71, v63, 23
-; VI-NEXT: v_readlane_b32 s70, v63, 22
-; VI-NEXT: v_readlane_b32 s69, v63, 21
-; VI-NEXT: v_readlane_b32 s68, v63, 20
-; VI-NEXT: v_readlane_b32 s67, v63, 19
-; VI-NEXT: v_readlane_b32 s66, v63, 18
-; VI-NEXT: v_readlane_b32 s65, v63, 17
-; VI-NEXT: v_readlane_b32 s64, v63, 16
-; VI-NEXT: v_readlane_b32 s55, v63, 15
-; VI-NEXT: v_readlane_b32 s54, v63, 14
-; VI-NEXT: v_readlane_b32 s53, v63, 13
-; VI-NEXT: v_readlane_b32 s52, v63, 12
-; VI-NEXT: v_readlane_b32 s51, v63, 11
-; VI-NEXT: v_readlane_b32 s50, v63, 10
-; VI-NEXT: v_readlane_b32 s49, v63, 9
-; VI-NEXT: v_readlane_b32 s48, v63, 8
-; VI-NEXT: v_readlane_b32 s39, v63, 7
-; VI-NEXT: v_readlane_b32 s38, v63, 6
-; VI-NEXT: v_readlane_b32 s37, v63, 5
-; VI-NEXT: v_readlane_b32 s36, v63, 4
-; VI-NEXT: v_readlane_b32 s35, v63, 3
-; VI-NEXT: v_readlane_b32 s34, v63, 2
-; VI-NEXT: v_readlane_b32 s31, v63, 1
-; VI-NEXT: v_readlane_b32 s30, v63, 0
+; VI-NEXT: v_readlane_b32 s30, v63, 30
+; VI-NEXT: v_readlane_b32 s31, v63, 31
+; VI-NEXT: v_readlane_b32 s87, v63, 29
+; VI-NEXT: v_readlane_b32 s86, v63, 28
+; VI-NEXT: v_readlane_b32 s85, v63, 27
+; VI-NEXT: v_readlane_b32 s84, v63, 26
+; VI-NEXT: v_readlane_b32 s83, v63, 25
+; VI-NEXT: v_readlane_b32 s82, v63, 24
+; VI-NEXT: v_readlane_b32 s81, v63, 23
+; VI-NEXT: v_readlane_b32 s80, v63, 22
+; VI-NEXT: v_readlane_b32 s71, v63, 21
+; VI-NEXT: v_readlane_b32 s70, v63, 20
+; VI-NEXT: v_readlane_b32 s69, v63, 19
+; VI-NEXT: v_readlane_b32 s68, v63, 18
+; VI-NEXT: v_readlane_b32 s67, v63, 17
+; VI-NEXT: v_readlane_b32 s66, v63, 16
+; VI-NEXT: v_readlane_b32 s65, v63, 15
+; VI-NEXT: v_readlane_b32 s64, v63, 14
+; VI-NEXT: v_readlane_b32 s55, v63, 13
+; VI-NEXT: v_readlane_b32 s54, v63, 12
+; VI-NEXT: v_readlane_b32 s53, v63, 11
+; VI-NEXT: v_readlane_b32 s52, v63, 10
+; VI-NEXT: v_readlane_b32 s51, v63, 9
+; VI-NEXT: v_readlane_b32 s50, v63, 8
+; VI-NEXT: v_readlane_b32 s49, v63, 7
+; VI-NEXT: v_readlane_b32 s48, v63, 6
+; VI-NEXT: v_readlane_b32 s39, v63, 5
+; VI-NEXT: v_readlane_b32 s38, v63, 4
+; VI-NEXT: v_readlane_b32 s37, v63, 3
+; VI-NEXT: v_readlane_b32 s36, v63, 2
+; VI-NEXT: v_readlane_b32 s35, v63, 1
+; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_or_b32_sdwa v58, v23, v58 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
@@ -195410,43 +195410,43 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v63, s30, 0
-; GFX9-NEXT: v_writelane_b32 v63, s31, 1
-; GFX9-NEXT: v_writelane_b32 v63, s34, 2
-; GFX9-NEXT: v_writelane_b32 v63, s35, 3
-; GFX9-NEXT: v_writelane_b32 v63, s36, 4
-; GFX9-NEXT: v_writelane_b32 v63, s37, 5
-; GFX9-NEXT: v_writelane_b32 v63, s38, 6
-; GFX9-NEXT: v_writelane_b32 v63, s39, 7
-; GFX9-NEXT: v_writelane_b32 v63, s48, 8
-; GFX9-NEXT: v_writelane_b32 v63, s49, 9
-; GFX9-NEXT: v_writelane_b32 v63, s50, 10
-; GFX9-NEXT: v_writelane_b32 v63, s51, 11
-; GFX9-NEXT: v_writelane_b32 v63, s52, 12
-; GFX9-NEXT: v_writelane_b32 v63, s53, 13
-; GFX9-NEXT: v_writelane_b32 v63, s54, 14
-; GFX9-NEXT: v_writelane_b32 v63, s55, 15
-; GFX9-NEXT: v_writelane_b32 v63, s64, 16
-; GFX9-NEXT: v_writelane_b32 v63, s65, 17
-; GFX9-NEXT: v_writelane_b32 v63, s66, 18
-; GFX9-NEXT: v_writelane_b32 v63, s67, 19
-; GFX9-NEXT: v_writelane_b32 v63, s68, 20
-; GFX9-NEXT: v_writelane_b32 v63, s69, 21
-; GFX9-NEXT: v_writelane_b32 v63, s70, 22
-; GFX9-NEXT: v_writelane_b32 v63, s71, 23
-; GFX9-NEXT: v_writelane_b32 v63, s80, 24
-; GFX9-NEXT: v_writelane_b32 v63, s81, 25
-; GFX9-NEXT: v_writelane_b32 v63, s82, 26
-; GFX9-NEXT: v_writelane_b32 v63, s83, 27
-; GFX9-NEXT: v_writelane_b32 v63, s84, 28
-; GFX9-NEXT: v_writelane_b32 v63, s85, 29
-; GFX9-NEXT: v_writelane_b32 v63, s86, 30
-; GFX9-NEXT: v_writelane_b32 v63, s87, 31
-; GFX9-NEXT: v_writelane_b32 v63, s96, 32
-; GFX9-NEXT: v_writelane_b32 v63, s97, 33
-; GFX9-NEXT: v_writelane_b32 v63, s98, 34
+; GFX9-NEXT: v_writelane_b32 v63, s34, 0
+; GFX9-NEXT: v_writelane_b32 v63, s35, 1
+; GFX9-NEXT: v_writelane_b32 v63, s36, 2
+; GFX9-NEXT: v_writelane_b32 v63, s37, 3
+; GFX9-NEXT: v_writelane_b32 v63, s38, 4
+; GFX9-NEXT: v_writelane_b32 v63, s39, 5
+; GFX9-NEXT: v_writelane_b32 v63, s48, 6
+; GFX9-NEXT: v_writelane_b32 v63, s49, 7
+; GFX9-NEXT: v_writelane_b32 v63, s50, 8
+; GFX9-NEXT: v_writelane_b32 v63, s51, 9
+; GFX9-NEXT: v_writelane_b32 v63, s52, 10
+; GFX9-NEXT: v_writelane_b32 v63, s53, 11
+; GFX9-NEXT: v_writelane_b32 v63, s54, 12
+; GFX9-NEXT: v_writelane_b32 v63, s55, 13
+; GFX9-NEXT: v_writelane_b32 v63, s64, 14
+; GFX9-NEXT: v_writelane_b32 v63, s65, 15
+; GFX9-NEXT: v_writelane_b32 v63, s66, 16
+; GFX9-NEXT: v_writelane_b32 v63, s67, 17
+; GFX9-NEXT: v_writelane_b32 v63, s68, 18
+; GFX9-NEXT: v_writelane_b32 v63, s69, 19
+; GFX9-NEXT: v_writelane_b32 v63, s70, 20
+; GFX9-NEXT: v_writelane_b32 v63, s71, 21
+; GFX9-NEXT: v_writelane_b32 v63, s80, 22
+; GFX9-NEXT: v_writelane_b32 v63, s81, 23
+; GFX9-NEXT: v_writelane_b32 v63, s82, 24
+; GFX9-NEXT: v_writelane_b32 v63, s83, 25
+; GFX9-NEXT: v_writelane_b32 v63, s84, 26
+; GFX9-NEXT: v_writelane_b32 v63, s85, 27
+; GFX9-NEXT: v_writelane_b32 v63, s86, 28
+; GFX9-NEXT: v_writelane_b32 v63, s87, 29
+; GFX9-NEXT: v_writelane_b32 v63, s96, 30
+; GFX9-NEXT: v_writelane_b32 v63, s97, 31
+; GFX9-NEXT: v_writelane_b32 v63, s98, 32
+; GFX9-NEXT: v_writelane_b32 v63, s99, 33
+; GFX9-NEXT: v_writelane_b32 v63, s30, 34
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; GFX9-NEXT: v_writelane_b32 v63, s99, 35
+; GFX9-NEXT: v_writelane_b32 v63, s31, 35
; GFX9-NEXT: v_readfirstlane_b32 s44, v3
; GFX9-NEXT: v_readfirstlane_b32 s45, v4
; GFX9-NEXT: v_readfirstlane_b32 s42, v5
@@ -196329,42 +196329,42 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: v_or_b32_sdwa v25, v25, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v30, 8, v44
; GFX9-NEXT: v_or_b32_sdwa v26, v26, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_readlane_b32 s99, v63, 35
-; GFX9-NEXT: v_readlane_b32 s98, v63, 34
-; GFX9-NEXT: v_readlane_b32 s97, v63, 33
-; GFX9-NEXT: v_readlane_b32 s96, v63, 32
-; GFX9-NEXT: v_readlane_b32 s87, v63, 31
-; GFX9-NEXT: v_readlane_b32 s86, v63, 30
-; GFX9-NEXT: v_readlane_b32 s85, v63, 29
-; GFX9-NEXT: v_readlane_b32 s84, v63, 28
-; GFX9-NEXT: v_readlane_b32 s83, v63, 27
-; GFX9-NEXT: v_readlane_b32 s82, v63, 26
-; GFX9-NEXT: v_readlane_b32 s81, v63, 25
-; GFX9-NEXT: v_readlane_b32 s80, v63, 24
-; GFX9-NEXT: v_readlane_b32 s71, v63, 23
-; GFX9-NEXT: v_readlane_b32 s70, v63, 22
-; GFX9-NEXT: v_readlane_b32 s69, v63, 21
-; GFX9-NEXT: v_readlane_b32 s68, v63, 20
-; GFX9-NEXT: v_readlane_b32 s67, v63, 19
-; GFX9-NEXT: v_readlane_b32 s66, v63, 18
-; GFX9-NEXT: v_readlane_b32 s65, v63, 17
-; GFX9-NEXT: v_readlane_b32 s64, v63, 16
-; GFX9-NEXT: v_readlane_b32 s55, v63, 15
-; GFX9-NEXT: v_readlane_b32 s54, v63, 14
-; GFX9-NEXT: v_readlane_b32 s53, v63, 13
-; GFX9-NEXT: v_readlane_b32 s52, v63, 12
-; GFX9-NEXT: v_readlane_b32 s51, v63, 11
-; GFX9-NEXT: v_readlane_b32 s50, v63, 10
-; GFX9-NEXT: v_readlane_b32 s49, v63, 9
-; GFX9-NEXT: v_readlane_b32 s48, v63, 8
-; GFX9-NEXT: v_readlane_b32 s39, v63, 7
-; GFX9-NEXT: v_readlane_b32 s38, v63, 6
-; GFX9-NEXT: v_readlane_b32 s37, v63, 5
-; GFX9-NEXT: v_readlane_b32 s36, v63, 4
-; GFX9-NEXT: v_readlane_b32 s35, v63, 3
-; GFX9-NEXT: v_readlane_b32 s34, v63, 2
-; GFX9-NEXT: v_readlane_b32 s31, v63, 1
-; GFX9-NEXT: v_readlane_b32 s30, v63, 0
+; GFX9-NEXT: v_readlane_b32 s30, v63, 34
+; GFX9-NEXT: v_readlane_b32 s31, v63, 35
+; GFX9-NEXT: v_readlane_b32 s99, v63, 33
+; GFX9-NEXT: v_readlane_b32 s98, v63, 32
+; GFX9-NEXT: v_readlane_b32 s97, v63, 31
+; GFX9-NEXT: v_readlane_b32 s96, v63, 30
+; GFX9-NEXT: v_readlane_b32 s87, v63, 29
+; GFX9-NEXT: v_readlane_b32 s86, v63, 28
+; GFX9-NEXT: v_readlane_b32 s85, v63, 27
+; GFX9-NEXT: v_readlane_b32 s84, v63, 26
+; GFX9-NEXT: v_readlane_b32 s83, v63, 25
+; GFX9-NEXT: v_readlane_b32 s82, v63, 24
+; GFX9-NEXT: v_readlane_b32 s81, v63, 23
+; GFX9-NEXT: v_readlane_b32 s80, v63, 22
+; GFX9-NEXT: v_readlane_b32 s71, v63, 21
+; GFX9-NEXT: v_readlane_b32 s70, v63, 20
+; GFX9-NEXT: v_readlane_b32 s69, v63, 19
+; GFX9-NEXT: v_readlane_b32 s68, v63, 18
+; GFX9-NEXT: v_readlane_b32 s67, v63, 17
+; GFX9-NEXT: v_readlane_b32 s66, v63, 16
+; GFX9-NEXT: v_readlane_b32 s65, v63, 15
+; GFX9-NEXT: v_readlane_b32 s64, v63, 14
+; GFX9-NEXT: v_readlane_b32 s55, v63, 13
+; GFX9-NEXT: v_readlane_b32 s54, v63, 12
+; GFX9-NEXT: v_readlane_b32 s53, v63, 11
+; GFX9-NEXT: v_readlane_b32 s52, v63, 10
+; GFX9-NEXT: v_readlane_b32 s51, v63, 9
+; GFX9-NEXT: v_readlane_b32 s50, v63, 8
+; GFX9-NEXT: v_readlane_b32 s49, v63, 7
+; GFX9-NEXT: v_readlane_b32 s48, v63, 6
+; GFX9-NEXT: v_readlane_b32 s39, v63, 5
+; GFX9-NEXT: v_readlane_b32 s38, v63, 4
+; GFX9-NEXT: v_readlane_b32 s37, v63, 3
+; GFX9-NEXT: v_readlane_b32 s36, v63, 2
+; GFX9-NEXT: v_readlane_b32 s35, v63, 1
+; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; GFX9-NEXT: v_or_b32_sdwa v15, v38, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -196721,33 +196721,33 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v75, s30, 0
-; GFX11-NEXT: v_writelane_b32 v76, s96, 0
+; GFX11-NEXT: v_writelane_b32 v75, s34, 0
+; GFX11-NEXT: v_writelane_b32 v76, s98, 0
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
; GFX11-NEXT: v_readfirstlane_b32 s40, v1
; GFX11-NEXT: v_readfirstlane_b32 s41, v2
-; GFX11-NEXT: v_writelane_b32 v75, s31, 1
-; GFX11-NEXT: v_writelane_b32 v76, s97, 1
+; GFX11-NEXT: v_writelane_b32 v75, s35, 1
+; GFX11-NEXT: v_writelane_b32 v76, s99, 1
; GFX11-NEXT: v_readfirstlane_b32 s14, v3
; GFX11-NEXT: v_readfirstlane_b32 s15, v4
; GFX11-NEXT: v_readfirstlane_b32 s12, v5
-; GFX11-NEXT: v_writelane_b32 v75, s34, 2
-; GFX11-NEXT: v_writelane_b32 v76, s98, 2
+; GFX11-NEXT: v_writelane_b32 v75, s36, 2
+; GFX11-NEXT: v_writelane_b32 v76, s100, 2
; GFX11-NEXT: v_readfirstlane_b32 s13, v6
; GFX11-NEXT: v_readfirstlane_b32 s10, v7
; GFX11-NEXT: v_readfirstlane_b32 s11, v8
-; GFX11-NEXT: v_writelane_b32 v75, s35, 3
-; GFX11-NEXT: v_writelane_b32 v76, s99, 3
+; GFX11-NEXT: v_writelane_b32 v75, s37, 3
+; GFX11-NEXT: v_writelane_b32 v76, s101, 3
; GFX11-NEXT: v_readfirstlane_b32 s8, v9
; GFX11-NEXT: v_readfirstlane_b32 s9, v10
; GFX11-NEXT: v_readfirstlane_b32 s6, v11
-; GFX11-NEXT: v_writelane_b32 v75, s36, 4
-; GFX11-NEXT: v_writelane_b32 v76, s100, 4
+; GFX11-NEXT: v_writelane_b32 v75, s38, 4
+; GFX11-NEXT: v_writelane_b32 v76, s102, 4
; GFX11-NEXT: v_readfirstlane_b32 s7, v12
; GFX11-NEXT: v_readfirstlane_b32 s4, v13
; GFX11-NEXT: v_readfirstlane_b32 s5, v14
-; GFX11-NEXT: v_writelane_b32 v75, s37, 5
-; GFX11-NEXT: v_writelane_b32 v76, s101, 5
+; GFX11-NEXT: v_writelane_b32 v75, s39, 5
+; GFX11-NEXT: v_writelane_b32 v76, s103, 5
; GFX11-NEXT: s_mov_b32 s99, 0
; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
; GFX11-NEXT: s_clause 0x12
@@ -196770,37 +196770,37 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:8
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:4
; GFX11-NEXT: scratch_store_b32 off, v74, s32
-; GFX11-NEXT: v_writelane_b32 v75, s38, 6
-; GFX11-NEXT: v_writelane_b32 v76, s102, 6
+; GFX11-NEXT: v_writelane_b32 v75, s48, 6
+; GFX11-NEXT: v_writelane_b32 v76, s104, 6
; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane
; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane
-; GFX11-NEXT: v_writelane_b32 v75, s39, 7
-; GFX11-NEXT: v_writelane_b32 v76, s103, 7
-; GFX11-NEXT: v_writelane_b32 v75, s48, 8
-; GFX11-NEXT: v_writelane_b32 v76, s104, 8
-; GFX11-NEXT: v_writelane_b32 v75, s49, 9
-; GFX11-NEXT: v_writelane_b32 v75, s50, 10
-; GFX11-NEXT: v_writelane_b32 v75, s51, 11
-; GFX11-NEXT: v_writelane_b32 v75, s52, 12
-; GFX11-NEXT: v_writelane_b32 v75, s53, 13
-; GFX11-NEXT: v_writelane_b32 v75, s54, 14
-; GFX11-NEXT: v_writelane_b32 v75, s55, 15
-; GFX11-NEXT: v_writelane_b32 v75, s64, 16
-; GFX11-NEXT: v_writelane_b32 v75, s65, 17
-; GFX11-NEXT: v_writelane_b32 v75, s66, 18
-; GFX11-NEXT: v_writelane_b32 v75, s67, 19
-; GFX11-NEXT: v_writelane_b32 v75, s68, 20
-; GFX11-NEXT: v_writelane_b32 v75, s69, 21
-; GFX11-NEXT: v_writelane_b32 v75, s70, 22
-; GFX11-NEXT: v_writelane_b32 v75, s71, 23
-; GFX11-NEXT: v_writelane_b32 v75, s80, 24
-; GFX11-NEXT: v_writelane_b32 v75, s81, 25
-; GFX11-NEXT: v_writelane_b32 v75, s82, 26
-; GFX11-NEXT: v_writelane_b32 v75, s83, 27
-; GFX11-NEXT: v_writelane_b32 v75, s84, 28
-; GFX11-NEXT: v_writelane_b32 v75, s85, 29
-; GFX11-NEXT: v_writelane_b32 v75, s86, 30
-; GFX11-NEXT: v_writelane_b32 v75, s87, 31
+; GFX11-NEXT: v_writelane_b32 v75, s49, 7
+; GFX11-NEXT: v_writelane_b32 v76, s30, 7
+; GFX11-NEXT: v_writelane_b32 v75, s50, 8
+; GFX11-NEXT: v_writelane_b32 v76, s31, 8
+; GFX11-NEXT: v_writelane_b32 v75, s51, 9
+; GFX11-NEXT: v_writelane_b32 v75, s52, 10
+; GFX11-NEXT: v_writelane_b32 v75, s53, 11
+; GFX11-NEXT: v_writelane_b32 v75, s54, 12
+; GFX11-NEXT: v_writelane_b32 v75, s55, 13
+; GFX11-NEXT: v_writelane_b32 v75, s64, 14
+; GFX11-NEXT: v_writelane_b32 v75, s65, 15
+; GFX11-NEXT: v_writelane_b32 v75, s66, 16
+; GFX11-NEXT: v_writelane_b32 v75, s67, 17
+; GFX11-NEXT: v_writelane_b32 v75, s68, 18
+; GFX11-NEXT: v_writelane_b32 v75, s69, 19
+; GFX11-NEXT: v_writelane_b32 v75, s70, 20
+; GFX11-NEXT: v_writelane_b32 v75, s71, 21
+; GFX11-NEXT: v_writelane_b32 v75, s80, 22
+; GFX11-NEXT: v_writelane_b32 v75, s81, 23
+; GFX11-NEXT: v_writelane_b32 v75, s82, 24
+; GFX11-NEXT: v_writelane_b32 v75, s83, 25
+; GFX11-NEXT: v_writelane_b32 v75, s84, 26
+; GFX11-NEXT: v_writelane_b32 v75, s85, 27
+; GFX11-NEXT: v_writelane_b32 v75, s86, 28
+; GFX11-NEXT: v_writelane_b32 v75, s87, 29
+; GFX11-NEXT: v_writelane_b32 v75, s96, 30
+; GFX11-NEXT: v_writelane_b32 v75, s97, 31
; GFX11-NEXT: s_cbranch_scc0 .LBB95_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s27, 16
@@ -197689,47 +197689,47 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:64
; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:68
; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:72
-; GFX11-NEXT: v_readlane_b32 s104, v76, 8
-; GFX11-NEXT: v_readlane_b32 s103, v76, 7
-; GFX11-NEXT: v_readlane_b32 s102, v76, 6
-; GFX11-NEXT: v_readlane_b32 s101, v76, 5
-; GFX11-NEXT: v_readlane_b32 s100, v76, 4
-; GFX11-NEXT: v_readlane_b32 s99, v76, 3
-; GFX11-NEXT: v_readlane_b32 s98, v76, 2
-; GFX11-NEXT: v_readlane_b32 s97, v76, 1
-; GFX11-NEXT: v_readlane_b32 s96, v76, 0
-; GFX11-NEXT: v_readlane_b32 s87, v75, 31
-; GFX11-NEXT: v_readlane_b32 s86, v75, 30
-; GFX11-NEXT: v_readlane_b32 s85, v75, 29
-; GFX11-NEXT: v_readlane_b32 s84, v75, 28
-; GFX11-NEXT: v_readlane_b32 s83, v75, 27
-; GFX11-NEXT: v_readlane_b32 s82, v75, 26
-; GFX11-NEXT: v_readlane_b32 s81, v75, 25
-; GFX11-NEXT: v_readlane_b32 s80, v75, 24
-; GFX11-NEXT: v_readlane_b32 s71, v75, 23
-; GFX11-NEXT: v_readlane_b32 s70, v75, 22
-; GFX11-NEXT: v_readlane_b32 s69, v75, 21
-; GFX11-NEXT: v_readlane_b32 s68, v75, 20
-; GFX11-NEXT: v_readlane_b32 s67, v75, 19
-; GFX11-NEXT: v_readlane_b32 s66, v75, 18
-; GFX11-NEXT: v_readlane_b32 s65, v75, 17
-; GFX11-NEXT: v_readlane_b32 s64, v75, 16
-; GFX11-NEXT: v_readlane_b32 s55, v75, 15
-; GFX11-NEXT: v_readlane_b32 s54, v75, 14
-; GFX11-NEXT: v_readlane_b32 s53, v75, 13
-; GFX11-NEXT: v_readlane_b32 s52, v75, 12
-; GFX11-NEXT: v_readlane_b32 s51, v75, 11
-; GFX11-NEXT: v_readlane_b32 s50, v75, 10
-; GFX11-NEXT: v_readlane_b32 s49, v75, 9
-; GFX11-NEXT: v_readlane_b32 s48, v75, 8
-; GFX11-NEXT: v_readlane_b32 s39, v75, 7
-; GFX11-NEXT: v_readlane_b32 s38, v75, 6
-; GFX11-NEXT: v_readlane_b32 s37, v75, 5
-; GFX11-NEXT: v_readlane_b32 s36, v75, 4
-; GFX11-NEXT: v_readlane_b32 s35, v75, 3
-; GFX11-NEXT: v_readlane_b32 s34, v75, 2
-; GFX11-NEXT: v_readlane_b32 s31, v75, 1
-; GFX11-NEXT: v_readlane_b32 s30, v75, 0
+; GFX11-NEXT: v_readlane_b32 s30, v76, 7
+; GFX11-NEXT: v_readlane_b32 s31, v76, 8
+; GFX11-NEXT: v_readlane_b32 s104, v76, 6
+; GFX11-NEXT: v_readlane_b32 s103, v76, 5
+; GFX11-NEXT: v_readlane_b32 s102, v76, 4
+; GFX11-NEXT: v_readlane_b32 s101, v76, 3
+; GFX11-NEXT: v_readlane_b32 s100, v76, 2
+; GFX11-NEXT: v_readlane_b32 s99, v76, 1
+; GFX11-NEXT: v_readlane_b32 s98, v76, 0
+; GFX11-NEXT: v_readlane_b32 s97, v75, 31
+; GFX11-NEXT: v_readlane_b32 s96, v75, 30
+; GFX11-NEXT: v_readlane_b32 s87, v75, 29
+; GFX11-NEXT: v_readlane_b32 s86, v75, 28
+; GFX11-NEXT: v_readlane_b32 s85, v75, 27
+; GFX11-NEXT: v_readlane_b32 s84, v75, 26
+; GFX11-NEXT: v_readlane_b32 s83, v75, 25
+; GFX11-NEXT: v_readlane_b32 s82, v75, 24
+; GFX11-NEXT: v_readlane_b32 s81, v75, 23
+; GFX11-NEXT: v_readlane_b32 s80, v75, 22
+; GFX11-NEXT: v_readlane_b32 s71, v75, 21
+; GFX11-NEXT: v_readlane_b32 s70, v75, 20
+; GFX11-NEXT: v_readlane_b32 s69, v75, 19
+; GFX11-NEXT: v_readlane_b32 s68, v75, 18
+; GFX11-NEXT: v_readlane_b32 s67, v75, 17
+; GFX11-NEXT: v_readlane_b32 s66, v75, 16
+; GFX11-NEXT: v_readlane_b32 s65, v75, 15
+; GFX11-NEXT: v_readlane_b32 s64, v75, 14
+; GFX11-NEXT: v_readlane_b32 s55, v75, 13
+; GFX11-NEXT: v_readlane_b32 s54, v75, 12
+; GFX11-NEXT: v_readlane_b32 s53, v75, 11
+; GFX11-NEXT: v_readlane_b32 s52, v75, 10
+; GFX11-NEXT: v_readlane_b32 s51, v75, 9
+; GFX11-NEXT: v_readlane_b32 s50, v75, 8
+; GFX11-NEXT: v_readlane_b32 s49, v75, 7
+; GFX11-NEXT: v_readlane_b32 s48, v75, 6
+; GFX11-NEXT: v_readlane_b32 s39, v75, 5
+; GFX11-NEXT: v_readlane_b32 s38, v75, 4
+; GFX11-NEXT: v_readlane_b32 s37, v75, 3
+; GFX11-NEXT: v_readlane_b32 s36, v75, 2
+; GFX11-NEXT: v_readlane_b32 s35, v75, 1
+; GFX11-NEXT: v_readlane_b32 s34, v75, 0
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_load_b32 v75, off, s32 offset:76
@@ -204098,7 +204098,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:304
; SI-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_writelane_b32 v41, s30, 0
+; SI-NEXT: v_writelane_b32 v41, s34, 0
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_writelane_b32 v43, s29, 0
; SI-NEXT: v_writelane_b32 v43, s28, 1
@@ -204114,40 +204114,41 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: v_writelane_b32 v43, s18, 11
; SI-NEXT: v_writelane_b32 v43, s17, 12
; SI-NEXT: v_writelane_b32 v43, s16, 13
-; SI-NEXT: v_writelane_b32 v41, s31, 1
-; SI-NEXT: v_writelane_b32 v41, s34, 2
-; SI-NEXT: v_writelane_b32 v41, s35, 3
-; SI-NEXT: v_writelane_b32 v41, s36, 4
-; SI-NEXT: v_writelane_b32 v41, s37, 5
-; SI-NEXT: v_writelane_b32 v41, s38, 6
-; SI-NEXT: v_writelane_b32 v41, s39, 7
-; SI-NEXT: v_writelane_b32 v41, s48, 8
-; SI-NEXT: v_writelane_b32 v41, s49, 9
-; SI-NEXT: v_writelane_b32 v41, s50, 10
-; SI-NEXT: v_writelane_b32 v41, s51, 11
-; SI-NEXT: v_writelane_b32 v41, s52, 12
-; SI-NEXT: v_writelane_b32 v41, s53, 13
-; SI-NEXT: v_writelane_b32 v41, s54, 14
-; SI-NEXT: v_writelane_b32 v41, s55, 15
-; SI-NEXT: v_writelane_b32 v41, s64, 16
-; SI-NEXT: v_writelane_b32 v41, s65, 17
-; SI-NEXT: v_writelane_b32 v41, s66, 18
-; SI-NEXT: v_writelane_b32 v41, s67, 19
-; SI-NEXT: v_writelane_b32 v41, s68, 20
-; SI-NEXT: v_writelane_b32 v41, s69, 21
-; SI-NEXT: v_writelane_b32 v41, s70, 22
-; SI-NEXT: v_writelane_b32 v41, s71, 23
-; SI-NEXT: v_writelane_b32 v41, s80, 24
-; SI-NEXT: v_writelane_b32 v41, s81, 25
-; SI-NEXT: v_writelane_b32 v41, s82, 26
-; SI-NEXT: v_writelane_b32 v41, s83, 27
-; SI-NEXT: v_writelane_b32 v41, s84, 28
-; SI-NEXT: v_writelane_b32 v41, s85, 29
-; SI-NEXT: v_writelane_b32 v41, s86, 30
-; SI-NEXT: v_writelane_b32 v41, s87, 31
-; SI-NEXT: v_writelane_b32 v41, s96, 32
-; SI-NEXT: v_writelane_b32 v41, s97, 33
-; SI-NEXT: v_writelane_b32 v41, s98, 34
+; SI-NEXT: v_writelane_b32 v41, s35, 1
+; SI-NEXT: v_writelane_b32 v41, s36, 2
+; SI-NEXT: v_writelane_b32 v41, s37, 3
+; SI-NEXT: v_writelane_b32 v41, s38, 4
+; SI-NEXT: v_writelane_b32 v41, s39, 5
+; SI-NEXT: v_writelane_b32 v41, s48, 6
+; SI-NEXT: v_writelane_b32 v41, s49, 7
+; SI-NEXT: v_writelane_b32 v41, s50, 8
+; SI-NEXT: v_writelane_b32 v41, s51, 9
+; SI-NEXT: v_writelane_b32 v41, s52, 10
+; SI-NEXT: v_writelane_b32 v41, s53, 11
+; SI-NEXT: v_writelane_b32 v41, s54, 12
+; SI-NEXT: v_writelane_b32 v41, s55, 13
+; SI-NEXT: v_writelane_b32 v41, s64, 14
+; SI-NEXT: v_writelane_b32 v41, s65, 15
+; SI-NEXT: v_writelane_b32 v41, s66, 16
+; SI-NEXT: v_writelane_b32 v41, s67, 17
+; SI-NEXT: v_writelane_b32 v41, s68, 18
+; SI-NEXT: v_writelane_b32 v41, s69, 19
+; SI-NEXT: v_writelane_b32 v41, s70, 20
+; SI-NEXT: v_writelane_b32 v41, s71, 21
+; SI-NEXT: v_writelane_b32 v41, s80, 22
+; SI-NEXT: v_writelane_b32 v41, s81, 23
+; SI-NEXT: v_writelane_b32 v41, s82, 24
+; SI-NEXT: v_writelane_b32 v41, s83, 25
+; SI-NEXT: v_writelane_b32 v41, s84, 26
+; SI-NEXT: v_writelane_b32 v41, s85, 27
+; SI-NEXT: v_writelane_b32 v41, s86, 28
+; SI-NEXT: v_writelane_b32 v41, s87, 29
+; SI-NEXT: v_writelane_b32 v41, s96, 30
+; SI-NEXT: v_writelane_b32 v41, s97, 31
+; SI-NEXT: v_writelane_b32 v41, s98, 32
+; SI-NEXT: v_writelane_b32 v41, s99, 33
+; SI-NEXT: v_writelane_b32 v41, s30, 34
+; SI-NEXT: v_writelane_b32 v41, s31, 35
; SI-NEXT: v_readfirstlane_b32 s39, v26
; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
; SI-NEXT: v_readfirstlane_b32 s47, v12
@@ -204171,7 +204172,6 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s60, v27
; SI-NEXT: v_readfirstlane_b32 s11, v1
; SI-NEXT: v_readfirstlane_b32 s12, v2
-; SI-NEXT: v_readfirstlane_b32 s13, v9
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_readfirstlane_b32 s4, v31
; SI-NEXT: v_writelane_b32 v43, s4, 14
@@ -204205,6 +204205,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:256
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s6, v38
+; SI-NEXT: v_readfirstlane_b32 s13, v9
; SI-NEXT: v_readfirstlane_b32 s14, v10
; SI-NEXT: v_readfirstlane_b32 s15, v8
; SI-NEXT: v_readfirstlane_b32 s18, v7
@@ -204217,7 +204218,6 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s76, v16
; SI-NEXT: v_readfirstlane_b32 s77, v15
; SI-NEXT: v_readfirstlane_b32 s38, v25
-; SI-NEXT: v_writelane_b32 v41, s99, 35
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_readfirstlane_b32 s4, v31
; SI-NEXT: v_writelane_b32 v43, s4, 19
@@ -205721,42 +205721,42 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: v_mov_b32_e32 v1, s4
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; SI-NEXT: v_readlane_b32 s99, v41, 35
-; SI-NEXT: v_readlane_b32 s98, v41, 34
-; SI-NEXT: v_readlane_b32 s97, v41, 33
-; SI-NEXT: v_readlane_b32 s96, v41, 32
-; SI-NEXT: v_readlane_b32 s87, v41, 31
-; SI-NEXT: v_readlane_b32 s86, v41, 30
-; SI-NEXT: v_readlane_b32 s85, v41, 29
-; SI-NEXT: v_readlane_b32 s84, v41, 28
-; SI-NEXT: v_readlane_b32 s83, v41, 27
-; SI-NEXT: v_readlane_b32 s82, v41, 26
-; SI-NEXT: v_readlane_b32 s81, v41, 25
-; SI-NEXT: v_readlane_b32 s80, v41, 24
-; SI-NEXT: v_readlane_b32 s71, v41, 23
-; SI-NEXT: v_readlane_b32 s70, v41, 22
-; SI-NEXT: v_readlane_b32 s69, v41, 21
-; SI-NEXT: v_readlane_b32 s68, v41, 20
-; SI-NEXT: v_readlane_b32 s67, v41, 19
-; SI-NEXT: v_readlane_b32 s66, v41, 18
-; SI-NEXT: v_readlane_b32 s65, v41, 17
-; SI-NEXT: v_readlane_b32 s64, v41, 16
-; SI-NEXT: v_readlane_b32 s55, v41, 15
-; SI-NEXT: v_readlane_b32 s54, v41, 14
-; SI-NEXT: v_readlane_b32 s53, v41, 13
-; SI-NEXT: v_readlane_b32 s52, v41, 12
-; SI-NEXT: v_readlane_b32 s51, v41, 11
-; SI-NEXT: v_readlane_b32 s50, v41, 10
-; SI-NEXT: v_readlane_b32 s49, v41, 9
-; SI-NEXT: v_readlane_b32 s48, v41, 8
-; SI-NEXT: v_readlane_b32 s39, v41, 7
-; SI-NEXT: v_readlane_b32 s38, v41, 6
-; SI-NEXT: v_readlane_b32 s37, v41, 5
-; SI-NEXT: v_readlane_b32 s36, v41, 4
-; SI-NEXT: v_readlane_b32 s35, v41, 3
-; SI-NEXT: v_readlane_b32 s34, v41, 2
-; SI-NEXT: v_readlane_b32 s31, v41, 1
-; SI-NEXT: v_readlane_b32 s30, v41, 0
+; SI-NEXT: v_readlane_b32 s30, v41, 34
+; SI-NEXT: v_readlane_b32 s31, v41, 35
+; SI-NEXT: v_readlane_b32 s99, v41, 33
+; SI-NEXT: v_readlane_b32 s98, v41, 32
+; SI-NEXT: v_readlane_b32 s97, v41, 31
+; SI-NEXT: v_readlane_b32 s96, v41, 30
+; SI-NEXT: v_readlane_b32 s87, v41, 29
+; SI-NEXT: v_readlane_b32 s86, v41, 28
+; SI-NEXT: v_readlane_b32 s85, v41, 27
+; SI-NEXT: v_readlane_b32 s84, v41, 26
+; SI-NEXT: v_readlane_b32 s83, v41, 25
+; SI-NEXT: v_readlane_b32 s82, v41, 24
+; SI-NEXT: v_readlane_b32 s81, v41, 23
+; SI-NEXT: v_readlane_b32 s80, v41, 22
+; SI-NEXT: v_readlane_b32 s71, v41, 21
+; SI-NEXT: v_readlane_b32 s70, v41, 20
+; SI-NEXT: v_readlane_b32 s69, v41, 19
+; SI-NEXT: v_readlane_b32 s68, v41, 18
+; SI-NEXT: v_readlane_b32 s67, v41, 17
+; SI-NEXT: v_readlane_b32 s66, v41, 16
+; SI-NEXT: v_readlane_b32 s65, v41, 15
+; SI-NEXT: v_readlane_b32 s64, v41, 14
+; SI-NEXT: v_readlane_b32 s55, v41, 13
+; SI-NEXT: v_readlane_b32 s54, v41, 12
+; SI-NEXT: v_readlane_b32 s53, v41, 11
+; SI-NEXT: v_readlane_b32 s52, v41, 10
+; SI-NEXT: v_readlane_b32 s51, v41, 9
+; SI-NEXT: v_readlane_b32 s50, v41, 8
+; SI-NEXT: v_readlane_b32 s49, v41, 7
+; SI-NEXT: v_readlane_b32 s48, v41, 6
+; SI-NEXT: v_readlane_b32 s39, v41, 5
+; SI-NEXT: v_readlane_b32 s38, v41, 4
+; SI-NEXT: v_readlane_b32 s37, v41, 3
+; SI-NEXT: v_readlane_b32 s36, v41, 2
+; SI-NEXT: v_readlane_b32 s35, v41, 1
+; SI-NEXT: v_readlane_b32 s34, v41, 0
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
@@ -214934,35 +214934,33 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:52
; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
; SI-NEXT: s_waitcnt expcnt(3)
-; SI-NEXT: v_writelane_b32 v40, s30, 0
-; SI-NEXT: v_writelane_b32 v40, s31, 1
-; SI-NEXT: v_writelane_b32 v40, s34, 2
-; SI-NEXT: v_writelane_b32 v40, s35, 3
-; SI-NEXT: v_writelane_b32 v40, s36, 4
-; SI-NEXT: v_writelane_b32 v40, s37, 5
-; SI-NEXT: v_writelane_b32 v40, s38, 6
-; SI-NEXT: v_writelane_b32 v40, s39, 7
-; SI-NEXT: v_writelane_b32 v40, s48, 8
-; SI-NEXT: v_writelane_b32 v40, s49, 9
-; SI-NEXT: v_writelane_b32 v40, s50, 10
-; SI-NEXT: v_writelane_b32 v40, s51, 11
-; SI-NEXT: v_writelane_b32 v40, s52, 12
-; SI-NEXT: v_writelane_b32 v40, s53, 13
-; SI-NEXT: v_writelane_b32 v40, s54, 14
-; SI-NEXT: v_writelane_b32 v40, s55, 15
-; SI-NEXT: v_writelane_b32 v40, s64, 16
-; SI-NEXT: v_writelane_b32 v40, s65, 17
-; SI-NEXT: v_writelane_b32 v40, s66, 18
-; SI-NEXT: v_writelane_b32 v40, s67, 19
-; SI-NEXT: v_writelane_b32 v40, s68, 20
-; SI-NEXT: v_writelane_b32 v40, s69, 21
-; SI-NEXT: v_writelane_b32 v40, s70, 22
+; SI-NEXT: v_writelane_b32 v40, s34, 0
+; SI-NEXT: v_writelane_b32 v40, s35, 1
+; SI-NEXT: v_writelane_b32 v40, s36, 2
+; SI-NEXT: v_writelane_b32 v40, s37, 3
+; SI-NEXT: v_writelane_b32 v40, s38, 4
+; SI-NEXT: v_writelane_b32 v40, s39, 5
+; SI-NEXT: v_writelane_b32 v40, s48, 6
+; SI-NEXT: v_writelane_b32 v40, s49, 7
+; SI-NEXT: v_writelane_b32 v40, s50, 8
+; SI-NEXT: v_writelane_b32 v40, s51, 9
+; SI-NEXT: v_writelane_b32 v40, s52, 10
+; SI-NEXT: v_writelane_b32 v40, s53, 11
+; SI-NEXT: v_writelane_b32 v40, s54, 12
+; SI-NEXT: v_writelane_b32 v40, s55, 13
+; SI-NEXT: v_writelane_b32 v40, s64, 14
+; SI-NEXT: v_writelane_b32 v40, s65, 15
+; SI-NEXT: v_writelane_b32 v40, s66, 16
+; SI-NEXT: v_writelane_b32 v40, s67, 17
+; SI-NEXT: v_writelane_b32 v40, s68, 18
+; SI-NEXT: v_writelane_b32 v40, s69, 19
+; SI-NEXT: v_writelane_b32 v40, s70, 20
; SI-NEXT: s_mov_b32 s88, s17
-; SI-NEXT: v_writelane_b32 v40, s71, 23
-; SI-NEXT: v_writelane_b32 v40, s80, 24
-; SI-NEXT: v_writelane_b32 v40, s81, 25
-; SI-NEXT: v_writelane_b32 v40, s82, 26
-; SI-NEXT: v_writelane_b32 v40, s83, 27
+; SI-NEXT: v_writelane_b32 v40, s71, 21
+; SI-NEXT: v_writelane_b32 v40, s80, 22
+; SI-NEXT: v_writelane_b32 v40, s81, 23
+; SI-NEXT: v_writelane_b32 v40, s82, 24
+; SI-NEXT: v_writelane_b32 v40, s83, 25
; SI-NEXT: v_readfirstlane_b32 s6, v16
; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
; SI-NEXT: v_readfirstlane_b32 s7, v15
@@ -214974,28 +214972,30 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: v_writelane_b32 v41, s8, 2
; SI-NEXT: v_readfirstlane_b32 s10, v19
; SI-NEXT: v_writelane_b32 v41, s9, 3
+; SI-NEXT: v_writelane_b32 v40, s84, 26
; SI-NEXT: v_readfirstlane_b32 s11, v25
; SI-NEXT: v_writelane_b32 v41, s10, 4
+; SI-NEXT: v_writelane_b32 v40, s85, 27
; SI-NEXT: v_readfirstlane_b32 s12, v24
; SI-NEXT: v_writelane_b32 v41, s11, 5
+; SI-NEXT: v_writelane_b32 v40, s86, 28
; SI-NEXT: v_readfirstlane_b32 s13, v23
; SI-NEXT: v_writelane_b32 v41, s12, 6
+; SI-NEXT: v_writelane_b32 v40, s87, 29
; SI-NEXT: v_readfirstlane_b32 s15, v29
; SI-NEXT: v_writelane_b32 v41, s13, 7
+; SI-NEXT: v_writelane_b32 v40, s96, 30
; SI-NEXT: v_readfirstlane_b32 s14, v28
; SI-NEXT: v_writelane_b32 v41, s15, 8
+; SI-NEXT: v_writelane_b32 v40, s97, 31
; SI-NEXT: s_mov_b32 s79, s16
; SI-NEXT: v_readfirstlane_b32 s16, v27
; SI-NEXT: v_writelane_b32 v41, s14, 9
+; SI-NEXT: v_writelane_b32 v40, s98, 32
; SI-NEXT: v_writelane_b32 v41, s16, 10
-; SI-NEXT: v_writelane_b32 v40, s84, 28
-; SI-NEXT: v_writelane_b32 v40, s85, 29
-; SI-NEXT: v_writelane_b32 v40, s86, 30
-; SI-NEXT: v_writelane_b32 v40, s87, 31
-; SI-NEXT: v_writelane_b32 v40, s96, 32
-; SI-NEXT: v_writelane_b32 v40, s97, 33
-; SI-NEXT: v_writelane_b32 v40, s98, 34
-; SI-NEXT: v_writelane_b32 v40, s99, 35
+; SI-NEXT: v_writelane_b32 v40, s99, 33
+; SI-NEXT: v_writelane_b32 v40, s30, 34
+; SI-NEXT: v_writelane_b32 v40, s31, 35
; SI-NEXT: v_readfirstlane_b32 s98, v30
; SI-NEXT: v_readfirstlane_b32 s97, v26
; SI-NEXT: v_readfirstlane_b32 s96, v22
@@ -216310,6 +216310,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v40, 34
; SI-NEXT: v_readlane_b32 s21, v41, 33
; SI-NEXT: v_readlane_b32 s19, v41, 51
; SI-NEXT: v_readlane_b32 s17, v41, 57
@@ -216318,42 +216319,41 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: v_readlane_b32 s11, v43, 11
; SI-NEXT: v_readlane_b32 s9, v43, 17
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s99, v40, 35
-; SI-NEXT: v_readlane_b32 s98, v40, 34
-; SI-NEXT: v_readlane_b32 s97, v40, 33
-; SI-NEXT: v_readlane_b32 s96, v40, 32
-; SI-NEXT: v_readlane_b32 s87, v40, 31
-; SI-NEXT: v_readlane_b32 s86, v40, 30
-; SI-NEXT: v_readlane_b32 s85, v40, 29
-; SI-NEXT: v_readlane_b32 s84, v40, 28
-; SI-NEXT: v_readlane_b32 s83, v40, 27
-; SI-NEXT: v_readlane_b32 s82, v40, 26
-; SI-NEXT: v_readlane_b32 s81, v40, 25
-; SI-NEXT: v_readlane_b32 s80, v40, 24
-; SI-NEXT: v_readlane_b32 s71, v40, 23
-; SI-NEXT: v_readlane_b32 s70, v40, 22
-; SI-NEXT: v_readlane_b32 s69, v40, 21
-; SI-NEXT: v_readlane_b32 s68, v40, 20
-; SI-NEXT: v_readlane_b32 s67, v40, 19
-; SI-NEXT: v_readlane_b32 s66, v40, 18
-; SI-NEXT: v_readlane_b32 s65, v40, 17
-; SI-NEXT: v_readlane_b32 s64, v40, 16
-; SI-NEXT: v_readlane_b32 s55, v40, 15
-; SI-NEXT: v_readlane_b32 s54, v40, 14
-; SI-NEXT: v_readlane_b32 s53, v40, 13
-; SI-NEXT: v_readlane_b32 s52, v40, 12
-; SI-NEXT: v_readlane_b32 s51, v40, 11
-; SI-NEXT: v_readlane_b32 s50, v40, 10
-; SI-NEXT: v_readlane_b32 s49, v40, 9
-; SI-NEXT: v_readlane_b32 s48, v40, 8
-; SI-NEXT: v_readlane_b32 s39, v40, 7
-; SI-NEXT: v_readlane_b32 s38, v40, 6
-; SI-NEXT: v_readlane_b32 s37, v40, 5
-; SI-NEXT: v_readlane_b32 s36, v40, 4
-; SI-NEXT: v_readlane_b32 s35, v40, 3
-; SI-NEXT: v_readlane_b32 s34, v40, 2
-; SI-NEXT: v_readlane_b32 s31, v40, 1
-; SI-NEXT: v_readlane_b32 s30, v40, 0
+; SI-NEXT: v_readlane_b32 s31, v40, 35
+; SI-NEXT: v_readlane_b32 s99, v40, 33
+; SI-NEXT: v_readlane_b32 s98, v40, 32
+; SI-NEXT: v_readlane_b32 s97, v40, 31
+; SI-NEXT: v_readlane_b32 s96, v40, 30
+; SI-NEXT: v_readlane_b32 s87, v40, 29
+; SI-NEXT: v_readlane_b32 s86, v40, 28
+; SI-NEXT: v_readlane_b32 s85, v40, 27
+; SI-NEXT: v_readlane_b32 s84, v40, 26
+; SI-NEXT: v_readlane_b32 s83, v40, 25
+; SI-NEXT: v_readlane_b32 s82, v40, 24
+; SI-NEXT: v_readlane_b32 s81, v40, 23
+; SI-NEXT: v_readlane_b32 s80, v40, 22
+; SI-NEXT: v_readlane_b32 s71, v40, 21
+; SI-NEXT: v_readlane_b32 s70, v40, 20
+; SI-NEXT: v_readlane_b32 s69, v40, 19
+; SI-NEXT: v_readlane_b32 s68, v40, 18
+; SI-NEXT: v_readlane_b32 s67, v40, 17
+; SI-NEXT: v_readlane_b32 s66, v40, 16
+; SI-NEXT: v_readlane_b32 s65, v40, 15
+; SI-NEXT: v_readlane_b32 s64, v40, 14
+; SI-NEXT: v_readlane_b32 s55, v40, 13
+; SI-NEXT: v_readlane_b32 s54, v40, 12
+; SI-NEXT: v_readlane_b32 s53, v40, 11
+; SI-NEXT: v_readlane_b32 s52, v40, 10
+; SI-NEXT: v_readlane_b32 s51, v40, 9
+; SI-NEXT: v_readlane_b32 s50, v40, 8
+; SI-NEXT: v_readlane_b32 s49, v40, 7
+; SI-NEXT: v_readlane_b32 s48, v40, 6
+; SI-NEXT: v_readlane_b32 s39, v40, 5
+; SI-NEXT: v_readlane_b32 s38, v40, 4
+; SI-NEXT: v_readlane_b32 s37, v40, 3
+; SI-NEXT: v_readlane_b32 s36, v40, 2
+; SI-NEXT: v_readlane_b32 s35, v40, 1
+; SI-NEXT: v_readlane_b32 s34, v40, 0
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
@@ -216595,38 +216595,38 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v20, s30, 0
-; VI-NEXT: v_writelane_b32 v20, s31, 1
-; VI-NEXT: v_writelane_b32 v20, s34, 2
-; VI-NEXT: v_writelane_b32 v20, s35, 3
-; VI-NEXT: v_writelane_b32 v20, s36, 4
-; VI-NEXT: v_writelane_b32 v20, s37, 5
-; VI-NEXT: v_writelane_b32 v20, s38, 6
-; VI-NEXT: v_writelane_b32 v20, s39, 7
-; VI-NEXT: v_writelane_b32 v20, s48, 8
-; VI-NEXT: v_writelane_b32 v20, s49, 9
-; VI-NEXT: v_writelane_b32 v20, s50, 10
-; VI-NEXT: v_writelane_b32 v20, s51, 11
-; VI-NEXT: v_writelane_b32 v20, s52, 12
-; VI-NEXT: v_writelane_b32 v20, s53, 13
-; VI-NEXT: v_writelane_b32 v20, s54, 14
-; VI-NEXT: v_writelane_b32 v20, s55, 15
-; VI-NEXT: v_writelane_b32 v20, s64, 16
-; VI-NEXT: v_writelane_b32 v20, s65, 17
-; VI-NEXT: v_writelane_b32 v20, s66, 18
-; VI-NEXT: v_writelane_b32 v20, s67, 19
-; VI-NEXT: v_writelane_b32 v20, s68, 20
-; VI-NEXT: v_writelane_b32 v20, s69, 21
-; VI-NEXT: v_writelane_b32 v20, s70, 22
-; VI-NEXT: v_writelane_b32 v20, s71, 23
-; VI-NEXT: v_writelane_b32 v20, s80, 24
-; VI-NEXT: v_writelane_b32 v20, s81, 25
-; VI-NEXT: v_writelane_b32 v20, s82, 26
-; VI-NEXT: v_writelane_b32 v20, s83, 27
-; VI-NEXT: v_writelane_b32 v20, s84, 28
-; VI-NEXT: v_writelane_b32 v20, s85, 29
+; VI-NEXT: v_writelane_b32 v20, s34, 0
+; VI-NEXT: v_writelane_b32 v20, s35, 1
+; VI-NEXT: v_writelane_b32 v20, s36, 2
+; VI-NEXT: v_writelane_b32 v20, s37, 3
+; VI-NEXT: v_writelane_b32 v20, s38, 4
+; VI-NEXT: v_writelane_b32 v20, s39, 5
+; VI-NEXT: v_writelane_b32 v20, s48, 6
+; VI-NEXT: v_writelane_b32 v20, s49, 7
+; VI-NEXT: v_writelane_b32 v20, s50, 8
+; VI-NEXT: v_writelane_b32 v20, s51, 9
+; VI-NEXT: v_writelane_b32 v20, s52, 10
+; VI-NEXT: v_writelane_b32 v20, s53, 11
+; VI-NEXT: v_writelane_b32 v20, s54, 12
+; VI-NEXT: v_writelane_b32 v20, s55, 13
+; VI-NEXT: v_writelane_b32 v20, s64, 14
+; VI-NEXT: v_writelane_b32 v20, s65, 15
+; VI-NEXT: v_writelane_b32 v20, s66, 16
+; VI-NEXT: v_writelane_b32 v20, s67, 17
+; VI-NEXT: v_writelane_b32 v20, s68, 18
+; VI-NEXT: v_writelane_b32 v20, s69, 19
+; VI-NEXT: v_writelane_b32 v20, s70, 20
+; VI-NEXT: v_writelane_b32 v20, s71, 21
+; VI-NEXT: v_writelane_b32 v20, s80, 22
+; VI-NEXT: v_writelane_b32 v20, s81, 23
+; VI-NEXT: v_writelane_b32 v20, s82, 24
+; VI-NEXT: v_writelane_b32 v20, s83, 25
+; VI-NEXT: v_writelane_b32 v20, s84, 26
+; VI-NEXT: v_writelane_b32 v20, s85, 27
+; VI-NEXT: v_writelane_b32 v20, s86, 28
+; VI-NEXT: v_writelane_b32 v20, s87, 29
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; VI-NEXT: v_writelane_b32 v20, s86, 30
+; VI-NEXT: v_writelane_b32 v20, s30, 30
; VI-NEXT: v_readfirstlane_b32 s42, v3
; VI-NEXT: v_readfirstlane_b32 s43, v4
; VI-NEXT: v_readfirstlane_b32 s40, v5
@@ -216646,7 +216646,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: s_and_b64 s[46:47], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s45, v2
-; VI-NEXT: v_writelane_b32 v20, s87, 31
+; VI-NEXT: v_writelane_b32 v20, s31, 31
; VI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; VI-NEXT: s_cbranch_scc0 .LBB99_4
; VI-NEXT: ; %bb.1: ; %cmp.false
@@ -217561,39 +217561,39 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
; VI-NEXT: v_mov_b32_e32 v1, s4
+; VI-NEXT: v_readlane_b32 s30, v20, 30
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT: v_readlane_b32 s87, v20, 31
-; VI-NEXT: v_readlane_b32 s86, v20, 30
-; VI-NEXT: v_readlane_b32 s85, v20, 29
-; VI-NEXT: v_readlane_b32 s84, v20, 28
-; VI-NEXT: v_readlane_b32 s83, v20, 27
-; VI-NEXT: v_readlane_b32 s82, v20, 26
-; VI-NEXT: v_readlane_b32 s81, v20, 25
-; VI-NEXT: v_readlane_b32 s80, v20, 24
-; VI-NEXT: v_readlane_b32 s71, v20, 23
-; VI-NEXT: v_readlane_b32 s70, v20, 22
-; VI-NEXT: v_readlane_b32 s69, v20, 21
-; VI-NEXT: v_readlane_b32 s68, v20, 20
-; VI-NEXT: v_readlane_b32 s67, v20, 19
-; VI-NEXT: v_readlane_b32 s66, v20, 18
-; VI-NEXT: v_readlane_b32 s65, v20, 17
-; VI-NEXT: v_readlane_b32 s64, v20, 16
-; VI-NEXT: v_readlane_b32 s55, v20, 15
-; VI-NEXT: v_readlane_b32 s54, v20, 14
-; VI-NEXT: v_readlane_b32 s53, v20, 13
-; VI-NEXT: v_readlane_b32 s52, v20, 12
-; VI-NEXT: v_readlane_b32 s51, v20, 11
-; VI-NEXT: v_readlane_b32 s50, v20, 10
-; VI-NEXT: v_readlane_b32 s49, v20, 9
-; VI-NEXT: v_readlane_b32 s48, v20, 8
-; VI-NEXT: v_readlane_b32 s39, v20, 7
-; VI-NEXT: v_readlane_b32 s38, v20, 6
-; VI-NEXT: v_readlane_b32 s37, v20, 5
-; VI-NEXT: v_readlane_b32 s36, v20, 4
-; VI-NEXT: v_readlane_b32 s35, v20, 3
-; VI-NEXT: v_readlane_b32 s34, v20, 2
-; VI-NEXT: v_readlane_b32 s31, v20, 1
-; VI-NEXT: v_readlane_b32 s30, v20, 0
+; VI-NEXT: v_readlane_b32 s31, v20, 31
+; VI-NEXT: v_readlane_b32 s87, v20, 29
+; VI-NEXT: v_readlane_b32 s86, v20, 28
+; VI-NEXT: v_readlane_b32 s85, v20, 27
+; VI-NEXT: v_readlane_b32 s84, v20, 26
+; VI-NEXT: v_readlane_b32 s83, v20, 25
+; VI-NEXT: v_readlane_b32 s82, v20, 24
+; VI-NEXT: v_readlane_b32 s81, v20, 23
+; VI-NEXT: v_readlane_b32 s80, v20, 22
+; VI-NEXT: v_readlane_b32 s71, v20, 21
+; VI-NEXT: v_readlane_b32 s70, v20, 20
+; VI-NEXT: v_readlane_b32 s69, v20, 19
+; VI-NEXT: v_readlane_b32 s68, v20, 18
+; VI-NEXT: v_readlane_b32 s67, v20, 17
+; VI-NEXT: v_readlane_b32 s66, v20, 16
+; VI-NEXT: v_readlane_b32 s65, v20, 15
+; VI-NEXT: v_readlane_b32 s64, v20, 14
+; VI-NEXT: v_readlane_b32 s55, v20, 13
+; VI-NEXT: v_readlane_b32 s54, v20, 12
+; VI-NEXT: v_readlane_b32 s53, v20, 11
+; VI-NEXT: v_readlane_b32 s52, v20, 10
+; VI-NEXT: v_readlane_b32 s51, v20, 9
+; VI-NEXT: v_readlane_b32 s50, v20, 8
+; VI-NEXT: v_readlane_b32 s49, v20, 7
+; VI-NEXT: v_readlane_b32 s48, v20, 6
+; VI-NEXT: v_readlane_b32 s39, v20, 5
+; VI-NEXT: v_readlane_b32 s38, v20, 4
+; VI-NEXT: v_readlane_b32 s37, v20, 3
+; VI-NEXT: v_readlane_b32 s36, v20, 2
+; VI-NEXT: v_readlane_b32 s35, v20, 1
+; VI-NEXT: v_readlane_b32 s34, v20, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -217764,43 +217764,43 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v63, s30, 0
-; GFX9-NEXT: v_writelane_b32 v63, s31, 1
-; GFX9-NEXT: v_writelane_b32 v63, s34, 2
-; GFX9-NEXT: v_writelane_b32 v63, s35, 3
-; GFX9-NEXT: v_writelane_b32 v63, s36, 4
-; GFX9-NEXT: v_writelane_b32 v63, s37, 5
-; GFX9-NEXT: v_writelane_b32 v63, s38, 6
-; GFX9-NEXT: v_writelane_b32 v63, s39, 7
-; GFX9-NEXT: v_writelane_b32 v63, s48, 8
-; GFX9-NEXT: v_writelane_b32 v63, s49, 9
-; GFX9-NEXT: v_writelane_b32 v63, s50, 10
-; GFX9-NEXT: v_writelane_b32 v63, s51, 11
-; GFX9-NEXT: v_writelane_b32 v63, s52, 12
-; GFX9-NEXT: v_writelane_b32 v63, s53, 13
-; GFX9-NEXT: v_writelane_b32 v63, s54, 14
-; GFX9-NEXT: v_writelane_b32 v63, s55, 15
-; GFX9-NEXT: v_writelane_b32 v63, s64, 16
-; GFX9-NEXT: v_writelane_b32 v63, s65, 17
-; GFX9-NEXT: v_writelane_b32 v63, s66, 18
-; GFX9-NEXT: v_writelane_b32 v63, s67, 19
-; GFX9-NEXT: v_writelane_b32 v63, s68, 20
-; GFX9-NEXT: v_writelane_b32 v63, s69, 21
-; GFX9-NEXT: v_writelane_b32 v63, s70, 22
-; GFX9-NEXT: v_writelane_b32 v63, s71, 23
-; GFX9-NEXT: v_writelane_b32 v63, s80, 24
-; GFX9-NEXT: v_writelane_b32 v63, s81, 25
-; GFX9-NEXT: v_writelane_b32 v63, s82, 26
-; GFX9-NEXT: v_writelane_b32 v63, s83, 27
-; GFX9-NEXT: v_writelane_b32 v63, s84, 28
-; GFX9-NEXT: v_writelane_b32 v63, s85, 29
-; GFX9-NEXT: v_writelane_b32 v63, s86, 30
-; GFX9-NEXT: v_writelane_b32 v63, s87, 31
-; GFX9-NEXT: v_writelane_b32 v63, s96, 32
-; GFX9-NEXT: v_writelane_b32 v63, s97, 33
-; GFX9-NEXT: v_writelane_b32 v63, s98, 34
+; GFX9-NEXT: v_writelane_b32 v63, s34, 0
+; GFX9-NEXT: v_writelane_b32 v63, s35, 1
+; GFX9-NEXT: v_writelane_b32 v63, s36, 2
+; GFX9-NEXT: v_writelane_b32 v63, s37, 3
+; GFX9-NEXT: v_writelane_b32 v63, s38, 4
+; GFX9-NEXT: v_writelane_b32 v63, s39, 5
+; GFX9-NEXT: v_writelane_b32 v63, s48, 6
+; GFX9-NEXT: v_writelane_b32 v63, s49, 7
+; GFX9-NEXT: v_writelane_b32 v63, s50, 8
+; GFX9-NEXT: v_writelane_b32 v63, s51, 9
+; GFX9-NEXT: v_writelane_b32 v63, s52, 10
+; GFX9-NEXT: v_writelane_b32 v63, s53, 11
+; GFX9-NEXT: v_writelane_b32 v63, s54, 12
+; GFX9-NEXT: v_writelane_b32 v63, s55, 13
+; GFX9-NEXT: v_writelane_b32 v63, s64, 14
+; GFX9-NEXT: v_writelane_b32 v63, s65, 15
+; GFX9-NEXT: v_writelane_b32 v63, s66, 16
+; GFX9-NEXT: v_writelane_b32 v63, s67, 17
+; GFX9-NEXT: v_writelane_b32 v63, s68, 18
+; GFX9-NEXT: v_writelane_b32 v63, s69, 19
+; GFX9-NEXT: v_writelane_b32 v63, s70, 20
+; GFX9-NEXT: v_writelane_b32 v63, s71, 21
+; GFX9-NEXT: v_writelane_b32 v63, s80, 22
+; GFX9-NEXT: v_writelane_b32 v63, s81, 23
+; GFX9-NEXT: v_writelane_b32 v63, s82, 24
+; GFX9-NEXT: v_writelane_b32 v63, s83, 25
+; GFX9-NEXT: v_writelane_b32 v63, s84, 26
+; GFX9-NEXT: v_writelane_b32 v63, s85, 27
+; GFX9-NEXT: v_writelane_b32 v63, s86, 28
+; GFX9-NEXT: v_writelane_b32 v63, s87, 29
+; GFX9-NEXT: v_writelane_b32 v63, s96, 30
+; GFX9-NEXT: v_writelane_b32 v63, s97, 31
+; GFX9-NEXT: v_writelane_b32 v63, s98, 32
+; GFX9-NEXT: v_writelane_b32 v63, s99, 33
+; GFX9-NEXT: v_writelane_b32 v63, s30, 34
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; GFX9-NEXT: v_writelane_b32 v63, s99, 35
+; GFX9-NEXT: v_writelane_b32 v63, s31, 35
; GFX9-NEXT: v_readfirstlane_b32 s44, v3
; GFX9-NEXT: v_readfirstlane_b32 s45, v4
; GFX9-NEXT: v_readfirstlane_b32 s42, v5
@@ -218682,42 +218682,42 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: v_or_b32_sdwa v25, v25, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v30, 8, v44
; GFX9-NEXT: v_or_b32_sdwa v26, v26, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_readlane_b32 s99, v63, 35
-; GFX9-NEXT: v_readlane_b32 s98, v63, 34
-; GFX9-NEXT: v_readlane_b32 s97, v63, 33
-; GFX9-NEXT: v_readlane_b32 s96, v63, 32
-; GFX9-NEXT: v_readlane_b32 s87, v63, 31
-; GFX9-NEXT: v_readlane_b32 s86, v63, 30
-; GFX9-NEXT: v_readlane_b32 s85, v63, 29
-; GFX9-NEXT: v_readlane_b32 s84, v63, 28
-; GFX9-NEXT: v_readlane_b32 s83, v63, 27
-; GFX9-NEXT: v_readlane_b32 s82, v63, 26
-; GFX9-NEXT: v_readlane_b32 s81, v63, 25
-; GFX9-NEXT: v_readlane_b32 s80, v63, 24
-; GFX9-NEXT: v_readlane_b32 s71, v63, 23
-; GFX9-NEXT: v_readlane_b32 s70, v63, 22
-; GFX9-NEXT: v_readlane_b32 s69, v63, 21
-; GFX9-NEXT: v_readlane_b32 s68, v63, 20
-; GFX9-NEXT: v_readlane_b32 s67, v63, 19
-; GFX9-NEXT: v_readlane_b32 s66, v63, 18
-; GFX9-NEXT: v_readlane_b32 s65, v63, 17
-; GFX9-NEXT: v_readlane_b32 s64, v63, 16
-; GFX9-NEXT: v_readlane_b32 s55, v63, 15
-; GFX9-NEXT: v_readlane_b32 s54, v63, 14
-; GFX9-NEXT: v_readlane_b32 s53, v63, 13
-; GFX9-NEXT: v_readlane_b32 s52, v63, 12
-; GFX9-NEXT: v_readlane_b32 s51, v63, 11
-; GFX9-NEXT: v_readlane_b32 s50, v63, 10
-; GFX9-NEXT: v_readlane_b32 s49, v63, 9
-; GFX9-NEXT: v_readlane_b32 s48, v63, 8
-; GFX9-NEXT: v_readlane_b32 s39, v63, 7
-; GFX9-NEXT: v_readlane_b32 s38, v63, 6
-; GFX9-NEXT: v_readlane_b32 s37, v63, 5
-; GFX9-NEXT: v_readlane_b32 s36, v63, 4
-; GFX9-NEXT: v_readlane_b32 s35, v63, 3
-; GFX9-NEXT: v_readlane_b32 s34, v63, 2
-; GFX9-NEXT: v_readlane_b32 s31, v63, 1
-; GFX9-NEXT: v_readlane_b32 s30, v63, 0
+; GFX9-NEXT: v_readlane_b32 s30, v63, 34
+; GFX9-NEXT: v_readlane_b32 s31, v63, 35
+; GFX9-NEXT: v_readlane_b32 s99, v63, 33
+; GFX9-NEXT: v_readlane_b32 s98, v63, 32
+; GFX9-NEXT: v_readlane_b32 s97, v63, 31
+; GFX9-NEXT: v_readlane_b32 s96, v63, 30
+; GFX9-NEXT: v_readlane_b32 s87, v63, 29
+; GFX9-NEXT: v_readlane_b32 s86, v63, 28
+; GFX9-NEXT: v_readlane_b32 s85, v63, 27
+; GFX9-NEXT: v_readlane_b32 s84, v63, 26
+; GFX9-NEXT: v_readlane_b32 s83, v63, 25
+; GFX9-NEXT: v_readlane_b32 s82, v63, 24
+; GFX9-NEXT: v_readlane_b32 s81, v63, 23
+; GFX9-NEXT: v_readlane_b32 s80, v63, 22
+; GFX9-NEXT: v_readlane_b32 s71, v63, 21
+; GFX9-NEXT: v_readlane_b32 s70, v63, 20
+; GFX9-NEXT: v_readlane_b32 s69, v63, 19
+; GFX9-NEXT: v_readlane_b32 s68, v63, 18
+; GFX9-NEXT: v_readlane_b32 s67, v63, 17
+; GFX9-NEXT: v_readlane_b32 s66, v63, 16
+; GFX9-NEXT: v_readlane_b32 s65, v63, 15
+; GFX9-NEXT: v_readlane_b32 s64, v63, 14
+; GFX9-NEXT: v_readlane_b32 s55, v63, 13
+; GFX9-NEXT: v_readlane_b32 s54, v63, 12
+; GFX9-NEXT: v_readlane_b32 s53, v63, 11
+; GFX9-NEXT: v_readlane_b32 s52, v63, 10
+; GFX9-NEXT: v_readlane_b32 s51, v63, 9
+; GFX9-NEXT: v_readlane_b32 s50, v63, 8
+; GFX9-NEXT: v_readlane_b32 s49, v63, 7
+; GFX9-NEXT: v_readlane_b32 s48, v63, 6
+; GFX9-NEXT: v_readlane_b32 s39, v63, 5
+; GFX9-NEXT: v_readlane_b32 s38, v63, 4
+; GFX9-NEXT: v_readlane_b32 s37, v63, 3
+; GFX9-NEXT: v_readlane_b32 s36, v63, 2
+; GFX9-NEXT: v_readlane_b32 s35, v63, 1
+; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 8, v15
; GFX9-NEXT: v_or_b32_sdwa v15, v38, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -219074,33 +219074,33 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v75, s30, 0
-; GFX11-NEXT: v_writelane_b32 v76, s96, 0
+; GFX11-NEXT: v_writelane_b32 v75, s34, 0
+; GFX11-NEXT: v_writelane_b32 v76, s98, 0
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
; GFX11-NEXT: v_readfirstlane_b32 s40, v1
; GFX11-NEXT: v_readfirstlane_b32 s41, v2
-; GFX11-NEXT: v_writelane_b32 v75, s31, 1
-; GFX11-NEXT: v_writelane_b32 v76, s97, 1
+; GFX11-NEXT: v_writelane_b32 v75, s35, 1
+; GFX11-NEXT: v_writelane_b32 v76, s99, 1
; GFX11-NEXT: v_readfirstlane_b32 s14, v3
; GFX11-NEXT: v_readfirstlane_b32 s15, v4
; GFX11-NEXT: v_readfirstlane_b32 s12, v5
-; GFX11-NEXT: v_writelane_b32 v75, s34, 2
-; GFX11-NEXT: v_writelane_b32 v76, s98, 2
+; GFX11-NEXT: v_writelane_b32 v75, s36, 2
+; GFX11-NEXT: v_writelane_b32 v76, s100, 2
; GFX11-NEXT: v_readfirstlane_b32 s13, v6
; GFX11-NEXT: v_readfirstlane_b32 s10, v7
; GFX11-NEXT: v_readfirstlane_b32 s11, v8
-; GFX11-NEXT: v_writelane_b32 v75, s35, 3
-; GFX11-NEXT: v_writelane_b32 v76, s99, 3
+; GFX11-NEXT: v_writelane_b32 v75, s37, 3
+; GFX11-NEXT: v_writelane_b32 v76, s101, 3
; GFX11-NEXT: v_readfirstlane_b32 s8, v9
; GFX11-NEXT: v_readfirstlane_b32 s9, v10
; GFX11-NEXT: v_readfirstlane_b32 s6, v11
-; GFX11-NEXT: v_writelane_b32 v75, s36, 4
-; GFX11-NEXT: v_writelane_b32 v76, s100, 4
+; GFX11-NEXT: v_writelane_b32 v75, s38, 4
+; GFX11-NEXT: v_writelane_b32 v76, s102, 4
; GFX11-NEXT: v_readfirstlane_b32 s7, v12
; GFX11-NEXT: v_readfirstlane_b32 s4, v13
; GFX11-NEXT: v_readfirstlane_b32 s5, v14
-; GFX11-NEXT: v_writelane_b32 v75, s37, 5
-; GFX11-NEXT: v_writelane_b32 v76, s101, 5
+; GFX11-NEXT: v_writelane_b32 v75, s39, 5
+; GFX11-NEXT: v_writelane_b32 v76, s103, 5
; GFX11-NEXT: s_mov_b32 s99, 0
; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
; GFX11-NEXT: s_clause 0x12
@@ -219123,37 +219123,37 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:8
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:4
; GFX11-NEXT: scratch_store_b32 off, v74, s32
-; GFX11-NEXT: v_writelane_b32 v75, s38, 6
-; GFX11-NEXT: v_writelane_b32 v76, s102, 6
+; GFX11-NEXT: v_writelane_b32 v75, s48, 6
+; GFX11-NEXT: v_writelane_b32 v76, s104, 6
; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane
; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane
-; GFX11-NEXT: v_writelane_b32 v75, s39, 7
-; GFX11-NEXT: v_writelane_b32 v76, s103, 7
-; GFX11-NEXT: v_writelane_b32 v75, s48, 8
-; GFX11-NEXT: v_writelane_b32 v76, s104, 8
-; GFX11-NEXT: v_writelane_b32 v75, s49, 9
-; GFX11-NEXT: v_writelane_b32 v75, s50, 10
-; GFX11-NEXT: v_writelane_b32 v75, s51, 11
-; GFX11-NEXT: v_writelane_b32 v75, s52, 12
-; GFX11-NEXT: v_writelane_b32 v75, s53, 13
-; GFX11-NEXT: v_writelane_b32 v75, s54, 14
-; GFX11-NEXT: v_writelane_b32 v75, s55, 15
-; GFX11-NEXT: v_writelane_b32 v75, s64, 16
-; GFX11-NEXT: v_writelane_b32 v75, s65, 17
-; GFX11-NEXT: v_writelane_b32 v75, s66, 18
-; GFX11-NEXT: v_writelane_b32 v75, s67, 19
-; GFX11-NEXT: v_writelane_b32 v75, s68, 20
-; GFX11-NEXT: v_writelane_b32 v75, s69, 21
-; GFX11-NEXT: v_writelane_b32 v75, s70, 22
-; GFX11-NEXT: v_writelane_b32 v75, s71, 23
-; GFX11-NEXT: v_writelane_b32 v75, s80, 24
-; GFX11-NEXT: v_writelane_b32 v75, s81, 25
-; GFX11-NEXT: v_writelane_b32 v75, s82, 26
-; GFX11-NEXT: v_writelane_b32 v75, s83, 27
-; GFX11-NEXT: v_writelane_b32 v75, s84, 28
-; GFX11-NEXT: v_writelane_b32 v75, s85, 29
-; GFX11-NEXT: v_writelane_b32 v75, s86, 30
-; GFX11-NEXT: v_writelane_b32 v75, s87, 31
+; GFX11-NEXT: v_writelane_b32 v75, s49, 7
+; GFX11-NEXT: v_writelane_b32 v76, s30, 7
+; GFX11-NEXT: v_writelane_b32 v75, s50, 8
+; GFX11-NEXT: v_writelane_b32 v76, s31, 8
+; GFX11-NEXT: v_writelane_b32 v75, s51, 9
+; GFX11-NEXT: v_writelane_b32 v75, s52, 10
+; GFX11-NEXT: v_writelane_b32 v75, s53, 11
+; GFX11-NEXT: v_writelane_b32 v75, s54, 12
+; GFX11-NEXT: v_writelane_b32 v75, s55, 13
+; GFX11-NEXT: v_writelane_b32 v75, s64, 14
+; GFX11-NEXT: v_writelane_b32 v75, s65, 15
+; GFX11-NEXT: v_writelane_b32 v75, s66, 16
+; GFX11-NEXT: v_writelane_b32 v75, s67, 17
+; GFX11-NEXT: v_writelane_b32 v75, s68, 18
+; GFX11-NEXT: v_writelane_b32 v75, s69, 19
+; GFX11-NEXT: v_writelane_b32 v75, s70, 20
+; GFX11-NEXT: v_writelane_b32 v75, s71, 21
+; GFX11-NEXT: v_writelane_b32 v75, s80, 22
+; GFX11-NEXT: v_writelane_b32 v75, s81, 23
+; GFX11-NEXT: v_writelane_b32 v75, s82, 24
+; GFX11-NEXT: v_writelane_b32 v75, s83, 25
+; GFX11-NEXT: v_writelane_b32 v75, s84, 26
+; GFX11-NEXT: v_writelane_b32 v75, s85, 27
+; GFX11-NEXT: v_writelane_b32 v75, s86, 28
+; GFX11-NEXT: v_writelane_b32 v75, s87, 29
+; GFX11-NEXT: v_writelane_b32 v75, s96, 30
+; GFX11-NEXT: v_writelane_b32 v75, s97, 31
; GFX11-NEXT: s_cbranch_scc0 .LBB99_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s27, 16
@@ -220042,47 +220042,47 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:64
; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:68
; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:72
-; GFX11-NEXT: v_readlane_b32 s104, v76, 8
-; GFX11-NEXT: v_readlane_b32 s103, v76, 7
-; GFX11-NEXT: v_readlane_b32 s102, v76, 6
-; GFX11-NEXT: v_readlane_b32 s101, v76, 5
-; GFX11-NEXT: v_readlane_b32 s100, v76, 4
-; GFX11-NEXT: v_readlane_b32 s99, v76, 3
-; GFX11-NEXT: v_readlane_b32 s98, v76, 2
-; GFX11-NEXT: v_readlane_b32 s97, v76, 1
-; GFX11-NEXT: v_readlane_b32 s96, v76, 0
-; GFX11-NEXT: v_readlane_b32 s87, v75, 31
-; GFX11-NEXT: v_readlane_b32 s86, v75, 30
-; GFX11-NEXT: v_readlane_b32 s85, v75, 29
-; GFX11-NEXT: v_readlane_b32 s84, v75, 28
-; GFX11-NEXT: v_readlane_b32 s83, v75, 27
-; GFX11-NEXT: v_readlane_b32 s82, v75, 26
-; GFX11-NEXT: v_readlane_b32 s81, v75, 25
-; GFX11-NEXT: v_readlane_b32 s80, v75, 24
-; GFX11-NEXT: v_readlane_b32 s71, v75, 23
-; GFX11-NEXT: v_readlane_b32 s70, v75, 22
-; GFX11-NEXT: v_readlane_b32 s69, v75, 21
-; GFX11-NEXT: v_readlane_b32 s68, v75, 20
-; GFX11-NEXT: v_readlane_b32 s67, v75, 19
-; GFX11-NEXT: v_readlane_b32 s66, v75, 18
-; GFX11-NEXT: v_readlane_b32 s65, v75, 17
-; GFX11-NEXT: v_readlane_b32 s64, v75, 16
-; GFX11-NEXT: v_readlane_b32 s55, v75, 15
-; GFX11-NEXT: v_readlane_b32 s54, v75, 14
-; GFX11-NEXT: v_readlane_b32 s53, v75, 13
-; GFX11-NEXT: v_readlane_b32 s52, v75, 12
-; GFX11-NEXT: v_readlane_b32 s51, v75, 11
-; GFX11-NEXT: v_readlane_b32 s50, v75, 10
-; GFX11-NEXT: v_readlane_b32 s49, v75, 9
-; GFX11-NEXT: v_readlane_b32 s48, v75, 8
-; GFX11-NEXT: v_readlane_b32 s39, v75, 7
-; GFX11-NEXT: v_readlane_b32 s38, v75, 6
-; GFX11-NEXT: v_readlane_b32 s37, v75, 5
-; GFX11-NEXT: v_readlane_b32 s36, v75, 4
-; GFX11-NEXT: v_readlane_b32 s35, v75, 3
-; GFX11-NEXT: v_readlane_b32 s34, v75, 2
-; GFX11-NEXT: v_readlane_b32 s31, v75, 1
-; GFX11-NEXT: v_readlane_b32 s30, v75, 0
+; GFX11-NEXT: v_readlane_b32 s30, v76, 7
+; GFX11-NEXT: v_readlane_b32 s31, v76, 8
+; GFX11-NEXT: v_readlane_b32 s104, v76, 6
+; GFX11-NEXT: v_readlane_b32 s103, v76, 5
+; GFX11-NEXT: v_readlane_b32 s102, v76, 4
+; GFX11-NEXT: v_readlane_b32 s101, v76, 3
+; GFX11-NEXT: v_readlane_b32 s100, v76, 2
+; GFX11-NEXT: v_readlane_b32 s99, v76, 1
+; GFX11-NEXT: v_readlane_b32 s98, v76, 0
+; GFX11-NEXT: v_readlane_b32 s97, v75, 31
+; GFX11-NEXT: v_readlane_b32 s96, v75, 30
+; GFX11-NEXT: v_readlane_b32 s87, v75, 29
+; GFX11-NEXT: v_readlane_b32 s86, v75, 28
+; GFX11-NEXT: v_readlane_b32 s85, v75, 27
+; GFX11-NEXT: v_readlane_b32 s84, v75, 26
+; GFX11-NEXT: v_readlane_b32 s83, v75, 25
+; GFX11-NEXT: v_readlane_b32 s82, v75, 24
+; GFX11-NEXT: v_readlane_b32 s81, v75, 23
+; GFX11-NEXT: v_readlane_b32 s80, v75, 22
+; GFX11-NEXT: v_readlane_b32 s71, v75, 21
+; GFX11-NEXT: v_readlane_b32 s70, v75, 20
+; GFX11-NEXT: v_readlane_b32 s69, v75, 19
+; GFX11-NEXT: v_readlane_b32 s68, v75, 18
+; GFX11-NEXT: v_readlane_b32 s67, v75, 17
+; GFX11-NEXT: v_readlane_b32 s66, v75, 16
+; GFX11-NEXT: v_readlane_b32 s65, v75, 15
+; GFX11-NEXT: v_readlane_b32 s64, v75, 14
+; GFX11-NEXT: v_readlane_b32 s55, v75, 13
+; GFX11-NEXT: v_readlane_b32 s54, v75, 12
+; GFX11-NEXT: v_readlane_b32 s53, v75, 11
+; GFX11-NEXT: v_readlane_b32 s52, v75, 10
+; GFX11-NEXT: v_readlane_b32 s51, v75, 9
+; GFX11-NEXT: v_readlane_b32 s50, v75, 8
+; GFX11-NEXT: v_readlane_b32 s49, v75, 7
+; GFX11-NEXT: v_readlane_b32 s48, v75, 6
+; GFX11-NEXT: v_readlane_b32 s39, v75, 5
+; GFX11-NEXT: v_readlane_b32 s38, v75, 4
+; GFX11-NEXT: v_readlane_b32 s37, v75, 3
+; GFX11-NEXT: v_readlane_b32 s36, v75, 2
+; GFX11-NEXT: v_readlane_b32 s35, v75, 1
+; GFX11-NEXT: v_readlane_b32 s34, v75, 0
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_load_b32 v75, off, s32 offset:76
@@ -225619,9 +225619,9 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; VI-NEXT: .LBB101_5: ; %end
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; VI-NEXT: v_readlane_b32 s30, v42, 0
; VI-NEXT: v_mov_b32_e32 v18, v32
; VI-NEXT: v_readlane_b32 s31, v42, 1
-; VI-NEXT: v_readlane_b32 s30, v42, 0
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -226297,9 +226297,9 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; GFX9-NEXT: v_readlane_b32 s30, v43, 0
; GFX9-NEXT: v_mov_b32_e32 v18, v32
; GFX9-NEXT: v_readlane_b32 s31, v43, 1
-; GFX9-NEXT: v_readlane_b32 s30, v43, 0
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -235838,9 +235838,9 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; VI-NEXT: .LBB105_5: ; %end
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; VI-NEXT: v_readlane_b32 s30, v42, 0
; VI-NEXT: v_mov_b32_e32 v18, v32
; VI-NEXT: v_readlane_b32 s31, v42, 1
-; VI-NEXT: v_readlane_b32 s30, v42, 0
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -236484,9 +236484,9 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
+; GFX9-NEXT: v_readlane_b32 s30, v43, 0
; GFX9-NEXT: v_mov_b32_e32 v18, v32
; GFX9-NEXT: v_readlane_b32 s31, v43, 1
-; GFX9-NEXT: v_readlane_b32 s30, v43, 0
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -238849,38 +238849,36 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:52
; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_writelane_b32 v40, s30, 0
-; SI-NEXT: v_writelane_b32 v40, s31, 1
-; SI-NEXT: v_writelane_b32 v40, s34, 2
-; SI-NEXT: v_writelane_b32 v40, s35, 3
-; SI-NEXT: v_writelane_b32 v40, s36, 4
-; SI-NEXT: v_writelane_b32 v40, s37, 5
-; SI-NEXT: v_writelane_b32 v40, s38, 6
-; SI-NEXT: v_writelane_b32 v40, s39, 7
-; SI-NEXT: v_writelane_b32 v40, s48, 8
-; SI-NEXT: v_writelane_b32 v40, s49, 9
-; SI-NEXT: v_writelane_b32 v40, s50, 10
-; SI-NEXT: v_writelane_b32 v40, s51, 11
-; SI-NEXT: v_writelane_b32 v40, s52, 12
-; SI-NEXT: v_writelane_b32 v40, s53, 13
-; SI-NEXT: v_writelane_b32 v40, s54, 14
-; SI-NEXT: v_writelane_b32 v40, s55, 15
-; SI-NEXT: v_writelane_b32 v40, s64, 16
-; SI-NEXT: v_writelane_b32 v40, s65, 17
-; SI-NEXT: v_writelane_b32 v40, s66, 18
-; SI-NEXT: v_writelane_b32 v40, s67, 19
-; SI-NEXT: v_writelane_b32 v40, s68, 20
-; SI-NEXT: v_writelane_b32 v40, s69, 21
-; SI-NEXT: v_writelane_b32 v40, s70, 22
-; SI-NEXT: v_writelane_b32 v40, s71, 23
-; SI-NEXT: v_writelane_b32 v40, s80, 24
-; SI-NEXT: v_writelane_b32 v40, s81, 25
-; SI-NEXT: v_writelane_b32 v40, s82, 26
-; SI-NEXT: v_writelane_b32 v40, s83, 27
-; SI-NEXT: v_writelane_b32 v40, s84, 28
-; SI-NEXT: v_writelane_b32 v40, s85, 29
-; SI-NEXT: v_writelane_b32 v40, s86, 30
-; SI-NEXT: v_writelane_b32 v40, s87, 31
+; SI-NEXT: v_writelane_b32 v40, s34, 0
+; SI-NEXT: v_writelane_b32 v40, s35, 1
+; SI-NEXT: v_writelane_b32 v40, s36, 2
+; SI-NEXT: v_writelane_b32 v40, s37, 3
+; SI-NEXT: v_writelane_b32 v40, s38, 4
+; SI-NEXT: v_writelane_b32 v40, s39, 5
+; SI-NEXT: v_writelane_b32 v40, s48, 6
+; SI-NEXT: v_writelane_b32 v40, s49, 7
+; SI-NEXT: v_writelane_b32 v40, s50, 8
+; SI-NEXT: v_writelane_b32 v40, s51, 9
+; SI-NEXT: v_writelane_b32 v40, s52, 10
+; SI-NEXT: v_writelane_b32 v40, s53, 11
+; SI-NEXT: v_writelane_b32 v40, s54, 12
+; SI-NEXT: v_writelane_b32 v40, s55, 13
+; SI-NEXT: v_writelane_b32 v40, s64, 14
+; SI-NEXT: v_writelane_b32 v40, s65, 15
+; SI-NEXT: v_writelane_b32 v40, s66, 16
+; SI-NEXT: v_writelane_b32 v40, s67, 17
+; SI-NEXT: v_writelane_b32 v40, s68, 18
+; SI-NEXT: v_writelane_b32 v40, s69, 19
+; SI-NEXT: v_writelane_b32 v40, s70, 20
+; SI-NEXT: v_writelane_b32 v40, s71, 21
+; SI-NEXT: v_writelane_b32 v40, s80, 22
+; SI-NEXT: v_writelane_b32 v40, s81, 23
+; SI-NEXT: v_writelane_b32 v40, s82, 24
+; SI-NEXT: v_writelane_b32 v40, s83, 25
+; SI-NEXT: v_writelane_b32 v40, s84, 26
+; SI-NEXT: v_writelane_b32 v40, s85, 27
+; SI-NEXT: v_writelane_b32 v40, s86, 28
+; SI-NEXT: v_writelane_b32 v40, s87, 29
; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
; SI-NEXT: s_mov_b32 s60, s16
; SI-NEXT: s_waitcnt expcnt(0)
@@ -238916,11 +238914,13 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: v_writelane_b32 v41, s90, 17
; SI-NEXT: v_readfirstlane_b32 s34, v8
; SI-NEXT: v_writelane_b32 v41, s91, 18
+; SI-NEXT: v_writelane_b32 v40, s96, 30
; SI-NEXT: v_readfirstlane_b32 s35, v7
; SI-NEXT: v_writelane_b32 v41, s34, 19
+; SI-NEXT: v_writelane_b32 v40, s97, 31
; SI-NEXT: v_readfirstlane_b32 s36, v10
; SI-NEXT: v_writelane_b32 v41, s35, 20
-; SI-NEXT: v_writelane_b32 v40, s96, 32
+; SI-NEXT: v_writelane_b32 v40, s98, 32
; SI-NEXT: v_readfirstlane_b32 s37, v9
; SI-NEXT: v_writelane_b32 v41, s36, 21
; SI-NEXT: s_waitcnt vmcnt(7)
@@ -238951,10 +238951,10 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:8
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:4
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32
-; SI-NEXT: v_writelane_b32 v40, s97, 33
+; SI-NEXT: v_writelane_b32 v40, s99, 33
; SI-NEXT: v_readfirstlane_b32 s38, v12
; SI-NEXT: v_writelane_b32 v41, s37, 22
-; SI-NEXT: v_writelane_b32 v40, s98, 34
+; SI-NEXT: v_writelane_b32 v40, s30, 34
; SI-NEXT: v_readfirstlane_b32 s14, v30
; SI-NEXT: v_readfirstlane_b32 s15, v29
; SI-NEXT: v_readfirstlane_b32 s12, v28
@@ -238976,7 +238976,7 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: v_readfirstlane_b32 s19, v11
; SI-NEXT: v_readfirstlane_b32 s18, v1
; SI-NEXT: v_writelane_b32 v41, s38, 23
-; SI-NEXT: v_writelane_b32 v40, s99, 35
+; SI-NEXT: v_writelane_b32 v40, s31, 35
; SI-NEXT: v_writelane_b32 v41, s39, 24
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s58, v31
@@ -239672,43 +239672,43 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s5
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0
+; SI-NEXT: v_readlane_b32 s30, v40, 34
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s99, v40, 35
-; SI-NEXT: v_readlane_b32 s98, v40, 34
-; SI-NEXT: v_readlane_b32 s97, v40, 33
-; SI-NEXT: v_readlane_b32 s96, v40, 32
-; SI-NEXT: v_readlane_b32 s87, v40, 31
-; SI-NEXT: v_readlane_b32 s86, v40, 30
-; SI-NEXT: v_readlane_b32 s85, v40, 29
-; SI-NEXT: v_readlane_b32 s84, v40, 28
-; SI-NEXT: v_readlane_b32 s83, v40, 27
-; SI-NEXT: v_readlane_b32 s82, v40, 26
-; SI-NEXT: v_readlane_b32 s81, v40, 25
-; SI-NEXT: v_readlane_b32 s80, v40, 24
-; SI-NEXT: v_readlane_b32 s71, v40, 23
-; SI-NEXT: v_readlane_b32 s70, v40, 22
-; SI-NEXT: v_readlane_b32 s69, v40, 21
-; SI-NEXT: v_readlane_b32 s68, v40, 20
-; SI-NEXT: v_readlane_b32 s67, v40, 19
-; SI-NEXT: v_readlane_b32 s66, v40, 18
-; SI-NEXT: v_readlane_b32 s65, v40, 17
-; SI-NEXT: v_readlane_b32 s64, v40, 16
-; SI-NEXT: v_readlane_b32 s55, v40, 15
-; SI-NEXT: v_readlane_b32 s54, v40, 14
-; SI-NEXT: v_readlane_b32 s53, v40, 13
-; SI-NEXT: v_readlane_b32 s52, v40, 12
-; SI-NEXT: v_readlane_b32 s51, v40, 11
-; SI-NEXT: v_readlane_b32 s50, v40, 10
-; SI-NEXT: v_readlane_b32 s49, v40, 9
-; SI-NEXT: v_readlane_b32 s48, v40, 8
-; SI-NEXT: v_readlane_b32 s39, v40, 7
-; SI-NEXT: v_readlane_b32 s38, v40, 6
-; SI-NEXT: v_readlane_b32 s37, v40, 5
-; SI-NEXT: v_readlane_b32 s36, v40, 4
-; SI-NEXT: v_readlane_b32 s35, v40, 3
-; SI-NEXT: v_readlane_b32 s34, v40, 2
-; SI-NEXT: v_readlane_b32 s31, v40, 1
-; SI-NEXT: v_readlane_b32 s30, v40, 0
+; SI-NEXT: v_readlane_b32 s31, v40, 35
+; SI-NEXT: v_readlane_b32 s99, v40, 33
+; SI-NEXT: v_readlane_b32 s98, v40, 32
+; SI-NEXT: v_readlane_b32 s97, v40, 31
+; SI-NEXT: v_readlane_b32 s96, v40, 30
+; SI-NEXT: v_readlane_b32 s87, v40, 29
+; SI-NEXT: v_readlane_b32 s86, v40, 28
+; SI-NEXT: v_readlane_b32 s85, v40, 27
+; SI-NEXT: v_readlane_b32 s84, v40, 26
+; SI-NEXT: v_readlane_b32 s83, v40, 25
+; SI-NEXT: v_readlane_b32 s82, v40, 24
+; SI-NEXT: v_readlane_b32 s81, v40, 23
+; SI-NEXT: v_readlane_b32 s80, v40, 22
+; SI-NEXT: v_readlane_b32 s71, v40, 21
+; SI-NEXT: v_readlane_b32 s70, v40, 20
+; SI-NEXT: v_readlane_b32 s69, v40, 19
+; SI-NEXT: v_readlane_b32 s68, v40, 18
+; SI-NEXT: v_readlane_b32 s67, v40, 17
+; SI-NEXT: v_readlane_b32 s66, v40, 16
+; SI-NEXT: v_readlane_b32 s65, v40, 15
+; SI-NEXT: v_readlane_b32 s64, v40, 14
+; SI-NEXT: v_readlane_b32 s55, v40, 13
+; SI-NEXT: v_readlane_b32 s54, v40, 12
+; SI-NEXT: v_readlane_b32 s53, v40, 11
+; SI-NEXT: v_readlane_b32 s52, v40, 10
+; SI-NEXT: v_readlane_b32 s51, v40, 9
+; SI-NEXT: v_readlane_b32 s50, v40, 8
+; SI-NEXT: v_readlane_b32 s49, v40, 7
+; SI-NEXT: v_readlane_b32 s48, v40, 6
+; SI-NEXT: v_readlane_b32 s39, v40, 5
+; SI-NEXT: v_readlane_b32 s38, v40, 4
+; SI-NEXT: v_readlane_b32 s37, v40, 3
+; SI-NEXT: v_readlane_b32 s36, v40, 2
+; SI-NEXT: v_readlane_b32 s35, v40, 1
+; SI-NEXT: v_readlane_b32 s34, v40, 0
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
@@ -239722,14 +239722,14 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v32, s30, 0
-; VI-NEXT: v_writelane_b32 v32, s31, 1
-; VI-NEXT: v_writelane_b32 v32, s34, 2
-; VI-NEXT: v_writelane_b32 v32, s35, 3
-; VI-NEXT: v_writelane_b32 v32, s36, 4
-; VI-NEXT: v_writelane_b32 v32, s37, 5
+; VI-NEXT: v_writelane_b32 v32, s34, 0
+; VI-NEXT: v_writelane_b32 v32, s35, 1
+; VI-NEXT: v_writelane_b32 v32, s36, 2
+; VI-NEXT: v_writelane_b32 v32, s37, 3
+; VI-NEXT: v_writelane_b32 v32, s38, 4
+; VI-NEXT: v_writelane_b32 v32, s39, 5
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
-; VI-NEXT: v_writelane_b32 v32, s38, 6
+; VI-NEXT: v_writelane_b32 v32, s30, 6
; VI-NEXT: v_readfirstlane_b32 s47, v2
; VI-NEXT: v_readfirstlane_b32 s46, v3
; VI-NEXT: v_readfirstlane_b32 s45, v4
@@ -239749,7 +239749,7 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; VI-NEXT: v_readfirstlane_b32 s6, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v1
-; VI-NEXT: v_writelane_b32 v32, s39, 7
+; VI-NEXT: v_writelane_b32 v32, s31, 7
; VI-NEXT: s_cbranch_scc0 .LBB107_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB107_3
@@ -239915,6 +239915,7 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; VI-NEXT: s_add_i32 s46, s46, 0x30000
; VI-NEXT: s_add_i32 s47, s4, 0x30000
; VI-NEXT: .LBB107_3: ; %end
+; VI-NEXT: v_readlane_b32 s30, v32, 6
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
@@ -239947,14 +239948,13 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; VI-NEXT: v_mov_b32_e32 v29, s10
; VI-NEXT: v_mov_b32_e32 v30, s9
; VI-NEXT: v_mov_b32_e32 v31, s8
-; VI-NEXT: v_readlane_b32 s39, v32, 7
-; VI-NEXT: v_readlane_b32 s38, v32, 6
-; VI-NEXT: v_readlane_b32 s37, v32, 5
-; VI-NEXT: v_readlane_b32 s36, v32, 4
-; VI-NEXT: v_readlane_b32 s35, v32, 3
-; VI-NEXT: v_readlane_b32 s34, v32, 2
-; VI-NEXT: v_readlane_b32 s31, v32, 1
-; VI-NEXT: v_readlane_b32 s30, v32, 0
+; VI-NEXT: v_readlane_b32 s31, v32, 7
+; VI-NEXT: v_readlane_b32 s39, v32, 5
+; VI-NEXT: v_readlane_b32 s38, v32, 4
+; VI-NEXT: v_readlane_b32 s37, v32, 3
+; VI-NEXT: v_readlane_b32 s36, v32, 2
+; VI-NEXT: v_readlane_b32 s35, v32, 1
+; VI-NEXT: v_readlane_b32 s34, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -244357,14 +244357,14 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v32, s30, 0
-; VI-NEXT: v_writelane_b32 v32, s31, 1
-; VI-NEXT: v_writelane_b32 v32, s34, 2
-; VI-NEXT: v_writelane_b32 v32, s35, 3
-; VI-NEXT: v_writelane_b32 v32, s36, 4
-; VI-NEXT: v_writelane_b32 v32, s37, 5
+; VI-NEXT: v_writelane_b32 v32, s34, 0
+; VI-NEXT: v_writelane_b32 v32, s35, 1
+; VI-NEXT: v_writelane_b32 v32, s36, 2
+; VI-NEXT: v_writelane_b32 v32, s37, 3
+; VI-NEXT: v_writelane_b32 v32, s38, 4
+; VI-NEXT: v_writelane_b32 v32, s39, 5
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
-; VI-NEXT: v_writelane_b32 v32, s38, 6
+; VI-NEXT: v_writelane_b32 v32, s30, 6
; VI-NEXT: v_readfirstlane_b32 s47, v2
; VI-NEXT: v_readfirstlane_b32 s46, v3
; VI-NEXT: v_readfirstlane_b32 s45, v4
@@ -244384,7 +244384,7 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s6, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v1
-; VI-NEXT: v_writelane_b32 v32, s39, 7
+; VI-NEXT: v_writelane_b32 v32, s31, 7
; VI-NEXT: s_cbranch_scc0 .LBB111_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB111_3
@@ -244550,6 +244550,7 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; VI-NEXT: s_add_i32 s46, s46, 0x30000
; VI-NEXT: s_add_i32 s47, s4, 0x30000
; VI-NEXT: .LBB111_3: ; %end
+; VI-NEXT: v_readlane_b32 s30, v32, 6
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
@@ -244582,14 +244583,13 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; VI-NEXT: v_mov_b32_e32 v29, s10
; VI-NEXT: v_mov_b32_e32 v30, s9
; VI-NEXT: v_mov_b32_e32 v31, s8
-; VI-NEXT: v_readlane_b32 s39, v32, 7
-; VI-NEXT: v_readlane_b32 s38, v32, 6
-; VI-NEXT: v_readlane_b32 s37, v32, 5
-; VI-NEXT: v_readlane_b32 s36, v32, 4
-; VI-NEXT: v_readlane_b32 s35, v32, 3
-; VI-NEXT: v_readlane_b32 s34, v32, 2
-; VI-NEXT: v_readlane_b32 s31, v32, 1
-; VI-NEXT: v_readlane_b32 s30, v32, 0
+; VI-NEXT: v_readlane_b32 s31, v32, 7
+; VI-NEXT: v_readlane_b32 s39, v32, 5
+; VI-NEXT: v_readlane_b32 s38, v32, 4
+; VI-NEXT: v_readlane_b32 s37, v32, 3
+; VI-NEXT: v_readlane_b32 s36, v32, 2
+; VI-NEXT: v_readlane_b32 s35, v32, 1
+; VI-NEXT: v_readlane_b32 s34, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
index 9041f64cb17fb..a431abbdeb288 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
@@ -16525,18 +16525,17 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v8, s30, 0
-; SI-NEXT: v_writelane_b32 v8, s31, 1
-; SI-NEXT: v_writelane_b32 v8, s34, 2
-; SI-NEXT: v_writelane_b32 v8, s35, 3
-; SI-NEXT: v_writelane_b32 v8, s36, 4
-; SI-NEXT: v_writelane_b32 v8, s37, 5
-; SI-NEXT: v_writelane_b32 v8, s38, 6
-; SI-NEXT: v_writelane_b32 v8, s39, 7
-; SI-NEXT: v_writelane_b32 v8, s48, 8
-; SI-NEXT: v_writelane_b32 v8, s49, 9
+; SI-NEXT: v_writelane_b32 v8, s34, 0
+; SI-NEXT: v_writelane_b32 v8, s35, 1
+; SI-NEXT: v_writelane_b32 v8, s36, 2
+; SI-NEXT: v_writelane_b32 v8, s37, 3
+; SI-NEXT: v_writelane_b32 v8, s38, 4
+; SI-NEXT: v_writelane_b32 v8, s39, 5
+; SI-NEXT: v_writelane_b32 v8, s48, 6
+; SI-NEXT: v_writelane_b32 v8, s49, 7
+; SI-NEXT: v_writelane_b32 v8, s50, 8
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; SI-NEXT: v_writelane_b32 v8, s50, 10
+; SI-NEXT: v_writelane_b32 v8, s30, 9
; SI-NEXT: v_readfirstlane_b32 s39, v6
; SI-NEXT: v_readfirstlane_b32 s48, v5
; SI-NEXT: v_readfirstlane_b32 s49, v4
@@ -16544,6 +16543,7 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; SI-NEXT: v_readfirstlane_b32 s35, v2
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s38, v1
+; SI-NEXT: v_writelane_b32 v8, s31, 10
; SI-NEXT: s_cbranch_scc0 .LBB49_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s4, s16, 0xffff
@@ -16815,18 +16815,18 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 36, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v8, 9
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s50, v8, 10
-; SI-NEXT: v_readlane_b32 s49, v8, 9
-; SI-NEXT: v_readlane_b32 s48, v8, 8
-; SI-NEXT: v_readlane_b32 s39, v8, 7
-; SI-NEXT: v_readlane_b32 s38, v8, 6
-; SI-NEXT: v_readlane_b32 s37, v8, 5
-; SI-NEXT: v_readlane_b32 s36, v8, 4
-; SI-NEXT: v_readlane_b32 s35, v8, 3
-; SI-NEXT: v_readlane_b32 s34, v8, 2
-; SI-NEXT: v_readlane_b32 s31, v8, 1
-; SI-NEXT: v_readlane_b32 s30, v8, 0
+; SI-NEXT: v_readlane_b32 s31, v8, 10
+; SI-NEXT: v_readlane_b32 s50, v8, 8
+; SI-NEXT: v_readlane_b32 s49, v8, 7
+; SI-NEXT: v_readlane_b32 s48, v8, 6
+; SI-NEXT: v_readlane_b32 s39, v8, 5
+; SI-NEXT: v_readlane_b32 s38, v8, 4
+; SI-NEXT: v_readlane_b32 s37, v8, 3
+; SI-NEXT: v_readlane_b32 s36, v8, 2
+; SI-NEXT: v_readlane_b32 s35, v8, 1
+; SI-NEXT: v_readlane_b32 s34, v8, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index ee23420c2a662..6fb4517583e38 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -6992,8 +6992,8 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_mov_b32_e32 v15, s31
; VI-NEXT: .LBB23_5: ; %end
-; VI-NEXT: v_readlane_b32 s31, v19, 1
; VI-NEXT: v_readlane_b32 s30, v19, 0
+; VI-NEXT: v_readlane_b32 s31, v19, 1
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -7343,8 +7343,8 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; GFX9-NEXT: v_mov_b32_e32 v14, s30
; GFX9-NEXT: v_mov_b32_e32 v15, s31
; GFX9-NEXT: .LBB23_5: ; %end
-; GFX9-NEXT: v_readlane_b32 s31, v20, 1
; GFX9-NEXT: v_readlane_b32 s30, v20, 0
+; GFX9-NEXT: v_readlane_b32 s31, v20, 1
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -9707,40 +9707,40 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v4, s30, 0
-; SI-NEXT: v_writelane_b32 v4, s31, 1
-; SI-NEXT: v_writelane_b32 v4, s34, 2
-; SI-NEXT: v_writelane_b32 v4, s35, 3
-; SI-NEXT: v_writelane_b32 v4, s36, 4
-; SI-NEXT: v_writelane_b32 v4, s37, 5
-; SI-NEXT: v_writelane_b32 v4, s38, 6
-; SI-NEXT: v_writelane_b32 v4, s39, 7
-; SI-NEXT: v_writelane_b32 v4, s48, 8
-; SI-NEXT: v_writelane_b32 v4, s49, 9
-; SI-NEXT: v_writelane_b32 v4, s50, 10
-; SI-NEXT: v_writelane_b32 v4, s51, 11
-; SI-NEXT: v_writelane_b32 v4, s52, 12
-; SI-NEXT: v_writelane_b32 v4, s53, 13
-; SI-NEXT: v_writelane_b32 v4, s54, 14
-; SI-NEXT: v_writelane_b32 v4, s55, 15
-; SI-NEXT: v_writelane_b32 v4, s64, 16
-; SI-NEXT: v_writelane_b32 v4, s65, 17
-; SI-NEXT: v_writelane_b32 v4, s66, 18
-; SI-NEXT: v_writelane_b32 v4, s67, 19
-; SI-NEXT: v_writelane_b32 v4, s68, 20
-; SI-NEXT: v_writelane_b32 v4, s69, 21
-; SI-NEXT: v_writelane_b32 v4, s70, 22
-; SI-NEXT: v_writelane_b32 v4, s71, 23
-; SI-NEXT: v_writelane_b32 v4, s80, 24
-; SI-NEXT: v_writelane_b32 v4, s81, 25
-; SI-NEXT: v_writelane_b32 v4, s82, 26
-; SI-NEXT: v_writelane_b32 v4, s83, 27
+; SI-NEXT: v_writelane_b32 v4, s34, 0
+; SI-NEXT: v_writelane_b32 v4, s35, 1
+; SI-NEXT: v_writelane_b32 v4, s36, 2
+; SI-NEXT: v_writelane_b32 v4, s37, 3
+; SI-NEXT: v_writelane_b32 v4, s38, 4
+; SI-NEXT: v_writelane_b32 v4, s39, 5
+; SI-NEXT: v_writelane_b32 v4, s48, 6
+; SI-NEXT: v_writelane_b32 v4, s49, 7
+; SI-NEXT: v_writelane_b32 v4, s50, 8
+; SI-NEXT: v_writelane_b32 v4, s51, 9
+; SI-NEXT: v_writelane_b32 v4, s52, 10
+; SI-NEXT: v_writelane_b32 v4, s53, 11
+; SI-NEXT: v_writelane_b32 v4, s54, 12
+; SI-NEXT: v_writelane_b32 v4, s55, 13
+; SI-NEXT: v_writelane_b32 v4, s64, 14
+; SI-NEXT: v_writelane_b32 v4, s65, 15
+; SI-NEXT: v_writelane_b32 v4, s66, 16
+; SI-NEXT: v_writelane_b32 v4, s67, 17
+; SI-NEXT: v_writelane_b32 v4, s68, 18
+; SI-NEXT: v_writelane_b32 v4, s69, 19
+; SI-NEXT: v_writelane_b32 v4, s70, 20
+; SI-NEXT: v_writelane_b32 v4, s71, 21
+; SI-NEXT: v_writelane_b32 v4, s80, 22
+; SI-NEXT: v_writelane_b32 v4, s81, 23
+; SI-NEXT: v_writelane_b32 v4, s82, 24
+; SI-NEXT: v_writelane_b32 v4, s83, 25
+; SI-NEXT: v_writelane_b32 v4, s84, 26
+; SI-NEXT: v_writelane_b32 v4, s85, 27
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; SI-NEXT: v_writelane_b32 v4, s84, 28
+; SI-NEXT: v_writelane_b32 v4, s30, 28
; SI-NEXT: v_readfirstlane_b32 s4, v1
; SI-NEXT: s_and_b64 s[6:7], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v2
-; SI-NEXT: v_writelane_b32 v4, s85, 29
+; SI-NEXT: v_writelane_b32 v4, s31, 29
; SI-NEXT: s_cbranch_scc0 .LBB25_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s38, s5, 24
@@ -10061,37 +10061,37 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v4, 28
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s85, v4, 29
-; SI-NEXT: v_readlane_b32 s84, v4, 28
-; SI-NEXT: v_readlane_b32 s83, v4, 27
-; SI-NEXT: v_readlane_b32 s82, v4, 26
-; SI-NEXT: v_readlane_b32 s81, v4, 25
-; SI-NEXT: v_readlane_b32 s80, v4, 24
-; SI-NEXT: v_readlane_b32 s71, v4, 23
-; SI-NEXT: v_readlane_b32 s70, v4, 22
-; SI-NEXT: v_readlane_b32 s69, v4, 21
-; SI-NEXT: v_readlane_b32 s68, v4, 20
-; SI-NEXT: v_readlane_b32 s67, v4, 19
-; SI-NEXT: v_readlane_b32 s66, v4, 18
-; SI-NEXT: v_readlane_b32 s65, v4, 17
-; SI-NEXT: v_readlane_b32 s64, v4, 16
-; SI-NEXT: v_readlane_b32 s55, v4, 15
-; SI-NEXT: v_readlane_b32 s54, v4, 14
-; SI-NEXT: v_readlane_b32 s53, v4, 13
-; SI-NEXT: v_readlane_b32 s52, v4, 12
-; SI-NEXT: v_readlane_b32 s51, v4, 11
-; SI-NEXT: v_readlane_b32 s50, v4, 10
-; SI-NEXT: v_readlane_b32 s49, v4, 9
-; SI-NEXT: v_readlane_b32 s48, v4, 8
-; SI-NEXT: v_readlane_b32 s39, v4, 7
-; SI-NEXT: v_readlane_b32 s38, v4, 6
-; SI-NEXT: v_readlane_b32 s37, v4, 5
-; SI-NEXT: v_readlane_b32 s36, v4, 4
-; SI-NEXT: v_readlane_b32 s35, v4, 3
-; SI-NEXT: v_readlane_b32 s34, v4, 2
-; SI-NEXT: v_readlane_b32 s31, v4, 1
-; SI-NEXT: v_readlane_b32 s30, v4, 0
+; SI-NEXT: v_readlane_b32 s31, v4, 29
+; SI-NEXT: v_readlane_b32 s85, v4, 27
+; SI-NEXT: v_readlane_b32 s84, v4, 26
+; SI-NEXT: v_readlane_b32 s83, v4, 25
+; SI-NEXT: v_readlane_b32 s82, v4, 24
+; SI-NEXT: v_readlane_b32 s81, v4, 23
+; SI-NEXT: v_readlane_b32 s80, v4, 22
+; SI-NEXT: v_readlane_b32 s71, v4, 21
+; SI-NEXT: v_readlane_b32 s70, v4, 20
+; SI-NEXT: v_readlane_b32 s69, v4, 19
+; SI-NEXT: v_readlane_b32 s68, v4, 18
+; SI-NEXT: v_readlane_b32 s67, v4, 17
+; SI-NEXT: v_readlane_b32 s66, v4, 16
+; SI-NEXT: v_readlane_b32 s65, v4, 15
+; SI-NEXT: v_readlane_b32 s64, v4, 14
+; SI-NEXT: v_readlane_b32 s55, v4, 13
+; SI-NEXT: v_readlane_b32 s54, v4, 12
+; SI-NEXT: v_readlane_b32 s53, v4, 11
+; SI-NEXT: v_readlane_b32 s52, v4, 10
+; SI-NEXT: v_readlane_b32 s51, v4, 9
+; SI-NEXT: v_readlane_b32 s50, v4, 8
+; SI-NEXT: v_readlane_b32 s49, v4, 7
+; SI-NEXT: v_readlane_b32 s48, v4, 6
+; SI-NEXT: v_readlane_b32 s39, v4, 5
+; SI-NEXT: v_readlane_b32 s38, v4, 4
+; SI-NEXT: v_readlane_b32 s37, v4, 3
+; SI-NEXT: v_readlane_b32 s36, v4, 2
+; SI-NEXT: v_readlane_b32 s35, v4, 1
+; SI-NEXT: v_readlane_b32 s34, v4, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
@@ -10154,30 +10154,30 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v4, s30, 0
-; VI-NEXT: v_writelane_b32 v4, s31, 1
-; VI-NEXT: v_writelane_b32 v4, s34, 2
-; VI-NEXT: v_writelane_b32 v4, s35, 3
-; VI-NEXT: v_writelane_b32 v4, s36, 4
-; VI-NEXT: v_writelane_b32 v4, s37, 5
-; VI-NEXT: v_writelane_b32 v4, s38, 6
-; VI-NEXT: v_writelane_b32 v4, s39, 7
-; VI-NEXT: v_writelane_b32 v4, s48, 8
-; VI-NEXT: v_writelane_b32 v4, s49, 9
-; VI-NEXT: v_writelane_b32 v4, s50, 10
-; VI-NEXT: v_writelane_b32 v4, s51, 11
-; VI-NEXT: v_writelane_b32 v4, s52, 12
-; VI-NEXT: v_writelane_b32 v4, s53, 13
-; VI-NEXT: v_writelane_b32 v4, s54, 14
-; VI-NEXT: v_writelane_b32 v4, s55, 15
-; VI-NEXT: v_writelane_b32 v4, s64, 16
-; VI-NEXT: v_writelane_b32 v4, s65, 17
+; VI-NEXT: v_writelane_b32 v4, s34, 0
+; VI-NEXT: v_writelane_b32 v4, s35, 1
+; VI-NEXT: v_writelane_b32 v4, s36, 2
+; VI-NEXT: v_writelane_b32 v4, s37, 3
+; VI-NEXT: v_writelane_b32 v4, s38, 4
+; VI-NEXT: v_writelane_b32 v4, s39, 5
+; VI-NEXT: v_writelane_b32 v4, s48, 6
+; VI-NEXT: v_writelane_b32 v4, s49, 7
+; VI-NEXT: v_writelane_b32 v4, s50, 8
+; VI-NEXT: v_writelane_b32 v4, s51, 9
+; VI-NEXT: v_writelane_b32 v4, s52, 10
+; VI-NEXT: v_writelane_b32 v4, s53, 11
+; VI-NEXT: v_writelane_b32 v4, s54, 12
+; VI-NEXT: v_writelane_b32 v4, s55, 13
+; VI-NEXT: v_writelane_b32 v4, s64, 14
+; VI-NEXT: v_writelane_b32 v4, s65, 15
+; VI-NEXT: v_writelane_b32 v4, s66, 16
+; VI-NEXT: v_writelane_b32 v4, s67, 17
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; VI-NEXT: v_writelane_b32 v4, s66, 18
+; VI-NEXT: v_writelane_b32 v4, s30, 18
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
-; VI-NEXT: v_writelane_b32 v4, s67, 19
+; VI-NEXT: v_writelane_b32 v4, s31, 19
; VI-NEXT: s_cbranch_scc0 .LBB25_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s56, s5, 24
@@ -10485,27 +10485,27 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: v_mov_b32_e32 v1, s4
+; VI-NEXT: v_readlane_b32 s30, v4, 18
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT: v_readlane_b32 s67, v4, 19
-; VI-NEXT: v_readlane_b32 s66, v4, 18
-; VI-NEXT: v_readlane_b32 s65, v4, 17
-; VI-NEXT: v_readlane_b32 s64, v4, 16
-; VI-NEXT: v_readlane_b32 s55, v4, 15
-; VI-NEXT: v_readlane_b32 s54, v4, 14
-; VI-NEXT: v_readlane_b32 s53, v4, 13
-; VI-NEXT: v_readlane_b32 s52, v4, 12
-; VI-NEXT: v_readlane_b32 s51, v4, 11
-; VI-NEXT: v_readlane_b32 s50, v4, 10
-; VI-NEXT: v_readlane_b32 s49, v4, 9
-; VI-NEXT: v_readlane_b32 s48, v4, 8
-; VI-NEXT: v_readlane_b32 s39, v4, 7
-; VI-NEXT: v_readlane_b32 s38, v4, 6
-; VI-NEXT: v_readlane_b32 s37, v4, 5
-; VI-NEXT: v_readlane_b32 s36, v4, 4
-; VI-NEXT: v_readlane_b32 s35, v4, 3
-; VI-NEXT: v_readlane_b32 s34, v4, 2
-; VI-NEXT: v_readlane_b32 s31, v4, 1
-; VI-NEXT: v_readlane_b32 s30, v4, 0
+; VI-NEXT: v_readlane_b32 s31, v4, 19
+; VI-NEXT: v_readlane_b32 s67, v4, 17
+; VI-NEXT: v_readlane_b32 s66, v4, 16
+; VI-NEXT: v_readlane_b32 s65, v4, 15
+; VI-NEXT: v_readlane_b32 s64, v4, 14
+; VI-NEXT: v_readlane_b32 s55, v4, 13
+; VI-NEXT: v_readlane_b32 s54, v4, 12
+; VI-NEXT: v_readlane_b32 s53, v4, 11
+; VI-NEXT: v_readlane_b32 s52, v4, 10
+; VI-NEXT: v_readlane_b32 s51, v4, 9
+; VI-NEXT: v_readlane_b32 s50, v4, 8
+; VI-NEXT: v_readlane_b32 s49, v4, 7
+; VI-NEXT: v_readlane_b32 s48, v4, 6
+; VI-NEXT: v_readlane_b32 s39, v4, 5
+; VI-NEXT: v_readlane_b32 s38, v4, 4
+; VI-NEXT: v_readlane_b32 s37, v4, 3
+; VI-NEXT: v_readlane_b32 s36, v4, 2
+; VI-NEXT: v_readlane_b32 s35, v4, 1
+; VI-NEXT: v_readlane_b32 s34, v4, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -10568,26 +10568,26 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v4, s30, 0
-; GFX9-NEXT: v_writelane_b32 v4, s31, 1
-; GFX9-NEXT: v_writelane_b32 v4, s34, 2
-; GFX9-NEXT: v_writelane_b32 v4, s35, 3
-; GFX9-NEXT: v_writelane_b32 v4, s36, 4
-; GFX9-NEXT: v_writelane_b32 v4, s37, 5
-; GFX9-NEXT: v_writelane_b32 v4, s38, 6
-; GFX9-NEXT: v_writelane_b32 v4, s39, 7
-; GFX9-NEXT: v_writelane_b32 v4, s48, 8
-; GFX9-NEXT: v_writelane_b32 v4, s49, 9
-; GFX9-NEXT: v_writelane_b32 v4, s50, 10
-; GFX9-NEXT: v_writelane_b32 v4, s51, 11
-; GFX9-NEXT: v_writelane_b32 v4, s52, 12
-; GFX9-NEXT: v_writelane_b32 v4, s53, 13
+; GFX9-NEXT: v_writelane_b32 v4, s34, 0
+; GFX9-NEXT: v_writelane_b32 v4, s35, 1
+; GFX9-NEXT: v_writelane_b32 v4, s36, 2
+; GFX9-NEXT: v_writelane_b32 v4, s37, 3
+; GFX9-NEXT: v_writelane_b32 v4, s38, 4
+; GFX9-NEXT: v_writelane_b32 v4, s39, 5
+; GFX9-NEXT: v_writelane_b32 v4, s48, 6
+; GFX9-NEXT: v_writelane_b32 v4, s49, 7
+; GFX9-NEXT: v_writelane_b32 v4, s50, 8
+; GFX9-NEXT: v_writelane_b32 v4, s51, 9
+; GFX9-NEXT: v_writelane_b32 v4, s52, 10
+; GFX9-NEXT: v_writelane_b32 v4, s53, 11
+; GFX9-NEXT: v_writelane_b32 v4, s54, 12
+; GFX9-NEXT: v_writelane_b32 v4, s55, 13
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; GFX9-NEXT: v_writelane_b32 v4, s54, 14
+; GFX9-NEXT: v_writelane_b32 v4, s30, 14
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: v_writelane_b32 v4, s55, 15
+; GFX9-NEXT: v_writelane_b32 v4, s31, 15
; GFX9-NEXT: s_cbranch_scc0 .LBB25_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
@@ -10880,23 +10880,23 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX9-NEXT: s_or_b32 s4, s4, s5
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_readlane_b32 s30, v4, 14
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_readlane_b32 s55, v4, 15
-; GFX9-NEXT: v_readlane_b32 s54, v4, 14
-; GFX9-NEXT: v_readlane_b32 s53, v4, 13
-; GFX9-NEXT: v_readlane_b32 s52, v4, 12
-; GFX9-NEXT: v_readlane_b32 s51, v4, 11
-; GFX9-NEXT: v_readlane_b32 s50, v4, 10
-; GFX9-NEXT: v_readlane_b32 s49, v4, 9
-; GFX9-NEXT: v_readlane_b32 s48, v4, 8
-; GFX9-NEXT: v_readlane_b32 s39, v4, 7
-; GFX9-NEXT: v_readlane_b32 s38, v4, 6
-; GFX9-NEXT: v_readlane_b32 s37, v4, 5
-; GFX9-NEXT: v_readlane_b32 s36, v4, 4
-; GFX9-NEXT: v_readlane_b32 s35, v4, 3
-; GFX9-NEXT: v_readlane_b32 s34, v4, 2
-; GFX9-NEXT: v_readlane_b32 s31, v4, 1
-; GFX9-NEXT: v_readlane_b32 s30, v4, 0
+; GFX9-NEXT: v_readlane_b32 s31, v4, 15
+; GFX9-NEXT: v_readlane_b32 s55, v4, 13
+; GFX9-NEXT: v_readlane_b32 s54, v4, 12
+; GFX9-NEXT: v_readlane_b32 s53, v4, 11
+; GFX9-NEXT: v_readlane_b32 s52, v4, 10
+; GFX9-NEXT: v_readlane_b32 s51, v4, 9
+; GFX9-NEXT: v_readlane_b32 s50, v4, 8
+; GFX9-NEXT: v_readlane_b32 s49, v4, 7
+; GFX9-NEXT: v_readlane_b32 s48, v4, 6
+; GFX9-NEXT: v_readlane_b32 s39, v4, 5
+; GFX9-NEXT: v_readlane_b32 s38, v4, 4
+; GFX9-NEXT: v_readlane_b32 s37, v4, 3
+; GFX9-NEXT: v_readlane_b32 s36, v4, 2
+; GFX9-NEXT: v_readlane_b32 s35, v4, 1
+; GFX9-NEXT: v_readlane_b32 s34, v4, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -10959,17 +10959,17 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX11-NEXT: s_xor_saveexec_b32 s4, -1
; GFX11-NEXT: scratch_store_b32 off, v17, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v17, s30, 0
+; GFX11-NEXT: v_writelane_b32 v17, s34, 0
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
; GFX11-NEXT: s_mov_b32 vcc_lo, 0
-; GFX11-NEXT: v_writelane_b32 v17, s31, 1
-; GFX11-NEXT: v_writelane_b32 v17, s34, 2
-; GFX11-NEXT: v_writelane_b32 v17, s35, 3
-; GFX11-NEXT: v_writelane_b32 v17, s36, 4
-; GFX11-NEXT: v_writelane_b32 v17, s37, 5
-; GFX11-NEXT: v_writelane_b32 v17, s38, 6
-; GFX11-NEXT: v_writelane_b32 v17, s39, 7
-; GFX11-NEXT: v_writelane_b32 v17, s48, 8
+; GFX11-NEXT: v_writelane_b32 v17, s35, 1
+; GFX11-NEXT: v_writelane_b32 v17, s36, 2
+; GFX11-NEXT: v_writelane_b32 v17, s37, 3
+; GFX11-NEXT: v_writelane_b32 v17, s38, 4
+; GFX11-NEXT: v_writelane_b32 v17, s39, 5
+; GFX11-NEXT: v_writelane_b32 v17, s48, 6
+; GFX11-NEXT: v_writelane_b32 v17, s30, 7
+; GFX11-NEXT: v_writelane_b32 v17, s31, 8
; GFX11-NEXT: s_cbranch_scc0 .LBB25_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s27, 24
@@ -11240,20 +11240,20 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX11-NEXT: s_or_b32 s3, s4, s5
; GFX11-NEXT: v_dual_mov_b32 v13, s0 :: v_dual_mov_b32 v14, s1
; GFX11-NEXT: v_dual_mov_b32 v15, s2 :: v_dual_mov_b32 v16, s3
+; GFX11-NEXT: v_readlane_b32 s30, v17, 7
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
-; GFX11-NEXT: v_readlane_b32 s48, v17, 8
-; GFX11-NEXT: v_readlane_b32 s39, v17, 7
-; GFX11-NEXT: v_readlane_b32 s38, v17, 6
-; GFX11-NEXT: v_readlane_b32 s37, v17, 5
-; GFX11-NEXT: v_readlane_b32 s36, v17, 4
-; GFX11-NEXT: v_readlane_b32 s35, v17, 3
-; GFX11-NEXT: v_readlane_b32 s34, v17, 2
-; GFX11-NEXT: v_readlane_b32 s31, v17, 1
-; GFX11-NEXT: v_readlane_b32 s30, v17, 0
+; GFX11-NEXT: v_readlane_b32 s31, v17, 8
+; GFX11-NEXT: v_readlane_b32 s48, v17, 6
+; GFX11-NEXT: v_readlane_b32 s39, v17, 5
+; GFX11-NEXT: v_readlane_b32 s38, v17, 4
+; GFX11-NEXT: v_readlane_b32 s37, v17, 3
+; GFX11-NEXT: v_readlane_b32 s36, v17, 2
+; GFX11-NEXT: v_readlane_b32 s35, v17, 1
+; GFX11-NEXT: v_readlane_b32 s34, v17, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v17, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
@@ -21883,8 +21883,8 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_mov_b32_e32 v15, s31
; VI-NEXT: .LBB47_5: ; %end
-; VI-NEXT: v_readlane_b32 s31, v19, 1
; VI-NEXT: v_readlane_b32 s30, v19, 0
+; VI-NEXT: v_readlane_b32 s31, v19, 1
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -22234,8 +22234,8 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; GFX9-NEXT: v_mov_b32_e32 v14, s30
; GFX9-NEXT: v_mov_b32_e32 v15, s31
; GFX9-NEXT: .LBB47_5: ; %end
-; GFX9-NEXT: v_readlane_b32 s31, v20, 1
; GFX9-NEXT: v_readlane_b32 s30, v20, 0
+; GFX9-NEXT: v_readlane_b32 s31, v20, 1
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -24582,40 +24582,40 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v40, s30, 0
-; SI-NEXT: v_writelane_b32 v40, s31, 1
-; SI-NEXT: v_writelane_b32 v40, s34, 2
-; SI-NEXT: v_writelane_b32 v40, s35, 3
-; SI-NEXT: v_writelane_b32 v40, s36, 4
-; SI-NEXT: v_writelane_b32 v40, s37, 5
-; SI-NEXT: v_writelane_b32 v40, s38, 6
-; SI-NEXT: v_writelane_b32 v40, s39, 7
-; SI-NEXT: v_writelane_b32 v40, s48, 8
-; SI-NEXT: v_writelane_b32 v40, s49, 9
-; SI-NEXT: v_writelane_b32 v40, s50, 10
-; SI-NEXT: v_writelane_b32 v40, s51, 11
-; SI-NEXT: v_writelane_b32 v40, s52, 12
-; SI-NEXT: v_writelane_b32 v40, s53, 13
-; SI-NEXT: v_writelane_b32 v40, s54, 14
-; SI-NEXT: v_writelane_b32 v40, s55, 15
-; SI-NEXT: v_writelane_b32 v40, s64, 16
-; SI-NEXT: v_writelane_b32 v40, s65, 17
-; SI-NEXT: v_writelane_b32 v40, s66, 18
-; SI-NEXT: v_writelane_b32 v40, s67, 19
-; SI-NEXT: v_writelane_b32 v40, s68, 20
-; SI-NEXT: v_writelane_b32 v40, s69, 21
-; SI-NEXT: v_writelane_b32 v40, s70, 22
-; SI-NEXT: v_writelane_b32 v40, s71, 23
-; SI-NEXT: v_writelane_b32 v40, s80, 24
-; SI-NEXT: v_writelane_b32 v40, s81, 25
-; SI-NEXT: v_writelane_b32 v40, s82, 26
-; SI-NEXT: v_writelane_b32 v40, s83, 27
+; SI-NEXT: v_writelane_b32 v40, s34, 0
+; SI-NEXT: v_writelane_b32 v40, s35, 1
+; SI-NEXT: v_writelane_b32 v40, s36, 2
+; SI-NEXT: v_writelane_b32 v40, s37, 3
+; SI-NEXT: v_writelane_b32 v40, s38, 4
+; SI-NEXT: v_writelane_b32 v40, s39, 5
+; SI-NEXT: v_writelane_b32 v40, s48, 6
+; SI-NEXT: v_writelane_b32 v40, s49, 7
+; SI-NEXT: v_writelane_b32 v40, s50, 8
+; SI-NEXT: v_writelane_b32 v40, s51, 9
+; SI-NEXT: v_writelane_b32 v40, s52, 10
+; SI-NEXT: v_writelane_b32 v40, s53, 11
+; SI-NEXT: v_writelane_b32 v40, s54, 12
+; SI-NEXT: v_writelane_b32 v40, s55, 13
+; SI-NEXT: v_writelane_b32 v40, s64, 14
+; SI-NEXT: v_writelane_b32 v40, s65, 15
+; SI-NEXT: v_writelane_b32 v40, s66, 16
+; SI-NEXT: v_writelane_b32 v40, s67, 17
+; SI-NEXT: v_writelane_b32 v40, s68, 18
+; SI-NEXT: v_writelane_b32 v40, s69, 19
+; SI-NEXT: v_writelane_b32 v40, s70, 20
+; SI-NEXT: v_writelane_b32 v40, s71, 21
+; SI-NEXT: v_writelane_b32 v40, s80, 22
+; SI-NEXT: v_writelane_b32 v40, s81, 23
+; SI-NEXT: v_writelane_b32 v40, s82, 24
+; SI-NEXT: v_writelane_b32 v40, s83, 25
+; SI-NEXT: v_writelane_b32 v40, s84, 26
+; SI-NEXT: v_writelane_b32 v40, s85, 27
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; SI-NEXT: v_writelane_b32 v40, s84, 28
+; SI-NEXT: v_writelane_b32 v40, s30, 28
; SI-NEXT: v_readfirstlane_b32 s36, v1
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s37, v2
-; SI-NEXT: v_writelane_b32 v40, s85, 29
+; SI-NEXT: v_writelane_b32 v40, s31, 29
; SI-NEXT: s_cbranch_scc0 .LBB49_3
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s82, s37, 24
@@ -25030,37 +25030,37 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
+; SI-NEXT: v_readlane_b32 s30, v40, 28
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s85, v40, 29
-; SI-NEXT: v_readlane_b32 s84, v40, 28
-; SI-NEXT: v_readlane_b32 s83, v40, 27
-; SI-NEXT: v_readlane_b32 s82, v40, 26
-; SI-NEXT: v_readlane_b32 s81, v40, 25
-; SI-NEXT: v_readlane_b32 s80, v40, 24
-; SI-NEXT: v_readlane_b32 s71, v40, 23
-; SI-NEXT: v_readlane_b32 s70, v40, 22
-; SI-NEXT: v_readlane_b32 s69, v40, 21
-; SI-NEXT: v_readlane_b32 s68, v40, 20
-; SI-NEXT: v_readlane_b32 s67, v40, 19
-; SI-NEXT: v_readlane_b32 s66, v40, 18
-; SI-NEXT: v_readlane_b32 s65, v40, 17
-; SI-NEXT: v_readlane_b32 s64, v40, 16
-; SI-NEXT: v_readlane_b32 s55, v40, 15
-; SI-NEXT: v_readlane_b32 s54, v40, 14
-; SI-NEXT: v_readlane_b32 s53, v40, 13
-; SI-NEXT: v_readlane_b32 s52, v40, 12
-; SI-NEXT: v_readlane_b32 s51, v40, 11
-; SI-NEXT: v_readlane_b32 s50, v40, 10
-; SI-NEXT: v_readlane_b32 s49, v40, 9
-; SI-NEXT: v_readlane_b32 s48, v40, 8
-; SI-NEXT: v_readlane_b32 s39, v40, 7
-; SI-NEXT: v_readlane_b32 s38, v40, 6
-; SI-NEXT: v_readlane_b32 s37, v40, 5
-; SI-NEXT: v_readlane_b32 s36, v40, 4
-; SI-NEXT: v_readlane_b32 s35, v40, 3
-; SI-NEXT: v_readlane_b32 s34, v40, 2
-; SI-NEXT: v_readlane_b32 s31, v40, 1
-; SI-NEXT: v_readlane_b32 s30, v40, 0
+; SI-NEXT: v_readlane_b32 s31, v40, 29
+; SI-NEXT: v_readlane_b32 s85, v40, 27
+; SI-NEXT: v_readlane_b32 s84, v40, 26
+; SI-NEXT: v_readlane_b32 s83, v40, 25
+; SI-NEXT: v_readlane_b32 s82, v40, 24
+; SI-NEXT: v_readlane_b32 s81, v40, 23
+; SI-NEXT: v_readlane_b32 s80, v40, 22
+; SI-NEXT: v_readlane_b32 s71, v40, 21
+; SI-NEXT: v_readlane_b32 s70, v40, 20
+; SI-NEXT: v_readlane_b32 s69, v40, 19
+; SI-NEXT: v_readlane_b32 s68, v40, 18
+; SI-NEXT: v_readlane_b32 s67, v40, 17
+; SI-NEXT: v_readlane_b32 s66, v40, 16
+; SI-NEXT: v_readlane_b32 s65, v40, 15
+; SI-NEXT: v_readlane_b32 s64, v40, 14
+; SI-NEXT: v_readlane_b32 s55, v40, 13
+; SI-NEXT: v_readlane_b32 s54, v40, 12
+; SI-NEXT: v_readlane_b32 s53, v40, 11
+; SI-NEXT: v_readlane_b32 s52, v40, 10
+; SI-NEXT: v_readlane_b32 s51, v40, 9
+; SI-NEXT: v_readlane_b32 s50, v40, 8
+; SI-NEXT: v_readlane_b32 s49, v40, 7
+; SI-NEXT: v_readlane_b32 s48, v40, 6
+; SI-NEXT: v_readlane_b32 s39, v40, 5
+; SI-NEXT: v_readlane_b32 s38, v40, 4
+; SI-NEXT: v_readlane_b32 s37, v40, 3
+; SI-NEXT: v_readlane_b32 s36, v40, 2
+; SI-NEXT: v_readlane_b32 s35, v40, 1
+; SI-NEXT: v_readlane_b32 s34, v40, 0
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
@@ -25073,27 +25073,27 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v63, s30, 0
-; VI-NEXT: v_writelane_b32 v63, s31, 1
-; VI-NEXT: v_writelane_b32 v63, s34, 2
-; VI-NEXT: v_writelane_b32 v63, s35, 3
-; VI-NEXT: v_writelane_b32 v63, s36, 4
-; VI-NEXT: v_writelane_b32 v63, s37, 5
-; VI-NEXT: v_writelane_b32 v63, s38, 6
-; VI-NEXT: v_writelane_b32 v63, s39, 7
-; VI-NEXT: v_writelane_b32 v63, s48, 8
-; VI-NEXT: v_writelane_b32 v63, s49, 9
-; VI-NEXT: v_writelane_b32 v63, s50, 10
-; VI-NEXT: v_writelane_b32 v63, s51, 11
-; VI-NEXT: v_writelane_b32 v63, s52, 12
-; VI-NEXT: v_writelane_b32 v63, s53, 13
-; VI-NEXT: v_writelane_b32 v63, s54, 14
-; VI-NEXT: v_writelane_b32 v63, s55, 15
-; VI-NEXT: v_writelane_b32 v63, s64, 16
-; VI-NEXT: v_writelane_b32 v63, s65, 17
-; VI-NEXT: v_writelane_b32 v63, s66, 18
+; VI-NEXT: v_writelane_b32 v63, s34, 0
+; VI-NEXT: v_writelane_b32 v63, s35, 1
+; VI-NEXT: v_writelane_b32 v63, s36, 2
+; VI-NEXT: v_writelane_b32 v63, s37, 3
+; VI-NEXT: v_writelane_b32 v63, s38, 4
+; VI-NEXT: v_writelane_b32 v63, s39, 5
+; VI-NEXT: v_writelane_b32 v63, s48, 6
+; VI-NEXT: v_writelane_b32 v63, s49, 7
+; VI-NEXT: v_writelane_b32 v63, s50, 8
+; VI-NEXT: v_writelane_b32 v63, s51, 9
+; VI-NEXT: v_writelane_b32 v63, s52, 10
+; VI-NEXT: v_writelane_b32 v63, s53, 11
+; VI-NEXT: v_writelane_b32 v63, s54, 12
+; VI-NEXT: v_writelane_b32 v63, s55, 13
+; VI-NEXT: v_writelane_b32 v63, s64, 14
+; VI-NEXT: v_writelane_b32 v63, s65, 15
+; VI-NEXT: v_writelane_b32 v63, s66, 16
+; VI-NEXT: v_writelane_b32 v63, s67, 17
+; VI-NEXT: v_writelane_b32 v63, s30, 18
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; VI-NEXT: v_writelane_b32 v63, s67, 19
+; VI-NEXT: v_writelane_b32 v63, s31, 19
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
@@ -25440,26 +25440,26 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; VI-NEXT: v_or_b32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; VI-NEXT: v_readlane_b32 s67, v63, 19
-; VI-NEXT: v_readlane_b32 s66, v63, 18
-; VI-NEXT: v_readlane_b32 s65, v63, 17
-; VI-NEXT: v_readlane_b32 s64, v63, 16
-; VI-NEXT: v_readlane_b32 s55, v63, 15
-; VI-NEXT: v_readlane_b32 s54, v63, 14
-; VI-NEXT: v_readlane_b32 s53, v63, 13
-; VI-NEXT: v_readlane_b32 s52, v63, 12
-; VI-NEXT: v_readlane_b32 s51, v63, 11
-; VI-NEXT: v_readlane_b32 s50, v63, 10
-; VI-NEXT: v_readlane_b32 s49, v63, 9
-; VI-NEXT: v_readlane_b32 s48, v63, 8
-; VI-NEXT: v_readlane_b32 s39, v63, 7
-; VI-NEXT: v_readlane_b32 s38, v63, 6
-; VI-NEXT: v_readlane_b32 s37, v63, 5
-; VI-NEXT: v_readlane_b32 s36, v63, 4
-; VI-NEXT: v_readlane_b32 s35, v63, 3
-; VI-NEXT: v_readlane_b32 s34, v63, 2
-; VI-NEXT: v_readlane_b32 s31, v63, 1
-; VI-NEXT: v_readlane_b32 s30, v63, 0
+; VI-NEXT: v_readlane_b32 s30, v63, 18
+; VI-NEXT: v_readlane_b32 s31, v63, 19
+; VI-NEXT: v_readlane_b32 s67, v63, 17
+; VI-NEXT: v_readlane_b32 s66, v63, 16
+; VI-NEXT: v_readlane_b32 s65, v63, 15
+; VI-NEXT: v_readlane_b32 s64, v63, 14
+; VI-NEXT: v_readlane_b32 s55, v63, 13
+; VI-NEXT: v_readlane_b32 s54, v63, 12
+; VI-NEXT: v_readlane_b32 s53, v63, 11
+; VI-NEXT: v_readlane_b32 s52, v63, 10
+; VI-NEXT: v_readlane_b32 s51, v63, 9
+; VI-NEXT: v_readlane_b32 s50, v63, 8
+; VI-NEXT: v_readlane_b32 s49, v63, 7
+; VI-NEXT: v_readlane_b32 s48, v63, 6
+; VI-NEXT: v_readlane_b32 s39, v63, 5
+; VI-NEXT: v_readlane_b32 s38, v63, 4
+; VI-NEXT: v_readlane_b32 s37, v63, 3
+; VI-NEXT: v_readlane_b32 s36, v63, 2
+; VI-NEXT: v_readlane_b32 s35, v63, 1
+; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; VI-NEXT: v_or_b32_sdwa v5, v33, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -25517,23 +25517,23 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v63, s30, 0
-; GFX9-NEXT: v_writelane_b32 v63, s31, 1
-; GFX9-NEXT: v_writelane_b32 v63, s34, 2
-; GFX9-NEXT: v_writelane_b32 v63, s35, 3
-; GFX9-NEXT: v_writelane_b32 v63, s36, 4
-; GFX9-NEXT: v_writelane_b32 v63, s37, 5
-; GFX9-NEXT: v_writelane_b32 v63, s38, 6
-; GFX9-NEXT: v_writelane_b32 v63, s39, 7
-; GFX9-NEXT: v_writelane_b32 v63, s48, 8
-; GFX9-NEXT: v_writelane_b32 v63, s49, 9
-; GFX9-NEXT: v_writelane_b32 v63, s50, 10
-; GFX9-NEXT: v_writelane_b32 v63, s51, 11
-; GFX9-NEXT: v_writelane_b32 v63, s52, 12
-; GFX9-NEXT: v_writelane_b32 v63, s53, 13
-; GFX9-NEXT: v_writelane_b32 v63, s54, 14
+; GFX9-NEXT: v_writelane_b32 v63, s34, 0
+; GFX9-NEXT: v_writelane_b32 v63, s35, 1
+; GFX9-NEXT: v_writelane_b32 v63, s36, 2
+; GFX9-NEXT: v_writelane_b32 v63, s37, 3
+; GFX9-NEXT: v_writelane_b32 v63, s38, 4
+; GFX9-NEXT: v_writelane_b32 v63, s39, 5
+; GFX9-NEXT: v_writelane_b32 v63, s48, 6
+; GFX9-NEXT: v_writelane_b32 v63, s49, 7
+; GFX9-NEXT: v_writelane_b32 v63, s50, 8
+; GFX9-NEXT: v_writelane_b32 v63, s51, 9
+; GFX9-NEXT: v_writelane_b32 v63, s52, 10
+; GFX9-NEXT: v_writelane_b32 v63, s53, 11
+; GFX9-NEXT: v_writelane_b32 v63, s54, 12
+; GFX9-NEXT: v_writelane_b32 v63, s55, 13
+; GFX9-NEXT: v_writelane_b32 v63, s30, 14
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; GFX9-NEXT: v_writelane_b32 v63, s55, 15
+; GFX9-NEXT: v_writelane_b32 v63, s31, 15
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
@@ -25873,22 +25873,22 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX9-NEXT: v_or_b32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s55, v63, 15
-; GFX9-NEXT: v_readlane_b32 s54, v63, 14
-; GFX9-NEXT: v_readlane_b32 s53, v63, 13
-; GFX9-NEXT: v_readlane_b32 s52, v63, 12
-; GFX9-NEXT: v_readlane_b32 s51, v63, 11
-; GFX9-NEXT: v_readlane_b32 s50, v63, 10
-; GFX9-NEXT: v_readlane_b32 s49, v63, 9
-; GFX9-NEXT: v_readlane_b32 s48, v63, 8
-; GFX9-NEXT: v_readlane_b32 s39, v63, 7
-; GFX9-NEXT: v_readlane_b32 s38, v63, 6
-; GFX9-NEXT: v_readlane_b32 s37, v63, 5
-; GFX9-NEXT: v_readlane_b32 s36, v63, 4
-; GFX9-NEXT: v_readlane_b32 s35, v63, 3
-; GFX9-NEXT: v_readlane_b32 s34, v63, 2
-; GFX9-NEXT: v_readlane_b32 s31, v63, 1
-; GFX9-NEXT: v_readlane_b32 s30, v63, 0
+; GFX9-NEXT: v_readlane_b32 s30, v63, 14
+; GFX9-NEXT: v_readlane_b32 s31, v63, 15
+; GFX9-NEXT: v_readlane_b32 s55, v63, 13
+; GFX9-NEXT: v_readlane_b32 s54, v63, 12
+; GFX9-NEXT: v_readlane_b32 s53, v63, 11
+; GFX9-NEXT: v_readlane_b32 s52, v63, 10
+; GFX9-NEXT: v_readlane_b32 s51, v63, 9
+; GFX9-NEXT: v_readlane_b32 s50, v63, 8
+; GFX9-NEXT: v_readlane_b32 s49, v63, 7
+; GFX9-NEXT: v_readlane_b32 s48, v63, 6
+; GFX9-NEXT: v_readlane_b32 s39, v63, 5
+; GFX9-NEXT: v_readlane_b32 s38, v63, 4
+; GFX9-NEXT: v_readlane_b32 s37, v63, 3
+; GFX9-NEXT: v_readlane_b32 s36, v63, 2
+; GFX9-NEXT: v_readlane_b32 s35, v63, 1
+; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v5, v33, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -25942,18 +25942,18 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX11-NEXT: s_or_saveexec_b32 s4, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s34, 0
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
; GFX11-NEXT: s_mov_b32 s42, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
-; GFX11-NEXT: v_writelane_b32 v40, s34, 2
-; GFX11-NEXT: v_writelane_b32 v40, s35, 3
-; GFX11-NEXT: v_writelane_b32 v40, s36, 4
-; GFX11-NEXT: v_writelane_b32 v40, s37, 5
-; GFX11-NEXT: v_writelane_b32 v40, s38, 6
-; GFX11-NEXT: v_writelane_b32 v40, s39, 7
-; GFX11-NEXT: v_writelane_b32 v40, s48, 8
-; GFX11-NEXT: v_writelane_b32 v40, s49, 9
+; GFX11-NEXT: v_writelane_b32 v40, s35, 1
+; GFX11-NEXT: v_writelane_b32 v40, s36, 2
+; GFX11-NEXT: v_writelane_b32 v40, s37, 3
+; GFX11-NEXT: v_writelane_b32 v40, s38, 4
+; GFX11-NEXT: v_writelane_b32 v40, s39, 5
+; GFX11-NEXT: v_writelane_b32 v40, s48, 6
+; GFX11-NEXT: v_writelane_b32 v40, s49, 7
+; GFX11-NEXT: v_writelane_b32 v40, s30, 8
+; GFX11-NEXT: v_writelane_b32 v40, s31, 9
; GFX11-NEXT: s_cbranch_scc0 .LBB49_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s43, s27, 24
@@ -26301,21 +26301,21 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX11-NEXT: v_or_b32_e32 v2, v4, v10
; GFX11-NEXT: v_or_b32_e32 v3, v11, v7
; GFX11-NEXT: v_or_b32_e32 v4, v12, v8
+; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[82:85], off
; GFX11-NEXT: scratch_store_b128 v0, v[23:26], off offset:16
; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48
-; GFX11-NEXT: v_readlane_b32 s49, v40, 9
-; GFX11-NEXT: v_readlane_b32 s48, v40, 8
-; GFX11-NEXT: v_readlane_b32 s39, v40, 7
-; GFX11-NEXT: v_readlane_b32 s38, v40, 6
-; GFX11-NEXT: v_readlane_b32 s37, v40, 5
-; GFX11-NEXT: v_readlane_b32 s36, v40, 4
-; GFX11-NEXT: v_readlane_b32 s35, v40, 3
-; GFX11-NEXT: v_readlane_b32 s34, v40, 2
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
-; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 9
+; GFX11-NEXT: v_readlane_b32 s49, v40, 7
+; GFX11-NEXT: v_readlane_b32 s48, v40, 6
+; GFX11-NEXT: v_readlane_b32 s39, v40, 5
+; GFX11-NEXT: v_readlane_b32 s38, v40, 4
+; GFX11-NEXT: v_readlane_b32 s37, v40, 3
+; GFX11-NEXT: v_readlane_b32 s36, v40, 2
+; GFX11-NEXT: v_readlane_b32 s35, v40, 1
+; GFX11-NEXT: v_readlane_b32 s34, v40, 0
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
@@ -36282,8 +36282,8 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_mov_b32_e32 v15, s31
; VI-NEXT: .LBB67_5: ; %end
-; VI-NEXT: v_readlane_b32 s31, v19, 1
; VI-NEXT: v_readlane_b32 s30, v19, 0
+; VI-NEXT: v_readlane_b32 s31, v19, 1
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -36633,8 +36633,8 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v14, s30
; GFX9-NEXT: v_mov_b32_e32 v15, s31
; GFX9-NEXT: .LBB67_5: ; %end
-; GFX9-NEXT: v_readlane_b32 s31, v20, 1
; GFX9-NEXT: v_readlane_b32 s30, v20, 0
+; GFX9-NEXT: v_readlane_b32 s31, v20, 1
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -39007,40 +39007,40 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v4, s30, 0
-; SI-NEXT: v_writelane_b32 v4, s31, 1
-; SI-NEXT: v_writelane_b32 v4, s34, 2
-; SI-NEXT: v_writelane_b32 v4, s35, 3
-; SI-NEXT: v_writelane_b32 v4, s36, 4
-; SI-NEXT: v_writelane_b32 v4, s37, 5
-; SI-NEXT: v_writelane_b32 v4, s38, 6
-; SI-NEXT: v_writelane_b32 v4, s39, 7
-; SI-NEXT: v_writelane_b32 v4, s48, 8
-; SI-NEXT: v_writelane_b32 v4, s49, 9
-; SI-NEXT: v_writelane_b32 v4, s50, 10
-; SI-NEXT: v_writelane_b32 v4, s51, 11
-; SI-NEXT: v_writelane_b32 v4, s52, 12
-; SI-NEXT: v_writelane_b32 v4, s53, 13
-; SI-NEXT: v_writelane_b32 v4, s54, 14
-; SI-NEXT: v_writelane_b32 v4, s55, 15
-; SI-NEXT: v_writelane_b32 v4, s64, 16
-; SI-NEXT: v_writelane_b32 v4, s65, 17
-; SI-NEXT: v_writelane_b32 v4, s66, 18
-; SI-NEXT: v_writelane_b32 v4, s67, 19
-; SI-NEXT: v_writelane_b32 v4, s68, 20
-; SI-NEXT: v_writelane_b32 v4, s69, 21
-; SI-NEXT: v_writelane_b32 v4, s70, 22
-; SI-NEXT: v_writelane_b32 v4, s71, 23
-; SI-NEXT: v_writelane_b32 v4, s80, 24
-; SI-NEXT: v_writelane_b32 v4, s81, 25
-; SI-NEXT: v_writelane_b32 v4, s82, 26
-; SI-NEXT: v_writelane_b32 v4, s83, 27
+; SI-NEXT: v_writelane_b32 v4, s34, 0
+; SI-NEXT: v_writelane_b32 v4, s35, 1
+; SI-NEXT: v_writelane_b32 v4, s36, 2
+; SI-NEXT: v_writelane_b32 v4, s37, 3
+; SI-NEXT: v_writelane_b32 v4, s38, 4
+; SI-NEXT: v_writelane_b32 v4, s39, 5
+; SI-NEXT: v_writelane_b32 v4, s48, 6
+; SI-NEXT: v_writelane_b32 v4, s49, 7
+; SI-NEXT: v_writelane_b32 v4, s50, 8
+; SI-NEXT: v_writelane_b32 v4, s51, 9
+; SI-NEXT: v_writelane_b32 v4, s52, 10
+; SI-NEXT: v_writelane_b32 v4, s53, 11
+; SI-NEXT: v_writelane_b32 v4, s54, 12
+; SI-NEXT: v_writelane_b32 v4, s55, 13
+; SI-NEXT: v_writelane_b32 v4, s64, 14
+; SI-NEXT: v_writelane_b32 v4, s65, 15
+; SI-NEXT: v_writelane_b32 v4, s66, 16
+; SI-NEXT: v_writelane_b32 v4, s67, 17
+; SI-NEXT: v_writelane_b32 v4, s68, 18
+; SI-NEXT: v_writelane_b32 v4, s69, 19
+; SI-NEXT: v_writelane_b32 v4, s70, 20
+; SI-NEXT: v_writelane_b32 v4, s71, 21
+; SI-NEXT: v_writelane_b32 v4, s80, 22
+; SI-NEXT: v_writelane_b32 v4, s81, 23
+; SI-NEXT: v_writelane_b32 v4, s82, 24
+; SI-NEXT: v_writelane_b32 v4, s83, 25
+; SI-NEXT: v_writelane_b32 v4, s84, 26
+; SI-NEXT: v_writelane_b32 v4, s85, 27
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; SI-NEXT: v_writelane_b32 v4, s84, 28
+; SI-NEXT: v_writelane_b32 v4, s30, 28
; SI-NEXT: v_readfirstlane_b32 s4, v1
; SI-NEXT: s_and_b64 s[6:7], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v2
-; SI-NEXT: v_writelane_b32 v4, s85, 29
+; SI-NEXT: v_writelane_b32 v4, s31, 29
; SI-NEXT: s_cbranch_scc0 .LBB69_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s38, s5, 24
@@ -39361,37 +39361,37 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v4, 28
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s85, v4, 29
-; SI-NEXT: v_readlane_b32 s84, v4, 28
-; SI-NEXT: v_readlane_b32 s83, v4, 27
-; SI-NEXT: v_readlane_b32 s82, v4, 26
-; SI-NEXT: v_readlane_b32 s81, v4, 25
-; SI-NEXT: v_readlane_b32 s80, v4, 24
-; SI-NEXT: v_readlane_b32 s71, v4, 23
-; SI-NEXT: v_readlane_b32 s70, v4, 22
-; SI-NEXT: v_readlane_b32 s69, v4, 21
-; SI-NEXT: v_readlane_b32 s68, v4, 20
-; SI-NEXT: v_readlane_b32 s67, v4, 19
-; SI-NEXT: v_readlane_b32 s66, v4, 18
-; SI-NEXT: v_readlane_b32 s65, v4, 17
-; SI-NEXT: v_readlane_b32 s64, v4, 16
-; SI-NEXT: v_readlane_b32 s55, v4, 15
-; SI-NEXT: v_readlane_b32 s54, v4, 14
-; SI-NEXT: v_readlane_b32 s53, v4, 13
-; SI-NEXT: v_readlane_b32 s52, v4, 12
-; SI-NEXT: v_readlane_b32 s51, v4, 11
-; SI-NEXT: v_readlane_b32 s50, v4, 10
-; SI-NEXT: v_readlane_b32 s49, v4, 9
-; SI-NEXT: v_readlane_b32 s48, v4, 8
-; SI-NEXT: v_readlane_b32 s39, v4, 7
-; SI-NEXT: v_readlane_b32 s38, v4, 6
-; SI-NEXT: v_readlane_b32 s37, v4, 5
-; SI-NEXT: v_readlane_b32 s36, v4, 4
-; SI-NEXT: v_readlane_b32 s35, v4, 3
-; SI-NEXT: v_readlane_b32 s34, v4, 2
-; SI-NEXT: v_readlane_b32 s31, v4, 1
-; SI-NEXT: v_readlane_b32 s30, v4, 0
+; SI-NEXT: v_readlane_b32 s31, v4, 29
+; SI-NEXT: v_readlane_b32 s85, v4, 27
+; SI-NEXT: v_readlane_b32 s84, v4, 26
+; SI-NEXT: v_readlane_b32 s83, v4, 25
+; SI-NEXT: v_readlane_b32 s82, v4, 24
+; SI-NEXT: v_readlane_b32 s81, v4, 23
+; SI-NEXT: v_readlane_b32 s80, v4, 22
+; SI-NEXT: v_readlane_b32 s71, v4, 21
+; SI-NEXT: v_readlane_b32 s70, v4, 20
+; SI-NEXT: v_readlane_b32 s69, v4, 19
+; SI-NEXT: v_readlane_b32 s68, v4, 18
+; SI-NEXT: v_readlane_b32 s67, v4, 17
+; SI-NEXT: v_readlane_b32 s66, v4, 16
+; SI-NEXT: v_readlane_b32 s65, v4, 15
+; SI-NEXT: v_readlane_b32 s64, v4, 14
+; SI-NEXT: v_readlane_b32 s55, v4, 13
+; SI-NEXT: v_readlane_b32 s54, v4, 12
+; SI-NEXT: v_readlane_b32 s53, v4, 11
+; SI-NEXT: v_readlane_b32 s52, v4, 10
+; SI-NEXT: v_readlane_b32 s51, v4, 9
+; SI-NEXT: v_readlane_b32 s50, v4, 8
+; SI-NEXT: v_readlane_b32 s49, v4, 7
+; SI-NEXT: v_readlane_b32 s48, v4, 6
+; SI-NEXT: v_readlane_b32 s39, v4, 5
+; SI-NEXT: v_readlane_b32 s38, v4, 4
+; SI-NEXT: v_readlane_b32 s37, v4, 3
+; SI-NEXT: v_readlane_b32 s36, v4, 2
+; SI-NEXT: v_readlane_b32 s35, v4, 1
+; SI-NEXT: v_readlane_b32 s34, v4, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
@@ -39454,30 +39454,30 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v4, s30, 0
-; VI-NEXT: v_writelane_b32 v4, s31, 1
-; VI-NEXT: v_writelane_b32 v4, s34, 2
-; VI-NEXT: v_writelane_b32 v4, s35, 3
-; VI-NEXT: v_writelane_b32 v4, s36, 4
-; VI-NEXT: v_writelane_b32 v4, s37, 5
-; VI-NEXT: v_writelane_b32 v4, s38, 6
-; VI-NEXT: v_writelane_b32 v4, s39, 7
-; VI-NEXT: v_writelane_b32 v4, s48, 8
-; VI-NEXT: v_writelane_b32 v4, s49, 9
-; VI-NEXT: v_writelane_b32 v4, s50, 10
-; VI-NEXT: v_writelane_b32 v4, s51, 11
-; VI-NEXT: v_writelane_b32 v4, s52, 12
-; VI-NEXT: v_writelane_b32 v4, s53, 13
-; VI-NEXT: v_writelane_b32 v4, s54, 14
-; VI-NEXT: v_writelane_b32 v4, s55, 15
-; VI-NEXT: v_writelane_b32 v4, s64, 16
-; VI-NEXT: v_writelane_b32 v4, s65, 17
+; VI-NEXT: v_writelane_b32 v4, s34, 0
+; VI-NEXT: v_writelane_b32 v4, s35, 1
+; VI-NEXT: v_writelane_b32 v4, s36, 2
+; VI-NEXT: v_writelane_b32 v4, s37, 3
+; VI-NEXT: v_writelane_b32 v4, s38, 4
+; VI-NEXT: v_writelane_b32 v4, s39, 5
+; VI-NEXT: v_writelane_b32 v4, s48, 6
+; VI-NEXT: v_writelane_b32 v4, s49, 7
+; VI-NEXT: v_writelane_b32 v4, s50, 8
+; VI-NEXT: v_writelane_b32 v4, s51, 9
+; VI-NEXT: v_writelane_b32 v4, s52, 10
+; VI-NEXT: v_writelane_b32 v4, s53, 11
+; VI-NEXT: v_writelane_b32 v4, s54, 12
+; VI-NEXT: v_writelane_b32 v4, s55, 13
+; VI-NEXT: v_writelane_b32 v4, s64, 14
+; VI-NEXT: v_writelane_b32 v4, s65, 15
+; VI-NEXT: v_writelane_b32 v4, s66, 16
+; VI-NEXT: v_writelane_b32 v4, s67, 17
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; VI-NEXT: v_writelane_b32 v4, s66, 18
+; VI-NEXT: v_writelane_b32 v4, s30, 18
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
-; VI-NEXT: v_writelane_b32 v4, s67, 19
+; VI-NEXT: v_writelane_b32 v4, s31, 19
; VI-NEXT: s_cbranch_scc0 .LBB69_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s56, s5, 24
@@ -39785,27 +39785,27 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: v_mov_b32_e32 v1, s4
+; VI-NEXT: v_readlane_b32 s30, v4, 18
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT: v_readlane_b32 s67, v4, 19
-; VI-NEXT: v_readlane_b32 s66, v4, 18
-; VI-NEXT: v_readlane_b32 s65, v4, 17
-; VI-NEXT: v_readlane_b32 s64, v4, 16
-; VI-NEXT: v_readlane_b32 s55, v4, 15
-; VI-NEXT: v_readlane_b32 s54, v4, 14
-; VI-NEXT: v_readlane_b32 s53, v4, 13
-; VI-NEXT: v_readlane_b32 s52, v4, 12
-; VI-NEXT: v_readlane_b32 s51, v4, 11
-; VI-NEXT: v_readlane_b32 s50, v4, 10
-; VI-NEXT: v_readlane_b32 s49, v4, 9
-; VI-NEXT: v_readlane_b32 s48, v4, 8
-; VI-NEXT: v_readlane_b32 s39, v4, 7
-; VI-NEXT: v_readlane_b32 s38, v4, 6
-; VI-NEXT: v_readlane_b32 s37, v4, 5
-; VI-NEXT: v_readlane_b32 s36, v4, 4
-; VI-NEXT: v_readlane_b32 s35, v4, 3
-; VI-NEXT: v_readlane_b32 s34, v4, 2
-; VI-NEXT: v_readlane_b32 s31, v4, 1
-; VI-NEXT: v_readlane_b32 s30, v4, 0
+; VI-NEXT: v_readlane_b32 s31, v4, 19
+; VI-NEXT: v_readlane_b32 s67, v4, 17
+; VI-NEXT: v_readlane_b32 s66, v4, 16
+; VI-NEXT: v_readlane_b32 s65, v4, 15
+; VI-NEXT: v_readlane_b32 s64, v4, 14
+; VI-NEXT: v_readlane_b32 s55, v4, 13
+; VI-NEXT: v_readlane_b32 s54, v4, 12
+; VI-NEXT: v_readlane_b32 s53, v4, 11
+; VI-NEXT: v_readlane_b32 s52, v4, 10
+; VI-NEXT: v_readlane_b32 s51, v4, 9
+; VI-NEXT: v_readlane_b32 s50, v4, 8
+; VI-NEXT: v_readlane_b32 s49, v4, 7
+; VI-NEXT: v_readlane_b32 s48, v4, 6
+; VI-NEXT: v_readlane_b32 s39, v4, 5
+; VI-NEXT: v_readlane_b32 s38, v4, 4
+; VI-NEXT: v_readlane_b32 s37, v4, 3
+; VI-NEXT: v_readlane_b32 s36, v4, 2
+; VI-NEXT: v_readlane_b32 s35, v4, 1
+; VI-NEXT: v_readlane_b32 s34, v4, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -39868,26 +39868,26 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v4, s30, 0
-; GFX9-NEXT: v_writelane_b32 v4, s31, 1
-; GFX9-NEXT: v_writelane_b32 v4, s34, 2
-; GFX9-NEXT: v_writelane_b32 v4, s35, 3
-; GFX9-NEXT: v_writelane_b32 v4, s36, 4
-; GFX9-NEXT: v_writelane_b32 v4, s37, 5
-; GFX9-NEXT: v_writelane_b32 v4, s38, 6
-; GFX9-NEXT: v_writelane_b32 v4, s39, 7
-; GFX9-NEXT: v_writelane_b32 v4, s48, 8
-; GFX9-NEXT: v_writelane_b32 v4, s49, 9
-; GFX9-NEXT: v_writelane_b32 v4, s50, 10
-; GFX9-NEXT: v_writelane_b32 v4, s51, 11
-; GFX9-NEXT: v_writelane_b32 v4, s52, 12
-; GFX9-NEXT: v_writelane_b32 v4, s53, 13
+; GFX9-NEXT: v_writelane_b32 v4, s34, 0
+; GFX9-NEXT: v_writelane_b32 v4, s35, 1
+; GFX9-NEXT: v_writelane_b32 v4, s36, 2
+; GFX9-NEXT: v_writelane_b32 v4, s37, 3
+; GFX9-NEXT: v_writelane_b32 v4, s38, 4
+; GFX9-NEXT: v_writelane_b32 v4, s39, 5
+; GFX9-NEXT: v_writelane_b32 v4, s48, 6
+; GFX9-NEXT: v_writelane_b32 v4, s49, 7
+; GFX9-NEXT: v_writelane_b32 v4, s50, 8
+; GFX9-NEXT: v_writelane_b32 v4, s51, 9
+; GFX9-NEXT: v_writelane_b32 v4, s52, 10
+; GFX9-NEXT: v_writelane_b32 v4, s53, 11
+; GFX9-NEXT: v_writelane_b32 v4, s54, 12
+; GFX9-NEXT: v_writelane_b32 v4, s55, 13
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; GFX9-NEXT: v_writelane_b32 v4, s54, 14
+; GFX9-NEXT: v_writelane_b32 v4, s30, 14
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: v_writelane_b32 v4, s55, 15
+; GFX9-NEXT: v_writelane_b32 v4, s31, 15
; GFX9-NEXT: s_cbranch_scc0 .LBB69_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
@@ -40180,23 +40180,23 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX9-NEXT: s_or_b32 s4, s4, s5
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_readlane_b32 s30, v4, 14
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_readlane_b32 s55, v4, 15
-; GFX9-NEXT: v_readlane_b32 s54, v4, 14
-; GFX9-NEXT: v_readlane_b32 s53, v4, 13
-; GFX9-NEXT: v_readlane_b32 s52, v4, 12
-; GFX9-NEXT: v_readlane_b32 s51, v4, 11
-; GFX9-NEXT: v_readlane_b32 s50, v4, 10
-; GFX9-NEXT: v_readlane_b32 s49, v4, 9
-; GFX9-NEXT: v_readlane_b32 s48, v4, 8
-; GFX9-NEXT: v_readlane_b32 s39, v4, 7
-; GFX9-NEXT: v_readlane_b32 s38, v4, 6
-; GFX9-NEXT: v_readlane_b32 s37, v4, 5
-; GFX9-NEXT: v_readlane_b32 s36, v4, 4
-; GFX9-NEXT: v_readlane_b32 s35, v4, 3
-; GFX9-NEXT: v_readlane_b32 s34, v4, 2
-; GFX9-NEXT: v_readlane_b32 s31, v4, 1
-; GFX9-NEXT: v_readlane_b32 s30, v4, 0
+; GFX9-NEXT: v_readlane_b32 s31, v4, 15
+; GFX9-NEXT: v_readlane_b32 s55, v4, 13
+; GFX9-NEXT: v_readlane_b32 s54, v4, 12
+; GFX9-NEXT: v_readlane_b32 s53, v4, 11
+; GFX9-NEXT: v_readlane_b32 s52, v4, 10
+; GFX9-NEXT: v_readlane_b32 s51, v4, 9
+; GFX9-NEXT: v_readlane_b32 s50, v4, 8
+; GFX9-NEXT: v_readlane_b32 s49, v4, 7
+; GFX9-NEXT: v_readlane_b32 s48, v4, 6
+; GFX9-NEXT: v_readlane_b32 s39, v4, 5
+; GFX9-NEXT: v_readlane_b32 s38, v4, 4
+; GFX9-NEXT: v_readlane_b32 s37, v4, 3
+; GFX9-NEXT: v_readlane_b32 s36, v4, 2
+; GFX9-NEXT: v_readlane_b32 s35, v4, 1
+; GFX9-NEXT: v_readlane_b32 s34, v4, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -40259,17 +40259,17 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX11-NEXT: s_xor_saveexec_b32 s4, -1
; GFX11-NEXT: scratch_store_b32 off, v17, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v17, s30, 0
+; GFX11-NEXT: v_writelane_b32 v17, s34, 0
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
; GFX11-NEXT: s_mov_b32 vcc_lo, 0
-; GFX11-NEXT: v_writelane_b32 v17, s31, 1
-; GFX11-NEXT: v_writelane_b32 v17, s34, 2
-; GFX11-NEXT: v_writelane_b32 v17, s35, 3
-; GFX11-NEXT: v_writelane_b32 v17, s36, 4
-; GFX11-NEXT: v_writelane_b32 v17, s37, 5
-; GFX11-NEXT: v_writelane_b32 v17, s38, 6
-; GFX11-NEXT: v_writelane_b32 v17, s39, 7
-; GFX11-NEXT: v_writelane_b32 v17, s48, 8
+; GFX11-NEXT: v_writelane_b32 v17, s35, 1
+; GFX11-NEXT: v_writelane_b32 v17, s36, 2
+; GFX11-NEXT: v_writelane_b32 v17, s37, 3
+; GFX11-NEXT: v_writelane_b32 v17, s38, 4
+; GFX11-NEXT: v_writelane_b32 v17, s39, 5
+; GFX11-NEXT: v_writelane_b32 v17, s48, 6
+; GFX11-NEXT: v_writelane_b32 v17, s30, 7
+; GFX11-NEXT: v_writelane_b32 v17, s31, 8
; GFX11-NEXT: s_cbranch_scc0 .LBB69_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s27, 24
@@ -40540,20 +40540,20 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX11-NEXT: s_or_b32 s3, s4, s5
; GFX11-NEXT: v_dual_mov_b32 v13, s0 :: v_dual_mov_b32 v14, s1
; GFX11-NEXT: v_dual_mov_b32 v15, s2 :: v_dual_mov_b32 v16, s3
+; GFX11-NEXT: v_readlane_b32 s30, v17, 7
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
-; GFX11-NEXT: v_readlane_b32 s48, v17, 8
-; GFX11-NEXT: v_readlane_b32 s39, v17, 7
-; GFX11-NEXT: v_readlane_b32 s38, v17, 6
-; GFX11-NEXT: v_readlane_b32 s37, v17, 5
-; GFX11-NEXT: v_readlane_b32 s36, v17, 4
-; GFX11-NEXT: v_readlane_b32 s35, v17, 3
-; GFX11-NEXT: v_readlane_b32 s34, v17, 2
-; GFX11-NEXT: v_readlane_b32 s31, v17, 1
-; GFX11-NEXT: v_readlane_b32 s30, v17, 0
+; GFX11-NEXT: v_readlane_b32 s31, v17, 8
+; GFX11-NEXT: v_readlane_b32 s48, v17, 6
+; GFX11-NEXT: v_readlane_b32 s39, v17, 5
+; GFX11-NEXT: v_readlane_b32 s38, v17, 4
+; GFX11-NEXT: v_readlane_b32 s37, v17, 3
+; GFX11-NEXT: v_readlane_b32 s36, v17, 2
+; GFX11-NEXT: v_readlane_b32 s35, v17, 1
+; GFX11-NEXT: v_readlane_b32 s34, v17, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v17, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
@@ -49741,8 +49741,8 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_mov_b32_e32 v15, s31
; VI-NEXT: .LBB83_5: ; %end
-; VI-NEXT: v_readlane_b32 s31, v19, 1
; VI-NEXT: v_readlane_b32 s30, v19, 0
+; VI-NEXT: v_readlane_b32 s31, v19, 1
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -50092,8 +50092,8 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; GFX9-NEXT: v_mov_b32_e32 v14, s30
; GFX9-NEXT: v_mov_b32_e32 v15, s31
; GFX9-NEXT: .LBB83_5: ; %end
-; GFX9-NEXT: v_readlane_b32 s31, v20, 1
; GFX9-NEXT: v_readlane_b32 s30, v20, 0
+; GFX9-NEXT: v_readlane_b32 s31, v20, 1
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -52416,42 +52416,42 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v40, s30, 0
-; SI-NEXT: v_writelane_b32 v40, s31, 1
-; SI-NEXT: v_writelane_b32 v40, s34, 2
-; SI-NEXT: v_writelane_b32 v40, s35, 3
-; SI-NEXT: v_writelane_b32 v40, s36, 4
-; SI-NEXT: v_writelane_b32 v40, s37, 5
-; SI-NEXT: v_writelane_b32 v40, s38, 6
-; SI-NEXT: v_writelane_b32 v40, s39, 7
-; SI-NEXT: v_writelane_b32 v40, s48, 8
-; SI-NEXT: v_writelane_b32 v40, s49, 9
-; SI-NEXT: v_writelane_b32 v40, s50, 10
-; SI-NEXT: v_writelane_b32 v40, s51, 11
-; SI-NEXT: v_writelane_b32 v40, s52, 12
-; SI-NEXT: v_writelane_b32 v40, s53, 13
-; SI-NEXT: v_writelane_b32 v40, s54, 14
-; SI-NEXT: v_writelane_b32 v40, s55, 15
-; SI-NEXT: v_writelane_b32 v40, s64, 16
-; SI-NEXT: v_writelane_b32 v40, s65, 17
-; SI-NEXT: v_writelane_b32 v40, s66, 18
-; SI-NEXT: v_writelane_b32 v40, s67, 19
-; SI-NEXT: v_writelane_b32 v40, s68, 20
-; SI-NEXT: v_writelane_b32 v40, s69, 21
-; SI-NEXT: v_writelane_b32 v40, s70, 22
-; SI-NEXT: v_writelane_b32 v40, s71, 23
-; SI-NEXT: v_writelane_b32 v40, s80, 24
-; SI-NEXT: v_writelane_b32 v40, s81, 25
-; SI-NEXT: v_writelane_b32 v40, s82, 26
-; SI-NEXT: v_writelane_b32 v40, s83, 27
-; SI-NEXT: v_writelane_b32 v40, s84, 28
-; SI-NEXT: v_writelane_b32 v40, s85, 29
+; SI-NEXT: v_writelane_b32 v40, s34, 0
+; SI-NEXT: v_writelane_b32 v40, s35, 1
+; SI-NEXT: v_writelane_b32 v40, s36, 2
+; SI-NEXT: v_writelane_b32 v40, s37, 3
+; SI-NEXT: v_writelane_b32 v40, s38, 4
+; SI-NEXT: v_writelane_b32 v40, s39, 5
+; SI-NEXT: v_writelane_b32 v40, s48, 6
+; SI-NEXT: v_writelane_b32 v40, s49, 7
+; SI-NEXT: v_writelane_b32 v40, s50, 8
+; SI-NEXT: v_writelane_b32 v40, s51, 9
+; SI-NEXT: v_writelane_b32 v40, s52, 10
+; SI-NEXT: v_writelane_b32 v40, s53, 11
+; SI-NEXT: v_writelane_b32 v40, s54, 12
+; SI-NEXT: v_writelane_b32 v40, s55, 13
+; SI-NEXT: v_writelane_b32 v40, s64, 14
+; SI-NEXT: v_writelane_b32 v40, s65, 15
+; SI-NEXT: v_writelane_b32 v40, s66, 16
+; SI-NEXT: v_writelane_b32 v40, s67, 17
+; SI-NEXT: v_writelane_b32 v40, s68, 18
+; SI-NEXT: v_writelane_b32 v40, s69, 19
+; SI-NEXT: v_writelane_b32 v40, s70, 20
+; SI-NEXT: v_writelane_b32 v40, s71, 21
+; SI-NEXT: v_writelane_b32 v40, s80, 22
+; SI-NEXT: v_writelane_b32 v40, s81, 23
+; SI-NEXT: v_writelane_b32 v40, s82, 24
+; SI-NEXT: v_writelane_b32 v40, s83, 25
+; SI-NEXT: v_writelane_b32 v40, s84, 26
+; SI-NEXT: v_writelane_b32 v40, s85, 27
+; SI-NEXT: v_writelane_b32 v40, s86, 28
+; SI-NEXT: v_writelane_b32 v40, s87, 29
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; SI-NEXT: v_writelane_b32 v40, s86, 30
+; SI-NEXT: v_writelane_b32 v40, s30, 30
; SI-NEXT: v_readfirstlane_b32 s4, v1
; SI-NEXT: s_and_b64 s[6:7], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v2
-; SI-NEXT: v_writelane_b32 v40, s87, 31
+; SI-NEXT: v_writelane_b32 v40, s31, 31
; SI-NEXT: s_cbranch_scc0 .LBB85_3
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s48, s5, 24
@@ -52850,39 +52850,39 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v40, 30
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s87, v40, 31
-; SI-NEXT: v_readlane_b32 s86, v40, 30
-; SI-NEXT: v_readlane_b32 s85, v40, 29
-; SI-NEXT: v_readlane_b32 s84, v40, 28
-; SI-NEXT: v_readlane_b32 s83, v40, 27
-; SI-NEXT: v_readlane_b32 s82, v40, 26
-; SI-NEXT: v_readlane_b32 s81, v40, 25
-; SI-NEXT: v_readlane_b32 s80, v40, 24
-; SI-NEXT: v_readlane_b32 s71, v40, 23
-; SI-NEXT: v_readlane_b32 s70, v40, 22
-; SI-NEXT: v_readlane_b32 s69, v40, 21
-; SI-NEXT: v_readlane_b32 s68, v40, 20
-; SI-NEXT: v_readlane_b32 s67, v40, 19
-; SI-NEXT: v_readlane_b32 s66, v40, 18
-; SI-NEXT: v_readlane_b32 s65, v40, 17
-; SI-NEXT: v_readlane_b32 s64, v40, 16
-; SI-NEXT: v_readlane_b32 s55, v40, 15
-; SI-NEXT: v_readlane_b32 s54, v40, 14
-; SI-NEXT: v_readlane_b32 s53, v40, 13
-; SI-NEXT: v_readlane_b32 s52, v40, 12
-; SI-NEXT: v_readlane_b32 s51, v40, 11
-; SI-NEXT: v_readlane_b32 s50, v40, 10
-; SI-NEXT: v_readlane_b32 s49, v40, 9
-; SI-NEXT: v_readlane_b32 s48, v40, 8
-; SI-NEXT: v_readlane_b32 s39, v40, 7
-; SI-NEXT: v_readlane_b32 s38, v40, 6
-; SI-NEXT: v_readlane_b32 s37, v40, 5
-; SI-NEXT: v_readlane_b32 s36, v40, 4
-; SI-NEXT: v_readlane_b32 s35, v40, 3
-; SI-NEXT: v_readlane_b32 s34, v40, 2
-; SI-NEXT: v_readlane_b32 s31, v40, 1
-; SI-NEXT: v_readlane_b32 s30, v40, 0
+; SI-NEXT: v_readlane_b32 s31, v40, 31
+; SI-NEXT: v_readlane_b32 s87, v40, 29
+; SI-NEXT: v_readlane_b32 s86, v40, 28
+; SI-NEXT: v_readlane_b32 s85, v40, 27
+; SI-NEXT: v_readlane_b32 s84, v40, 26
+; SI-NEXT: v_readlane_b32 s83, v40, 25
+; SI-NEXT: v_readlane_b32 s82, v40, 24
+; SI-NEXT: v_readlane_b32 s81, v40, 23
+; SI-NEXT: v_readlane_b32 s80, v40, 22
+; SI-NEXT: v_readlane_b32 s71, v40, 21
+; SI-NEXT: v_readlane_b32 s70, v40, 20
+; SI-NEXT: v_readlane_b32 s69, v40, 19
+; SI-NEXT: v_readlane_b32 s68, v40, 18
+; SI-NEXT: v_readlane_b32 s67, v40, 17
+; SI-NEXT: v_readlane_b32 s66, v40, 16
+; SI-NEXT: v_readlane_b32 s65, v40, 15
+; SI-NEXT: v_readlane_b32 s64, v40, 14
+; SI-NEXT: v_readlane_b32 s55, v40, 13
+; SI-NEXT: v_readlane_b32 s54, v40, 12
+; SI-NEXT: v_readlane_b32 s53, v40, 11
+; SI-NEXT: v_readlane_b32 s52, v40, 10
+; SI-NEXT: v_readlane_b32 s51, v40, 9
+; SI-NEXT: v_readlane_b32 s50, v40, 8
+; SI-NEXT: v_readlane_b32 s49, v40, 7
+; SI-NEXT: v_readlane_b32 s48, v40, 6
+; SI-NEXT: v_readlane_b32 s39, v40, 5
+; SI-NEXT: v_readlane_b32 s38, v40, 4
+; SI-NEXT: v_readlane_b32 s37, v40, 3
+; SI-NEXT: v_readlane_b32 s36, v40, 2
+; SI-NEXT: v_readlane_b32 s35, v40, 1
+; SI-NEXT: v_readlane_b32 s34, v40, 0
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
@@ -52895,30 +52895,30 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v40, s30, 0
-; VI-NEXT: v_writelane_b32 v40, s31, 1
-; VI-NEXT: v_writelane_b32 v40, s34, 2
-; VI-NEXT: v_writelane_b32 v40, s35, 3
-; VI-NEXT: v_writelane_b32 v40, s36, 4
-; VI-NEXT: v_writelane_b32 v40, s37, 5
-; VI-NEXT: v_writelane_b32 v40, s38, 6
-; VI-NEXT: v_writelane_b32 v40, s39, 7
-; VI-NEXT: v_writelane_b32 v40, s48, 8
-; VI-NEXT: v_writelane_b32 v40, s49, 9
-; VI-NEXT: v_writelane_b32 v40, s50, 10
-; VI-NEXT: v_writelane_b32 v40, s51, 11
-; VI-NEXT: v_writelane_b32 v40, s52, 12
-; VI-NEXT: v_writelane_b32 v40, s53, 13
-; VI-NEXT: v_writelane_b32 v40, s54, 14
-; VI-NEXT: v_writelane_b32 v40, s55, 15
-; VI-NEXT: v_writelane_b32 v40, s64, 16
-; VI-NEXT: v_writelane_b32 v40, s65, 17
+; VI-NEXT: v_writelane_b32 v40, s34, 0
+; VI-NEXT: v_writelane_b32 v40, s35, 1
+; VI-NEXT: v_writelane_b32 v40, s36, 2
+; VI-NEXT: v_writelane_b32 v40, s37, 3
+; VI-NEXT: v_writelane_b32 v40, s38, 4
+; VI-NEXT: v_writelane_b32 v40, s39, 5
+; VI-NEXT: v_writelane_b32 v40, s48, 6
+; VI-NEXT: v_writelane_b32 v40, s49, 7
+; VI-NEXT: v_writelane_b32 v40, s50, 8
+; VI-NEXT: v_writelane_b32 v40, s51, 9
+; VI-NEXT: v_writelane_b32 v40, s52, 10
+; VI-NEXT: v_writelane_b32 v40, s53, 11
+; VI-NEXT: v_writelane_b32 v40, s54, 12
+; VI-NEXT: v_writelane_b32 v40, s55, 13
+; VI-NEXT: v_writelane_b32 v40, s64, 14
+; VI-NEXT: v_writelane_b32 v40, s65, 15
+; VI-NEXT: v_writelane_b32 v40, s66, 16
+; VI-NEXT: v_writelane_b32 v40, s67, 17
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; VI-NEXT: v_writelane_b32 v40, s66, 18
+; VI-NEXT: v_writelane_b32 v40, s30, 18
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
-; VI-NEXT: v_writelane_b32 v40, s67, 19
+; VI-NEXT: v_writelane_b32 v40, s31, 19
; VI-NEXT: s_cbranch_scc0 .LBB85_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s56, s5, 24
@@ -53270,27 +53270,27 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: v_mov_b32_e32 v1, s4
+; VI-NEXT: v_readlane_b32 s30, v40, 18
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT: v_readlane_b32 s67, v40, 19
-; VI-NEXT: v_readlane_b32 s66, v40, 18
-; VI-NEXT: v_readlane_b32 s65, v40, 17
-; VI-NEXT: v_readlane_b32 s64, v40, 16
-; VI-NEXT: v_readlane_b32 s55, v40, 15
-; VI-NEXT: v_readlane_b32 s54, v40, 14
-; VI-NEXT: v_readlane_b32 s53, v40, 13
-; VI-NEXT: v_readlane_b32 s52, v40, 12
-; VI-NEXT: v_readlane_b32 s51, v40, 11
-; VI-NEXT: v_readlane_b32 s50, v40, 10
-; VI-NEXT: v_readlane_b32 s49, v40, 9
-; VI-NEXT: v_readlane_b32 s48, v40, 8
-; VI-NEXT: v_readlane_b32 s39, v40, 7
-; VI-NEXT: v_readlane_b32 s38, v40, 6
-; VI-NEXT: v_readlane_b32 s37, v40, 5
-; VI-NEXT: v_readlane_b32 s36, v40, 4
-; VI-NEXT: v_readlane_b32 s35, v40, 3
-; VI-NEXT: v_readlane_b32 s34, v40, 2
-; VI-NEXT: v_readlane_b32 s31, v40, 1
-; VI-NEXT: v_readlane_b32 s30, v40, 0
+; VI-NEXT: v_readlane_b32 s31, v40, 19
+; VI-NEXT: v_readlane_b32 s67, v40, 17
+; VI-NEXT: v_readlane_b32 s66, v40, 16
+; VI-NEXT: v_readlane_b32 s65, v40, 15
+; VI-NEXT: v_readlane_b32 s64, v40, 14
+; VI-NEXT: v_readlane_b32 s55, v40, 13
+; VI-NEXT: v_readlane_b32 s54, v40, 12
+; VI-NEXT: v_readlane_b32 s53, v40, 11
+; VI-NEXT: v_readlane_b32 s52, v40, 10
+; VI-NEXT: v_readlane_b32 s51, v40, 9
+; VI-NEXT: v_readlane_b32 s50, v40, 8
+; VI-NEXT: v_readlane_b32 s49, v40, 7
+; VI-NEXT: v_readlane_b32 s48, v40, 6
+; VI-NEXT: v_readlane_b32 s39, v40, 5
+; VI-NEXT: v_readlane_b32 s38, v40, 4
+; VI-NEXT: v_readlane_b32 s37, v40, 3
+; VI-NEXT: v_readlane_b32 s36, v40, 2
+; VI-NEXT: v_readlane_b32 s35, v40, 1
+; VI-NEXT: v_readlane_b32 s34, v40, 0
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -53303,26 +53303,26 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: v_writelane_b32 v40, s35, 3
-; GFX9-NEXT: v_writelane_b32 v40, s36, 4
-; GFX9-NEXT: v_writelane_b32 v40, s37, 5
-; GFX9-NEXT: v_writelane_b32 v40, s38, 6
-; GFX9-NEXT: v_writelane_b32 v40, s39, 7
-; GFX9-NEXT: v_writelane_b32 v40, s48, 8
-; GFX9-NEXT: v_writelane_b32 v40, s49, 9
-; GFX9-NEXT: v_writelane_b32 v40, s50, 10
-; GFX9-NEXT: v_writelane_b32 v40, s51, 11
-; GFX9-NEXT: v_writelane_b32 v40, s52, 12
-; GFX9-NEXT: v_writelane_b32 v40, s53, 13
+; GFX9-NEXT: v_writelane_b32 v40, s34, 0
+; GFX9-NEXT: v_writelane_b32 v40, s35, 1
+; GFX9-NEXT: v_writelane_b32 v40, s36, 2
+; GFX9-NEXT: v_writelane_b32 v40, s37, 3
+; GFX9-NEXT: v_writelane_b32 v40, s38, 4
+; GFX9-NEXT: v_writelane_b32 v40, s39, 5
+; GFX9-NEXT: v_writelane_b32 v40, s48, 6
+; GFX9-NEXT: v_writelane_b32 v40, s49, 7
+; GFX9-NEXT: v_writelane_b32 v40, s50, 8
+; GFX9-NEXT: v_writelane_b32 v40, s51, 9
+; GFX9-NEXT: v_writelane_b32 v40, s52, 10
+; GFX9-NEXT: v_writelane_b32 v40, s53, 11
+; GFX9-NEXT: v_writelane_b32 v40, s54, 12
+; GFX9-NEXT: v_writelane_b32 v40, s55, 13
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; GFX9-NEXT: v_writelane_b32 v40, s54, 14
+; GFX9-NEXT: v_writelane_b32 v40, s30, 14
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: v_writelane_b32 v40, s55, 15
+; GFX9-NEXT: v_writelane_b32 v40, s31, 15
; GFX9-NEXT: s_cbranch_scc0 .LBB85_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
@@ -53659,23 +53659,23 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX9-NEXT: s_or_b32 s4, s4, s5
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_readlane_b32 s30, v40, 14
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_readlane_b32 s55, v40, 15
-; GFX9-NEXT: v_readlane_b32 s54, v40, 14
-; GFX9-NEXT: v_readlane_b32 s53, v40, 13
-; GFX9-NEXT: v_readlane_b32 s52, v40, 12
-; GFX9-NEXT: v_readlane_b32 s51, v40, 11
-; GFX9-NEXT: v_readlane_b32 s50, v40, 10
-; GFX9-NEXT: v_readlane_b32 s49, v40, 9
-; GFX9-NEXT: v_readlane_b32 s48, v40, 8
-; GFX9-NEXT: v_readlane_b32 s39, v40, 7
-; GFX9-NEXT: v_readlane_b32 s38, v40, 6
-; GFX9-NEXT: v_readlane_b32 s37, v40, 5
-; GFX9-NEXT: v_readlane_b32 s36, v40, 4
-; GFX9-NEXT: v_readlane_b32 s35, v40, 3
-; GFX9-NEXT: v_readlane_b32 s34, v40, 2
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
-; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 15
+; GFX9-NEXT: v_readlane_b32 s55, v40, 13
+; GFX9-NEXT: v_readlane_b32 s54, v40, 12
+; GFX9-NEXT: v_readlane_b32 s53, v40, 11
+; GFX9-NEXT: v_readlane_b32 s52, v40, 10
+; GFX9-NEXT: v_readlane_b32 s51, v40, 9
+; GFX9-NEXT: v_readlane_b32 s50, v40, 8
+; GFX9-NEXT: v_readlane_b32 s49, v40, 7
+; GFX9-NEXT: v_readlane_b32 s48, v40, 6
+; GFX9-NEXT: v_readlane_b32 s39, v40, 5
+; GFX9-NEXT: v_readlane_b32 s38, v40, 4
+; GFX9-NEXT: v_readlane_b32 s37, v40, 3
+; GFX9-NEXT: v_readlane_b32 s36, v40, 2
+; GFX9-NEXT: v_readlane_b32 s35, v40, 1
+; GFX9-NEXT: v_readlane_b32 s34, v40, 0
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -53688,18 +53688,18 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX11-NEXT: s_xor_saveexec_b32 s4, -1
; GFX11-NEXT: scratch_store_b32 off, v33, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v33, s30, 0
+; GFX11-NEXT: v_writelane_b32 v33, s34, 0
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
; GFX11-NEXT: s_mov_b32 s90, 0
-; GFX11-NEXT: v_writelane_b32 v33, s31, 1
-; GFX11-NEXT: v_writelane_b32 v33, s34, 2
-; GFX11-NEXT: v_writelane_b32 v33, s35, 3
-; GFX11-NEXT: v_writelane_b32 v33, s36, 4
-; GFX11-NEXT: v_writelane_b32 v33, s37, 5
-; GFX11-NEXT: v_writelane_b32 v33, s38, 6
-; GFX11-NEXT: v_writelane_b32 v33, s39, 7
-; GFX11-NEXT: v_writelane_b32 v33, s48, 8
-; GFX11-NEXT: v_writelane_b32 v33, s49, 9
+; GFX11-NEXT: v_writelane_b32 v33, s35, 1
+; GFX11-NEXT: v_writelane_b32 v33, s36, 2
+; GFX11-NEXT: v_writelane_b32 v33, s37, 3
+; GFX11-NEXT: v_writelane_b32 v33, s38, 4
+; GFX11-NEXT: v_writelane_b32 v33, s39, 5
+; GFX11-NEXT: v_writelane_b32 v33, s48, 6
+; GFX11-NEXT: v_writelane_b32 v33, s49, 7
+; GFX11-NEXT: v_writelane_b32 v33, s30, 8
+; GFX11-NEXT: v_writelane_b32 v33, s31, 9
; GFX11-NEXT: s_cbranch_scc0 .LBB85_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s27, 24
@@ -54037,21 +54037,21 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX11-NEXT: v_or_b32_e32 v3, v3, v2
; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: v_mov_b32_e32 v4, s1
+; GFX11-NEXT: v_readlane_b32 s30, v33, 8
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[22:25], off
; GFX11-NEXT: scratch_store_b128 v0, v[14:17], off offset:16
; GFX11-NEXT: scratch_store_b128 v0, v[10:13], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48
-; GFX11-NEXT: v_readlane_b32 s49, v33, 9
-; GFX11-NEXT: v_readlane_b32 s48, v33, 8
-; GFX11-NEXT: v_readlane_b32 s39, v33, 7
-; GFX11-NEXT: v_readlane_b32 s38, v33, 6
-; GFX11-NEXT: v_readlane_b32 s37, v33, 5
-; GFX11-NEXT: v_readlane_b32 s36, v33, 4
-; GFX11-NEXT: v_readlane_b32 s35, v33, 3
-; GFX11-NEXT: v_readlane_b32 s34, v33, 2
-; GFX11-NEXT: v_readlane_b32 s31, v33, 1
-; GFX11-NEXT: v_readlane_b32 s30, v33, 0
+; GFX11-NEXT: v_readlane_b32 s31, v33, 9
+; GFX11-NEXT: v_readlane_b32 s49, v33, 7
+; GFX11-NEXT: v_readlane_b32 s48, v33, 6
+; GFX11-NEXT: v_readlane_b32 s39, v33, 5
+; GFX11-NEXT: v_readlane_b32 s38, v33, 4
+; GFX11-NEXT: v_readlane_b32 s37, v33, 3
+; GFX11-NEXT: v_readlane_b32 s36, v33, 2
+; GFX11-NEXT: v_readlane_b32 s35, v33, 1
+; GFX11-NEXT: v_readlane_b32 s34, v33, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v33, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
@@ -62566,8 +62566,8 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_mov_b32_e32 v15, s31
; VI-NEXT: .LBB95_5: ; %end
-; VI-NEXT: v_readlane_b32 s31, v20, 1
; VI-NEXT: v_readlane_b32 s30, v20, 0
+; VI-NEXT: v_readlane_b32 s31, v20, 1
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -62901,8 +62901,8 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; GFX9-NEXT: v_mov_b32_e32 v14, s30
; GFX9-NEXT: v_mov_b32_e32 v15, s31
; GFX9-NEXT: .LBB95_5: ; %end
-; GFX9-NEXT: v_readlane_b32 s31, v20, 1
; GFX9-NEXT: v_readlane_b32 s30, v20, 0
+; GFX9-NEXT: v_readlane_b32 s31, v20, 1
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -65725,43 +65725,43 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_writelane_b32 v20, s30, 0
-; SI-NEXT: v_writelane_b32 v20, s31, 1
-; SI-NEXT: v_writelane_b32 v20, s34, 2
-; SI-NEXT: v_writelane_b32 v20, s35, 3
-; SI-NEXT: v_writelane_b32 v20, s36, 4
-; SI-NEXT: v_writelane_b32 v20, s37, 5
-; SI-NEXT: v_writelane_b32 v20, s38, 6
-; SI-NEXT: v_writelane_b32 v20, s39, 7
-; SI-NEXT: v_writelane_b32 v20, s48, 8
-; SI-NEXT: v_writelane_b32 v20, s49, 9
-; SI-NEXT: v_writelane_b32 v20, s50, 10
-; SI-NEXT: v_writelane_b32 v20, s51, 11
-; SI-NEXT: v_writelane_b32 v20, s52, 12
-; SI-NEXT: v_writelane_b32 v20, s53, 13
-; SI-NEXT: v_writelane_b32 v20, s54, 14
-; SI-NEXT: v_writelane_b32 v20, s55, 15
-; SI-NEXT: v_writelane_b32 v20, s64, 16
-; SI-NEXT: v_writelane_b32 v20, s65, 17
-; SI-NEXT: v_writelane_b32 v20, s66, 18
-; SI-NEXT: v_writelane_b32 v20, s67, 19
-; SI-NEXT: v_writelane_b32 v20, s68, 20
-; SI-NEXT: v_writelane_b32 v20, s69, 21
-; SI-NEXT: v_writelane_b32 v20, s70, 22
-; SI-NEXT: v_writelane_b32 v20, s71, 23
-; SI-NEXT: v_writelane_b32 v20, s80, 24
-; SI-NEXT: v_writelane_b32 v20, s81, 25
-; SI-NEXT: v_writelane_b32 v20, s82, 26
-; SI-NEXT: v_writelane_b32 v20, s83, 27
-; SI-NEXT: v_writelane_b32 v20, s84, 28
-; SI-NEXT: v_writelane_b32 v20, s85, 29
-; SI-NEXT: v_writelane_b32 v20, s86, 30
-; SI-NEXT: v_writelane_b32 v20, s87, 31
-; SI-NEXT: v_writelane_b32 v20, s96, 32
-; SI-NEXT: v_writelane_b32 v20, s97, 33
-; SI-NEXT: v_writelane_b32 v20, s98, 34
+; SI-NEXT: v_writelane_b32 v20, s34, 0
+; SI-NEXT: v_writelane_b32 v20, s35, 1
+; SI-NEXT: v_writelane_b32 v20, s36, 2
+; SI-NEXT: v_writelane_b32 v20, s37, 3
+; SI-NEXT: v_writelane_b32 v20, s38, 4
+; SI-NEXT: v_writelane_b32 v20, s39, 5
+; SI-NEXT: v_writelane_b32 v20, s48, 6
+; SI-NEXT: v_writelane_b32 v20, s49, 7
+; SI-NEXT: v_writelane_b32 v20, s50, 8
+; SI-NEXT: v_writelane_b32 v20, s51, 9
+; SI-NEXT: v_writelane_b32 v20, s52, 10
+; SI-NEXT: v_writelane_b32 v20, s53, 11
+; SI-NEXT: v_writelane_b32 v20, s54, 12
+; SI-NEXT: v_writelane_b32 v20, s55, 13
+; SI-NEXT: v_writelane_b32 v20, s64, 14
+; SI-NEXT: v_writelane_b32 v20, s65, 15
+; SI-NEXT: v_writelane_b32 v20, s66, 16
+; SI-NEXT: v_writelane_b32 v20, s67, 17
+; SI-NEXT: v_writelane_b32 v20, s68, 18
+; SI-NEXT: v_writelane_b32 v20, s69, 19
+; SI-NEXT: v_writelane_b32 v20, s70, 20
+; SI-NEXT: v_writelane_b32 v20, s71, 21
+; SI-NEXT: v_writelane_b32 v20, s80, 22
+; SI-NEXT: v_writelane_b32 v20, s81, 23
+; SI-NEXT: v_writelane_b32 v20, s82, 24
+; SI-NEXT: v_writelane_b32 v20, s83, 25
+; SI-NEXT: v_writelane_b32 v20, s84, 26
+; SI-NEXT: v_writelane_b32 v20, s85, 27
+; SI-NEXT: v_writelane_b32 v20, s86, 28
+; SI-NEXT: v_writelane_b32 v20, s87, 29
+; SI-NEXT: v_writelane_b32 v20, s96, 30
+; SI-NEXT: v_writelane_b32 v20, s97, 31
+; SI-NEXT: v_writelane_b32 v20, s98, 32
+; SI-NEXT: v_writelane_b32 v20, s99, 33
+; SI-NEXT: v_writelane_b32 v20, s30, 34
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_writelane_b32 v20, s99, 35
+; SI-NEXT: v_writelane_b32 v20, s31, 35
; SI-NEXT: s_mov_b32 s93, s18
; SI-NEXT: s_mov_b32 s31, s17
; SI-NEXT: v_readfirstlane_b32 s59, v18
@@ -66280,45 +66280,45 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v20, 34
; SI-NEXT: v_readlane_b32 s19, v21, 11
; SI-NEXT: v_readlane_b32 s17, v21, 17
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s99, v20, 35
-; SI-NEXT: v_readlane_b32 s98, v20, 34
-; SI-NEXT: v_readlane_b32 s97, v20, 33
-; SI-NEXT: v_readlane_b32 s96, v20, 32
-; SI-NEXT: v_readlane_b32 s87, v20, 31
-; SI-NEXT: v_readlane_b32 s86, v20, 30
-; SI-NEXT: v_readlane_b32 s85, v20, 29
-; SI-NEXT: v_readlane_b32 s84, v20, 28
-; SI-NEXT: v_readlane_b32 s83, v20, 27
-; SI-NEXT: v_readlane_b32 s82, v20, 26
-; SI-NEXT: v_readlane_b32 s81, v20, 25
-; SI-NEXT: v_readlane_b32 s80, v20, 24
-; SI-NEXT: v_readlane_b32 s71, v20, 23
-; SI-NEXT: v_readlane_b32 s70, v20, 22
-; SI-NEXT: v_readlane_b32 s69, v20, 21
-; SI-NEXT: v_readlane_b32 s68, v20, 20
-; SI-NEXT: v_readlane_b32 s67, v20, 19
-; SI-NEXT: v_readlane_b32 s66, v20, 18
-; SI-NEXT: v_readlane_b32 s65, v20, 17
-; SI-NEXT: v_readlane_b32 s64, v20, 16
-; SI-NEXT: v_readlane_b32 s55, v20, 15
-; SI-NEXT: v_readlane_b32 s54, v20, 14
-; SI-NEXT: v_readlane_b32 s53, v20, 13
-; SI-NEXT: v_readlane_b32 s52, v20, 12
-; SI-NEXT: v_readlane_b32 s51, v20, 11
-; SI-NEXT: v_readlane_b32 s50, v20, 10
-; SI-NEXT: v_readlane_b32 s49, v20, 9
-; SI-NEXT: v_readlane_b32 s48, v20, 8
-; SI-NEXT: v_readlane_b32 s39, v20, 7
-; SI-NEXT: v_readlane_b32 s38, v20, 6
-; SI-NEXT: v_readlane_b32 s37, v20, 5
-; SI-NEXT: v_readlane_b32 s36, v20, 4
-; SI-NEXT: v_readlane_b32 s35, v20, 3
-; SI-NEXT: v_readlane_b32 s34, v20, 2
-; SI-NEXT: v_readlane_b32 s31, v20, 1
-; SI-NEXT: v_readlane_b32 s30, v20, 0
+; SI-NEXT: v_readlane_b32 s31, v20, 35
+; SI-NEXT: v_readlane_b32 s99, v20, 33
+; SI-NEXT: v_readlane_b32 s98, v20, 32
+; SI-NEXT: v_readlane_b32 s97, v20, 31
+; SI-NEXT: v_readlane_b32 s96, v20, 30
+; SI-NEXT: v_readlane_b32 s87, v20, 29
+; SI-NEXT: v_readlane_b32 s86, v20, 28
+; SI-NEXT: v_readlane_b32 s85, v20, 27
+; SI-NEXT: v_readlane_b32 s84, v20, 26
+; SI-NEXT: v_readlane_b32 s83, v20, 25
+; SI-NEXT: v_readlane_b32 s82, v20, 24
+; SI-NEXT: v_readlane_b32 s81, v20, 23
+; SI-NEXT: v_readlane_b32 s80, v20, 22
+; SI-NEXT: v_readlane_b32 s71, v20, 21
+; SI-NEXT: v_readlane_b32 s70, v20, 20
+; SI-NEXT: v_readlane_b32 s69, v20, 19
+; SI-NEXT: v_readlane_b32 s68, v20, 18
+; SI-NEXT: v_readlane_b32 s67, v20, 17
+; SI-NEXT: v_readlane_b32 s66, v20, 16
+; SI-NEXT: v_readlane_b32 s65, v20, 15
+; SI-NEXT: v_readlane_b32 s64, v20, 14
+; SI-NEXT: v_readlane_b32 s55, v20, 13
+; SI-NEXT: v_readlane_b32 s54, v20, 12
+; SI-NEXT: v_readlane_b32 s53, v20, 11
+; SI-NEXT: v_readlane_b32 s52, v20, 10
+; SI-NEXT: v_readlane_b32 s51, v20, 9
+; SI-NEXT: v_readlane_b32 s50, v20, 8
+; SI-NEXT: v_readlane_b32 s49, v20, 7
+; SI-NEXT: v_readlane_b32 s48, v20, 6
+; SI-NEXT: v_readlane_b32 s39, v20, 5
+; SI-NEXT: v_readlane_b32 s38, v20, 4
+; SI-NEXT: v_readlane_b32 s37, v20, 3
+; SI-NEXT: v_readlane_b32 s36, v20, 2
+; SI-NEXT: v_readlane_b32 s35, v20, 1
+; SI-NEXT: v_readlane_b32 s34, v20, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -66409,30 +66409,30 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v4, s30, 0
-; VI-NEXT: v_writelane_b32 v4, s31, 1
-; VI-NEXT: v_writelane_b32 v4, s34, 2
-; VI-NEXT: v_writelane_b32 v4, s35, 3
-; VI-NEXT: v_writelane_b32 v4, s36, 4
-; VI-NEXT: v_writelane_b32 v4, s37, 5
-; VI-NEXT: v_writelane_b32 v4, s38, 6
-; VI-NEXT: v_writelane_b32 v4, s39, 7
-; VI-NEXT: v_writelane_b32 v4, s48, 8
-; VI-NEXT: v_writelane_b32 v4, s49, 9
-; VI-NEXT: v_writelane_b32 v4, s50, 10
-; VI-NEXT: v_writelane_b32 v4, s51, 11
-; VI-NEXT: v_writelane_b32 v4, s52, 12
-; VI-NEXT: v_writelane_b32 v4, s53, 13
-; VI-NEXT: v_writelane_b32 v4, s54, 14
-; VI-NEXT: v_writelane_b32 v4, s55, 15
-; VI-NEXT: v_writelane_b32 v4, s64, 16
-; VI-NEXT: v_writelane_b32 v4, s65, 17
+; VI-NEXT: v_writelane_b32 v4, s34, 0
+; VI-NEXT: v_writelane_b32 v4, s35, 1
+; VI-NEXT: v_writelane_b32 v4, s36, 2
+; VI-NEXT: v_writelane_b32 v4, s37, 3
+; VI-NEXT: v_writelane_b32 v4, s38, 4
+; VI-NEXT: v_writelane_b32 v4, s39, 5
+; VI-NEXT: v_writelane_b32 v4, s48, 6
+; VI-NEXT: v_writelane_b32 v4, s49, 7
+; VI-NEXT: v_writelane_b32 v4, s50, 8
+; VI-NEXT: v_writelane_b32 v4, s51, 9
+; VI-NEXT: v_writelane_b32 v4, s52, 10
+; VI-NEXT: v_writelane_b32 v4, s53, 11
+; VI-NEXT: v_writelane_b32 v4, s54, 12
+; VI-NEXT: v_writelane_b32 v4, s55, 13
+; VI-NEXT: v_writelane_b32 v4, s64, 14
+; VI-NEXT: v_writelane_b32 v4, s65, 15
+; VI-NEXT: v_writelane_b32 v4, s66, 16
+; VI-NEXT: v_writelane_b32 v4, s67, 17
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; VI-NEXT: v_writelane_b32 v4, s66, 18
+; VI-NEXT: v_writelane_b32 v4, s30, 18
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
-; VI-NEXT: v_writelane_b32 v4, s67, 19
+; VI-NEXT: v_writelane_b32 v4, s31, 19
; VI-NEXT: s_cbranch_scc0 .LBB97_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s56, s5, 24
@@ -66804,27 +66804,27 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: v_mov_b32_e32 v1, s4
+; VI-NEXT: v_readlane_b32 s30, v4, 18
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; VI-NEXT: v_readlane_b32 s67, v4, 19
-; VI-NEXT: v_readlane_b32 s66, v4, 18
-; VI-NEXT: v_readlane_b32 s65, v4, 17
-; VI-NEXT: v_readlane_b32 s64, v4, 16
-; VI-NEXT: v_readlane_b32 s55, v4, 15
-; VI-NEXT: v_readlane_b32 s54, v4, 14
-; VI-NEXT: v_readlane_b32 s53, v4, 13
-; VI-NEXT: v_readlane_b32 s52, v4, 12
-; VI-NEXT: v_readlane_b32 s51, v4, 11
-; VI-NEXT: v_readlane_b32 s50, v4, 10
-; VI-NEXT: v_readlane_b32 s49, v4, 9
-; VI-NEXT: v_readlane_b32 s48, v4, 8
-; VI-NEXT: v_readlane_b32 s39, v4, 7
-; VI-NEXT: v_readlane_b32 s38, v4, 6
-; VI-NEXT: v_readlane_b32 s37, v4, 5
-; VI-NEXT: v_readlane_b32 s36, v4, 4
-; VI-NEXT: v_readlane_b32 s35, v4, 3
-; VI-NEXT: v_readlane_b32 s34, v4, 2
-; VI-NEXT: v_readlane_b32 s31, v4, 1
-; VI-NEXT: v_readlane_b32 s30, v4, 0
+; VI-NEXT: v_readlane_b32 s31, v4, 19
+; VI-NEXT: v_readlane_b32 s67, v4, 17
+; VI-NEXT: v_readlane_b32 s66, v4, 16
+; VI-NEXT: v_readlane_b32 s65, v4, 15
+; VI-NEXT: v_readlane_b32 s64, v4, 14
+; VI-NEXT: v_readlane_b32 s55, v4, 13
+; VI-NEXT: v_readlane_b32 s54, v4, 12
+; VI-NEXT: v_readlane_b32 s53, v4, 11
+; VI-NEXT: v_readlane_b32 s52, v4, 10
+; VI-NEXT: v_readlane_b32 s51, v4, 9
+; VI-NEXT: v_readlane_b32 s50, v4, 8
+; VI-NEXT: v_readlane_b32 s49, v4, 7
+; VI-NEXT: v_readlane_b32 s48, v4, 6
+; VI-NEXT: v_readlane_b32 s39, v4, 5
+; VI-NEXT: v_readlane_b32 s38, v4, 4
+; VI-NEXT: v_readlane_b32 s37, v4, 3
+; VI-NEXT: v_readlane_b32 s36, v4, 2
+; VI-NEXT: v_readlane_b32 s35, v4, 1
+; VI-NEXT: v_readlane_b32 s34, v4, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -66887,23 +66887,23 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v63, s30, 0
-; GFX9-NEXT: v_writelane_b32 v63, s31, 1
-; GFX9-NEXT: v_writelane_b32 v63, s34, 2
-; GFX9-NEXT: v_writelane_b32 v63, s35, 3
-; GFX9-NEXT: v_writelane_b32 v63, s36, 4
-; GFX9-NEXT: v_writelane_b32 v63, s37, 5
-; GFX9-NEXT: v_writelane_b32 v63, s38, 6
-; GFX9-NEXT: v_writelane_b32 v63, s39, 7
-; GFX9-NEXT: v_writelane_b32 v63, s48, 8
-; GFX9-NEXT: v_writelane_b32 v63, s49, 9
-; GFX9-NEXT: v_writelane_b32 v63, s50, 10
-; GFX9-NEXT: v_writelane_b32 v63, s51, 11
-; GFX9-NEXT: v_writelane_b32 v63, s52, 12
-; GFX9-NEXT: v_writelane_b32 v63, s53, 13
-; GFX9-NEXT: v_writelane_b32 v63, s54, 14
+; GFX9-NEXT: v_writelane_b32 v63, s34, 0
+; GFX9-NEXT: v_writelane_b32 v63, s35, 1
+; GFX9-NEXT: v_writelane_b32 v63, s36, 2
+; GFX9-NEXT: v_writelane_b32 v63, s37, 3
+; GFX9-NEXT: v_writelane_b32 v63, s38, 4
+; GFX9-NEXT: v_writelane_b32 v63, s39, 5
+; GFX9-NEXT: v_writelane_b32 v63, s48, 6
+; GFX9-NEXT: v_writelane_b32 v63, s49, 7
+; GFX9-NEXT: v_writelane_b32 v63, s50, 8
+; GFX9-NEXT: v_writelane_b32 v63, s51, 9
+; GFX9-NEXT: v_writelane_b32 v63, s52, 10
+; GFX9-NEXT: v_writelane_b32 v63, s53, 11
+; GFX9-NEXT: v_writelane_b32 v63, s54, 12
+; GFX9-NEXT: v_writelane_b32 v63, s55, 13
+; GFX9-NEXT: v_writelane_b32 v63, s30, 14
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; GFX9-NEXT: v_writelane_b32 v63, s55, 15
+; GFX9-NEXT: v_writelane_b32 v63, s31, 15
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
@@ -67243,22 +67243,22 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX9-NEXT: v_or_b32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s55, v63, 15
-; GFX9-NEXT: v_readlane_b32 s54, v63, 14
-; GFX9-NEXT: v_readlane_b32 s53, v63, 13
-; GFX9-NEXT: v_readlane_b32 s52, v63, 12
-; GFX9-NEXT: v_readlane_b32 s51, v63, 11
-; GFX9-NEXT: v_readlane_b32 s50, v63, 10
-; GFX9-NEXT: v_readlane_b32 s49, v63, 9
-; GFX9-NEXT: v_readlane_b32 s48, v63, 8
-; GFX9-NEXT: v_readlane_b32 s39, v63, 7
-; GFX9-NEXT: v_readlane_b32 s38, v63, 6
-; GFX9-NEXT: v_readlane_b32 s37, v63, 5
-; GFX9-NEXT: v_readlane_b32 s36, v63, 4
-; GFX9-NEXT: v_readlane_b32 s35, v63, 3
-; GFX9-NEXT: v_readlane_b32 s34, v63, 2
-; GFX9-NEXT: v_readlane_b32 s31, v63, 1
-; GFX9-NEXT: v_readlane_b32 s30, v63, 0
+; GFX9-NEXT: v_readlane_b32 s30, v63, 14
+; GFX9-NEXT: v_readlane_b32 s31, v63, 15
+; GFX9-NEXT: v_readlane_b32 s55, v63, 13
+; GFX9-NEXT: v_readlane_b32 s54, v63, 12
+; GFX9-NEXT: v_readlane_b32 s53, v63, 11
+; GFX9-NEXT: v_readlane_b32 s52, v63, 10
+; GFX9-NEXT: v_readlane_b32 s51, v63, 9
+; GFX9-NEXT: v_readlane_b32 s50, v63, 8
+; GFX9-NEXT: v_readlane_b32 s49, v63, 7
+; GFX9-NEXT: v_readlane_b32 s48, v63, 6
+; GFX9-NEXT: v_readlane_b32 s39, v63, 5
+; GFX9-NEXT: v_readlane_b32 s38, v63, 4
+; GFX9-NEXT: v_readlane_b32 s37, v63, 3
+; GFX9-NEXT: v_readlane_b32 s36, v63, 2
+; GFX9-NEXT: v_readlane_b32 s35, v63, 1
+; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v5, v33, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -67312,18 +67312,18 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX11-NEXT: s_or_saveexec_b32 s4, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s34, 0
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
; GFX11-NEXT: s_mov_b32 s42, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
-; GFX11-NEXT: v_writelane_b32 v40, s34, 2
-; GFX11-NEXT: v_writelane_b32 v40, s35, 3
-; GFX11-NEXT: v_writelane_b32 v40, s36, 4
-; GFX11-NEXT: v_writelane_b32 v40, s37, 5
-; GFX11-NEXT: v_writelane_b32 v40, s38, 6
-; GFX11-NEXT: v_writelane_b32 v40, s39, 7
-; GFX11-NEXT: v_writelane_b32 v40, s48, 8
-; GFX11-NEXT: v_writelane_b32 v40, s49, 9
+; GFX11-NEXT: v_writelane_b32 v40, s35, 1
+; GFX11-NEXT: v_writelane_b32 v40, s36, 2
+; GFX11-NEXT: v_writelane_b32 v40, s37, 3
+; GFX11-NEXT: v_writelane_b32 v40, s38, 4
+; GFX11-NEXT: v_writelane_b32 v40, s39, 5
+; GFX11-NEXT: v_writelane_b32 v40, s48, 6
+; GFX11-NEXT: v_writelane_b32 v40, s49, 7
+; GFX11-NEXT: v_writelane_b32 v40, s30, 8
+; GFX11-NEXT: v_writelane_b32 v40, s31, 9
; GFX11-NEXT: s_cbranch_scc0 .LBB97_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s43, s27, 24
@@ -67671,21 +67671,21 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX11-NEXT: v_or_b32_e32 v2, v4, v10
; GFX11-NEXT: v_or_b32_e32 v3, v11, v7
; GFX11-NEXT: v_or_b32_e32 v4, v12, v8
+; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[82:85], off
; GFX11-NEXT: scratch_store_b128 v0, v[23:26], off offset:16
; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48
-; GFX11-NEXT: v_readlane_b32 s49, v40, 9
-; GFX11-NEXT: v_readlane_b32 s48, v40, 8
-; GFX11-NEXT: v_readlane_b32 s39, v40, 7
-; GFX11-NEXT: v_readlane_b32 s38, v40, 6
-; GFX11-NEXT: v_readlane_b32 s37, v40, 5
-; GFX11-NEXT: v_readlane_b32 s36, v40, 4
-; GFX11-NEXT: v_readlane_b32 s35, v40, 3
-; GFX11-NEXT: v_readlane_b32 s34, v40, 2
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
-; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 9
+; GFX11-NEXT: v_readlane_b32 s49, v40, 7
+; GFX11-NEXT: v_readlane_b32 s48, v40, 6
+; GFX11-NEXT: v_readlane_b32 s39, v40, 5
+; GFX11-NEXT: v_readlane_b32 s38, v40, 4
+; GFX11-NEXT: v_readlane_b32 s37, v40, 3
+; GFX11-NEXT: v_readlane_b32 s36, v40, 2
+; GFX11-NEXT: v_readlane_b32 s35, v40, 1
+; GFX11-NEXT: v_readlane_b32 s34, v40, 0
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
@@ -75212,8 +75212,8 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_mov_b32_e32 v15, s31
; VI-NEXT: .LBB103_5: ; %end
-; VI-NEXT: v_readlane_b32 s31, v20, 1
; VI-NEXT: v_readlane_b32 s30, v20, 0
+; VI-NEXT: v_readlane_b32 s31, v20, 1
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -75563,8 +75563,8 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX9-NEXT: v_mov_b32_e32 v14, s30
; GFX9-NEXT: v_mov_b32_e32 v15, s31
; GFX9-NEXT: .LBB103_5: ; %end
-; GFX9-NEXT: v_readlane_b32 s31, v20, 1
; GFX9-NEXT: v_readlane_b32 s30, v20, 0
+; GFX9-NEXT: v_readlane_b32 s31, v20, 1
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -78293,8 +78293,8 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v40, s30, 0
-; SI-NEXT: v_writelane_b32 v40, s31, 1
+; SI-NEXT: v_writelane_b32 v40, s34, 0
+; SI-NEXT: v_writelane_b32 v40, s35, 1
; SI-NEXT: v_cvt_f16_f32_e32 v21, s17
; SI-NEXT: v_cvt_f16_f32_e32 v20, v2
; SI-NEXT: v_cvt_f16_f32_e32 v22, v1
@@ -78327,12 +78327,12 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: v_cvt_f16_f32_e32 v13, s26
; SI-NEXT: v_cvt_f16_f32_e32 v17, s29
; SI-NEXT: v_cvt_f16_f32_e32 v16, s28
-; SI-NEXT: v_writelane_b32 v40, s34, 2
-; SI-NEXT: v_writelane_b32 v40, s35, 3
+; SI-NEXT: v_writelane_b32 v40, s36, 2
+; SI-NEXT: v_writelane_b32 v40, s37, 3
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_writelane_b32 v40, s36, 4
+; SI-NEXT: v_writelane_b32 v40, s30, 4
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_writelane_b32 v40, s37, 5
+; SI-NEXT: v_writelane_b32 v40, s31, 5
; SI-NEXT: s_cbranch_scc0 .LBB105_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_readfirstlane_b32 s4, v21
@@ -78833,13 +78833,13 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v1, s4, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
+; SI-NEXT: v_readlane_b32 s30, v40, 4
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s37, v40, 5
-; SI-NEXT: v_readlane_b32 s36, v40, 4
-; SI-NEXT: v_readlane_b32 s35, v40, 3
-; SI-NEXT: v_readlane_b32 s34, v40, 2
-; SI-NEXT: v_readlane_b32 s31, v40, 1
-; SI-NEXT: v_readlane_b32 s30, v40, 0
+; SI-NEXT: v_readlane_b32 s31, v40, 5
+; SI-NEXT: v_readlane_b32 s37, v40, 3
+; SI-NEXT: v_readlane_b32 s36, v40, 2
+; SI-NEXT: v_readlane_b32 s35, v40, 1
+; SI-NEXT: v_readlane_b32 s34, v40, 0
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
@@ -78902,27 +78902,27 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v63, s30, 0
-; VI-NEXT: v_writelane_b32 v63, s31, 1
-; VI-NEXT: v_writelane_b32 v63, s34, 2
-; VI-NEXT: v_writelane_b32 v63, s35, 3
-; VI-NEXT: v_writelane_b32 v63, s36, 4
-; VI-NEXT: v_writelane_b32 v63, s37, 5
-; VI-NEXT: v_writelane_b32 v63, s38, 6
-; VI-NEXT: v_writelane_b32 v63, s39, 7
-; VI-NEXT: v_writelane_b32 v63, s48, 8
-; VI-NEXT: v_writelane_b32 v63, s49, 9
-; VI-NEXT: v_writelane_b32 v63, s50, 10
-; VI-NEXT: v_writelane_b32 v63, s51, 11
-; VI-NEXT: v_writelane_b32 v63, s52, 12
-; VI-NEXT: v_writelane_b32 v63, s53, 13
-; VI-NEXT: v_writelane_b32 v63, s54, 14
-; VI-NEXT: v_writelane_b32 v63, s55, 15
-; VI-NEXT: v_writelane_b32 v63, s64, 16
-; VI-NEXT: v_writelane_b32 v63, s65, 17
-; VI-NEXT: v_writelane_b32 v63, s66, 18
+; VI-NEXT: v_writelane_b32 v63, s34, 0
+; VI-NEXT: v_writelane_b32 v63, s35, 1
+; VI-NEXT: v_writelane_b32 v63, s36, 2
+; VI-NEXT: v_writelane_b32 v63, s37, 3
+; VI-NEXT: v_writelane_b32 v63, s38, 4
+; VI-NEXT: v_writelane_b32 v63, s39, 5
+; VI-NEXT: v_writelane_b32 v63, s48, 6
+; VI-NEXT: v_writelane_b32 v63, s49, 7
+; VI-NEXT: v_writelane_b32 v63, s50, 8
+; VI-NEXT: v_writelane_b32 v63, s51, 9
+; VI-NEXT: v_writelane_b32 v63, s52, 10
+; VI-NEXT: v_writelane_b32 v63, s53, 11
+; VI-NEXT: v_writelane_b32 v63, s54, 12
+; VI-NEXT: v_writelane_b32 v63, s55, 13
+; VI-NEXT: v_writelane_b32 v63, s64, 14
+; VI-NEXT: v_writelane_b32 v63, s65, 15
+; VI-NEXT: v_writelane_b32 v63, s66, 16
+; VI-NEXT: v_writelane_b32 v63, s67, 17
+; VI-NEXT: v_writelane_b32 v63, s30, 18
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; VI-NEXT: v_writelane_b32 v63, s67, 19
+; VI-NEXT: v_writelane_b32 v63, s31, 19
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
@@ -79320,26 +79320,26 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v54
; VI-NEXT: v_or_b32_sdwa v1, v49, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_readlane_b32 s67, v63, 19
-; VI-NEXT: v_readlane_b32 s66, v63, 18
-; VI-NEXT: v_readlane_b32 s65, v63, 17
-; VI-NEXT: v_readlane_b32 s64, v63, 16
-; VI-NEXT: v_readlane_b32 s55, v63, 15
-; VI-NEXT: v_readlane_b32 s54, v63, 14
-; VI-NEXT: v_readlane_b32 s53, v63, 13
-; VI-NEXT: v_readlane_b32 s52, v63, 12
-; VI-NEXT: v_readlane_b32 s51, v63, 11
-; VI-NEXT: v_readlane_b32 s50, v63, 10
-; VI-NEXT: v_readlane_b32 s49, v63, 9
-; VI-NEXT: v_readlane_b32 s48, v63, 8
-; VI-NEXT: v_readlane_b32 s39, v63, 7
-; VI-NEXT: v_readlane_b32 s38, v63, 6
-; VI-NEXT: v_readlane_b32 s37, v63, 5
-; VI-NEXT: v_readlane_b32 s36, v63, 4
-; VI-NEXT: v_readlane_b32 s35, v63, 3
-; VI-NEXT: v_readlane_b32 s34, v63, 2
-; VI-NEXT: v_readlane_b32 s31, v63, 1
-; VI-NEXT: v_readlane_b32 s30, v63, 0
+; VI-NEXT: v_readlane_b32 s30, v63, 18
+; VI-NEXT: v_readlane_b32 s31, v63, 19
+; VI-NEXT: v_readlane_b32 s67, v63, 17
+; VI-NEXT: v_readlane_b32 s66, v63, 16
+; VI-NEXT: v_readlane_b32 s65, v63, 15
+; VI-NEXT: v_readlane_b32 s64, v63, 14
+; VI-NEXT: v_readlane_b32 s55, v63, 13
+; VI-NEXT: v_readlane_b32 s54, v63, 12
+; VI-NEXT: v_readlane_b32 s53, v63, 11
+; VI-NEXT: v_readlane_b32 s52, v63, 10
+; VI-NEXT: v_readlane_b32 s51, v63, 9
+; VI-NEXT: v_readlane_b32 s50, v63, 8
+; VI-NEXT: v_readlane_b32 s49, v63, 7
+; VI-NEXT: v_readlane_b32 s48, v63, 6
+; VI-NEXT: v_readlane_b32 s39, v63, 5
+; VI-NEXT: v_readlane_b32 s38, v63, 4
+; VI-NEXT: v_readlane_b32 s37, v63, 3
+; VI-NEXT: v_readlane_b32 s36, v63, 2
+; VI-NEXT: v_readlane_b32 s35, v63, 1
+; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: v_or_b32_sdwa v2, v25, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -79399,23 +79399,23 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v63, s30, 0
-; GFX9-NEXT: v_writelane_b32 v63, s31, 1
-; GFX9-NEXT: v_writelane_b32 v63, s34, 2
-; GFX9-NEXT: v_writelane_b32 v63, s35, 3
-; GFX9-NEXT: v_writelane_b32 v63, s36, 4
-; GFX9-NEXT: v_writelane_b32 v63, s37, 5
-; GFX9-NEXT: v_writelane_b32 v63, s38, 6
-; GFX9-NEXT: v_writelane_b32 v63, s39, 7
-; GFX9-NEXT: v_writelane_b32 v63, s48, 8
-; GFX9-NEXT: v_writelane_b32 v63, s49, 9
-; GFX9-NEXT: v_writelane_b32 v63, s50, 10
-; GFX9-NEXT: v_writelane_b32 v63, s51, 11
-; GFX9-NEXT: v_writelane_b32 v63, s52, 12
-; GFX9-NEXT: v_writelane_b32 v63, s53, 13
-; GFX9-NEXT: v_writelane_b32 v63, s54, 14
+; GFX9-NEXT: v_writelane_b32 v63, s34, 0
+; GFX9-NEXT: v_writelane_b32 v63, s35, 1
+; GFX9-NEXT: v_writelane_b32 v63, s36, 2
+; GFX9-NEXT: v_writelane_b32 v63, s37, 3
+; GFX9-NEXT: v_writelane_b32 v63, s38, 4
+; GFX9-NEXT: v_writelane_b32 v63, s39, 5
+; GFX9-NEXT: v_writelane_b32 v63, s48, 6
+; GFX9-NEXT: v_writelane_b32 v63, s49, 7
+; GFX9-NEXT: v_writelane_b32 v63, s50, 8
+; GFX9-NEXT: v_writelane_b32 v63, s51, 9
+; GFX9-NEXT: v_writelane_b32 v63, s52, 10
+; GFX9-NEXT: v_writelane_b32 v63, s53, 11
+; GFX9-NEXT: v_writelane_b32 v63, s54, 12
+; GFX9-NEXT: v_writelane_b32 v63, s55, 13
+; GFX9-NEXT: v_writelane_b32 v63, s30, 14
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; GFX9-NEXT: v_writelane_b32 v63, s55, 15
+; GFX9-NEXT: v_writelane_b32 v63, s31, 15
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
@@ -79756,22 +79756,22 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX9-NEXT: v_or_b32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s55, v63, 15
-; GFX9-NEXT: v_readlane_b32 s54, v63, 14
-; GFX9-NEXT: v_readlane_b32 s53, v63, 13
-; GFX9-NEXT: v_readlane_b32 s52, v63, 12
-; GFX9-NEXT: v_readlane_b32 s51, v63, 11
-; GFX9-NEXT: v_readlane_b32 s50, v63, 10
-; GFX9-NEXT: v_readlane_b32 s49, v63, 9
-; GFX9-NEXT: v_readlane_b32 s48, v63, 8
-; GFX9-NEXT: v_readlane_b32 s39, v63, 7
-; GFX9-NEXT: v_readlane_b32 s38, v63, 6
-; GFX9-NEXT: v_readlane_b32 s37, v63, 5
-; GFX9-NEXT: v_readlane_b32 s36, v63, 4
-; GFX9-NEXT: v_readlane_b32 s35, v63, 3
-; GFX9-NEXT: v_readlane_b32 s34, v63, 2
-; GFX9-NEXT: v_readlane_b32 s31, v63, 1
-; GFX9-NEXT: v_readlane_b32 s30, v63, 0
+; GFX9-NEXT: v_readlane_b32 s30, v63, 14
+; GFX9-NEXT: v_readlane_b32 s31, v63, 15
+; GFX9-NEXT: v_readlane_b32 s55, v63, 13
+; GFX9-NEXT: v_readlane_b32 s54, v63, 12
+; GFX9-NEXT: v_readlane_b32 s53, v63, 11
+; GFX9-NEXT: v_readlane_b32 s52, v63, 10
+; GFX9-NEXT: v_readlane_b32 s51, v63, 9
+; GFX9-NEXT: v_readlane_b32 s50, v63, 8
+; GFX9-NEXT: v_readlane_b32 s49, v63, 7
+; GFX9-NEXT: v_readlane_b32 s48, v63, 6
+; GFX9-NEXT: v_readlane_b32 s39, v63, 5
+; GFX9-NEXT: v_readlane_b32 s38, v63, 4
+; GFX9-NEXT: v_readlane_b32 s37, v63, 3
+; GFX9-NEXT: v_readlane_b32 s36, v63, 2
+; GFX9-NEXT: v_readlane_b32 s35, v63, 1
+; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v5, v33, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -79825,18 +79825,18 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX11-NEXT: s_or_saveexec_b32 s4, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s34, 0
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
; GFX11-NEXT: s_mov_b32 s42, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
-; GFX11-NEXT: v_writelane_b32 v40, s34, 2
-; GFX11-NEXT: v_writelane_b32 v40, s35, 3
-; GFX11-NEXT: v_writelane_b32 v40, s36, 4
-; GFX11-NEXT: v_writelane_b32 v40, s37, 5
-; GFX11-NEXT: v_writelane_b32 v40, s38, 6
-; GFX11-NEXT: v_writelane_b32 v40, s39, 7
-; GFX11-NEXT: v_writelane_b32 v40, s48, 8
-; GFX11-NEXT: v_writelane_b32 v40, s49, 9
+; GFX11-NEXT: v_writelane_b32 v40, s35, 1
+; GFX11-NEXT: v_writelane_b32 v40, s36, 2
+; GFX11-NEXT: v_writelane_b32 v40, s37, 3
+; GFX11-NEXT: v_writelane_b32 v40, s38, 4
+; GFX11-NEXT: v_writelane_b32 v40, s39, 5
+; GFX11-NEXT: v_writelane_b32 v40, s48, 6
+; GFX11-NEXT: v_writelane_b32 v40, s49, 7
+; GFX11-NEXT: v_writelane_b32 v40, s30, 8
+; GFX11-NEXT: v_writelane_b32 v40, s31, 9
; GFX11-NEXT: s_cbranch_scc0 .LBB105_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s43, s27, 24
@@ -80184,21 +80184,21 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX11-NEXT: v_or_b32_e32 v2, v4, v10
; GFX11-NEXT: v_or_b32_e32 v3, v11, v7
; GFX11-NEXT: v_or_b32_e32 v4, v12, v8
+; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[82:85], off
; GFX11-NEXT: scratch_store_b128 v0, v[23:26], off offset:16
; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48
-; GFX11-NEXT: v_readlane_b32 s49, v40, 9
-; GFX11-NEXT: v_readlane_b32 s48, v40, 8
-; GFX11-NEXT: v_readlane_b32 s39, v40, 7
-; GFX11-NEXT: v_readlane_b32 s38, v40, 6
-; GFX11-NEXT: v_readlane_b32 s37, v40, 5
-; GFX11-NEXT: v_readlane_b32 s36, v40, 4
-; GFX11-NEXT: v_readlane_b32 s35, v40, 3
-; GFX11-NEXT: v_readlane_b32 s34, v40, 2
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
-; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 9
+; GFX11-NEXT: v_readlane_b32 s49, v40, 7
+; GFX11-NEXT: v_readlane_b32 s48, v40, 6
+; GFX11-NEXT: v_readlane_b32 s39, v40, 5
+; GFX11-NEXT: v_readlane_b32 s38, v40, 4
+; GFX11-NEXT: v_readlane_b32 s37, v40, 3
+; GFX11-NEXT: v_readlane_b32 s36, v40, 2
+; GFX11-NEXT: v_readlane_b32 s35, v40, 1
+; GFX11-NEXT: v_readlane_b32 s34, v40, 0
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
@@ -82608,14 +82608,14 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:72
; SI-NEXT: v_readfirstlane_b32 s46, v20
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v32, s30, 0
-; SI-NEXT: v_writelane_b32 v32, s31, 1
-; SI-NEXT: v_writelane_b32 v32, s34, 2
-; SI-NEXT: v_writelane_b32 v32, s35, 3
-; SI-NEXT: v_writelane_b32 v32, s36, 4
-; SI-NEXT: v_writelane_b32 v32, s37, 5
-; SI-NEXT: v_writelane_b32 v32, s38, 6
-; SI-NEXT: v_writelane_b32 v32, s39, 7
+; SI-NEXT: v_writelane_b32 v32, s34, 0
+; SI-NEXT: v_writelane_b32 v32, s35, 1
+; SI-NEXT: v_writelane_b32 v32, s36, 2
+; SI-NEXT: v_writelane_b32 v32, s37, 3
+; SI-NEXT: v_writelane_b32 v32, s38, 4
+; SI-NEXT: v_writelane_b32 v32, s39, 5
+; SI-NEXT: v_writelane_b32 v32, s30, 6
+; SI-NEXT: v_writelane_b32 v32, s31, 7
; SI-NEXT: v_readfirstlane_b32 s74, v30
; SI-NEXT: v_readfirstlane_b32 s61, v29
; SI-NEXT: v_readfirstlane_b32 s63, v28
@@ -83031,14 +83031,14 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: v_cvt_f32_f16_e32 v30, s5
; SI-NEXT: v_cvt_f32_f16_e32 v31, s4
; SI-NEXT: .LBB107_3: ; %end
-; SI-NEXT: v_readlane_b32 s39, v32, 7
-; SI-NEXT: v_readlane_b32 s38, v32, 6
-; SI-NEXT: v_readlane_b32 s37, v32, 5
-; SI-NEXT: v_readlane_b32 s36, v32, 4
-; SI-NEXT: v_readlane_b32 s35, v32, 3
-; SI-NEXT: v_readlane_b32 s34, v32, 2
-; SI-NEXT: v_readlane_b32 s31, v32, 1
-; SI-NEXT: v_readlane_b32 s30, v32, 0
+; SI-NEXT: v_readlane_b32 s30, v32, 6
+; SI-NEXT: v_readlane_b32 s31, v32, 7
+; SI-NEXT: v_readlane_b32 s39, v32, 5
+; SI-NEXT: v_readlane_b32 s38, v32, 4
+; SI-NEXT: v_readlane_b32 s37, v32, 3
+; SI-NEXT: v_readlane_b32 s36, v32, 2
+; SI-NEXT: v_readlane_b32 s35, v32, 1
+; SI-NEXT: v_readlane_b32 s34, v32, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
@@ -88167,27 +88167,27 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v63, s30, 0
-; VI-NEXT: v_writelane_b32 v63, s31, 1
-; VI-NEXT: v_writelane_b32 v63, s34, 2
-; VI-NEXT: v_writelane_b32 v63, s35, 3
-; VI-NEXT: v_writelane_b32 v63, s36, 4
-; VI-NEXT: v_writelane_b32 v63, s37, 5
-; VI-NEXT: v_writelane_b32 v63, s38, 6
-; VI-NEXT: v_writelane_b32 v63, s39, 7
-; VI-NEXT: v_writelane_b32 v63, s48, 8
-; VI-NEXT: v_writelane_b32 v63, s49, 9
-; VI-NEXT: v_writelane_b32 v63, s50, 10
-; VI-NEXT: v_writelane_b32 v63, s51, 11
-; VI-NEXT: v_writelane_b32 v63, s52, 12
-; VI-NEXT: v_writelane_b32 v63, s53, 13
-; VI-NEXT: v_writelane_b32 v63, s54, 14
-; VI-NEXT: v_writelane_b32 v63, s55, 15
-; VI-NEXT: v_writelane_b32 v63, s64, 16
-; VI-NEXT: v_writelane_b32 v63, s65, 17
-; VI-NEXT: v_writelane_b32 v63, s66, 18
+; VI-NEXT: v_writelane_b32 v63, s34, 0
+; VI-NEXT: v_writelane_b32 v63, s35, 1
+; VI-NEXT: v_writelane_b32 v63, s36, 2
+; VI-NEXT: v_writelane_b32 v63, s37, 3
+; VI-NEXT: v_writelane_b32 v63, s38, 4
+; VI-NEXT: v_writelane_b32 v63, s39, 5
+; VI-NEXT: v_writelane_b32 v63, s48, 6
+; VI-NEXT: v_writelane_b32 v63, s49, 7
+; VI-NEXT: v_writelane_b32 v63, s50, 8
+; VI-NEXT: v_writelane_b32 v63, s51, 9
+; VI-NEXT: v_writelane_b32 v63, s52, 10
+; VI-NEXT: v_writelane_b32 v63, s53, 11
+; VI-NEXT: v_writelane_b32 v63, s54, 12
+; VI-NEXT: v_writelane_b32 v63, s55, 13
+; VI-NEXT: v_writelane_b32 v63, s64, 14
+; VI-NEXT: v_writelane_b32 v63, s65, 15
+; VI-NEXT: v_writelane_b32 v63, s66, 16
+; VI-NEXT: v_writelane_b32 v63, s67, 17
+; VI-NEXT: v_writelane_b32 v63, s30, 18
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; VI-NEXT: v_writelane_b32 v63, s67, 19
+; VI-NEXT: v_writelane_b32 v63, s31, 19
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
@@ -88807,26 +88807,26 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v34
; VI-NEXT: v_or_b32_sdwa v1, v13, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_readlane_b32 s67, v63, 19
-; VI-NEXT: v_readlane_b32 s66, v63, 18
-; VI-NEXT: v_readlane_b32 s65, v63, 17
-; VI-NEXT: v_readlane_b32 s64, v63, 16
-; VI-NEXT: v_readlane_b32 s55, v63, 15
-; VI-NEXT: v_readlane_b32 s54, v63, 14
-; VI-NEXT: v_readlane_b32 s53, v63, 13
-; VI-NEXT: v_readlane_b32 s52, v63, 12
-; VI-NEXT: v_readlane_b32 s51, v63, 11
-; VI-NEXT: v_readlane_b32 s50, v63, 10
-; VI-NEXT: v_readlane_b32 s49, v63, 9
-; VI-NEXT: v_readlane_b32 s48, v63, 8
-; VI-NEXT: v_readlane_b32 s39, v63, 7
-; VI-NEXT: v_readlane_b32 s38, v63, 6
-; VI-NEXT: v_readlane_b32 s37, v63, 5
-; VI-NEXT: v_readlane_b32 s36, v63, 4
-; VI-NEXT: v_readlane_b32 s35, v63, 3
-; VI-NEXT: v_readlane_b32 s34, v63, 2
-; VI-NEXT: v_readlane_b32 s31, v63, 1
-; VI-NEXT: v_readlane_b32 s30, v63, 0
+; VI-NEXT: v_readlane_b32 s30, v63, 18
+; VI-NEXT: v_readlane_b32 s31, v63, 19
+; VI-NEXT: v_readlane_b32 s67, v63, 17
+; VI-NEXT: v_readlane_b32 s66, v63, 16
+; VI-NEXT: v_readlane_b32 s65, v63, 15
+; VI-NEXT: v_readlane_b32 s64, v63, 14
+; VI-NEXT: v_readlane_b32 s55, v63, 13
+; VI-NEXT: v_readlane_b32 s54, v63, 12
+; VI-NEXT: v_readlane_b32 s53, v63, 11
+; VI-NEXT: v_readlane_b32 s52, v63, 10
+; VI-NEXT: v_readlane_b32 s51, v63, 9
+; VI-NEXT: v_readlane_b32 s50, v63, 8
+; VI-NEXT: v_readlane_b32 s49, v63, 7
+; VI-NEXT: v_readlane_b32 s48, v63, 6
+; VI-NEXT: v_readlane_b32 s39, v63, 5
+; VI-NEXT: v_readlane_b32 s38, v63, 4
+; VI-NEXT: v_readlane_b32 s37, v63, 3
+; VI-NEXT: v_readlane_b32 s36, v63, 2
+; VI-NEXT: v_readlane_b32 s35, v63, 1
+; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: v_or_b32_sdwa v2, v33, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -88884,26 +88884,26 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v4, s30, 0
-; GFX9-NEXT: v_writelane_b32 v4, s31, 1
-; GFX9-NEXT: v_writelane_b32 v4, s34, 2
-; GFX9-NEXT: v_writelane_b32 v4, s35, 3
-; GFX9-NEXT: v_writelane_b32 v4, s36, 4
-; GFX9-NEXT: v_writelane_b32 v4, s37, 5
-; GFX9-NEXT: v_writelane_b32 v4, s38, 6
-; GFX9-NEXT: v_writelane_b32 v4, s39, 7
-; GFX9-NEXT: v_writelane_b32 v4, s48, 8
-; GFX9-NEXT: v_writelane_b32 v4, s49, 9
-; GFX9-NEXT: v_writelane_b32 v4, s50, 10
-; GFX9-NEXT: v_writelane_b32 v4, s51, 11
-; GFX9-NEXT: v_writelane_b32 v4, s52, 12
-; GFX9-NEXT: v_writelane_b32 v4, s53, 13
+; GFX9-NEXT: v_writelane_b32 v4, s34, 0
+; GFX9-NEXT: v_writelane_b32 v4, s35, 1
+; GFX9-NEXT: v_writelane_b32 v4, s36, 2
+; GFX9-NEXT: v_writelane_b32 v4, s37, 3
+; GFX9-NEXT: v_writelane_b32 v4, s38, 4
+; GFX9-NEXT: v_writelane_b32 v4, s39, 5
+; GFX9-NEXT: v_writelane_b32 v4, s48, 6
+; GFX9-NEXT: v_writelane_b32 v4, s49, 7
+; GFX9-NEXT: v_writelane_b32 v4, s50, 8
+; GFX9-NEXT: v_writelane_b32 v4, s51, 9
+; GFX9-NEXT: v_writelane_b32 v4, s52, 10
+; GFX9-NEXT: v_writelane_b32 v4, s53, 11
+; GFX9-NEXT: v_writelane_b32 v4, s54, 12
+; GFX9-NEXT: v_writelane_b32 v4, s55, 13
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; GFX9-NEXT: v_writelane_b32 v4, s54, 14
+; GFX9-NEXT: v_writelane_b32 v4, s30, 14
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: v_writelane_b32 v4, s55, 15
+; GFX9-NEXT: v_writelane_b32 v4, s31, 15
; GFX9-NEXT: s_cbranch_scc0 .LBB109_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s92, s5, 24
@@ -89541,23 +89541,23 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX9-NEXT: s_or_b32 s4, s4, s5
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_readlane_b32 s30, v4, 14
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_readlane_b32 s55, v4, 15
-; GFX9-NEXT: v_readlane_b32 s54, v4, 14
-; GFX9-NEXT: v_readlane_b32 s53, v4, 13
-; GFX9-NEXT: v_readlane_b32 s52, v4, 12
-; GFX9-NEXT: v_readlane_b32 s51, v4, 11
-; GFX9-NEXT: v_readlane_b32 s50, v4, 10
-; GFX9-NEXT: v_readlane_b32 s49, v4, 9
-; GFX9-NEXT: v_readlane_b32 s48, v4, 8
-; GFX9-NEXT: v_readlane_b32 s39, v4, 7
-; GFX9-NEXT: v_readlane_b32 s38, v4, 6
-; GFX9-NEXT: v_readlane_b32 s37, v4, 5
-; GFX9-NEXT: v_readlane_b32 s36, v4, 4
-; GFX9-NEXT: v_readlane_b32 s35, v4, 3
-; GFX9-NEXT: v_readlane_b32 s34, v4, 2
-; GFX9-NEXT: v_readlane_b32 s31, v4, 1
-; GFX9-NEXT: v_readlane_b32 s30, v4, 0
+; GFX9-NEXT: v_readlane_b32 s31, v4, 15
+; GFX9-NEXT: v_readlane_b32 s55, v4, 13
+; GFX9-NEXT: v_readlane_b32 s54, v4, 12
+; GFX9-NEXT: v_readlane_b32 s53, v4, 11
+; GFX9-NEXT: v_readlane_b32 s52, v4, 10
+; GFX9-NEXT: v_readlane_b32 s51, v4, 9
+; GFX9-NEXT: v_readlane_b32 s50, v4, 8
+; GFX9-NEXT: v_readlane_b32 s49, v4, 7
+; GFX9-NEXT: v_readlane_b32 s48, v4, 6
+; GFX9-NEXT: v_readlane_b32 s39, v4, 5
+; GFX9-NEXT: v_readlane_b32 s38, v4, 4
+; GFX9-NEXT: v_readlane_b32 s37, v4, 3
+; GFX9-NEXT: v_readlane_b32 s36, v4, 2
+; GFX9-NEXT: v_readlane_b32 s35, v4, 1
+; GFX9-NEXT: v_readlane_b32 s34, v4, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -89620,19 +89620,19 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-NEXT: s_xor_saveexec_b32 s4, -1
; GFX11-NEXT: scratch_store_b32 off, v17, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v17, s30, 0
+; GFX11-NEXT: v_writelane_b32 v17, s34, 0
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
; GFX11-NEXT: s_mov_b32 vcc_lo, 0
-; GFX11-NEXT: v_writelane_b32 v17, s31, 1
-; GFX11-NEXT: v_writelane_b32 v17, s34, 2
-; GFX11-NEXT: v_writelane_b32 v17, s35, 3
-; GFX11-NEXT: v_writelane_b32 v17, s36, 4
-; GFX11-NEXT: v_writelane_b32 v17, s37, 5
-; GFX11-NEXT: v_writelane_b32 v17, s38, 6
-; GFX11-NEXT: v_writelane_b32 v17, s39, 7
-; GFX11-NEXT: v_writelane_b32 v17, s48, 8
-; GFX11-NEXT: v_writelane_b32 v17, s50, 9
-; GFX11-NEXT: v_writelane_b32 v17, s51, 10
+; GFX11-NEXT: v_writelane_b32 v17, s35, 1
+; GFX11-NEXT: v_writelane_b32 v17, s36, 2
+; GFX11-NEXT: v_writelane_b32 v17, s37, 3
+; GFX11-NEXT: v_writelane_b32 v17, s38, 4
+; GFX11-NEXT: v_writelane_b32 v17, s39, 5
+; GFX11-NEXT: v_writelane_b32 v17, s48, 6
+; GFX11-NEXT: v_writelane_b32 v17, s50, 7
+; GFX11-NEXT: v_writelane_b32 v17, s51, 8
+; GFX11-NEXT: v_writelane_b32 v17, s30, 9
+; GFX11-NEXT: v_writelane_b32 v17, s31, 10
; GFX11-NEXT: s_cbranch_scc0 .LBB109_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s62, s27, 24
@@ -90280,22 +90280,22 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-NEXT: s_or_b32 s3, s4, s5
; GFX11-NEXT: v_dual_mov_b32 v13, s0 :: v_dual_mov_b32 v14, s1
; GFX11-NEXT: v_dual_mov_b32 v15, s2 :: v_dual_mov_b32 v16, s3
+; GFX11-NEXT: v_readlane_b32 s30, v17, 9
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
-; GFX11-NEXT: v_readlane_b32 s51, v17, 10
-; GFX11-NEXT: v_readlane_b32 s50, v17, 9
-; GFX11-NEXT: v_readlane_b32 s48, v17, 8
-; GFX11-NEXT: v_readlane_b32 s39, v17, 7
-; GFX11-NEXT: v_readlane_b32 s38, v17, 6
-; GFX11-NEXT: v_readlane_b32 s37, v17, 5
-; GFX11-NEXT: v_readlane_b32 s36, v17, 4
-; GFX11-NEXT: v_readlane_b32 s35, v17, 3
-; GFX11-NEXT: v_readlane_b32 s34, v17, 2
-; GFX11-NEXT: v_readlane_b32 s31, v17, 1
-; GFX11-NEXT: v_readlane_b32 s30, v17, 0
+; GFX11-NEXT: v_readlane_b32 s31, v17, 10
+; GFX11-NEXT: v_readlane_b32 s51, v17, 8
+; GFX11-NEXT: v_readlane_b32 s50, v17, 7
+; GFX11-NEXT: v_readlane_b32 s48, v17, 6
+; GFX11-NEXT: v_readlane_b32 s39, v17, 5
+; GFX11-NEXT: v_readlane_b32 s38, v17, 4
+; GFX11-NEXT: v_readlane_b32 s37, v17, 3
+; GFX11-NEXT: v_readlane_b32 s36, v17, 2
+; GFX11-NEXT: v_readlane_b32 s35, v17, 1
+; GFX11-NEXT: v_readlane_b32 s34, v17, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v17, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
index fb2e94fc3b87a..6c1f1249ffb7f 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
@@ -3193,10 +3193,10 @@ define inreg <48 x i16> @bitcast_v24i32_to_v48i16_scalar(<24 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v12, s30, 0
-; SI-NEXT: v_writelane_b32 v12, s31, 1
+; SI-NEXT: v_writelane_b32 v12, s34, 0
+; SI-NEXT: v_writelane_b32 v12, s35, 1
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
-; SI-NEXT: v_writelane_b32 v12, s34, 2
+; SI-NEXT: v_writelane_b32 v12, s30, 2
; SI-NEXT: v_readfirstlane_b32 s12, v1
; SI-NEXT: v_readfirstlane_b32 s13, v2
; SI-NEXT: v_readfirstlane_b32 s10, v3
@@ -3208,7 +3208,7 @@ define inreg <48 x i16> @bitcast_v24i32_to_v48i16_scalar(<24 x i32> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v9
; SI-NEXT: s_and_b64 s[14:15], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v10
-; SI-NEXT: v_writelane_b32 v12, s35, 3
+; SI-NEXT: v_writelane_b32 v12, s31, 3
; SI-NEXT: s_cbranch_scc0 .LBB13_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s88, s5, 16
@@ -3449,11 +3449,11 @@ define inreg <48 x i16> @bitcast_v24i32_to_v48i16_scalar(<24 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x5c, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v12, 2
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s35, v12, 3
-; SI-NEXT: v_readlane_b32 s34, v12, 2
-; SI-NEXT: v_readlane_b32 s31, v12, 1
-; SI-NEXT: v_readlane_b32 s30, v12, 0
+; SI-NEXT: v_readlane_b32 s31, v12, 3
+; SI-NEXT: v_readlane_b32 s35, v12, 1
+; SI-NEXT: v_readlane_b32 s34, v12, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
@@ -22130,10 +22130,10 @@ define inreg <48 x i16> @bitcast_v12i64_to_v48i16_scalar(<12 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v12, s30, 0
-; SI-NEXT: v_writelane_b32 v12, s31, 1
+; SI-NEXT: v_writelane_b32 v12, s34, 0
+; SI-NEXT: v_writelane_b32 v12, s35, 1
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
-; SI-NEXT: v_writelane_b32 v12, s34, 2
+; SI-NEXT: v_writelane_b32 v12, s30, 2
; SI-NEXT: v_readfirstlane_b32 s12, v1
; SI-NEXT: v_readfirstlane_b32 s13, v2
; SI-NEXT: v_readfirstlane_b32 s10, v3
@@ -22145,7 +22145,7 @@ define inreg <48 x i16> @bitcast_v12i64_to_v48i16_scalar(<12 x i64> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v9
; SI-NEXT: s_and_b64 s[14:15], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v10
-; SI-NEXT: v_writelane_b32 v12, s35, 3
+; SI-NEXT: v_writelane_b32 v12, s31, 3
; SI-NEXT: s_cbranch_scc0 .LBB41_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s88, s5, 16
@@ -22386,11 +22386,11 @@ define inreg <48 x i16> @bitcast_v12i64_to_v48i16_scalar(<12 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x5c, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v12, 2
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s35, v12, 3
-; SI-NEXT: v_readlane_b32 s34, v12, 2
-; SI-NEXT: v_readlane_b32 s31, v12, 1
-; SI-NEXT: v_readlane_b32 s30, v12, 0
+; SI-NEXT: v_readlane_b32 s31, v12, 3
+; SI-NEXT: v_readlane_b32 s35, v12, 1
+; SI-NEXT: v_readlane_b32 s34, v12, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
index 07cdbef82d892..58cfae21bd8d5 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
@@ -3412,15 +3412,15 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v14, s30, 0
-; SI-NEXT: v_writelane_b32 v14, s31, 1
-; SI-NEXT: v_writelane_b32 v14, s34, 2
-; SI-NEXT: v_writelane_b32 v14, s35, 3
-; SI-NEXT: v_writelane_b32 v14, s36, 4
-; SI-NEXT: v_writelane_b32 v14, s37, 5
-; SI-NEXT: v_writelane_b32 v14, s38, 6
+; SI-NEXT: v_writelane_b32 v14, s34, 0
+; SI-NEXT: v_writelane_b32 v14, s35, 1
+; SI-NEXT: v_writelane_b32 v14, s36, 2
+; SI-NEXT: v_writelane_b32 v14, s37, 3
+; SI-NEXT: v_writelane_b32 v14, s38, 4
+; SI-NEXT: v_writelane_b32 v14, s39, 5
+; SI-NEXT: v_writelane_b32 v14, s48, 6
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
-; SI-NEXT: v_writelane_b32 v14, s39, 7
+; SI-NEXT: v_writelane_b32 v14, s30, 7
; SI-NEXT: v_readfirstlane_b32 s14, v1
; SI-NEXT: v_readfirstlane_b32 s15, v2
; SI-NEXT: v_readfirstlane_b32 s12, v3
@@ -3434,7 +3434,7 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v11
; SI-NEXT: s_and_b64 s[40:41], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v12
-; SI-NEXT: v_writelane_b32 v14, s48, 8
+; SI-NEXT: v_writelane_b32 v14, s31, 8
; SI-NEXT: s_cbranch_scc0 .LBB13_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s92, s5, 16
@@ -3693,16 +3693,16 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x64, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v14, 7
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s48, v14, 8
-; SI-NEXT: v_readlane_b32 s39, v14, 7
-; SI-NEXT: v_readlane_b32 s38, v14, 6
-; SI-NEXT: v_readlane_b32 s37, v14, 5
-; SI-NEXT: v_readlane_b32 s36, v14, 4
-; SI-NEXT: v_readlane_b32 s35, v14, 3
-; SI-NEXT: v_readlane_b32 s34, v14, 2
-; SI-NEXT: v_readlane_b32 s31, v14, 1
-; SI-NEXT: v_readlane_b32 s30, v14, 0
+; SI-NEXT: v_readlane_b32 s31, v14, 8
+; SI-NEXT: v_readlane_b32 s48, v14, 6
+; SI-NEXT: v_readlane_b32 s39, v14, 5
+; SI-NEXT: v_readlane_b32 s38, v14, 4
+; SI-NEXT: v_readlane_b32 s37, v14, 3
+; SI-NEXT: v_readlane_b32 s36, v14, 2
+; SI-NEXT: v_readlane_b32 s35, v14, 1
+; SI-NEXT: v_readlane_b32 s34, v14, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
@@ -24094,15 +24094,15 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v14, s30, 0
-; SI-NEXT: v_writelane_b32 v14, s31, 1
-; SI-NEXT: v_writelane_b32 v14, s34, 2
-; SI-NEXT: v_writelane_b32 v14, s35, 3
-; SI-NEXT: v_writelane_b32 v14, s36, 4
-; SI-NEXT: v_writelane_b32 v14, s37, 5
-; SI-NEXT: v_writelane_b32 v14, s38, 6
+; SI-NEXT: v_writelane_b32 v14, s34, 0
+; SI-NEXT: v_writelane_b32 v14, s35, 1
+; SI-NEXT: v_writelane_b32 v14, s36, 2
+; SI-NEXT: v_writelane_b32 v14, s37, 3
+; SI-NEXT: v_writelane_b32 v14, s38, 4
+; SI-NEXT: v_writelane_b32 v14, s39, 5
+; SI-NEXT: v_writelane_b32 v14, s48, 6
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
-; SI-NEXT: v_writelane_b32 v14, s39, 7
+; SI-NEXT: v_writelane_b32 v14, s30, 7
; SI-NEXT: v_readfirstlane_b32 s14, v1
; SI-NEXT: v_readfirstlane_b32 s15, v2
; SI-NEXT: v_readfirstlane_b32 s12, v3
@@ -24116,7 +24116,7 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v11
; SI-NEXT: s_and_b64 s[40:41], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v12
-; SI-NEXT: v_writelane_b32 v14, s48, 8
+; SI-NEXT: v_writelane_b32 v14, s31, 8
; SI-NEXT: s_cbranch_scc0 .LBB41_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s92, s5, 16
@@ -24375,16 +24375,16 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x64, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v14, 7
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s48, v14, 8
-; SI-NEXT: v_readlane_b32 s39, v14, 7
-; SI-NEXT: v_readlane_b32 s38, v14, 6
-; SI-NEXT: v_readlane_b32 s37, v14, 5
-; SI-NEXT: v_readlane_b32 s36, v14, 4
-; SI-NEXT: v_readlane_b32 s35, v14, 3
-; SI-NEXT: v_readlane_b32 s34, v14, 2
-; SI-NEXT: v_readlane_b32 s31, v14, 1
-; SI-NEXT: v_readlane_b32 s30, v14, 0
+; SI-NEXT: v_readlane_b32 s31, v14, 8
+; SI-NEXT: v_readlane_b32 s48, v14, 6
+; SI-NEXT: v_readlane_b32 s39, v14, 5
+; SI-NEXT: v_readlane_b32 s38, v14, 4
+; SI-NEXT: v_readlane_b32 s37, v14, 3
+; SI-NEXT: v_readlane_b32 s36, v14, 2
+; SI-NEXT: v_readlane_b32 s35, v14, 1
+; SI-NEXT: v_readlane_b32 s34, v14, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
index 8eb71e90f8504..7d04400ebe009 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
@@ -3641,20 +3641,20 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v16, s30, 0
-; SI-NEXT: v_writelane_b32 v16, s31, 1
-; SI-NEXT: v_writelane_b32 v16, s34, 2
-; SI-NEXT: v_writelane_b32 v16, s35, 3
-; SI-NEXT: v_writelane_b32 v16, s36, 4
-; SI-NEXT: v_writelane_b32 v16, s37, 5
-; SI-NEXT: v_writelane_b32 v16, s38, 6
-; SI-NEXT: v_writelane_b32 v16, s39, 7
-; SI-NEXT: v_writelane_b32 v16, s48, 8
-; SI-NEXT: v_writelane_b32 v16, s49, 9
-; SI-NEXT: v_writelane_b32 v16, s50, 10
-; SI-NEXT: v_writelane_b32 v16, s51, 11
+; SI-NEXT: v_writelane_b32 v16, s34, 0
+; SI-NEXT: v_writelane_b32 v16, s35, 1
+; SI-NEXT: v_writelane_b32 v16, s36, 2
+; SI-NEXT: v_writelane_b32 v16, s37, 3
+; SI-NEXT: v_writelane_b32 v16, s38, 4
+; SI-NEXT: v_writelane_b32 v16, s39, 5
+; SI-NEXT: v_writelane_b32 v16, s48, 6
+; SI-NEXT: v_writelane_b32 v16, s49, 7
+; SI-NEXT: v_writelane_b32 v16, s50, 8
+; SI-NEXT: v_writelane_b32 v16, s51, 9
+; SI-NEXT: v_writelane_b32 v16, s52, 10
+; SI-NEXT: v_writelane_b32 v16, s53, 11
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
-; SI-NEXT: v_writelane_b32 v16, s52, 12
+; SI-NEXT: v_writelane_b32 v16, s30, 12
; SI-NEXT: v_readfirstlane_b32 s40, v1
; SI-NEXT: v_readfirstlane_b32 s41, v2
; SI-NEXT: v_readfirstlane_b32 s14, v3
@@ -3670,7 +3670,7 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v13
; SI-NEXT: s_and_b64 s[42:43], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v14
-; SI-NEXT: v_writelane_b32 v16, s53, 13
+; SI-NEXT: v_writelane_b32 v16, s31, 13
; SI-NEXT: s_cbranch_scc0 .LBB13_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s30, s5, 16
@@ -3950,21 +3950,21 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x6c, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v16, 12
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s53, v16, 13
-; SI-NEXT: v_readlane_b32 s52, v16, 12
-; SI-NEXT: v_readlane_b32 s51, v16, 11
-; SI-NEXT: v_readlane_b32 s50, v16, 10
-; SI-NEXT: v_readlane_b32 s49, v16, 9
-; SI-NEXT: v_readlane_b32 s48, v16, 8
-; SI-NEXT: v_readlane_b32 s39, v16, 7
-; SI-NEXT: v_readlane_b32 s38, v16, 6
-; SI-NEXT: v_readlane_b32 s37, v16, 5
-; SI-NEXT: v_readlane_b32 s36, v16, 4
-; SI-NEXT: v_readlane_b32 s35, v16, 3
-; SI-NEXT: v_readlane_b32 s34, v16, 2
-; SI-NEXT: v_readlane_b32 s31, v16, 1
-; SI-NEXT: v_readlane_b32 s30, v16, 0
+; SI-NEXT: v_readlane_b32 s31, v16, 13
+; SI-NEXT: v_readlane_b32 s53, v16, 11
+; SI-NEXT: v_readlane_b32 s52, v16, 10
+; SI-NEXT: v_readlane_b32 s51, v16, 9
+; SI-NEXT: v_readlane_b32 s50, v16, 8
+; SI-NEXT: v_readlane_b32 s49, v16, 7
+; SI-NEXT: v_readlane_b32 s48, v16, 6
+; SI-NEXT: v_readlane_b32 s39, v16, 5
+; SI-NEXT: v_readlane_b32 s38, v16, 4
+; SI-NEXT: v_readlane_b32 s37, v16, 3
+; SI-NEXT: v_readlane_b32 s36, v16, 2
+; SI-NEXT: v_readlane_b32 s35, v16, 1
+; SI-NEXT: v_readlane_b32 s34, v16, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
@@ -4007,10 +4007,10 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v28, s30, 0
-; VI-NEXT: v_writelane_b32 v28, s31, 1
+; VI-NEXT: v_writelane_b32 v28, s34, 0
+; VI-NEXT: v_writelane_b32 v28, s35, 1
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
-; VI-NEXT: v_writelane_b32 v28, s34, 2
+; VI-NEXT: v_writelane_b32 v28, s30, 2
; VI-NEXT: v_readfirstlane_b32 s43, v0
; VI-NEXT: v_readfirstlane_b32 s42, v1
; VI-NEXT: v_readfirstlane_b32 s41, v2
@@ -4026,7 +4026,7 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s6, v12
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v13
-; VI-NEXT: v_writelane_b32 v28, s35, 3
+; VI-NEXT: v_writelane_b32 v28, s31, 3
; VI-NEXT: s_cbranch_scc0 .LBB13_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s44, s7, 16
@@ -4200,6 +4200,7 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3
; VI-NEXT: s_and_b32 s7, 0xffff, s7
; VI-NEXT: s_lshl_b32 s42, s44, 16
; VI-NEXT: s_or_b32 s7, s7, s42
+; VI-NEXT: v_readlane_b32 s30, v28, 2
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s16
@@ -4228,10 +4229,9 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v25, s8
; VI-NEXT: v_mov_b32_e32 v26, s6
; VI-NEXT: v_mov_b32_e32 v27, s7
-; VI-NEXT: v_readlane_b32 s35, v28, 3
-; VI-NEXT: v_readlane_b32 s34, v28, 2
-; VI-NEXT: v_readlane_b32 s31, v28, 1
-; VI-NEXT: v_readlane_b32 s30, v28, 0
+; VI-NEXT: v_readlane_b32 s31, v28, 3
+; VI-NEXT: v_readlane_b32 s35, v28, 1
+; VI-NEXT: v_readlane_b32 s34, v28, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -8964,10 +8964,10 @@ define inreg <56 x half> @bitcast_v28i32_to_v56f16_scalar(<28 x i32> inreg %a, i
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v28, s30, 0
-; VI-NEXT: v_writelane_b32 v28, s31, 1
+; VI-NEXT: v_writelane_b32 v28, s34, 0
+; VI-NEXT: v_writelane_b32 v28, s35, 1
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
-; VI-NEXT: v_writelane_b32 v28, s34, 2
+; VI-NEXT: v_writelane_b32 v28, s30, 2
; VI-NEXT: v_readfirstlane_b32 s43, v0
; VI-NEXT: v_readfirstlane_b32 s42, v1
; VI-NEXT: v_readfirstlane_b32 s41, v2
@@ -8983,7 +8983,7 @@ define inreg <56 x half> @bitcast_v28i32_to_v56f16_scalar(<28 x i32> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s6, v12
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v13
-; VI-NEXT: v_writelane_b32 v28, s35, 3
+; VI-NEXT: v_writelane_b32 v28, s31, 3
; VI-NEXT: s_cbranch_scc0 .LBB17_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s44, s7, 16
@@ -9157,6 +9157,7 @@ define inreg <56 x half> @bitcast_v28i32_to_v56f16_scalar(<28 x i32> inreg %a, i
; VI-NEXT: s_and_b32 s7, 0xffff, s7
; VI-NEXT: s_lshl_b32 s42, s44, 16
; VI-NEXT: s_or_b32 s7, s7, s42
+; VI-NEXT: v_readlane_b32 s30, v28, 2
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s16
@@ -9185,10 +9186,9 @@ define inreg <56 x half> @bitcast_v28i32_to_v56f16_scalar(<28 x i32> inreg %a, i
; VI-NEXT: v_mov_b32_e32 v25, s8
; VI-NEXT: v_mov_b32_e32 v26, s6
; VI-NEXT: v_mov_b32_e32 v27, s7
-; VI-NEXT: v_readlane_b32 s35, v28, 3
-; VI-NEXT: v_readlane_b32 s34, v28, 2
-; VI-NEXT: v_readlane_b32 s31, v28, 1
-; VI-NEXT: v_readlane_b32 s30, v28, 0
+; VI-NEXT: v_readlane_b32 s31, v28, 3
+; VI-NEXT: v_readlane_b32 s35, v28, 1
+; VI-NEXT: v_readlane_b32 s34, v28, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -26056,20 +26056,20 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v16, s30, 0
-; SI-NEXT: v_writelane_b32 v16, s31, 1
-; SI-NEXT: v_writelane_b32 v16, s34, 2
-; SI-NEXT: v_writelane_b32 v16, s35, 3
-; SI-NEXT: v_writelane_b32 v16, s36, 4
-; SI-NEXT: v_writelane_b32 v16, s37, 5
-; SI-NEXT: v_writelane_b32 v16, s38, 6
-; SI-NEXT: v_writelane_b32 v16, s39, 7
-; SI-NEXT: v_writelane_b32 v16, s48, 8
-; SI-NEXT: v_writelane_b32 v16, s49, 9
-; SI-NEXT: v_writelane_b32 v16, s50, 10
-; SI-NEXT: v_writelane_b32 v16, s51, 11
+; SI-NEXT: v_writelane_b32 v16, s34, 0
+; SI-NEXT: v_writelane_b32 v16, s35, 1
+; SI-NEXT: v_writelane_b32 v16, s36, 2
+; SI-NEXT: v_writelane_b32 v16, s37, 3
+; SI-NEXT: v_writelane_b32 v16, s38, 4
+; SI-NEXT: v_writelane_b32 v16, s39, 5
+; SI-NEXT: v_writelane_b32 v16, s48, 6
+; SI-NEXT: v_writelane_b32 v16, s49, 7
+; SI-NEXT: v_writelane_b32 v16, s50, 8
+; SI-NEXT: v_writelane_b32 v16, s51, 9
+; SI-NEXT: v_writelane_b32 v16, s52, 10
+; SI-NEXT: v_writelane_b32 v16, s53, 11
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
-; SI-NEXT: v_writelane_b32 v16, s52, 12
+; SI-NEXT: v_writelane_b32 v16, s30, 12
; SI-NEXT: v_readfirstlane_b32 s40, v1
; SI-NEXT: v_readfirstlane_b32 s41, v2
; SI-NEXT: v_readfirstlane_b32 s14, v3
@@ -26085,7 +26085,7 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v13
; SI-NEXT: s_and_b64 s[42:43], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v14
-; SI-NEXT: v_writelane_b32 v16, s53, 13
+; SI-NEXT: v_writelane_b32 v16, s31, 13
; SI-NEXT: s_cbranch_scc0 .LBB41_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s30, s5, 16
@@ -26365,21 +26365,21 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x6c, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v16, 12
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s53, v16, 13
-; SI-NEXT: v_readlane_b32 s52, v16, 12
-; SI-NEXT: v_readlane_b32 s51, v16, 11
-; SI-NEXT: v_readlane_b32 s50, v16, 10
-; SI-NEXT: v_readlane_b32 s49, v16, 9
-; SI-NEXT: v_readlane_b32 s48, v16, 8
-; SI-NEXT: v_readlane_b32 s39, v16, 7
-; SI-NEXT: v_readlane_b32 s38, v16, 6
-; SI-NEXT: v_readlane_b32 s37, v16, 5
-; SI-NEXT: v_readlane_b32 s36, v16, 4
-; SI-NEXT: v_readlane_b32 s35, v16, 3
-; SI-NEXT: v_readlane_b32 s34, v16, 2
-; SI-NEXT: v_readlane_b32 s31, v16, 1
-; SI-NEXT: v_readlane_b32 s30, v16, 0
+; SI-NEXT: v_readlane_b32 s31, v16, 13
+; SI-NEXT: v_readlane_b32 s53, v16, 11
+; SI-NEXT: v_readlane_b32 s52, v16, 10
+; SI-NEXT: v_readlane_b32 s51, v16, 9
+; SI-NEXT: v_readlane_b32 s50, v16, 8
+; SI-NEXT: v_readlane_b32 s49, v16, 7
+; SI-NEXT: v_readlane_b32 s48, v16, 6
+; SI-NEXT: v_readlane_b32 s39, v16, 5
+; SI-NEXT: v_readlane_b32 s38, v16, 4
+; SI-NEXT: v_readlane_b32 s37, v16, 3
+; SI-NEXT: v_readlane_b32 s36, v16, 2
+; SI-NEXT: v_readlane_b32 s35, v16, 1
+; SI-NEXT: v_readlane_b32 s34, v16, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
@@ -26422,10 +26422,10 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v28, s30, 0
-; VI-NEXT: v_writelane_b32 v28, s31, 1
+; VI-NEXT: v_writelane_b32 v28, s34, 0
+; VI-NEXT: v_writelane_b32 v28, s35, 1
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
-; VI-NEXT: v_writelane_b32 v28, s34, 2
+; VI-NEXT: v_writelane_b32 v28, s30, 2
; VI-NEXT: v_readfirstlane_b32 s43, v0
; VI-NEXT: v_readfirstlane_b32 s42, v1
; VI-NEXT: v_readfirstlane_b32 s41, v2
@@ -26441,7 +26441,7 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s6, v12
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v13
-; VI-NEXT: v_writelane_b32 v28, s35, 3
+; VI-NEXT: v_writelane_b32 v28, s31, 3
; VI-NEXT: s_cbranch_scc0 .LBB41_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s44, s7, 16
@@ -26615,6 +26615,7 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3
; VI-NEXT: s_and_b32 s7, 0xffff, s7
; VI-NEXT: s_lshl_b32 s42, s44, 16
; VI-NEXT: s_or_b32 s7, s7, s42
+; VI-NEXT: v_readlane_b32 s30, v28, 2
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s16
@@ -26643,10 +26644,9 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v25, s8
; VI-NEXT: v_mov_b32_e32 v26, s6
; VI-NEXT: v_mov_b32_e32 v27, s7
-; VI-NEXT: v_readlane_b32 s35, v28, 3
-; VI-NEXT: v_readlane_b32 s34, v28, 2
-; VI-NEXT: v_readlane_b32 s31, v28, 1
-; VI-NEXT: v_readlane_b32 s30, v28, 0
+; VI-NEXT: v_readlane_b32 s31, v28, 3
+; VI-NEXT: v_readlane_b32 s35, v28, 1
+; VI-NEXT: v_readlane_b32 s34, v28, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -31393,10 +31393,10 @@ define inreg <56 x half> @bitcast_v14i64_to_v56f16_scalar(<14 x i64> inreg %a, i
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v28, s30, 0
-; VI-NEXT: v_writelane_b32 v28, s31, 1
+; VI-NEXT: v_writelane_b32 v28, s34, 0
+; VI-NEXT: v_writelane_b32 v28, s35, 1
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
-; VI-NEXT: v_writelane_b32 v28, s34, 2
+; VI-NEXT: v_writelane_b32 v28, s30, 2
; VI-NEXT: v_readfirstlane_b32 s43, v0
; VI-NEXT: v_readfirstlane_b32 s42, v1
; VI-NEXT: v_readfirstlane_b32 s41, v2
@@ -31412,7 +31412,7 @@ define inreg <56 x half> @bitcast_v14i64_to_v56f16_scalar(<14 x i64> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s6, v12
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v13
-; VI-NEXT: v_writelane_b32 v28, s35, 3
+; VI-NEXT: v_writelane_b32 v28, s31, 3
; VI-NEXT: s_cbranch_scc0 .LBB45_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s44, s7, 16
@@ -31586,6 +31586,7 @@ define inreg <56 x half> @bitcast_v14i64_to_v56f16_scalar(<14 x i64> inreg %a, i
; VI-NEXT: s_and_b32 s7, 0xffff, s7
; VI-NEXT: s_lshl_b32 s42, s44, 16
; VI-NEXT: s_or_b32 s7, s7, s42
+; VI-NEXT: v_readlane_b32 s30, v28, 2
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s16
@@ -31614,10 +31615,9 @@ define inreg <56 x half> @bitcast_v14i64_to_v56f16_scalar(<14 x i64> inreg %a, i
; VI-NEXT: v_mov_b32_e32 v25, s8
; VI-NEXT: v_mov_b32_e32 v26, s6
; VI-NEXT: v_mov_b32_e32 v27, s7
-; VI-NEXT: v_readlane_b32 s35, v28, 3
-; VI-NEXT: v_readlane_b32 s34, v28, 2
-; VI-NEXT: v_readlane_b32 s31, v28, 1
-; VI-NEXT: v_readlane_b32 s30, v28, 0
+; VI-NEXT: v_readlane_b32 s31, v28, 3
+; VI-NEXT: v_readlane_b32 s35, v28, 1
+; VI-NEXT: v_readlane_b32 s34, v28, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
index 93c11f13ce3ce..c23182f2b30b9 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
@@ -3851,23 +3851,23 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v18, s30, 0
-; SI-NEXT: v_writelane_b32 v18, s31, 1
-; SI-NEXT: v_writelane_b32 v18, s34, 2
-; SI-NEXT: v_writelane_b32 v18, s35, 3
-; SI-NEXT: v_writelane_b32 v18, s36, 4
-; SI-NEXT: v_writelane_b32 v18, s37, 5
-; SI-NEXT: v_writelane_b32 v18, s38, 6
-; SI-NEXT: v_writelane_b32 v18, s39, 7
-; SI-NEXT: v_writelane_b32 v18, s48, 8
-; SI-NEXT: v_writelane_b32 v18, s49, 9
-; SI-NEXT: v_writelane_b32 v18, s50, 10
-; SI-NEXT: v_writelane_b32 v18, s51, 11
-; SI-NEXT: v_writelane_b32 v18, s52, 12
-; SI-NEXT: v_writelane_b32 v18, s53, 13
-; SI-NEXT: v_writelane_b32 v18, s54, 14
+; SI-NEXT: v_writelane_b32 v18, s34, 0
+; SI-NEXT: v_writelane_b32 v18, s35, 1
+; SI-NEXT: v_writelane_b32 v18, s36, 2
+; SI-NEXT: v_writelane_b32 v18, s37, 3
+; SI-NEXT: v_writelane_b32 v18, s38, 4
+; SI-NEXT: v_writelane_b32 v18, s39, 5
+; SI-NEXT: v_writelane_b32 v18, s48, 6
+; SI-NEXT: v_writelane_b32 v18, s49, 7
+; SI-NEXT: v_writelane_b32 v18, s50, 8
+; SI-NEXT: v_writelane_b32 v18, s51, 9
+; SI-NEXT: v_writelane_b32 v18, s52, 10
+; SI-NEXT: v_writelane_b32 v18, s53, 11
+; SI-NEXT: v_writelane_b32 v18, s54, 12
+; SI-NEXT: v_writelane_b32 v18, s55, 13
+; SI-NEXT: v_writelane_b32 v18, s64, 14
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; SI-NEXT: v_writelane_b32 v18, s55, 15
+; SI-NEXT: v_writelane_b32 v18, s30, 15
; SI-NEXT: v_readfirstlane_b32 s42, v1
; SI-NEXT: v_readfirstlane_b32 s43, v2
; SI-NEXT: v_readfirstlane_b32 s40, v3
@@ -3885,7 +3885,7 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v15
; SI-NEXT: s_and_b64 s[44:45], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v16
-; SI-NEXT: v_writelane_b32 v18, s64, 16
+; SI-NEXT: v_writelane_b32 v18, s31, 16
; SI-NEXT: s_cbranch_scc0 .LBB13_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s34, s5, 16
@@ -4183,24 +4183,24 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x74, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v18, 15
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s64, v18, 16
-; SI-NEXT: v_readlane_b32 s55, v18, 15
-; SI-NEXT: v_readlane_b32 s54, v18, 14
-; SI-NEXT: v_readlane_b32 s53, v18, 13
-; SI-NEXT: v_readlane_b32 s52, v18, 12
-; SI-NEXT: v_readlane_b32 s51, v18, 11
-; SI-NEXT: v_readlane_b32 s50, v18, 10
-; SI-NEXT: v_readlane_b32 s49, v18, 9
-; SI-NEXT: v_readlane_b32 s48, v18, 8
-; SI-NEXT: v_readlane_b32 s39, v18, 7
-; SI-NEXT: v_readlane_b32 s38, v18, 6
-; SI-NEXT: v_readlane_b32 s37, v18, 5
-; SI-NEXT: v_readlane_b32 s36, v18, 4
-; SI-NEXT: v_readlane_b32 s35, v18, 3
-; SI-NEXT: v_readlane_b32 s34, v18, 2
-; SI-NEXT: v_readlane_b32 s31, v18, 1
-; SI-NEXT: v_readlane_b32 s30, v18, 0
+; SI-NEXT: v_readlane_b32 s31, v18, 16
+; SI-NEXT: v_readlane_b32 s64, v18, 14
+; SI-NEXT: v_readlane_b32 s55, v18, 13
+; SI-NEXT: v_readlane_b32 s54, v18, 12
+; SI-NEXT: v_readlane_b32 s53, v18, 11
+; SI-NEXT: v_readlane_b32 s52, v18, 10
+; SI-NEXT: v_readlane_b32 s51, v18, 9
+; SI-NEXT: v_readlane_b32 s50, v18, 8
+; SI-NEXT: v_readlane_b32 s49, v18, 7
+; SI-NEXT: v_readlane_b32 s48, v18, 6
+; SI-NEXT: v_readlane_b32 s39, v18, 5
+; SI-NEXT: v_readlane_b32 s38, v18, 4
+; SI-NEXT: v_readlane_b32 s37, v18, 3
+; SI-NEXT: v_readlane_b32 s36, v18, 2
+; SI-NEXT: v_readlane_b32 s35, v18, 1
+; SI-NEXT: v_readlane_b32 s34, v18, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
@@ -4245,14 +4245,14 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v30, s30, 0
-; VI-NEXT: v_writelane_b32 v30, s31, 1
-; VI-NEXT: v_writelane_b32 v30, s34, 2
-; VI-NEXT: v_writelane_b32 v30, s35, 3
-; VI-NEXT: v_writelane_b32 v30, s36, 4
-; VI-NEXT: v_writelane_b32 v30, s37, 5
+; VI-NEXT: v_writelane_b32 v30, s34, 0
+; VI-NEXT: v_writelane_b32 v30, s35, 1
+; VI-NEXT: v_writelane_b32 v30, s36, 2
+; VI-NEXT: v_writelane_b32 v30, s37, 3
+; VI-NEXT: v_writelane_b32 v30, s38, 4
+; VI-NEXT: v_writelane_b32 v30, s39, 5
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; VI-NEXT: v_writelane_b32 v30, s38, 6
+; VI-NEXT: v_writelane_b32 v30, s30, 6
; VI-NEXT: v_readfirstlane_b32 s45, v0
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: v_readfirstlane_b32 s43, v2
@@ -4270,7 +4270,7 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s6, v14
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v15
-; VI-NEXT: v_writelane_b32 v30, s39, 7
+; VI-NEXT: v_writelane_b32 v30, s31, 7
; VI-NEXT: s_cbranch_scc0 .LBB13_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s46, s7, 16
@@ -4456,6 +4456,7 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; VI-NEXT: s_and_b32 s7, 0xffff, s7
; VI-NEXT: s_lshl_b32 s44, s46, 16
; VI-NEXT: s_or_b32 s7, s7, s44
+; VI-NEXT: v_readlane_b32 s30, v30, 6
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s16
@@ -4486,14 +4487,13 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v27, s8
; VI-NEXT: v_mov_b32_e32 v28, s6
; VI-NEXT: v_mov_b32_e32 v29, s7
-; VI-NEXT: v_readlane_b32 s39, v30, 7
-; VI-NEXT: v_readlane_b32 s38, v30, 6
-; VI-NEXT: v_readlane_b32 s37, v30, 5
-; VI-NEXT: v_readlane_b32 s36, v30, 4
-; VI-NEXT: v_readlane_b32 s35, v30, 3
-; VI-NEXT: v_readlane_b32 s34, v30, 2
-; VI-NEXT: v_readlane_b32 s31, v30, 1
-; VI-NEXT: v_readlane_b32 s30, v30, 0
+; VI-NEXT: v_readlane_b32 s31, v30, 7
+; VI-NEXT: v_readlane_b32 s39, v30, 5
+; VI-NEXT: v_readlane_b32 s38, v30, 4
+; VI-NEXT: v_readlane_b32 s37, v30, 3
+; VI-NEXT: v_readlane_b32 s36, v30, 2
+; VI-NEXT: v_readlane_b32 s35, v30, 1
+; VI-NEXT: v_readlane_b32 s34, v30, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -4538,10 +4538,10 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v30, s30, 0
-; GFX9-NEXT: v_writelane_b32 v30, s31, 1
+; GFX9-NEXT: v_writelane_b32 v30, s34, 0
+; GFX9-NEXT: v_writelane_b32 v30, s35, 1
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; GFX9-NEXT: v_writelane_b32 v30, s34, 2
+; GFX9-NEXT: v_writelane_b32 v30, s30, 2
; GFX9-NEXT: v_readfirstlane_b32 s6, v0
; GFX9-NEXT: v_readfirstlane_b32 s7, v1
; GFX9-NEXT: v_readfirstlane_b32 s8, v2
@@ -4559,7 +4559,7 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s44, v14
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s45, v15
-; GFX9-NEXT: v_writelane_b32 v30, s35, 3
+; GFX9-NEXT: v_writelane_b32 v30, s31, 3
; GFX9-NEXT: s_cbranch_scc0 .LBB13_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s46, s45, 16
@@ -4685,6 +4685,7 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; GFX9-NEXT: s_pack_ll_b32_b16 s41, s43, s56
; GFX9-NEXT: s_pack_ll_b32_b16 s42, s44, s47
; GFX9-NEXT: s_pack_ll_b32_b16 s43, s45, s46
+; GFX9-NEXT: v_readlane_b32 s30, v30, 2
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s16
@@ -4715,10 +4716,9 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v27, s41
; GFX9-NEXT: v_mov_b32_e32 v28, s42
; GFX9-NEXT: v_mov_b32_e32 v29, s43
-; GFX9-NEXT: v_readlane_b32 s35, v30, 3
-; GFX9-NEXT: v_readlane_b32 s34, v30, 2
-; GFX9-NEXT: v_readlane_b32 s31, v30, 1
-; GFX9-NEXT: v_readlane_b32 s30, v30, 0
+; GFX9-NEXT: v_readlane_b32 s31, v30, 3
+; GFX9-NEXT: v_readlane_b32 s35, v30, 1
+; GFX9-NEXT: v_readlane_b32 s34, v30, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -9603,14 +9603,14 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v30, s30, 0
-; VI-NEXT: v_writelane_b32 v30, s31, 1
-; VI-NEXT: v_writelane_b32 v30, s34, 2
-; VI-NEXT: v_writelane_b32 v30, s35, 3
-; VI-NEXT: v_writelane_b32 v30, s36, 4
-; VI-NEXT: v_writelane_b32 v30, s37, 5
+; VI-NEXT: v_writelane_b32 v30, s34, 0
+; VI-NEXT: v_writelane_b32 v30, s35, 1
+; VI-NEXT: v_writelane_b32 v30, s36, 2
+; VI-NEXT: v_writelane_b32 v30, s37, 3
+; VI-NEXT: v_writelane_b32 v30, s38, 4
+; VI-NEXT: v_writelane_b32 v30, s39, 5
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; VI-NEXT: v_writelane_b32 v30, s38, 6
+; VI-NEXT: v_writelane_b32 v30, s30, 6
; VI-NEXT: v_readfirstlane_b32 s45, v0
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: v_readfirstlane_b32 s43, v2
@@ -9628,7 +9628,7 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s6, v14
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v15
-; VI-NEXT: v_writelane_b32 v30, s39, 7
+; VI-NEXT: v_writelane_b32 v30, s31, 7
; VI-NEXT: s_cbranch_scc0 .LBB17_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s46, s7, 16
@@ -9814,6 +9814,7 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i
; VI-NEXT: s_and_b32 s7, 0xffff, s7
; VI-NEXT: s_lshl_b32 s44, s46, 16
; VI-NEXT: s_or_b32 s7, s7, s44
+; VI-NEXT: v_readlane_b32 s30, v30, 6
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s16
@@ -9844,14 +9845,13 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i
; VI-NEXT: v_mov_b32_e32 v27, s8
; VI-NEXT: v_mov_b32_e32 v28, s6
; VI-NEXT: v_mov_b32_e32 v29, s7
-; VI-NEXT: v_readlane_b32 s39, v30, 7
-; VI-NEXT: v_readlane_b32 s38, v30, 6
-; VI-NEXT: v_readlane_b32 s37, v30, 5
-; VI-NEXT: v_readlane_b32 s36, v30, 4
-; VI-NEXT: v_readlane_b32 s35, v30, 3
-; VI-NEXT: v_readlane_b32 s34, v30, 2
-; VI-NEXT: v_readlane_b32 s31, v30, 1
-; VI-NEXT: v_readlane_b32 s30, v30, 0
+; VI-NEXT: v_readlane_b32 s31, v30, 7
+; VI-NEXT: v_readlane_b32 s39, v30, 5
+; VI-NEXT: v_readlane_b32 s38, v30, 4
+; VI-NEXT: v_readlane_b32 s37, v30, 3
+; VI-NEXT: v_readlane_b32 s36, v30, 2
+; VI-NEXT: v_readlane_b32 s35, v30, 1
+; VI-NEXT: v_readlane_b32 s34, v30, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -9896,10 +9896,10 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v30, s30, 0
-; GFX9-NEXT: v_writelane_b32 v30, s31, 1
+; GFX9-NEXT: v_writelane_b32 v30, s34, 0
+; GFX9-NEXT: v_writelane_b32 v30, s35, 1
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; GFX9-NEXT: v_writelane_b32 v30, s34, 2
+; GFX9-NEXT: v_writelane_b32 v30, s30, 2
; GFX9-NEXT: v_readfirstlane_b32 s6, v0
; GFX9-NEXT: v_readfirstlane_b32 s7, v1
; GFX9-NEXT: v_readfirstlane_b32 s8, v2
@@ -9917,7 +9917,7 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i
; GFX9-NEXT: v_readfirstlane_b32 s44, v14
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s45, v15
-; GFX9-NEXT: v_writelane_b32 v30, s35, 3
+; GFX9-NEXT: v_writelane_b32 v30, s31, 3
; GFX9-NEXT: s_cbranch_scc0 .LBB17_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s46, s45, 16
@@ -10043,6 +10043,7 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i
; GFX9-NEXT: s_pack_ll_b32_b16 s41, s43, s56
; GFX9-NEXT: s_pack_ll_b32_b16 s42, s44, s47
; GFX9-NEXT: s_pack_ll_b32_b16 s43, s45, s46
+; GFX9-NEXT: v_readlane_b32 s30, v30, 2
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s16
@@ -10073,10 +10074,9 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i
; GFX9-NEXT: v_mov_b32_e32 v27, s41
; GFX9-NEXT: v_mov_b32_e32 v28, s42
; GFX9-NEXT: v_mov_b32_e32 v29, s43
-; GFX9-NEXT: v_readlane_b32 s35, v30, 3
-; GFX9-NEXT: v_readlane_b32 s34, v30, 2
-; GFX9-NEXT: v_readlane_b32 s31, v30, 1
-; GFX9-NEXT: v_readlane_b32 s30, v30, 0
+; GFX9-NEXT: v_readlane_b32 s31, v30, 3
+; GFX9-NEXT: v_readlane_b32 s35, v30, 1
+; GFX9-NEXT: v_readlane_b32 s34, v30, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -28059,23 +28059,23 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_writelane_b32 v18, s30, 0
-; SI-NEXT: v_writelane_b32 v18, s31, 1
-; SI-NEXT: v_writelane_b32 v18, s34, 2
-; SI-NEXT: v_writelane_b32 v18, s35, 3
-; SI-NEXT: v_writelane_b32 v18, s36, 4
-; SI-NEXT: v_writelane_b32 v18, s37, 5
-; SI-NEXT: v_writelane_b32 v18, s38, 6
-; SI-NEXT: v_writelane_b32 v18, s39, 7
-; SI-NEXT: v_writelane_b32 v18, s48, 8
-; SI-NEXT: v_writelane_b32 v18, s49, 9
-; SI-NEXT: v_writelane_b32 v18, s50, 10
-; SI-NEXT: v_writelane_b32 v18, s51, 11
-; SI-NEXT: v_writelane_b32 v18, s52, 12
-; SI-NEXT: v_writelane_b32 v18, s53, 13
-; SI-NEXT: v_writelane_b32 v18, s54, 14
+; SI-NEXT: v_writelane_b32 v18, s34, 0
+; SI-NEXT: v_writelane_b32 v18, s35, 1
+; SI-NEXT: v_writelane_b32 v18, s36, 2
+; SI-NEXT: v_writelane_b32 v18, s37, 3
+; SI-NEXT: v_writelane_b32 v18, s38, 4
+; SI-NEXT: v_writelane_b32 v18, s39, 5
+; SI-NEXT: v_writelane_b32 v18, s48, 6
+; SI-NEXT: v_writelane_b32 v18, s49, 7
+; SI-NEXT: v_writelane_b32 v18, s50, 8
+; SI-NEXT: v_writelane_b32 v18, s51, 9
+; SI-NEXT: v_writelane_b32 v18, s52, 10
+; SI-NEXT: v_writelane_b32 v18, s53, 11
+; SI-NEXT: v_writelane_b32 v18, s54, 12
+; SI-NEXT: v_writelane_b32 v18, s55, 13
+; SI-NEXT: v_writelane_b32 v18, s64, 14
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; SI-NEXT: v_writelane_b32 v18, s55, 15
+; SI-NEXT: v_writelane_b32 v18, s30, 15
; SI-NEXT: v_readfirstlane_b32 s42, v1
; SI-NEXT: v_readfirstlane_b32 s43, v2
; SI-NEXT: v_readfirstlane_b32 s40, v3
@@ -28093,7 +28093,7 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v15
; SI-NEXT: s_and_b64 s[44:45], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v16
-; SI-NEXT: v_writelane_b32 v18, s64, 16
+; SI-NEXT: v_writelane_b32 v18, s31, 16
; SI-NEXT: s_cbranch_scc0 .LBB41_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s34, s5, 16
@@ -28391,24 +28391,24 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x74, v0
; SI-NEXT: v_mov_b32_e32 v1, s4
+; SI-NEXT: v_readlane_b32 s30, v18, 15
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_readlane_b32 s64, v18, 16
-; SI-NEXT: v_readlane_b32 s55, v18, 15
-; SI-NEXT: v_readlane_b32 s54, v18, 14
-; SI-NEXT: v_readlane_b32 s53, v18, 13
-; SI-NEXT: v_readlane_b32 s52, v18, 12
-; SI-NEXT: v_readlane_b32 s51, v18, 11
-; SI-NEXT: v_readlane_b32 s50, v18, 10
-; SI-NEXT: v_readlane_b32 s49, v18, 9
-; SI-NEXT: v_readlane_b32 s48, v18, 8
-; SI-NEXT: v_readlane_b32 s39, v18, 7
-; SI-NEXT: v_readlane_b32 s38, v18, 6
-; SI-NEXT: v_readlane_b32 s37, v18, 5
-; SI-NEXT: v_readlane_b32 s36, v18, 4
-; SI-NEXT: v_readlane_b32 s35, v18, 3
-; SI-NEXT: v_readlane_b32 s34, v18, 2
-; SI-NEXT: v_readlane_b32 s31, v18, 1
-; SI-NEXT: v_readlane_b32 s30, v18, 0
+; SI-NEXT: v_readlane_b32 s31, v18, 16
+; SI-NEXT: v_readlane_b32 s64, v18, 14
+; SI-NEXT: v_readlane_b32 s55, v18, 13
+; SI-NEXT: v_readlane_b32 s54, v18, 12
+; SI-NEXT: v_readlane_b32 s53, v18, 11
+; SI-NEXT: v_readlane_b32 s52, v18, 10
+; SI-NEXT: v_readlane_b32 s51, v18, 9
+; SI-NEXT: v_readlane_b32 s50, v18, 8
+; SI-NEXT: v_readlane_b32 s49, v18, 7
+; SI-NEXT: v_readlane_b32 s48, v18, 6
+; SI-NEXT: v_readlane_b32 s39, v18, 5
+; SI-NEXT: v_readlane_b32 s38, v18, 4
+; SI-NEXT: v_readlane_b32 s37, v18, 3
+; SI-NEXT: v_readlane_b32 s36, v18, 2
+; SI-NEXT: v_readlane_b32 s35, v18, 1
+; SI-NEXT: v_readlane_b32 s34, v18, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
@@ -28453,14 +28453,14 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v30, s30, 0
-; VI-NEXT: v_writelane_b32 v30, s31, 1
-; VI-NEXT: v_writelane_b32 v30, s34, 2
-; VI-NEXT: v_writelane_b32 v30, s35, 3
-; VI-NEXT: v_writelane_b32 v30, s36, 4
-; VI-NEXT: v_writelane_b32 v30, s37, 5
+; VI-NEXT: v_writelane_b32 v30, s34, 0
+; VI-NEXT: v_writelane_b32 v30, s35, 1
+; VI-NEXT: v_writelane_b32 v30, s36, 2
+; VI-NEXT: v_writelane_b32 v30, s37, 3
+; VI-NEXT: v_writelane_b32 v30, s38, 4
+; VI-NEXT: v_writelane_b32 v30, s39, 5
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; VI-NEXT: v_writelane_b32 v30, s38, 6
+; VI-NEXT: v_writelane_b32 v30, s30, 6
; VI-NEXT: v_readfirstlane_b32 s45, v0
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: v_readfirstlane_b32 s43, v2
@@ -28478,7 +28478,7 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s6, v14
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v15
-; VI-NEXT: v_writelane_b32 v30, s39, 7
+; VI-NEXT: v_writelane_b32 v30, s31, 7
; VI-NEXT: s_cbranch_scc0 .LBB41_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s46, s7, 16
@@ -28664,6 +28664,7 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; VI-NEXT: s_and_b32 s7, 0xffff, s7
; VI-NEXT: s_lshl_b32 s44, s46, 16
; VI-NEXT: s_or_b32 s7, s7, s44
+; VI-NEXT: v_readlane_b32 s30, v30, 6
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s16
@@ -28694,14 +28695,13 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v27, s8
; VI-NEXT: v_mov_b32_e32 v28, s6
; VI-NEXT: v_mov_b32_e32 v29, s7
-; VI-NEXT: v_readlane_b32 s39, v30, 7
-; VI-NEXT: v_readlane_b32 s38, v30, 6
-; VI-NEXT: v_readlane_b32 s37, v30, 5
-; VI-NEXT: v_readlane_b32 s36, v30, 4
-; VI-NEXT: v_readlane_b32 s35, v30, 3
-; VI-NEXT: v_readlane_b32 s34, v30, 2
-; VI-NEXT: v_readlane_b32 s31, v30, 1
-; VI-NEXT: v_readlane_b32 s30, v30, 0
+; VI-NEXT: v_readlane_b32 s31, v30, 7
+; VI-NEXT: v_readlane_b32 s39, v30, 5
+; VI-NEXT: v_readlane_b32 s38, v30, 4
+; VI-NEXT: v_readlane_b32 s37, v30, 3
+; VI-NEXT: v_readlane_b32 s36, v30, 2
+; VI-NEXT: v_readlane_b32 s35, v30, 1
+; VI-NEXT: v_readlane_b32 s34, v30, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -28746,10 +28746,10 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v30, s30, 0
-; GFX9-NEXT: v_writelane_b32 v30, s31, 1
+; GFX9-NEXT: v_writelane_b32 v30, s34, 0
+; GFX9-NEXT: v_writelane_b32 v30, s35, 1
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; GFX9-NEXT: v_writelane_b32 v30, s34, 2
+; GFX9-NEXT: v_writelane_b32 v30, s30, 2
; GFX9-NEXT: v_readfirstlane_b32 s6, v0
; GFX9-NEXT: v_readfirstlane_b32 s7, v1
; GFX9-NEXT: v_readfirstlane_b32 s8, v2
@@ -28767,7 +28767,7 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s44, v14
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s45, v15
-; GFX9-NEXT: v_writelane_b32 v30, s35, 3
+; GFX9-NEXT: v_writelane_b32 v30, s31, 3
; GFX9-NEXT: s_cbranch_scc0 .LBB41_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s46, s45, 16
@@ -28893,6 +28893,7 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; GFX9-NEXT: s_pack_ll_b32_b16 s41, s43, s56
; GFX9-NEXT: s_pack_ll_b32_b16 s42, s44, s47
; GFX9-NEXT: s_pack_ll_b32_b16 s43, s45, s46
+; GFX9-NEXT: v_readlane_b32 s30, v30, 2
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s16
@@ -28923,10 +28924,9 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v27, s41
; GFX9-NEXT: v_mov_b32_e32 v28, s42
; GFX9-NEXT: v_mov_b32_e32 v29, s43
-; GFX9-NEXT: v_readlane_b32 s35, v30, 3
-; GFX9-NEXT: v_readlane_b32 s34, v30, 2
-; GFX9-NEXT: v_readlane_b32 s31, v30, 1
-; GFX9-NEXT: v_readlane_b32 s30, v30, 0
+; GFX9-NEXT: v_readlane_b32 s31, v30, 3
+; GFX9-NEXT: v_readlane_b32 s35, v30, 1
+; GFX9-NEXT: v_readlane_b32 s34, v30, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -33828,14 +33828,14 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
-; VI-NEXT: v_writelane_b32 v30, s30, 0
-; VI-NEXT: v_writelane_b32 v30, s31, 1
-; VI-NEXT: v_writelane_b32 v30, s34, 2
-; VI-NEXT: v_writelane_b32 v30, s35, 3
-; VI-NEXT: v_writelane_b32 v30, s36, 4
-; VI-NEXT: v_writelane_b32 v30, s37, 5
+; VI-NEXT: v_writelane_b32 v30, s34, 0
+; VI-NEXT: v_writelane_b32 v30, s35, 1
+; VI-NEXT: v_writelane_b32 v30, s36, 2
+; VI-NEXT: v_writelane_b32 v30, s37, 3
+; VI-NEXT: v_writelane_b32 v30, s38, 4
+; VI-NEXT: v_writelane_b32 v30, s39, 5
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; VI-NEXT: v_writelane_b32 v30, s38, 6
+; VI-NEXT: v_writelane_b32 v30, s30, 6
; VI-NEXT: v_readfirstlane_b32 s45, v0
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: v_readfirstlane_b32 s43, v2
@@ -33853,7 +33853,7 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s6, v14
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v15
-; VI-NEXT: v_writelane_b32 v30, s39, 7
+; VI-NEXT: v_writelane_b32 v30, s31, 7
; VI-NEXT: s_cbranch_scc0 .LBB45_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s46, s7, 16
@@ -34039,6 +34039,7 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i
; VI-NEXT: s_and_b32 s7, 0xffff, s7
; VI-NEXT: s_lshl_b32 s44, s46, 16
; VI-NEXT: s_or_b32 s7, s7, s44
+; VI-NEXT: v_readlane_b32 s30, v30, 6
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s16
@@ -34069,14 +34070,13 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i
; VI-NEXT: v_mov_b32_e32 v27, s8
; VI-NEXT: v_mov_b32_e32 v28, s6
; VI-NEXT: v_mov_b32_e32 v29, s7
-; VI-NEXT: v_readlane_b32 s39, v30, 7
-; VI-NEXT: v_readlane_b32 s38, v30, 6
-; VI-NEXT: v_readlane_b32 s37, v30, 5
-; VI-NEXT: v_readlane_b32 s36, v30, 4
-; VI-NEXT: v_readlane_b32 s35, v30, 3
-; VI-NEXT: v_readlane_b32 s34, v30, 2
-; VI-NEXT: v_readlane_b32 s31, v30, 1
-; VI-NEXT: v_readlane_b32 s30, v30, 0
+; VI-NEXT: v_readlane_b32 s31, v30, 7
+; VI-NEXT: v_readlane_b32 s39, v30, 5
+; VI-NEXT: v_readlane_b32 s38, v30, 4
+; VI-NEXT: v_readlane_b32 s37, v30, 3
+; VI-NEXT: v_readlane_b32 s36, v30, 2
+; VI-NEXT: v_readlane_b32 s35, v30, 1
+; VI-NEXT: v_readlane_b32 s34, v30, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
@@ -34121,10 +34121,10 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: v_writelane_b32 v30, s30, 0
-; GFX9-NEXT: v_writelane_b32 v30, s31, 1
+; GFX9-NEXT: v_writelane_b32 v30, s34, 0
+; GFX9-NEXT: v_writelane_b32 v30, s35, 1
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
-; GFX9-NEXT: v_writelane_b32 v30, s34, 2
+; GFX9-NEXT: v_writelane_b32 v30, s30, 2
; GFX9-NEXT: v_readfirstlane_b32 s6, v0
; GFX9-NEXT: v_readfirstlane_b32 s7, v1
; GFX9-NEXT: v_readfirstlane_b32 s8, v2
@@ -34142,7 +34142,7 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i
; GFX9-NEXT: v_readfirstlane_b32 s44, v14
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s45, v15
-; GFX9-NEXT: v_writelane_b32 v30, s35, 3
+; GFX9-NEXT: v_writelane_b32 v30, s31, 3
; GFX9-NEXT: s_cbranch_scc0 .LBB45_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s46, s45, 16
@@ -34268,6 +34268,7 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i
; GFX9-NEXT: s_pack_ll_b32_b16 s41, s43, s56
; GFX9-NEXT: s_pack_ll_b32_b16 s42, s44, s47
; GFX9-NEXT: s_pack_ll_b32_b16 s43, s45, s46
+; GFX9-NEXT: v_readlane_b32 s30, v30, 2
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s16
@@ -34298,10 +34299,9 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i
; GFX9-NEXT: v_mov_b32_e32 v27, s41
; GFX9-NEXT: v_mov_b32_e32 v28, s42
; GFX9-NEXT: v_mov_b32_e32 v29, s43
-; GFX9-NEXT: v_readlane_b32 s35, v30, 3
-; GFX9-NEXT: v_readlane_b32 s34, v30, 2
-; GFX9-NEXT: v_readlane_b32 s31, v30, 1
-; GFX9-NEXT: v_readlane_b32 s30, v30, 0
+; GFX9-NEXT: v_readlane_b32 s31, v30, 3
+; GFX9-NEXT: v_readlane_b32 s35, v30, 1
+; GFX9-NEXT: v_readlane_b32 s34, v30, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
index 0329f23ea434f..6bbfcc9f52d95 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
@@ -118,32 +118,32 @@ define double @test_pow_fast_f64__integral_y(double %x, i32 %y.i) {
; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
; CHECK-NEXT: v_writelane_b32 v43, s16, 14
-; CHECK-NEXT: v_writelane_b32 v43, s30, 0
-; CHECK-NEXT: v_writelane_b32 v43, s31, 1
-; CHECK-NEXT: v_writelane_b32 v43, s34, 2
-; CHECK-NEXT: v_writelane_b32 v43, s35, 3
-; CHECK-NEXT: v_writelane_b32 v43, s36, 4
-; CHECK-NEXT: v_writelane_b32 v43, s37, 5
-; CHECK-NEXT: v_writelane_b32 v43, s38, 6
-; CHECK-NEXT: v_writelane_b32 v43, s39, 7
+; CHECK-NEXT: v_writelane_b32 v43, s34, 0
+; CHECK-NEXT: v_writelane_b32 v43, s35, 1
+; CHECK-NEXT: v_writelane_b32 v43, s36, 2
+; CHECK-NEXT: v_writelane_b32 v43, s37, 3
+; CHECK-NEXT: v_writelane_b32 v43, s38, 4
+; CHECK-NEXT: v_writelane_b32 v43, s39, 5
; CHECK-NEXT: s_addk_i32 s32, 0x800
-; CHECK-NEXT: v_writelane_b32 v43, s48, 8
-; CHECK-NEXT: v_writelane_b32 v43, s49, 9
+; CHECK-NEXT: v_writelane_b32 v43, s48, 6
+; CHECK-NEXT: v_writelane_b32 v43, s49, 7
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d at gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d at gotpcrel32@hi+12
+; CHECK-NEXT: v_writelane_b32 v43, s50, 8
; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; CHECK-NEXT: v_writelane_b32 v43, s50, 10
+; CHECK-NEXT: v_writelane_b32 v43, s51, 9
+; CHECK-NEXT: v_writelane_b32 v43, s52, 10
; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
-; CHECK-NEXT: v_writelane_b32 v43, s51, 11
+; CHECK-NEXT: v_writelane_b32 v43, s53, 11
; CHECK-NEXT: v_mov_b32_e32 v42, v1
-; CHECK-NEXT: v_writelane_b32 v43, s52, 12
+; CHECK-NEXT: v_writelane_b32 v43, s30, 12
; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v42
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
-; CHECK-NEXT: v_writelane_b32 v43, s53, 13
+; CHECK-NEXT: v_writelane_b32 v43, s31, 13
; CHECK-NEXT: v_mov_b32_e32 v40, v31
; CHECK-NEXT: v_mov_b32_e32 v41, v2
; CHECK-NEXT: s_mov_b32 s50, s15
@@ -177,21 +177,21 @@ define double @test_pow_fast_f64__integral_y(double %x, i32 %y.i) {
; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; CHECK-NEXT: v_readlane_b32 s30, v43, 12
; CHECK-NEXT: v_or_b32_e32 v1, v2, v1
-; CHECK-NEXT: v_readlane_b32 s53, v43, 13
-; CHECK-NEXT: v_readlane_b32 s52, v43, 12
-; CHECK-NEXT: v_readlane_b32 s51, v43, 11
-; CHECK-NEXT: v_readlane_b32 s50, v43, 10
-; CHECK-NEXT: v_readlane_b32 s49, v43, 9
-; CHECK-NEXT: v_readlane_b32 s48, v43, 8
-; CHECK-NEXT: v_readlane_b32 s39, v43, 7
-; CHECK-NEXT: v_readlane_b32 s38, v43, 6
-; CHECK-NEXT: v_readlane_b32 s37, v43, 5
-; CHECK-NEXT: v_readlane_b32 s36, v43, 4
-; CHECK-NEXT: v_readlane_b32 s35, v43, 3
-; CHECK-NEXT: v_readlane_b32 s34, v43, 2
-; CHECK-NEXT: v_readlane_b32 s31, v43, 1
-; CHECK-NEXT: v_readlane_b32 s30, v43, 0
+; CHECK-NEXT: v_readlane_b32 s31, v43, 13
+; CHECK-NEXT: v_readlane_b32 s53, v43, 11
+; CHECK-NEXT: v_readlane_b32 s52, v43, 10
+; CHECK-NEXT: v_readlane_b32 s51, v43, 9
+; CHECK-NEXT: v_readlane_b32 s50, v43, 8
+; CHECK-NEXT: v_readlane_b32 s49, v43, 7
+; CHECK-NEXT: v_readlane_b32 s48, v43, 6
+; CHECK-NEXT: v_readlane_b32 s39, v43, 5
+; CHECK-NEXT: v_readlane_b32 s38, v43, 4
+; CHECK-NEXT: v_readlane_b32 s37, v43, 3
+; CHECK-NEXT: v_readlane_b32 s36, v43, 2
+; CHECK-NEXT: v_readlane_b32 s35, v43, 1
+; CHECK-NEXT: v_readlane_b32 s34, v43, 0
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: v_readlane_b32 s4, v43, 14
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -258,30 +258,30 @@ define double @test_powr_fast_f64(double %x, double %y) {
; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
; CHECK-NEXT: v_writelane_b32 v43, s16, 14
-; CHECK-NEXT: v_writelane_b32 v43, s30, 0
-; CHECK-NEXT: v_writelane_b32 v43, s31, 1
-; CHECK-NEXT: v_writelane_b32 v43, s34, 2
-; CHECK-NEXT: v_writelane_b32 v43, s35, 3
-; CHECK-NEXT: v_writelane_b32 v43, s36, 4
-; CHECK-NEXT: v_writelane_b32 v43, s37, 5
-; CHECK-NEXT: v_writelane_b32 v43, s38, 6
-; CHECK-NEXT: v_writelane_b32 v43, s39, 7
+; CHECK-NEXT: v_writelane_b32 v43, s34, 0
+; CHECK-NEXT: v_writelane_b32 v43, s35, 1
+; CHECK-NEXT: v_writelane_b32 v43, s36, 2
+; CHECK-NEXT: v_writelane_b32 v43, s37, 3
+; CHECK-NEXT: v_writelane_b32 v43, s38, 4
+; CHECK-NEXT: v_writelane_b32 v43, s39, 5
; CHECK-NEXT: s_addk_i32 s32, 0x800
-; CHECK-NEXT: v_writelane_b32 v43, s48, 8
-; CHECK-NEXT: v_writelane_b32 v43, s49, 9
+; CHECK-NEXT: v_writelane_b32 v43, s48, 6
+; CHECK-NEXT: v_writelane_b32 v43, s49, 7
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d at gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d at gotpcrel32@hi+12
+; CHECK-NEXT: v_writelane_b32 v43, s50, 8
; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; CHECK-NEXT: v_writelane_b32 v43, s50, 10
-; CHECK-NEXT: v_writelane_b32 v43, s51, 11
-; CHECK-NEXT: v_writelane_b32 v43, s52, 12
+; CHECK-NEXT: v_writelane_b32 v43, s51, 9
+; CHECK-NEXT: v_writelane_b32 v43, s52, 10
+; CHECK-NEXT: v_writelane_b32 v43, s53, 11
+; CHECK-NEXT: v_writelane_b32 v43, s30, 12
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
-; CHECK-NEXT: v_writelane_b32 v43, s53, 13
+; CHECK-NEXT: v_writelane_b32 v43, s31, 13
; CHECK-NEXT: v_mov_b32_e32 v42, v31
; CHECK-NEXT: v_mov_b32_e32 v41, v3
; CHECK-NEXT: v_mov_b32_e32 v40, v2
@@ -313,20 +313,20 @@ define double @test_powr_fast_f64(double %x, double %y) {
; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; CHECK-NEXT: v_readlane_b32 s53, v43, 13
-; CHECK-NEXT: v_readlane_b32 s52, v43, 12
-; CHECK-NEXT: v_readlane_b32 s51, v43, 11
-; CHECK-NEXT: v_readlane_b32 s50, v43, 10
-; CHECK-NEXT: v_readlane_b32 s49, v43, 9
-; CHECK-NEXT: v_readlane_b32 s48, v43, 8
-; CHECK-NEXT: v_readlane_b32 s39, v43, 7
-; CHECK-NEXT: v_readlane_b32 s38, v43, 6
-; CHECK-NEXT: v_readlane_b32 s37, v43, 5
-; CHECK-NEXT: v_readlane_b32 s36, v43, 4
-; CHECK-NEXT: v_readlane_b32 s35, v43, 3
-; CHECK-NEXT: v_readlane_b32 s34, v43, 2
-; CHECK-NEXT: v_readlane_b32 s31, v43, 1
-; CHECK-NEXT: v_readlane_b32 s30, v43, 0
+; CHECK-NEXT: v_readlane_b32 s30, v43, 12
+; CHECK-NEXT: v_readlane_b32 s31, v43, 13
+; CHECK-NEXT: v_readlane_b32 s53, v43, 11
+; CHECK-NEXT: v_readlane_b32 s52, v43, 10
+; CHECK-NEXT: v_readlane_b32 s51, v43, 9
+; CHECK-NEXT: v_readlane_b32 s50, v43, 8
+; CHECK-NEXT: v_readlane_b32 s49, v43, 7
+; CHECK-NEXT: v_readlane_b32 s48, v43, 6
+; CHECK-NEXT: v_readlane_b32 s39, v43, 5
+; CHECK-NEXT: v_readlane_b32 s38, v43, 4
+; CHECK-NEXT: v_readlane_b32 s37, v43, 3
+; CHECK-NEXT: v_readlane_b32 s36, v43, 2
+; CHECK-NEXT: v_readlane_b32 s35, v43, 1
+; CHECK-NEXT: v_readlane_b32 s34, v43, 0
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: v_readlane_b32 s4, v43, 14
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -400,32 +400,32 @@ define double @test_pown_fast_f64(double %x, i32 %y) {
; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
; CHECK-NEXT: v_writelane_b32 v43, s16, 14
-; CHECK-NEXT: v_writelane_b32 v43, s30, 0
-; CHECK-NEXT: v_writelane_b32 v43, s31, 1
-; CHECK-NEXT: v_writelane_b32 v43, s34, 2
-; CHECK-NEXT: v_writelane_b32 v43, s35, 3
-; CHECK-NEXT: v_writelane_b32 v43, s36, 4
-; CHECK-NEXT: v_writelane_b32 v43, s37, 5
-; CHECK-NEXT: v_writelane_b32 v43, s38, 6
-; CHECK-NEXT: v_writelane_b32 v43, s39, 7
+; CHECK-NEXT: v_writelane_b32 v43, s34, 0
+; CHECK-NEXT: v_writelane_b32 v43, s35, 1
+; CHECK-NEXT: v_writelane_b32 v43, s36, 2
+; CHECK-NEXT: v_writelane_b32 v43, s37, 3
+; CHECK-NEXT: v_writelane_b32 v43, s38, 4
+; CHECK-NEXT: v_writelane_b32 v43, s39, 5
; CHECK-NEXT: s_addk_i32 s32, 0x800
-; CHECK-NEXT: v_writelane_b32 v43, s48, 8
-; CHECK-NEXT: v_writelane_b32 v43, s49, 9
+; CHECK-NEXT: v_writelane_b32 v43, s48, 6
+; CHECK-NEXT: v_writelane_b32 v43, s49, 7
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d at gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d at gotpcrel32@hi+12
+; CHECK-NEXT: v_writelane_b32 v43, s50, 8
; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; CHECK-NEXT: v_writelane_b32 v43, s50, 10
+; CHECK-NEXT: v_writelane_b32 v43, s51, 9
+; CHECK-NEXT: v_writelane_b32 v43, s52, 10
; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
-; CHECK-NEXT: v_writelane_b32 v43, s51, 11
+; CHECK-NEXT: v_writelane_b32 v43, s53, 11
; CHECK-NEXT: v_mov_b32_e32 v42, v1
-; CHECK-NEXT: v_writelane_b32 v43, s52, 12
+; CHECK-NEXT: v_writelane_b32 v43, s30, 12
; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v42
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
-; CHECK-NEXT: v_writelane_b32 v43, s53, 13
+; CHECK-NEXT: v_writelane_b32 v43, s31, 13
; CHECK-NEXT: v_mov_b32_e32 v40, v31
; CHECK-NEXT: v_mov_b32_e32 v41, v2
; CHECK-NEXT: s_mov_b32 s50, s15
@@ -459,21 +459,21 @@ define double @test_pown_fast_f64(double %x, i32 %y) {
; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; CHECK-NEXT: v_readlane_b32 s30, v43, 12
; CHECK-NEXT: v_or_b32_e32 v1, v2, v1
-; CHECK-NEXT: v_readlane_b32 s53, v43, 13
-; CHECK-NEXT: v_readlane_b32 s52, v43, 12
-; CHECK-NEXT: v_readlane_b32 s51, v43, 11
-; CHECK-NEXT: v_readlane_b32 s50, v43, 10
-; CHECK-NEXT: v_readlane_b32 s49, v43, 9
-; CHECK-NEXT: v_readlane_b32 s48, v43, 8
-; CHECK-NEXT: v_readlane_b32 s39, v43, 7
-; CHECK-NEXT: v_readlane_b32 s38, v43, 6
-; CHECK-NEXT: v_readlane_b32 s37, v43, 5
-; CHECK-NEXT: v_readlane_b32 s36, v43, 4
-; CHECK-NEXT: v_readlane_b32 s35, v43, 3
-; CHECK-NEXT: v_readlane_b32 s34, v43, 2
-; CHECK-NEXT: v_readlane_b32 s31, v43, 1
-; CHECK-NEXT: v_readlane_b32 s30, v43, 0
+; CHECK-NEXT: v_readlane_b32 s31, v43, 13
+; CHECK-NEXT: v_readlane_b32 s53, v43, 11
+; CHECK-NEXT: v_readlane_b32 s52, v43, 10
+; CHECK-NEXT: v_readlane_b32 s51, v43, 9
+; CHECK-NEXT: v_readlane_b32 s50, v43, 8
+; CHECK-NEXT: v_readlane_b32 s49, v43, 7
+; CHECK-NEXT: v_readlane_b32 s48, v43, 6
+; CHECK-NEXT: v_readlane_b32 s39, v43, 5
+; CHECK-NEXT: v_readlane_b32 s38, v43, 4
+; CHECK-NEXT: v_readlane_b32 s37, v43, 3
+; CHECK-NEXT: v_readlane_b32 s36, v43, 2
+; CHECK-NEXT: v_readlane_b32 s35, v43, 1
+; CHECK-NEXT: v_readlane_b32 s34, v43, 0
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: v_readlane_b32 s4, v43, 14
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -542,30 +542,30 @@ define double @test_pown_fast_f64_known_even(double %x, i32 %y.arg) {
; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
; CHECK-NEXT: v_writelane_b32 v42, s16, 14
-; CHECK-NEXT: v_writelane_b32 v42, s30, 0
-; CHECK-NEXT: v_writelane_b32 v42, s31, 1
-; CHECK-NEXT: v_writelane_b32 v42, s34, 2
-; CHECK-NEXT: v_writelane_b32 v42, s35, 3
-; CHECK-NEXT: v_writelane_b32 v42, s36, 4
-; CHECK-NEXT: v_writelane_b32 v42, s37, 5
-; CHECK-NEXT: v_writelane_b32 v42, s38, 6
-; CHECK-NEXT: v_writelane_b32 v42, s39, 7
+; CHECK-NEXT: v_writelane_b32 v42, s34, 0
+; CHECK-NEXT: v_writelane_b32 v42, s35, 1
+; CHECK-NEXT: v_writelane_b32 v42, s36, 2
+; CHECK-NEXT: v_writelane_b32 v42, s37, 3
+; CHECK-NEXT: v_writelane_b32 v42, s38, 4
+; CHECK-NEXT: v_writelane_b32 v42, s39, 5
; CHECK-NEXT: s_addk_i32 s32, 0x400
-; CHECK-NEXT: v_writelane_b32 v42, s48, 8
-; CHECK-NEXT: v_writelane_b32 v42, s49, 9
+; CHECK-NEXT: v_writelane_b32 v42, s48, 6
+; CHECK-NEXT: v_writelane_b32 v42, s49, 7
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d at gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d at gotpcrel32@hi+12
+; CHECK-NEXT: v_writelane_b32 v42, s50, 8
; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; CHECK-NEXT: v_writelane_b32 v42, s50, 10
-; CHECK-NEXT: v_writelane_b32 v42, s51, 11
-; CHECK-NEXT: v_writelane_b32 v42, s52, 12
+; CHECK-NEXT: v_writelane_b32 v42, s51, 9
+; CHECK-NEXT: v_writelane_b32 v42, s52, 10
+; CHECK-NEXT: v_writelane_b32 v42, s53, 11
+; CHECK-NEXT: v_writelane_b32 v42, s30, 12
; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; CHECK-NEXT: v_writelane_b32 v42, s53, 13
+; CHECK-NEXT: v_writelane_b32 v42, s31, 13
; CHECK-NEXT: v_mov_b32_e32 v40, v31
; CHECK-NEXT: s_mov_b32 s50, s15
; CHECK-NEXT: s_mov_b32 s51, s14
@@ -596,20 +596,20 @@ define double @test_pown_fast_f64_known_even(double %x, i32 %y.arg) {
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; CHECK-NEXT: v_readlane_b32 s53, v42, 13
-; CHECK-NEXT: v_readlane_b32 s52, v42, 12
-; CHECK-NEXT: v_readlane_b32 s51, v42, 11
-; CHECK-NEXT: v_readlane_b32 s50, v42, 10
-; CHECK-NEXT: v_readlane_b32 s49, v42, 9
-; CHECK-NEXT: v_readlane_b32 s48, v42, 8
-; CHECK-NEXT: v_readlane_b32 s39, v42, 7
-; CHECK-NEXT: v_readlane_b32 s38, v42, 6
-; CHECK-NEXT: v_readlane_b32 s37, v42, 5
-; CHECK-NEXT: v_readlane_b32 s36, v42, 4
-; CHECK-NEXT: v_readlane_b32 s35, v42, 3
-; CHECK-NEXT: v_readlane_b32 s34, v42, 2
-; CHECK-NEXT: v_readlane_b32 s31, v42, 1
-; CHECK-NEXT: v_readlane_b32 s30, v42, 0
+; CHECK-NEXT: v_readlane_b32 s30, v42, 12
+; CHECK-NEXT: v_readlane_b32 s31, v42, 13
+; CHECK-NEXT: v_readlane_b32 s53, v42, 11
+; CHECK-NEXT: v_readlane_b32 s52, v42, 10
+; CHECK-NEXT: v_readlane_b32 s51, v42, 9
+; CHECK-NEXT: v_readlane_b32 s50, v42, 8
+; CHECK-NEXT: v_readlane_b32 s49, v42, 7
+; CHECK-NEXT: v_readlane_b32 s48, v42, 6
+; CHECK-NEXT: v_readlane_b32 s39, v42, 5
+; CHECK-NEXT: v_readlane_b32 s38, v42, 4
+; CHECK-NEXT: v_readlane_b32 s37, v42, 3
+; CHECK-NEXT: v_readlane_b32 s36, v42, 2
+; CHECK-NEXT: v_readlane_b32 s35, v42, 1
+; CHECK-NEXT: v_readlane_b32 s34, v42, 0
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: v_readlane_b32 s4, v42, 14
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -683,32 +683,32 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) {
; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
; CHECK-NEXT: v_writelane_b32 v43, s16, 14
-; CHECK-NEXT: v_writelane_b32 v43, s30, 0
-; CHECK-NEXT: v_writelane_b32 v43, s31, 1
-; CHECK-NEXT: v_writelane_b32 v43, s34, 2
-; CHECK-NEXT: v_writelane_b32 v43, s35, 3
-; CHECK-NEXT: v_writelane_b32 v43, s36, 4
-; CHECK-NEXT: v_writelane_b32 v43, s37, 5
-; CHECK-NEXT: v_writelane_b32 v43, s38, 6
-; CHECK-NEXT: v_writelane_b32 v43, s39, 7
+; CHECK-NEXT: v_writelane_b32 v43, s34, 0
+; CHECK-NEXT: v_writelane_b32 v43, s35, 1
+; CHECK-NEXT: v_writelane_b32 v43, s36, 2
+; CHECK-NEXT: v_writelane_b32 v43, s37, 3
+; CHECK-NEXT: v_writelane_b32 v43, s38, 4
+; CHECK-NEXT: v_writelane_b32 v43, s39, 5
; CHECK-NEXT: s_addk_i32 s32, 0x800
-; CHECK-NEXT: v_writelane_b32 v43, s48, 8
-; CHECK-NEXT: v_writelane_b32 v43, s49, 9
+; CHECK-NEXT: v_writelane_b32 v43, s48, 6
+; CHECK-NEXT: v_writelane_b32 v43, s49, 7
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d at gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d at gotpcrel32@hi+12
+; CHECK-NEXT: v_writelane_b32 v43, s50, 8
; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; CHECK-NEXT: v_writelane_b32 v43, s50, 10
+; CHECK-NEXT: v_writelane_b32 v43, s51, 9
+; CHECK-NEXT: v_writelane_b32 v43, s52, 10
; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
-; CHECK-NEXT: v_writelane_b32 v43, s51, 11
+; CHECK-NEXT: v_writelane_b32 v43, s53, 11
; CHECK-NEXT: v_mov_b32_e32 v41, v1
-; CHECK-NEXT: v_writelane_b32 v43, s52, 12
+; CHECK-NEXT: v_writelane_b32 v43, s30, 12
; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v41
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
-; CHECK-NEXT: v_writelane_b32 v43, s53, 13
+; CHECK-NEXT: v_writelane_b32 v43, s31, 13
; CHECK-NEXT: v_mov_b32_e32 v40, v31
; CHECK-NEXT: s_mov_b32 s50, s15
; CHECK-NEXT: s_mov_b32 s51, s14
@@ -741,21 +741,21 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) {
; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; CHECK-NEXT: v_readlane_b32 s30, v43, 12
; CHECK-NEXT: v_or_b32_e32 v1, v2, v1
-; CHECK-NEXT: v_readlane_b32 s53, v43, 13
-; CHECK-NEXT: v_readlane_b32 s52, v43, 12
-; CHECK-NEXT: v_readlane_b32 s51, v43, 11
-; CHECK-NEXT: v_readlane_b32 s50, v43, 10
-; CHECK-NEXT: v_readlane_b32 s49, v43, 9
-; CHECK-NEXT: v_readlane_b32 s48, v43, 8
-; CHECK-NEXT: v_readlane_b32 s39, v43, 7
-; CHECK-NEXT: v_readlane_b32 s38, v43, 6
-; CHECK-NEXT: v_readlane_b32 s37, v43, 5
-; CHECK-NEXT: v_readlane_b32 s36, v43, 4
-; CHECK-NEXT: v_readlane_b32 s35, v43, 3
-; CHECK-NEXT: v_readlane_b32 s34, v43, 2
-; CHECK-NEXT: v_readlane_b32 s31, v43, 1
-; CHECK-NEXT: v_readlane_b32 s30, v43, 0
+; CHECK-NEXT: v_readlane_b32 s31, v43, 13
+; CHECK-NEXT: v_readlane_b32 s53, v43, 11
+; CHECK-NEXT: v_readlane_b32 s52, v43, 10
+; CHECK-NEXT: v_readlane_b32 s51, v43, 9
+; CHECK-NEXT: v_readlane_b32 s50, v43, 8
+; CHECK-NEXT: v_readlane_b32 s49, v43, 7
+; CHECK-NEXT: v_readlane_b32 s48, v43, 6
+; CHECK-NEXT: v_readlane_b32 s39, v43, 5
+; CHECK-NEXT: v_readlane_b32 s38, v43, 4
+; CHECK-NEXT: v_readlane_b32 s37, v43, 3
+; CHECK-NEXT: v_readlane_b32 s36, v43, 2
+; CHECK-NEXT: v_readlane_b32 s35, v43, 1
+; CHECK-NEXT: v_readlane_b32 s34, v43, 0
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: v_readlane_b32 s4, v43, 14
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
index 583b6fe0a81ca..3bed751c979c3 100644
--- a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
+++ b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
@@ -214,8 +214,8 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
; GFX8-NEXT: v_writelane_b32 v3, s31, 1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX8-NEXT: v_readlane_b32 s31, v3, 1
; GFX8-NEXT: v_readlane_b32 s30, v3, 0
+; GFX8-NEXT: v_readlane_b32 s31, v3, 1
; GFX8-NEXT: s_mov_b32 s32, s33
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -242,8 +242,8 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
; GFX8-ARCH-FLAT-NEXT: v_writelane_b32 v3, s31, 1
; GFX8-ARCH-FLAT-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-ARCH-FLAT-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX8-ARCH-FLAT-NEXT: v_readlane_b32 s31, v3, 1
; GFX8-ARCH-FLAT-NEXT: v_readlane_b32 s30, v3, 0
+; GFX8-ARCH-FLAT-NEXT: v_readlane_b32 s31, v3, 1
; GFX8-ARCH-FLAT-NEXT: s_mov_b32 s32, s33
; GFX8-ARCH-FLAT-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX8-ARCH-FLAT-NEXT: s_add_i32 s3, s33, 8
@@ -270,8 +270,8 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
; GFX9-NEXT: v_writelane_b32 v3, s31, 1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX9-NEXT: v_readlane_b32 s31, v3, 1
; GFX9-NEXT: v_readlane_b32 s30, v3, 0
+; GFX9-NEXT: v_readlane_b32 s31, v3, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -297,8 +297,8 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
; GFX9-ARCH-FLAT-NEXT: v_writelane_b32 v3, s31, 1
; GFX9-ARCH-FLAT-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-ARCH-FLAT-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX9-ARCH-FLAT-NEXT: v_readlane_b32 s31, v3, 1
; GFX9-ARCH-FLAT-NEXT: v_readlane_b32 s30, v3, 0
+; GFX9-ARCH-FLAT-NEXT: v_readlane_b32 s31, v3, 1
; GFX9-ARCH-FLAT-NEXT: s_mov_b32 s32, s33
; GFX9-ARCH-FLAT-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX9-ARCH-FLAT-NEXT: scratch_load_dword v3, off, s33 ; 4-byte Folded Reload
@@ -321,11 +321,12 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
; GFX942-ARCH-FLAT-NEXT: s_addc_u32 s1, s1, with_private_to_flat_addrspacecast at gotpcrel32@hi+12
; GFX942-ARCH-FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX942-ARCH-FLAT-NEXT: v_writelane_b32 v3, s30, 0
+; GFX942-ARCH-FLAT-NEXT: s_nop 1
; GFX942-ARCH-FLAT-NEXT: v_writelane_b32 v3, s31, 1
; GFX942-ARCH-FLAT-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-ARCH-FLAT-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX942-ARCH-FLAT-NEXT: v_readlane_b32 s31, v3, 1
; GFX942-ARCH-FLAT-NEXT: v_readlane_b32 s30, v3, 0
+; GFX942-ARCH-FLAT-NEXT: v_readlane_b32 s31, v3, 1
; GFX942-ARCH-FLAT-NEXT: s_mov_b32 s32, s33
; GFX942-ARCH-FLAT-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-ARCH-FLAT-NEXT: scratch_load_dword v3, off, s33 ; 4-byte Folded Reload
@@ -352,8 +353,8 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
; GFX10-NEXT: v_writelane_b32 v3, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX10-NEXT: v_readlane_b32 s31, v3, 1
; GFX10-NEXT: v_readlane_b32 s30, v3, 0
+; GFX10-NEXT: v_readlane_b32 s31, v3, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index 30ad46d959b7e..ec430bb443b21 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -4392,8 +4392,8 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GCN-NEXT: buffer_store_short v0, v1, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readlane_b32 s31, v2, 1
; GCN-NEXT: v_readlane_b32 s30, v2, 0
+; GCN-NEXT: v_readlane_b32 s31, v2, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -4421,10 +4421,10 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-NEXT: v_readlane_b32 s30, v2, 0
; GFX7-NEXT: buffer_store_short v0, v1, s[0:3], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_readlane_b32 s31, v2, 1
-; GFX7-NEXT: v_readlane_b32 s30, v2, 0
; GFX7-NEXT: s_mov_b32 s32, s33
; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX7-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -4450,10 +4450,10 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX8-NEXT: v_writelane_b32 v2, s31, 1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GFX8-NEXT: v_readlane_b32 s30, v2, 0
; GFX8-NEXT: buffer_store_short v0, v1, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_readlane_b32 s31, v2, 1
-; GFX8-NEXT: v_readlane_b32 s30, v2, 0
; GFX8-NEXT: s_mov_b32 s32, s33
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -4479,10 +4479,10 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX900-NEXT: v_writelane_b32 v2, s31, 1
; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GFX900-NEXT: v_readlane_b32 s30, v2, 0
; GFX900-NEXT: buffer_store_short v0, v1, s[0:3], 0 offen
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_readlane_b32 s31, v2, 1
-; GFX900-NEXT: v_readlane_b32 s30, v2, 0
; GFX900-NEXT: s_mov_b32 s32, s33
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -4505,13 +4505,14 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store at gotpcrel32@hi+12
; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX950-NEXT: v_writelane_b32 v4, s30, 0
+; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_writelane_b32 v4, s31, 1
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX950-NEXT: v_readlane_b32 s30, v4, 0
; GFX950-NEXT: scratch_store_short v1, v0, off sc0 sc1
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_readlane_b32 s31, v4, 1
-; GFX950-NEXT: v_readlane_b32 s30, v4, 0
; GFX950-NEXT: s_mov_b32 s32, s33
; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX950-NEXT: scratch_load_dword v4, off, s33 ; 4-byte Folded Reload
@@ -4538,10 +4539,10 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX10-NEXT: v_writelane_b32 v2, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GFX10-NEXT: v_readlane_b32 s30, v2, 0
; GFX10-NEXT: buffer_store_short v0, v1, s[0:3], 0 offen
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_readlane_b32 s31, v2, 1
-; GFX10-NEXT: v_readlane_b32 s30, v2, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -4568,10 +4569,11 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX11-NEXT: v_writelane_b32 v2, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readlane_b32 s30, v2, 0
; GFX11-NEXT: scratch_store_b16 v1, v0, off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_readlane_b32 s31, v2, 1
-; GFX11-NEXT: v_readlane_b32 s30, v2, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v2, off, s33 ; 4-byte Folded Reload
@@ -4598,10 +4600,11 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX1250-NEXT: v_writelane_b32 v4, s31, 1
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_readlane_b32 s30, v4, 0
; GFX1250-NEXT: scratch_store_b16 v1, v0, off scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: v_readlane_b32 s31, v4, 1
-; GFX1250-NEXT: v_readlane_b32 s30, v4, 0
; GFX1250-NEXT: s_mov_b32 s32, s33
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1
@@ -4645,8 +4648,8 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_short v0, v2, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readlane_b32 s31, v4, 1
; GCN-NEXT: v_readlane_b32 s30, v4, 0
+; GCN-NEXT: v_readlane_b32 s31, v4, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -4676,13 +4679,13 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX7-NEXT: v_add_i32_e32 v3, vcc, 2, v2
+; GFX7-NEXT: v_readlane_b32 s30, v4, 0
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7-NEXT: buffer_store_short v1, v3, s[0:3], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: buffer_store_short v0, v2, s[0:3], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_readlane_b32 s31, v4, 1
-; GFX7-NEXT: v_readlane_b32 s30, v4, 0
; GFX7-NEXT: s_mov_b32 s32, s33
; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX7-NEXT: buffer_load_dword v4, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -4708,10 +4711,10 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX8-NEXT: v_writelane_b32 v2, s31, 1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GFX8-NEXT: v_readlane_b32 s30, v2, 0
; GFX8-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_readlane_b32 s31, v2, 1
-; GFX8-NEXT: v_readlane_b32 s30, v2, 0
; GFX8-NEXT: s_mov_b32 s32, s33
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -4737,10 +4740,10 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX900-NEXT: v_writelane_b32 v2, s31, 1
; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GFX900-NEXT: v_readlane_b32 s30, v2, 0
; GFX900-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_readlane_b32 s31, v2, 1
-; GFX900-NEXT: v_readlane_b32 s30, v2, 0
; GFX900-NEXT: s_mov_b32 s32, s33
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -4763,13 +4766,14 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX950-NEXT: v_writelane_b32 v4, s30, 0
+; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_writelane_b32 v4, s31, 1
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX950-NEXT: v_readlane_b32 s30, v4, 0
; GFX950-NEXT: scratch_store_dword v1, v0, off sc0 sc1
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_readlane_b32 s31, v4, 1
-; GFX950-NEXT: v_readlane_b32 s30, v4, 0
; GFX950-NEXT: s_mov_b32 s32, s33
; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX950-NEXT: scratch_load_dword v4, off, s33 ; 4-byte Folded Reload
@@ -4796,10 +4800,10 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: v_writelane_b32 v2, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GFX10-NEXT: v_readlane_b32 s30, v2, 0
; GFX10-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_readlane_b32 s31, v2, 1
-; GFX10-NEXT: v_readlane_b32 s30, v2, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -4826,10 +4830,11 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX11-NEXT: v_writelane_b32 v2, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readlane_b32 s30, v2, 0
; GFX11-NEXT: scratch_store_b32 v1, v0, off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_readlane_b32 s31, v2, 1
-; GFX11-NEXT: v_readlane_b32 s30, v2, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v2, off, s33 ; 4-byte Folded Reload
@@ -4856,10 +4861,11 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX1250-NEXT: v_writelane_b32 v4, s31, 1
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_readlane_b32 s30, v4, 0
; GFX1250-NEXT: scratch_store_b32 v1, v0, off scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: v_readlane_b32 s31, v4, 1
-; GFX1250-NEXT: v_readlane_b32 s30, v4, 0
; GFX1250-NEXT: s_mov_b32 s32, s33
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1
@@ -4905,8 +4911,8 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v0, v3, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readlane_b32 s31, v5, 1
; GCN-NEXT: v_readlane_b32 s30, v5, 0
+; GCN-NEXT: v_readlane_b32 s31, v5, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -4939,12 +4945,12 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v2
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX7-NEXT: v_add_i32_e32 v2, vcc, 4, v3
+; GFX7-NEXT: v_readlane_b32 s30, v4, 0
; GFX7-NEXT: buffer_store_short v1, v2, s[0:3], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: buffer_store_dword v0, v3, s[0:3], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_readlane_b32 s31, v4, 1
-; GFX7-NEXT: v_readlane_b32 s30, v4, 0
; GFX7-NEXT: s_mov_b32 s32, s33
; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX7-NEXT: buffer_load_dword v4, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -4971,12 +4977,12 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 4, v2
+; GFX8-NEXT: v_readlane_b32 s30, v4, 0
; GFX8-NEXT: buffer_store_short v1, v3, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_readlane_b32 s31, v4, 1
-; GFX8-NEXT: v_readlane_b32 s30, v4, 0
; GFX8-NEXT: s_mov_b32 s32, s33
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: buffer_load_dword v4, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -5002,12 +5008,12 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX900-NEXT: v_writelane_b32 v3, s31, 1
; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GFX900-NEXT: v_readlane_b32 s30, v3, 0
; GFX900-NEXT: buffer_store_short v1, v2, s[0:3], 0 offen offset:4
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_readlane_b32 s31, v3, 1
-; GFX900-NEXT: v_readlane_b32 s30, v3, 0
; GFX900-NEXT: s_mov_b32 s32, s33
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -5030,16 +5036,17 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX950-NEXT: v_writelane_b32 v5, s30, 0
-; GFX950-NEXT: v_writelane_b32 v5, s31, 1
; GFX950-NEXT: v_mov_b32_e32 v4, v2
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_writelane_b32 v5, s31, 1
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX950-NEXT: v_readlane_b32 s30, v5, 0
; GFX950-NEXT: scratch_store_short v4, v1, off offset:4 sc0 sc1
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: scratch_store_dword v4, v0, off sc0 sc1
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_readlane_b32 s31, v5, 1
-; GFX950-NEXT: v_readlane_b32 s30, v5, 0
; GFX950-NEXT: s_mov_b32 s32, s33
; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX950-NEXT: scratch_load_dword v5, off, s33 ; 4-byte Folded Reload
@@ -5066,12 +5073,12 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: v_writelane_b32 v3, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GFX10-NEXT: v_readlane_b32 s30, v3, 0
; GFX10-NEXT: buffer_store_short v1, v2, s[0:3], 0 offen offset:4
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_readlane_b32 s31, v3, 1
-; GFX10-NEXT: v_readlane_b32 s30, v3, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -5098,12 +5105,13 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX11-NEXT: v_writelane_b32 v3, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readlane_b32 s30, v3, 0
; GFX11-NEXT: scratch_store_b16 v2, v1, off offset:4 dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: scratch_store_b32 v2, v0, off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_readlane_b32 s31, v3, 1
-; GFX11-NEXT: v_readlane_b32 s30, v3, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v3, off, s33 ; 4-byte Folded Reload
@@ -5131,12 +5139,13 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX1250-NEXT: v_writelane_b32 v5, s31, 1
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_readlane_b32 s30, v5, 0
; GFX1250-NEXT: scratch_store_b16 v4, v1, off offset:4 scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: scratch_store_b32 v4, v0, off scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: v_readlane_b32 s31, v5, 1
-; GFX1250-NEXT: v_readlane_b32 s30, v5, 0
; GFX1250-NEXT: s_mov_b32 s32, s33
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1
@@ -5190,8 +5199,8 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_short v0, v4, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readlane_b32 s31, v8, 1
; GCN-NEXT: v_readlane_b32 s30, v8, 0
+; GCN-NEXT: v_readlane_b32 s31, v8, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GCN-NEXT: buffer_load_dword v8, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -5231,13 +5240,13 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX7-NEXT: buffer_store_short v2, v3, s[0:3], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_add_i32_e32 v2, vcc, 2, v4
+; GFX7-NEXT: v_readlane_b32 s30, v6, 0
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7-NEXT: buffer_store_short v1, v2, s[0:3], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: buffer_store_short v0, v4, s[0:3], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_readlane_b32 s31, v6, 1
-; GFX7-NEXT: v_readlane_b32 s30, v6, 0
; GFX7-NEXT: s_mov_b32 s32, s33
; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX7-NEXT: buffer_load_dword v6, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -5264,12 +5273,12 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 4, v2
+; GFX8-NEXT: v_readlane_b32 s30, v4, 0
; GFX8-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_readlane_b32 s31, v4, 1
-; GFX8-NEXT: v_readlane_b32 s30, v4, 0
; GFX8-NEXT: s_mov_b32 s32, s33
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: buffer_load_dword v4, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -5295,12 +5304,12 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX900-NEXT: v_writelane_b32 v3, s31, 1
; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GFX900-NEXT: v_readlane_b32 s30, v3, 0
; GFX900-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:4
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_readlane_b32 s31, v3, 1
-; GFX900-NEXT: v_readlane_b32 s30, v3, 0
; GFX900-NEXT: s_mov_b32 s32, s33
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -5323,14 +5332,15 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX950-NEXT: v_writelane_b32 v5, s30, 0
-; GFX950-NEXT: v_writelane_b32 v5, s31, 1
; GFX950-NEXT: v_mov_b32_e32 v4, v2
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_writelane_b32 v5, s31, 1
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX950-NEXT: v_readlane_b32 s30, v5, 0
; GFX950-NEXT: scratch_store_dwordx2 v4, v[0:1], off sc0 sc1
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_readlane_b32 s31, v5, 1
-; GFX950-NEXT: v_readlane_b32 s30, v5, 0
; GFX950-NEXT: s_mov_b32 s32, s33
; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX950-NEXT: scratch_load_dword v5, off, s33 ; 4-byte Folded Reload
@@ -5357,12 +5367,12 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: v_writelane_b32 v3, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GFX10-NEXT: v_readlane_b32 s30, v3, 0
; GFX10-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:4
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_readlane_b32 s31, v3, 1
-; GFX10-NEXT: v_readlane_b32 s30, v3, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -5389,10 +5399,11 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX11-NEXT: v_writelane_b32 v3, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readlane_b32 s30, v3, 0
; GFX11-NEXT: scratch_store_b64 v2, v[0:1], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_readlane_b32 s31, v3, 1
-; GFX11-NEXT: v_readlane_b32 s30, v3, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v3, off, s33 ; 4-byte Folded Reload
@@ -5420,10 +5431,11 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX1250-NEXT: v_writelane_b32 v5, s31, 1
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_readlane_b32 s30, v5, 0
; GFX1250-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: v_readlane_b32 s31, v5, 1
-; GFX1250-NEXT: v_readlane_b32 s30, v5, 0
; GFX1250-NEXT: s_mov_b32 s32, s33
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1
@@ -5497,8 +5509,8 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_short v0, v8, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readlane_b32 s31, v16, 1
; GCN-NEXT: v_readlane_b32 s30, v16, 0
+; GCN-NEXT: v_readlane_b32 s31, v16, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -5558,13 +5570,13 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX7-NEXT: buffer_store_short v2, v3, s[0:3], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_add_i32_e32 v2, vcc, 2, v8
+; GFX7-NEXT: v_readlane_b32 s30, v10, 0
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7-NEXT: buffer_store_short v1, v2, s[0:3], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: buffer_store_short v0, v8, s[0:3], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_readlane_b32 s31, v10, 1
-; GFX7-NEXT: v_readlane_b32 s30, v10, 0
; GFX7-NEXT: s_mov_b32 s32, s33
; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX7-NEXT: buffer_load_dword v10, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -5597,12 +5609,12 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX8-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v4
+; GFX8-NEXT: v_readlane_b32 s30, v6, 0
; GFX8-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_readlane_b32 s31, v6, 1
-; GFX8-NEXT: v_readlane_b32 s30, v6, 0
; GFX8-NEXT: s_mov_b32 s32, s33
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: buffer_load_dword v6, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -5628,6 +5640,7 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX900-NEXT: v_writelane_b32 v5, s31, 1
; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GFX900-NEXT: v_readlane_b32 s30, v5, 0
; GFX900-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:12
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen offset:8
@@ -5637,7 +5650,6 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX900-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_readlane_b32 s31, v5, 1
-; GFX900-NEXT: v_readlane_b32 s30, v5, 0
; GFX900-NEXT: s_mov_b32 s32, s33
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v5, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -5660,13 +5672,14 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX950-NEXT: v_writelane_b32 v5, s30, 0
+; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_writelane_b32 v5, s31, 1
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX950-NEXT: v_readlane_b32 s30, v5, 0
; GFX950-NEXT: scratch_store_dwordx4 v4, v[0:3], off sc0 sc1
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_readlane_b32 s31, v5, 1
-; GFX950-NEXT: v_readlane_b32 s30, v5, 0
; GFX950-NEXT: s_mov_b32 s32, s33
; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX950-NEXT: scratch_load_dword v5, off, s33 ; 4-byte Folded Reload
@@ -5693,6 +5706,7 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: v_writelane_b32 v5, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GFX10-NEXT: v_readlane_b32 s30, v5, 0
; GFX10-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:12
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen offset:8
@@ -5702,7 +5716,6 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_readlane_b32 s31, v5, 1
-; GFX10-NEXT: v_readlane_b32 s30, v5, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v5, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -5729,10 +5742,11 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX11-NEXT: v_writelane_b32 v5, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readlane_b32 s30, v5, 0
; GFX11-NEXT: scratch_store_b128 v4, v[0:3], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_readlane_b32 s31, v5, 1
-; GFX11-NEXT: v_readlane_b32 s30, v5, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v5, off, s33 ; 4-byte Folded Reload
@@ -5759,10 +5773,11 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX1250-NEXT: v_writelane_b32 v5, s31, 1
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_readlane_b32 s30, v5, 0
; GFX1250-NEXT: scratch_store_b128 v4, v[0:3], off scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: v_readlane_b32 s31, v5, 1
-; GFX1250-NEXT: v_readlane_b32 s30, v5, 0
; GFX1250-NEXT: s_mov_b32 s32, s33
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1
@@ -5876,8 +5891,8 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_short v0, v16, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readlane_b32 s31, v20, 1
; GCN-NEXT: v_readlane_b32 s30, v20, 0
+; GCN-NEXT: v_readlane_b32 s31, v20, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -5977,13 +5992,13 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX7-NEXT: buffer_store_short v2, v3, s[0:3], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_add_i32_e32 v2, vcc, 2, v16
+; GFX7-NEXT: v_readlane_b32 s30, v18, 0
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7-NEXT: buffer_store_short v1, v2, s[0:3], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: buffer_store_short v0, v16, s[0:3], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_readlane_b32 s31, v18, 1
-; GFX7-NEXT: v_readlane_b32 s30, v18, 0
; GFX7-NEXT: s_mov_b32 s32, s33
; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX7-NEXT: buffer_load_dword v18, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -6028,12 +6043,12 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX8-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v8
+; GFX8-NEXT: v_readlane_b32 s30, v10, 0
; GFX8-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_store_dword v0, v8, s[0:3], 0 offen
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_readlane_b32 s31, v10, 1
-; GFX8-NEXT: v_readlane_b32 s30, v10, 0
; GFX8-NEXT: s_mov_b32 s32, s33
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: buffer_load_dword v10, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -6059,6 +6074,7 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX900-NEXT: v_writelane_b32 v9, s31, 1
; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GFX900-NEXT: v_readlane_b32 s30, v9, 0
; GFX900-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen offset:28
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_store_dword v6, v8, s[0:3], 0 offen offset:24
@@ -6076,7 +6092,6 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX900-NEXT: buffer_store_dword v0, v8, s[0:3], 0 offen
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_readlane_b32 s31, v9, 1
-; GFX900-NEXT: v_readlane_b32 s30, v9, 0
; GFX900-NEXT: s_mov_b32 s32, s33
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v9, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -6099,15 +6114,16 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX950-NEXT: v_writelane_b32 v9, s30, 0
+; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_writelane_b32 v9, s31, 1
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX950-NEXT: v_readlane_b32 s30, v9, 0
; GFX950-NEXT: scratch_store_dwordx4 v8, v[4:7], off offset:16 sc0 sc1
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: scratch_store_dwordx4 v8, v[0:3], off sc0 sc1
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_readlane_b32 s31, v9, 1
-; GFX950-NEXT: v_readlane_b32 s30, v9, 0
; GFX950-NEXT: s_mov_b32 s32, s33
; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX950-NEXT: scratch_load_dword v9, off, s33 ; 4-byte Folded Reload
@@ -6134,6 +6150,7 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: v_writelane_b32 v9, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17]
+; GFX10-NEXT: v_readlane_b32 s30, v9, 0
; GFX10-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen offset:28
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_store_dword v6, v8, s[0:3], 0 offen offset:24
@@ -6151,7 +6168,6 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: buffer_store_dword v0, v8, s[0:3], 0 offen
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_readlane_b32 s31, v9, 1
-; GFX10-NEXT: v_readlane_b32 s30, v9, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v9, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -6178,12 +6194,13 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX11-NEXT: v_writelane_b32 v9, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readlane_b32 s30, v9, 0
; GFX11-NEXT: scratch_store_b128 v8, v[4:7], off offset:16 dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: scratch_store_b128 v8, v[0:3], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_readlane_b32 s31, v9, 1
-; GFX11-NEXT: v_readlane_b32 s30, v9, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v9, off, s33 ; 4-byte Folded Reload
@@ -6210,12 +6227,13 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX1250-NEXT: v_writelane_b32 v9, s31, 1
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_readlane_b32 s30, v9, 0
; GFX1250-NEXT: scratch_store_b128 v8, v[4:7], off offset:16 scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: scratch_store_b128 v8, v[0:3], off scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
; GFX1250-NEXT: v_readlane_b32 s31, v9, 1
-; GFX1250-NEXT: v_readlane_b32 s30, v9, 0
; GFX1250-NEXT: s_mov_b32 s32, s33
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1
@@ -48852,34 +48870,34 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX8-NEXT: v_and_b32_e32 v0, 1, v20
; GFX8-NEXT: v_cmp_eq_u32_e64 s[60:61], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v21
+; GFX8-NEXT: v_writelane_b32 v34, s34, 0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[62:63], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v22
+; GFX8-NEXT: v_writelane_b32 v34, s35, 1
; GFX8-NEXT: v_cmp_eq_u32_e64 s[72:73], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v23
+; GFX8-NEXT: v_writelane_b32 v34, s36, 2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[74:75], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v24
+; GFX8-NEXT: v_writelane_b32 v34, s37, 3
; GFX8-NEXT: v_cmp_eq_u32_e64 s[76:77], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v25
-; GFX8-NEXT: v_writelane_b32 v34, s30, 0
+; GFX8-NEXT: v_writelane_b32 v34, s38, 4
; GFX8-NEXT: v_cmp_eq_u32_e64 s[78:79], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v26
-; GFX8-NEXT: v_writelane_b32 v34, s31, 1
+; GFX8-NEXT: v_writelane_b32 v34, s39, 5
; GFX8-NEXT: v_cmp_eq_u32_e64 s[88:89], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v27
-; GFX8-NEXT: v_writelane_b32 v34, s34, 2
+; GFX8-NEXT: v_writelane_b32 v34, s30, 6
; GFX8-NEXT: v_cmp_eq_u32_e64 s[90:91], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v28
-; GFX8-NEXT: v_writelane_b32 v34, s35, 3
+; GFX8-NEXT: v_writelane_b32 v34, s31, 7
; GFX8-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v29
-; GFX8-NEXT: v_writelane_b32 v34, s36, 4
; GFX8-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v30
-; GFX8-NEXT: v_writelane_b32 v34, s37, 5
; GFX8-NEXT: v_cmp_eq_u32_e64 s[36:37], 1, v0
; GFX8-NEXT: buffer_load_ushort v0, off, s[0:3], s32
-; GFX8-NEXT: v_writelane_b32 v34, s38, 6
-; GFX8-NEXT: v_writelane_b32 v34, s39, 7
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[38:39], 1, v0
@@ -49005,6 +49023,7 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v28
; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v26
; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v24
+; GFX8-NEXT: v_readlane_b32 s30, v34, 6
; GFX8-NEXT: v_or_b32_sdwa v8, v16, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_sdwa v9, v18, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_sdwa v10, v20, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
@@ -49013,14 +49032,13 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX8-NEXT: v_or_b32_sdwa v13, v29, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_sdwa v14, v27, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_sdwa v15, v25, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_readlane_b32 s39, v34, 7
-; GFX8-NEXT: v_readlane_b32 s38, v34, 6
-; GFX8-NEXT: v_readlane_b32 s37, v34, 5
-; GFX8-NEXT: v_readlane_b32 s36, v34, 4
-; GFX8-NEXT: v_readlane_b32 s35, v34, 3
-; GFX8-NEXT: v_readlane_b32 s34, v34, 2
-; GFX8-NEXT: v_readlane_b32 s31, v34, 1
-; GFX8-NEXT: v_readlane_b32 s30, v34, 0
+; GFX8-NEXT: v_readlane_b32 s31, v34, 7
+; GFX8-NEXT: v_readlane_b32 s39, v34, 5
+; GFX8-NEXT: v_readlane_b32 s38, v34, 4
+; GFX8-NEXT: v_readlane_b32 s37, v34, 3
+; GFX8-NEXT: v_readlane_b32 s36, v34, 2
+; GFX8-NEXT: v_readlane_b32 s35, v34, 1
+; GFX8-NEXT: v_readlane_b32 s34, v34, 0
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
@@ -49092,11 +49110,11 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX900-NEXT: v_and_b32_e32 v0, 1, v28
; GFX900-NEXT: v_cmp_eq_u32_e64 s[94:95], 1, v0
; GFX900-NEXT: buffer_load_ushort v0, off, s[0:3], s32
-; GFX900-NEXT: v_writelane_b32 v33, s30, 0
-; GFX900-NEXT: v_writelane_b32 v33, s31, 1
-; GFX900-NEXT: v_writelane_b32 v33, s34, 2
+; GFX900-NEXT: v_writelane_b32 v33, s34, 0
+; GFX900-NEXT: v_writelane_b32 v33, s35, 1
+; GFX900-NEXT: v_writelane_b32 v33, s30, 2
+; GFX900-NEXT: v_writelane_b32 v33, s31, 3
; GFX900-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX900-NEXT: v_writelane_b32 v33, s35, 3
; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_and_b32_e32 v0, 1, v0
@@ -49201,6 +49219,7 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX900-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-NEXT: s_mov_b32 s4, 0x5040100
+; GFX900-NEXT: v_readlane_b32 s30, v33, 2
; GFX900-NEXT: v_perm_b32 v0, v0, v3, s4
; GFX900-NEXT: v_perm_b32 v1, v2, v5, s4
; GFX900-NEXT: v_perm_b32 v2, v4, v7, s4
@@ -49217,10 +49236,9 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX900-NEXT: v_perm_b32 v13, v26, v29, s4
; GFX900-NEXT: v_perm_b32 v14, v28, v32, s4
; GFX900-NEXT: v_perm_b32 v15, v31, v30, s4
-; GFX900-NEXT: v_readlane_b32 s35, v33, 3
-; GFX900-NEXT: v_readlane_b32 s34, v33, 2
-; GFX900-NEXT: v_readlane_b32 s31, v33, 1
-; GFX900-NEXT: v_readlane_b32 s30, v33, 0
+; GFX900-NEXT: v_readlane_b32 s31, v33, 3
+; GFX900-NEXT: v_readlane_b32 s35, v33, 1
+; GFX900-NEXT: v_readlane_b32 s34, v33, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll b/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
index ab2ad19d0f1bf..fb11d3b7d9d65 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
+++ b/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
@@ -902,47 +902,47 @@ define void @spill_func(ptr addrspace(1) %arg) #0 {
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[4:5]
; CHECK-NEXT: s_waitcnt expcnt(0)
-; CHECK-NEXT: v_writelane_b32 v0, s30, 0
-; CHECK-NEXT: v_writelane_b32 v0, s31, 1
-; CHECK-NEXT: v_writelane_b32 v0, s33, 2
-; CHECK-NEXT: v_writelane_b32 v0, s34, 3
-; CHECK-NEXT: v_writelane_b32 v0, s35, 4
-; CHECK-NEXT: v_writelane_b32 v0, s36, 5
-; CHECK-NEXT: v_writelane_b32 v0, s37, 6
-; CHECK-NEXT: v_writelane_b32 v0, s38, 7
-; CHECK-NEXT: v_writelane_b32 v0, s39, 8
-; CHECK-NEXT: v_writelane_b32 v0, s48, 9
-; CHECK-NEXT: v_writelane_b32 v0, s49, 10
-; CHECK-NEXT: v_writelane_b32 v0, s50, 11
-; CHECK-NEXT: v_writelane_b32 v0, s51, 12
-; CHECK-NEXT: v_writelane_b32 v0, s52, 13
-; CHECK-NEXT: v_writelane_b32 v0, s53, 14
-; CHECK-NEXT: v_writelane_b32 v0, s54, 15
-; CHECK-NEXT: v_writelane_b32 v0, s55, 16
-; CHECK-NEXT: v_writelane_b32 v0, s64, 17
-; CHECK-NEXT: v_writelane_b32 v0, s65, 18
-; CHECK-NEXT: v_writelane_b32 v0, s66, 19
-; CHECK-NEXT: v_writelane_b32 v0, s67, 20
-; CHECK-NEXT: v_writelane_b32 v0, s68, 21
-; CHECK-NEXT: v_writelane_b32 v0, s69, 22
-; CHECK-NEXT: v_writelane_b32 v0, s70, 23
-; CHECK-NEXT: v_writelane_b32 v0, s71, 24
-; CHECK-NEXT: v_writelane_b32 v0, s80, 25
-; CHECK-NEXT: v_writelane_b32 v0, s81, 26
-; CHECK-NEXT: v_writelane_b32 v0, s82, 27
-; CHECK-NEXT: v_writelane_b32 v0, s83, 28
-; CHECK-NEXT: v_writelane_b32 v0, s84, 29
-; CHECK-NEXT: v_writelane_b32 v0, s85, 30
-; CHECK-NEXT: v_writelane_b32 v0, s86, 31
-; CHECK-NEXT: v_writelane_b32 v0, s87, 32
-; CHECK-NEXT: v_writelane_b32 v0, s96, 33
-; CHECK-NEXT: v_writelane_b32 v0, s97, 34
-; CHECK-NEXT: v_writelane_b32 v0, s98, 35
-; CHECK-NEXT: v_writelane_b32 v0, s99, 36
+; CHECK-NEXT: v_writelane_b32 v0, s33, 0
+; CHECK-NEXT: v_writelane_b32 v0, s34, 1
+; CHECK-NEXT: v_writelane_b32 v0, s35, 2
+; CHECK-NEXT: v_writelane_b32 v0, s36, 3
+; CHECK-NEXT: v_writelane_b32 v0, s37, 4
+; CHECK-NEXT: v_writelane_b32 v0, s38, 5
+; CHECK-NEXT: v_writelane_b32 v0, s39, 6
+; CHECK-NEXT: v_writelane_b32 v0, s48, 7
+; CHECK-NEXT: v_writelane_b32 v0, s49, 8
+; CHECK-NEXT: v_writelane_b32 v0, s50, 9
+; CHECK-NEXT: v_writelane_b32 v0, s51, 10
+; CHECK-NEXT: v_writelane_b32 v0, s52, 11
+; CHECK-NEXT: v_writelane_b32 v0, s53, 12
+; CHECK-NEXT: v_writelane_b32 v0, s54, 13
+; CHECK-NEXT: v_writelane_b32 v0, s55, 14
+; CHECK-NEXT: v_writelane_b32 v0, s64, 15
+; CHECK-NEXT: v_writelane_b32 v0, s65, 16
+; CHECK-NEXT: v_writelane_b32 v0, s66, 17
+; CHECK-NEXT: v_writelane_b32 v0, s67, 18
+; CHECK-NEXT: v_writelane_b32 v0, s68, 19
+; CHECK-NEXT: v_writelane_b32 v0, s69, 20
+; CHECK-NEXT: v_writelane_b32 v0, s70, 21
+; CHECK-NEXT: v_writelane_b32 v0, s71, 22
+; CHECK-NEXT: v_writelane_b32 v0, s80, 23
+; CHECK-NEXT: v_writelane_b32 v0, s81, 24
+; CHECK-NEXT: v_writelane_b32 v0, s82, 25
+; CHECK-NEXT: v_writelane_b32 v0, s83, 26
+; CHECK-NEXT: v_writelane_b32 v0, s84, 27
+; CHECK-NEXT: v_writelane_b32 v0, s85, 28
+; CHECK-NEXT: v_writelane_b32 v0, s86, 29
+; CHECK-NEXT: v_writelane_b32 v0, s87, 30
+; CHECK-NEXT: v_writelane_b32 v0, s96, 31
+; CHECK-NEXT: v_writelane_b32 v0, s97, 32
+; CHECK-NEXT: v_writelane_b32 v0, s98, 33
+; CHECK-NEXT: v_writelane_b32 v0, s99, 34
+; CHECK-NEXT: v_writelane_b32 v0, s100, 35
+; CHECK-NEXT: v_writelane_b32 v0, s101, 36
; CHECK-NEXT: s_mov_b32 s40, s12
-; CHECK-NEXT: v_writelane_b32 v0, s100, 37
+; CHECK-NEXT: v_writelane_b32 v0, s30, 37
; CHECK-NEXT: s_cmp_eq_u32 s40, 0
-; CHECK-NEXT: v_writelane_b32 v0, s101, 38
+; CHECK-NEXT: v_writelane_b32 v0, s31, 38
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: s_mov_b32 s0, 0
; CHECK-NEXT: ;;#ASMEND
@@ -1380,6 +1380,7 @@ define void @spill_func(ptr addrspace(1) %arg) #0 {
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; reg use s31
; CHECK-NEXT: ;;#ASMEND
+; CHECK-NEXT: v_readlane_b32 s30, v0, 37
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; reg use s32
; CHECK-NEXT: ;;#ASMEND
@@ -1596,45 +1597,44 @@ define void @spill_func(ptr addrspace(1) %arg) #0 {
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; reg use vcc_hi
; CHECK-NEXT: ;;#ASMEND
-; CHECK-NEXT: v_readlane_b32 s101, v0, 38
-; CHECK-NEXT: v_readlane_b32 s100, v0, 37
-; CHECK-NEXT: v_readlane_b32 s99, v0, 36
-; CHECK-NEXT: v_readlane_b32 s98, v0, 35
-; CHECK-NEXT: v_readlane_b32 s97, v0, 34
-; CHECK-NEXT: v_readlane_b32 s96, v0, 33
-; CHECK-NEXT: v_readlane_b32 s87, v0, 32
-; CHECK-NEXT: v_readlane_b32 s86, v0, 31
-; CHECK-NEXT: v_readlane_b32 s85, v0, 30
-; CHECK-NEXT: v_readlane_b32 s84, v0, 29
-; CHECK-NEXT: v_readlane_b32 s83, v0, 28
-; CHECK-NEXT: v_readlane_b32 s82, v0, 27
-; CHECK-NEXT: v_readlane_b32 s81, v0, 26
-; CHECK-NEXT: v_readlane_b32 s80, v0, 25
-; CHECK-NEXT: v_readlane_b32 s71, v0, 24
-; CHECK-NEXT: v_readlane_b32 s70, v0, 23
-; CHECK-NEXT: v_readlane_b32 s69, v0, 22
-; CHECK-NEXT: v_readlane_b32 s68, v0, 21
-; CHECK-NEXT: v_readlane_b32 s67, v0, 20
-; CHECK-NEXT: v_readlane_b32 s66, v0, 19
-; CHECK-NEXT: v_readlane_b32 s65, v0, 18
-; CHECK-NEXT: v_readlane_b32 s64, v0, 17
-; CHECK-NEXT: v_readlane_b32 s55, v0, 16
-; CHECK-NEXT: v_readlane_b32 s54, v0, 15
-; CHECK-NEXT: v_readlane_b32 s53, v0, 14
-; CHECK-NEXT: v_readlane_b32 s52, v0, 13
-; CHECK-NEXT: v_readlane_b32 s51, v0, 12
-; CHECK-NEXT: v_readlane_b32 s50, v0, 11
-; CHECK-NEXT: v_readlane_b32 s49, v0, 10
-; CHECK-NEXT: v_readlane_b32 s48, v0, 9
-; CHECK-NEXT: v_readlane_b32 s39, v0, 8
-; CHECK-NEXT: v_readlane_b32 s38, v0, 7
-; CHECK-NEXT: v_readlane_b32 s37, v0, 6
-; CHECK-NEXT: v_readlane_b32 s36, v0, 5
-; CHECK-NEXT: v_readlane_b32 s35, v0, 4
-; CHECK-NEXT: v_readlane_b32 s34, v0, 3
-; CHECK-NEXT: v_readlane_b32 s33, v0, 2
-; CHECK-NEXT: v_readlane_b32 s31, v0, 1
-; CHECK-NEXT: v_readlane_b32 s30, v0, 0
+; CHECK-NEXT: v_readlane_b32 s31, v0, 38
+; CHECK-NEXT: v_readlane_b32 s101, v0, 36
+; CHECK-NEXT: v_readlane_b32 s100, v0, 35
+; CHECK-NEXT: v_readlane_b32 s99, v0, 34
+; CHECK-NEXT: v_readlane_b32 s98, v0, 33
+; CHECK-NEXT: v_readlane_b32 s97, v0, 32
+; CHECK-NEXT: v_readlane_b32 s96, v0, 31
+; CHECK-NEXT: v_readlane_b32 s87, v0, 30
+; CHECK-NEXT: v_readlane_b32 s86, v0, 29
+; CHECK-NEXT: v_readlane_b32 s85, v0, 28
+; CHECK-NEXT: v_readlane_b32 s84, v0, 27
+; CHECK-NEXT: v_readlane_b32 s83, v0, 26
+; CHECK-NEXT: v_readlane_b32 s82, v0, 25
+; CHECK-NEXT: v_readlane_b32 s81, v0, 24
+; CHECK-NEXT: v_readlane_b32 s80, v0, 23
+; CHECK-NEXT: v_readlane_b32 s71, v0, 22
+; CHECK-NEXT: v_readlane_b32 s70, v0, 21
+; CHECK-NEXT: v_readlane_b32 s69, v0, 20
+; CHECK-NEXT: v_readlane_b32 s68, v0, 19
+; CHECK-NEXT: v_readlane_b32 s67, v0, 18
+; CHECK-NEXT: v_readlane_b32 s66, v0, 17
+; CHECK-NEXT: v_readlane_b32 s65, v0, 16
+; CHECK-NEXT: v_readlane_b32 s64, v0, 15
+; CHECK-NEXT: v_readlane_b32 s55, v0, 14
+; CHECK-NEXT: v_readlane_b32 s54, v0, 13
+; CHECK-NEXT: v_readlane_b32 s53, v0, 12
+; CHECK-NEXT: v_readlane_b32 s52, v0, 11
+; CHECK-NEXT: v_readlane_b32 s51, v0, 10
+; CHECK-NEXT: v_readlane_b32 s50, v0, 9
+; CHECK-NEXT: v_readlane_b32 s49, v0, 8
+; CHECK-NEXT: v_readlane_b32 s48, v0, 7
+; CHECK-NEXT: v_readlane_b32 s39, v0, 6
+; CHECK-NEXT: v_readlane_b32 s38, v0, 5
+; CHECK-NEXT: v_readlane_b32 s37, v0, 4
+; CHECK-NEXT: v_readlane_b32 s36, v0, 3
+; CHECK-NEXT: v_readlane_b32 s35, v0, 2
+; CHECK-NEXT: v_readlane_b32 s34, v0, 1
+; CHECK-NEXT: v_readlane_b32 s33, v0, 0
; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; CHECK-NEXT: s_mov_b64 exec, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll b/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
index d1cede64ce71d..7f9b09350886a 100644
--- a/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
@@ -49,8 +49,8 @@ define void @test_call_external_void_func_i8_inreg(i8 inreg %arg) #0 {
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -77,8 +77,8 @@ define void @test_call_external_void_func_i8_inreg(i8 inreg %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -109,8 +109,8 @@ define void @test_call_external_void_func_i16_inreg(i16 inreg %arg) #0 {
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -137,8 +137,8 @@ define void @test_call_external_void_func_i16_inreg(i16 inreg %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -169,8 +169,8 @@ define void @test_call_external_void_func_i32_inreg(i32 inreg %arg) #0 {
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -197,8 +197,8 @@ define void @test_call_external_void_func_i32_inreg(i32 inreg %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -230,8 +230,8 @@ define void @test_call_external_void_func_i64_inreg(i64 inreg %arg) #0 {
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -258,8 +258,8 @@ define void @test_call_external_void_func_i64_inreg(i64 inreg %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -291,8 +291,8 @@ define void @test_call_external_void_func_v2i32_inreg(<2 x i32> inreg %arg) #0 {
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -319,8 +319,8 @@ define void @test_call_external_void_func_v2i32_inreg(<2 x i32> inreg %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -353,8 +353,8 @@ define void @test_call_external_void_func_v3i32_inreg(<3 x i32> inreg %arg) #0 {
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[20:21]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -381,8 +381,8 @@ define void @test_call_external_void_func_v3i32_inreg(<3 x i32> inreg %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -416,8 +416,8 @@ define void @test_call_external_void_func_v4i32_inreg(<4 x i32> inreg %arg) #0 {
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[20:21]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -444,8 +444,8 @@ define void @test_call_external_void_func_v4i32_inreg(<4 x i32> inreg %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -483,8 +483,8 @@ define void @test_call_external_void_func_v8i32_inreg(<8 x i32> inreg %arg) #0 {
; GFX9-NEXT: s_mov_b32 s19, s23
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[24:25]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -511,8 +511,8 @@ define void @test_call_external_void_func_v8i32_inreg(<8 x i32> inreg %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[20:21]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -543,8 +543,8 @@ define void @test_call_external_void_func_f16_inreg(half inreg %arg) #0 {
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -571,8 +571,8 @@ define void @test_call_external_void_func_f16_inreg(half inreg %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -603,8 +603,8 @@ define void @test_call_external_void_func_bf16_inreg(bfloat inreg %arg) #0 {
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -631,8 +631,8 @@ define void @test_call_external_void_func_bf16_inreg(bfloat inreg %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -663,8 +663,8 @@ define void @test_call_external_void_func_f32_inreg(float inreg %arg) #0 {
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -691,8 +691,8 @@ define void @test_call_external_void_func_f32_inreg(float inreg %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -724,8 +724,8 @@ define void @test_call_external_void_func_f64_inreg(double inreg %arg) #0 {
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -752,8 +752,8 @@ define void @test_call_external_void_func_f64_inreg(double inreg %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -784,8 +784,8 @@ define void @test_call_external_void_func_v2f16_inreg(<2 x half> inreg %arg) #0
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -812,8 +812,8 @@ define void @test_call_external_void_func_v2f16_inreg(<2 x half> inreg %arg) #0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -845,8 +845,8 @@ define void @test_call_external_void_func_v2bf16_inreg(<2 x bfloat> inreg %arg)
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -873,8 +873,8 @@ define void @test_call_external_void_func_v2bf16_inreg(<2 x bfloat> inreg %arg)
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -906,8 +906,8 @@ define void @test_call_external_void_func_v3f16_inreg(<3 x half> inreg %arg) #0
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -934,8 +934,8 @@ define void @test_call_external_void_func_v3f16_inreg(<3 x half> inreg %arg) #0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -967,8 +967,8 @@ define void @test_call_external_void_func_v4f16_inreg(<4 x half> inreg %arg) #0
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -995,8 +995,8 @@ define void @test_call_external_void_func_v4f16_inreg(<4 x half> inreg %arg) #0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -1028,8 +1028,8 @@ define void @test_call_external_void_func_p0_inreg(ptr inreg %arg) #0 {
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -1056,8 +1056,8 @@ define void @test_call_external_void_func_p0_inreg(ptr inreg %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -1089,8 +1089,8 @@ define void @test_call_external_void_func_p1_inreg(ptr addrspace(1) inreg %arg)
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -1117,8 +1117,8 @@ define void @test_call_external_void_func_p1_inreg(ptr addrspace(1) inreg %arg)
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -1149,8 +1149,8 @@ define void @test_call_external_void_func_p3_inreg(ptr addrspace(3) inreg %arg)
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -1177,8 +1177,8 @@ define void @test_call_external_void_func_p3_inreg(ptr addrspace(3) inreg %arg)
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -1212,8 +1212,8 @@ define void @test_call_external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inre
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[20:21]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -1240,8 +1240,8 @@ define void @test_call_external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inre
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -1273,8 +1273,8 @@ define void @test_call_external_void_func_v2p5_inreg(<2 x ptr addrspace(5)> inre
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -1301,8 +1301,8 @@ define void @test_call_external_void_func_v2p5_inreg(<2 x ptr addrspace(5)> inre
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -1337,8 +1337,8 @@ define void @test_call_external_void_func_i64_inreg_i32_inreg_i64_inreg(i64 inre
; GFX9-NEXT: s_mov_b32 s16, s20
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[22:23]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -1365,8 +1365,8 @@ define void @test_call_external_void_func_i64_inreg_i32_inreg_i64_inreg(i64 inre
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -1409,8 +1409,8 @@ define void @test_call_external_void_func_a15i32_inreg([13 x i32] inreg %arg0) #
; GFX9-NEXT: s_mov_b32 s24, s28
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[40:41]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -1437,8 +1437,8 @@ define void @test_call_external_void_func_a15i32_inreg([13 x i32] inreg %arg0) #
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[26:27]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -1484,8 +1484,8 @@ define void @test_call_external_void_func_a15i32_inreg_i32_inreg([13 x i32] inre
; GFX9-NEXT: s_mov_b32 s16, s20
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[22:23]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -1512,8 +1512,8 @@ define void @test_call_external_void_func_a15i32_inreg_i32_inreg([13 x i32] inre
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
diff --git a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
index 8e12e7e03947b..2ee71c403416a 100644
--- a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
@@ -5901,8 +5901,8 @@ define void @stack_12xv3i32() #0 {
; VI-NEXT: v_mov_b32_e32 v30, 10
; VI-NEXT: v_writelane_b32 v40, s31, 1
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; VI-NEXT: v_readlane_b32 s31, v40, 1
; VI-NEXT: v_readlane_b32 s30, v40, 0
+; VI-NEXT: v_readlane_b32 s31, v40, 1
; VI-NEXT: s_mov_b32 s32, s33
; VI-NEXT: v_readlane_b32 s4, v40, 2
; VI-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -5969,8 +5969,8 @@ define void @stack_12xv3i32() #0 {
; CI-NEXT: v_mov_b32_e32 v30, 10
; CI-NEXT: v_writelane_b32 v40, s31, 1
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; CI-NEXT: v_readlane_b32 s31, v40, 1
; CI-NEXT: v_readlane_b32 s30, v40, 0
+; CI-NEXT: v_readlane_b32 s31, v40, 1
; CI-NEXT: s_mov_b32 s32, s33
; CI-NEXT: v_readlane_b32 s4, v40, 2
; CI-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -6037,8 +6037,8 @@ define void @stack_12xv3i32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v30, 10
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -6087,8 +6087,8 @@ define void @stack_12xv3i32() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -6155,8 +6155,8 @@ define void @stack_12xv3i32() #0 {
; HSA-NEXT: v_mov_b32_e32 v30, 10
; HSA-NEXT: v_writelane_b32 v40, s31, 1
; HSA-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; HSA-NEXT: v_readlane_b32 s31, v40, 1
; HSA-NEXT: v_readlane_b32 s30, v40, 0
+; HSA-NEXT: v_readlane_b32 s31, v40, 1
; HSA-NEXT: s_mov_b32 s32, s33
; HSA-NEXT: v_readlane_b32 s4, v40, 2
; HSA-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -6240,8 +6240,8 @@ define void @stack_12xv3f32() #0 {
; VI-NEXT: v_mov_b32_e32 v30, 0x41200000
; VI-NEXT: v_writelane_b32 v40, s31, 1
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; VI-NEXT: v_readlane_b32 s31, v40, 1
; VI-NEXT: v_readlane_b32 s30, v40, 0
+; VI-NEXT: v_readlane_b32 s31, v40, 1
; VI-NEXT: s_mov_b32 s32, s33
; VI-NEXT: v_readlane_b32 s4, v40, 2
; VI-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -6308,8 +6308,8 @@ define void @stack_12xv3f32() #0 {
; CI-NEXT: v_mov_b32_e32 v30, 0x41200000
; CI-NEXT: v_writelane_b32 v40, s31, 1
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; CI-NEXT: v_readlane_b32 s31, v40, 1
; CI-NEXT: v_readlane_b32 s30, v40, 0
+; CI-NEXT: v_readlane_b32 s31, v40, 1
; CI-NEXT: s_mov_b32 s32, s33
; CI-NEXT: v_readlane_b32 s4, v40, 2
; CI-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -6376,8 +6376,8 @@ define void @stack_12xv3f32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v30, 0x41200000
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -6430,8 +6430,8 @@ define void @stack_12xv3f32() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -6498,8 +6498,8 @@ define void @stack_12xv3f32() #0 {
; HSA-NEXT: v_mov_b32_e32 v30, 0x41200000
; HSA-NEXT: v_writelane_b32 v40, s31, 1
; HSA-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; HSA-NEXT: v_readlane_b32 s31, v40, 1
; HSA-NEXT: v_readlane_b32 s30, v40, 0
+; HSA-NEXT: v_readlane_b32 s31, v40, 1
; HSA-NEXT: s_mov_b32 s32, s33
; HSA-NEXT: v_readlane_b32 s4, v40, 2
; HSA-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -6591,8 +6591,8 @@ define void @stack_8xv5i32() #0 {
; VI-NEXT: v_mov_b32_e32 v30, 6
; VI-NEXT: v_writelane_b32 v40, s31, 1
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; VI-NEXT: v_readlane_b32 s31, v40, 1
; VI-NEXT: v_readlane_b32 s30, v40, 0
+; VI-NEXT: v_readlane_b32 s31, v40, 1
; VI-NEXT: s_mov_b32 s32, s33
; VI-NEXT: v_readlane_b32 s4, v40, 2
; VI-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -6667,8 +6667,8 @@ define void @stack_8xv5i32() #0 {
; CI-NEXT: v_mov_b32_e32 v30, 6
; CI-NEXT: v_writelane_b32 v40, s31, 1
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; CI-NEXT: v_readlane_b32 s31, v40, 1
; CI-NEXT: v_readlane_b32 s30, v40, 0
+; CI-NEXT: v_readlane_b32 s31, v40, 1
; CI-NEXT: s_mov_b32 s32, s33
; CI-NEXT: v_readlane_b32 s4, v40, 2
; CI-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -6743,8 +6743,8 @@ define void @stack_8xv5i32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v30, 6
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -6798,8 +6798,8 @@ define void @stack_8xv5i32() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -6874,8 +6874,8 @@ define void @stack_8xv5i32() #0 {
; HSA-NEXT: v_mov_b32_e32 v30, 6
; HSA-NEXT: v_writelane_b32 v40, s31, 1
; HSA-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; HSA-NEXT: v_readlane_b32 s31, v40, 1
; HSA-NEXT: v_readlane_b32 s30, v40, 0
+; HSA-NEXT: v_readlane_b32 s31, v40, 1
; HSA-NEXT: s_mov_b32 s32, s33
; HSA-NEXT: v_readlane_b32 s4, v40, 2
; HSA-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -6963,8 +6963,8 @@ define void @stack_8xv5f32() #0 {
; VI-NEXT: v_mov_b32_e32 v30, 0x40c00000
; VI-NEXT: v_writelane_b32 v40, s31, 1
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; VI-NEXT: v_readlane_b32 s31, v40, 1
; VI-NEXT: v_readlane_b32 s30, v40, 0
+; VI-NEXT: v_readlane_b32 s31, v40, 1
; VI-NEXT: s_mov_b32 s32, s33
; VI-NEXT: v_readlane_b32 s4, v40, 2
; VI-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -7039,8 +7039,8 @@ define void @stack_8xv5f32() #0 {
; CI-NEXT: v_mov_b32_e32 v30, 0x40c00000
; CI-NEXT: v_writelane_b32 v40, s31, 1
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; CI-NEXT: v_readlane_b32 s31, v40, 1
; CI-NEXT: v_readlane_b32 s30, v40, 0
+; CI-NEXT: v_readlane_b32 s31, v40, 1
; CI-NEXT: s_mov_b32 s32, s33
; CI-NEXT: v_readlane_b32 s4, v40, 2
; CI-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -7115,8 +7115,8 @@ define void @stack_8xv5f32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v30, 0x40c00000
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -7173,8 +7173,8 @@ define void @stack_8xv5f32() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -7249,8 +7249,8 @@ define void @stack_8xv5f32() #0 {
; HSA-NEXT: v_mov_b32_e32 v30, 0x40c00000
; HSA-NEXT: v_writelane_b32 v40, s31, 1
; HSA-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; HSA-NEXT: v_readlane_b32 s31, v40, 1
; HSA-NEXT: v_readlane_b32 s30, v40, 0
+; HSA-NEXT: v_readlane_b32 s31, v40, 1
; HSA-NEXT: s_mov_b32 s32, s33
; HSA-NEXT: v_readlane_b32 s4, v40, 2
; HSA-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll b/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
index 4df10497bcd27..cdec3b6751e3a 100644
--- a/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
@@ -20,8 +20,8 @@ define void @use_vcc() #1 {
; GCN: v_writelane_b32 v40, s30, 0
; GCN: v_writelane_b32 v40, s31, 1
; GCN: s_swappc_b64
-; GCN: v_readlane_b32 s31, v40, 1
; GCN: v_readlane_b32 s30, v40, 0
+; GCN: v_readlane_b32 s31, v40, 1
; GCN: v_readlane_b32 s4, v40, 2
; GCN: s_mov_b32 s33, s4
; GCN: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll b/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
index 61a195f9c314f..eef727b1a31b6 100644
--- a/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
@@ -36,22 +36,22 @@ define void @test_func_call_external_void_func_void_clobber_s30_s31_call_externa
; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[6:7]
; MUBUF-NEXT: v_writelane_b32 v40, s4, 4
-; MUBUF-NEXT: v_writelane_b32 v40, s30, 0
-; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
+; MUBUF-NEXT: v_writelane_b32 v40, s34, 0
; MUBUF-NEXT: s_addk_i32 s32, 0x400
-; MUBUF-NEXT: v_writelane_b32 v40, s34, 2
-; MUBUF-NEXT: v_writelane_b32 v40, s35, 3
+; MUBUF-NEXT: v_writelane_b32 v40, s35, 1
+; MUBUF-NEXT: v_writelane_b32 v40, s30, 2
; MUBUF-NEXT: s_getpc_b64 s[34:35]
; MUBUF-NEXT: s_add_u32 s34, s34, external_void_func_void at rel32@lo+4
; MUBUF-NEXT: s_addc_u32 s35, s35, external_void_func_void at rel32@hi+12
+; MUBUF-NEXT: v_writelane_b32 v40, s31, 3
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[34:35]
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ;;#ASMEND
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; MUBUF-NEXT: v_readlane_b32 s35, v40, 3
-; MUBUF-NEXT: v_readlane_b32 s34, v40, 2
-; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
-; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
+; MUBUF-NEXT: v_readlane_b32 s30, v40, 2
+; MUBUF-NEXT: v_readlane_b32 s31, v40, 3
+; MUBUF-NEXT: v_readlane_b32 s35, v40, 1
+; MUBUF-NEXT: v_readlane_b32 s34, v40, 0
; MUBUF-NEXT: s_mov_b32 s32, s33
; MUBUF-NEXT: v_readlane_b32 s4, v40, 4
; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -70,22 +70,22 @@ define void @test_func_call_external_void_func_void_clobber_s30_s31_call_externa
; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
; FLATSCR-NEXT: v_writelane_b32 v40, s0, 4
-; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0
-; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
+; FLATSCR-NEXT: v_writelane_b32 v40, s34, 0
; FLATSCR-NEXT: s_add_i32 s32, s32, 16
-; FLATSCR-NEXT: v_writelane_b32 v40, s34, 2
-; FLATSCR-NEXT: v_writelane_b32 v40, s35, 3
+; FLATSCR-NEXT: v_writelane_b32 v40, s35, 1
+; FLATSCR-NEXT: v_writelane_b32 v40, s30, 2
; FLATSCR-NEXT: s_getpc_b64 s[34:35]
; FLATSCR-NEXT: s_add_u32 s34, s34, external_void_func_void at rel32@lo+4
; FLATSCR-NEXT: s_addc_u32 s35, s35, external_void_func_void at rel32@hi+12
+; FLATSCR-NEXT: v_writelane_b32 v40, s31, 3
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[34:35]
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ;;#ASMEND
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; FLATSCR-NEXT: v_readlane_b32 s35, v40, 3
-; FLATSCR-NEXT: v_readlane_b32 s34, v40, 2
-; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
-; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
+; FLATSCR-NEXT: v_readlane_b32 s30, v40, 2
+; FLATSCR-NEXT: v_readlane_b32 s31, v40, 3
+; FLATSCR-NEXT: v_readlane_b32 s35, v40, 1
+; FLATSCR-NEXT: v_readlane_b32 s34, v40, 0
; FLATSCR-NEXT: s_mov_b32 s32, s33
; FLATSCR-NEXT: v_readlane_b32 s0, v40, 4
; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1
@@ -110,20 +110,20 @@ define void @test_func_call_external_void_funcx2() #0 {
; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[6:7]
; MUBUF-NEXT: v_writelane_b32 v40, s4, 4
-; MUBUF-NEXT: v_writelane_b32 v40, s30, 0
-; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
+; MUBUF-NEXT: v_writelane_b32 v40, s34, 0
; MUBUF-NEXT: s_addk_i32 s32, 0x400
-; MUBUF-NEXT: v_writelane_b32 v40, s34, 2
-; MUBUF-NEXT: v_writelane_b32 v40, s35, 3
+; MUBUF-NEXT: v_writelane_b32 v40, s35, 1
+; MUBUF-NEXT: v_writelane_b32 v40, s30, 2
; MUBUF-NEXT: s_getpc_b64 s[34:35]
; MUBUF-NEXT: s_add_u32 s34, s34, external_void_func_void at rel32@lo+4
; MUBUF-NEXT: s_addc_u32 s35, s35, external_void_func_void at rel32@hi+12
+; MUBUF-NEXT: v_writelane_b32 v40, s31, 3
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[34:35]
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; MUBUF-NEXT: v_readlane_b32 s35, v40, 3
-; MUBUF-NEXT: v_readlane_b32 s34, v40, 2
-; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
-; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
+; MUBUF-NEXT: v_readlane_b32 s30, v40, 2
+; MUBUF-NEXT: v_readlane_b32 s31, v40, 3
+; MUBUF-NEXT: v_readlane_b32 s35, v40, 1
+; MUBUF-NEXT: v_readlane_b32 s34, v40, 0
; MUBUF-NEXT: s_mov_b32 s32, s33
; MUBUF-NEXT: v_readlane_b32 s4, v40, 4
; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -142,20 +142,20 @@ define void @test_func_call_external_void_funcx2() #0 {
; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
; FLATSCR-NEXT: v_writelane_b32 v40, s0, 4
-; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0
-; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
+; FLATSCR-NEXT: v_writelane_b32 v40, s34, 0
; FLATSCR-NEXT: s_add_i32 s32, s32, 16
-; FLATSCR-NEXT: v_writelane_b32 v40, s34, 2
-; FLATSCR-NEXT: v_writelane_b32 v40, s35, 3
+; FLATSCR-NEXT: v_writelane_b32 v40, s35, 1
+; FLATSCR-NEXT: v_writelane_b32 v40, s30, 2
; FLATSCR-NEXT: s_getpc_b64 s[34:35]
; FLATSCR-NEXT: s_add_u32 s34, s34, external_void_func_void at rel32@lo+4
; FLATSCR-NEXT: s_addc_u32 s35, s35, external_void_func_void at rel32@hi+12
+; FLATSCR-NEXT: v_writelane_b32 v40, s31, 3
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[34:35]
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; FLATSCR-NEXT: v_readlane_b32 s35, v40, 3
-; FLATSCR-NEXT: v_readlane_b32 s34, v40, 2
-; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
-; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
+; FLATSCR-NEXT: v_readlane_b32 s30, v40, 2
+; FLATSCR-NEXT: v_readlane_b32 s31, v40, 3
+; FLATSCR-NEXT: v_readlane_b32 s35, v40, 1
+; FLATSCR-NEXT: v_readlane_b32 s34, v40, 0
; FLATSCR-NEXT: s_mov_b32 s32, s33
; FLATSCR-NEXT: v_readlane_b32 s0, v40, 4
; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1
@@ -181,8 +181,8 @@ define void @void_func_void_clobber_s30_s31() #2 {
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; clobber
; MUBUF-NEXT: ;;#ASMEND
-; MUBUF-NEXT: v_readlane_b32 s31, v0, 1
; MUBUF-NEXT: v_readlane_b32 s30, v0, 0
+; MUBUF-NEXT: v_readlane_b32 s31, v0, 1
; MUBUF-NEXT: s_xor_saveexec_b64 s[4:5], -1
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; MUBUF-NEXT: s_mov_b64 exec, s[4:5]
@@ -200,8 +200,8 @@ define void @void_func_void_clobber_s30_s31() #2 {
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; clobber
; FLATSCR-NEXT: ;;#ASMEND
-; FLATSCR-NEXT: v_readlane_b32 s31, v0, 1
; FLATSCR-NEXT: v_readlane_b32 s30, v0, 0
+; FLATSCR-NEXT: v_readlane_b32 s31, v0, 1
; FLATSCR-NEXT: s_xor_saveexec_b64 s[0:1], -1
; FLATSCR-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; FLATSCR-NEXT: s_mov_b64 exec, s[0:1]
@@ -523,23 +523,23 @@ define void @callee_saved_sgpr_func() #2 {
; MUBUF-NEXT: s_mov_b64 exec, s[6:7]
; MUBUF-NEXT: v_writelane_b32 v40, s4, 3
; MUBUF-NEXT: s_addk_i32 s32, 0x400
-; MUBUF-NEXT: v_writelane_b32 v40, s30, 0
-; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
+; MUBUF-NEXT: v_writelane_b32 v40, s34, 0
+; MUBUF-NEXT: v_writelane_b32 v40, s30, 1
; MUBUF-NEXT: s_getpc_b64 s[4:5]
; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_void at rel32@lo+4
; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_void at rel32@hi+12
-; MUBUF-NEXT: v_writelane_b32 v40, s34, 2
+; MUBUF-NEXT: v_writelane_b32 v40, s31, 2
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; def s40
; MUBUF-NEXT: ;;#ASMEND
; MUBUF-NEXT: s_mov_b32 s34, s40
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5]
+; MUBUF-NEXT: v_readlane_b32 s30, v40, 1
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; use s34
; MUBUF-NEXT: ;;#ASMEND
-; MUBUF-NEXT: v_readlane_b32 s34, v40, 2
-; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
-; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
+; MUBUF-NEXT: v_readlane_b32 s31, v40, 2
+; MUBUF-NEXT: v_readlane_b32 s34, v40, 0
; MUBUF-NEXT: s_mov_b32 s32, s33
; MUBUF-NEXT: v_readlane_b32 s4, v40, 3
; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -559,23 +559,23 @@ define void @callee_saved_sgpr_func() #2 {
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
; FLATSCR-NEXT: v_writelane_b32 v40, s0, 3
; FLATSCR-NEXT: s_add_i32 s32, s32, 16
-; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0
-; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
+; FLATSCR-NEXT: v_writelane_b32 v40, s34, 0
+; FLATSCR-NEXT: v_writelane_b32 v40, s30, 1
; FLATSCR-NEXT: s_getpc_b64 s[0:1]
; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_void at rel32@lo+4
; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_void at rel32@hi+12
-; FLATSCR-NEXT: v_writelane_b32 v40, s34, 2
+; FLATSCR-NEXT: v_writelane_b32 v40, s31, 2
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; def s40
; FLATSCR-NEXT: ;;#ASMEND
; FLATSCR-NEXT: s_mov_b32 s34, s40
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; FLATSCR-NEXT: v_readlane_b32 s30, v40, 1
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; use s34
; FLATSCR-NEXT: ;;#ASMEND
-; FLATSCR-NEXT: v_readlane_b32 s34, v40, 2
-; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
-; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
+; FLATSCR-NEXT: v_readlane_b32 s31, v40, 2
+; FLATSCR-NEXT: v_readlane_b32 s34, v40, 0
; FLATSCR-NEXT: s_mov_b32 s32, s33
; FLATSCR-NEXT: v_readlane_b32 s0, v40, 3
; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1
@@ -626,13 +626,13 @@ define void @callee_saved_sgpr_vgpr_func() #2 {
; MUBUF-NEXT: s_mov_b64 exec, s[6:7]
; MUBUF-NEXT: v_writelane_b32 v41, s4, 3
; MUBUF-NEXT: s_addk_i32 s32, 0x400
-; MUBUF-NEXT: v_writelane_b32 v41, s30, 0
-; MUBUF-NEXT: v_writelane_b32 v41, s31, 1
+; MUBUF-NEXT: v_writelane_b32 v41, s34, 0
+; MUBUF-NEXT: v_writelane_b32 v41, s30, 1
; MUBUF-NEXT: s_getpc_b64 s[4:5]
; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_void at rel32@lo+4
; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_void at rel32@hi+12
; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; MUBUF-NEXT: v_writelane_b32 v41, s34, 2
+; MUBUF-NEXT: v_writelane_b32 v41, s31, 2
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; def s40
; MUBUF-NEXT: ;;#ASMEND
@@ -648,9 +648,9 @@ define void @callee_saved_sgpr_vgpr_func() #2 {
; MUBUF-NEXT: ; use v40
; MUBUF-NEXT: ;;#ASMEND
; MUBUF-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; MUBUF-NEXT: v_readlane_b32 s34, v41, 2
-; MUBUF-NEXT: v_readlane_b32 s31, v41, 1
-; MUBUF-NEXT: v_readlane_b32 s30, v41, 0
+; MUBUF-NEXT: v_readlane_b32 s30, v41, 1
+; MUBUF-NEXT: v_readlane_b32 s31, v41, 2
+; MUBUF-NEXT: v_readlane_b32 s34, v41, 0
; MUBUF-NEXT: s_mov_b32 s32, s33
; MUBUF-NEXT: v_readlane_b32 s4, v41, 3
; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -670,13 +670,13 @@ define void @callee_saved_sgpr_vgpr_func() #2 {
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
; FLATSCR-NEXT: v_writelane_b32 v41, s0, 3
; FLATSCR-NEXT: s_add_i32 s32, s32, 16
-; FLATSCR-NEXT: v_writelane_b32 v41, s30, 0
-; FLATSCR-NEXT: v_writelane_b32 v41, s31, 1
+; FLATSCR-NEXT: v_writelane_b32 v41, s34, 0
+; FLATSCR-NEXT: v_writelane_b32 v41, s30, 1
; FLATSCR-NEXT: s_getpc_b64 s[0:1]
; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_void at rel32@lo+4
; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_void at rel32@hi+12
; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; FLATSCR-NEXT: v_writelane_b32 v41, s34, 2
+; FLATSCR-NEXT: v_writelane_b32 v41, s31, 2
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; def s40
; FLATSCR-NEXT: ;;#ASMEND
@@ -692,9 +692,9 @@ define void @callee_saved_sgpr_vgpr_func() #2 {
; FLATSCR-NEXT: ; use v40
; FLATSCR-NEXT: ;;#ASMEND
; FLATSCR-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
-; FLATSCR-NEXT: v_readlane_b32 s34, v41, 2
-; FLATSCR-NEXT: v_readlane_b32 s31, v41, 1
-; FLATSCR-NEXT: v_readlane_b32 s30, v41, 0
+; FLATSCR-NEXT: v_readlane_b32 s30, v41, 1
+; FLATSCR-NEXT: v_readlane_b32 s31, v41, 2
+; FLATSCR-NEXT: v_readlane_b32 s34, v41, 0
; FLATSCR-NEXT: s_mov_b32 s32, s33
; FLATSCR-NEXT: v_readlane_b32 s0, v41, 3
; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1
diff --git a/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll b/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
index e7254eb5c3465..07f58df81c502 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
@@ -132,8 +132,8 @@ define void @callee_with_stack_and_call() #0 {
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
+; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
; MUBUF-NEXT: s_mov_b32 s32, s33
; MUBUF-NEXT: v_readlane_b32 s4, v40, 2
; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -162,8 +162,8 @@ define void @callee_with_stack_and_call() #0 {
; FLATSCR-NEXT: scratch_store_dword off, v0, s33
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
+; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
; FLATSCR-NEXT: s_mov_b32 s32, s33
; FLATSCR-NEXT: v_readlane_b32 s0, v40, 2
; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1
@@ -201,8 +201,8 @@ define void @callee_no_stack_with_call() #0 {
; MUBUF-NEXT: s_addc_u32 s17, s17, external_void_func_void at rel32@hi+12
; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
+; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
; MUBUF-NEXT: s_mov_b32 s32, s33
; MUBUF-NEXT: v_readlane_b32 s4, v40, 2
; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -228,8 +228,8 @@ define void @callee_no_stack_with_call() #0 {
; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_void at rel32@hi+12
; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
+; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
; FLATSCR-NEXT: s_mov_b32 s32, s33
; FLATSCR-NEXT: v_readlane_b32 s0, v40, 2
; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1
@@ -359,24 +359,24 @@ define void @callee_func_sgpr_spill_no_calls(i32 %in) #0 {
; FLATSCR-NEXT: s_or_saveexec_b64 s[0:1], -1
; FLATSCR-NEXT: scratch_store_dword off, v40, s32 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[0:1]
-; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0
-; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
-; FLATSCR-NEXT: v_writelane_b32 v40, s36, 2
-; FLATSCR-NEXT: v_writelane_b32 v40, s37, 3
-; FLATSCR-NEXT: v_writelane_b32 v40, s38, 4
-; FLATSCR-NEXT: v_writelane_b32 v40, s39, 5
-; FLATSCR-NEXT: v_writelane_b32 v40, s48, 6
-; FLATSCR-NEXT: v_writelane_b32 v40, s49, 7
-; FLATSCR-NEXT: v_writelane_b32 v40, s50, 8
-; FLATSCR-NEXT: v_writelane_b32 v40, s51, 9
-; FLATSCR-NEXT: v_writelane_b32 v40, s52, 10
-; FLATSCR-NEXT: v_writelane_b32 v40, s53, 11
-; FLATSCR-NEXT: v_writelane_b32 v40, s54, 12
-; FLATSCR-NEXT: v_writelane_b32 v40, s55, 13
-; FLATSCR-NEXT: v_writelane_b32 v40, s64, 14
-; FLATSCR-NEXT: v_writelane_b32 v40, s65, 15
-; FLATSCR-NEXT: v_writelane_b32 v40, s66, 16
-; FLATSCR-NEXT: v_writelane_b32 v40, s67, 17
+; FLATSCR-NEXT: v_writelane_b32 v40, s36, 0
+; FLATSCR-NEXT: v_writelane_b32 v40, s37, 1
+; FLATSCR-NEXT: v_writelane_b32 v40, s38, 2
+; FLATSCR-NEXT: v_writelane_b32 v40, s39, 3
+; FLATSCR-NEXT: v_writelane_b32 v40, s48, 4
+; FLATSCR-NEXT: v_writelane_b32 v40, s49, 5
+; FLATSCR-NEXT: v_writelane_b32 v40, s50, 6
+; FLATSCR-NEXT: v_writelane_b32 v40, s51, 7
+; FLATSCR-NEXT: v_writelane_b32 v40, s52, 8
+; FLATSCR-NEXT: v_writelane_b32 v40, s53, 9
+; FLATSCR-NEXT: v_writelane_b32 v40, s54, 10
+; FLATSCR-NEXT: v_writelane_b32 v40, s55, 11
+; FLATSCR-NEXT: v_writelane_b32 v40, s64, 12
+; FLATSCR-NEXT: v_writelane_b32 v40, s65, 13
+; FLATSCR-NEXT: v_writelane_b32 v40, s66, 14
+; FLATSCR-NEXT: v_writelane_b32 v40, s67, 15
+; FLATSCR-NEXT: v_writelane_b32 v40, s30, 16
+; FLATSCR-NEXT: v_writelane_b32 v40, s31, 17
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ;;#ASMEND
; FLATSCR-NEXT: ;;#ASMSTART
@@ -414,6 +414,7 @@ define void @callee_func_sgpr_spill_no_calls(i32 %in) #0 {
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; use s[16:31]
; FLATSCR-NEXT: ;;#ASMEND
+; FLATSCR-NEXT: v_readlane_b32 s30, v40, 16
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; use s[72:79]
; FLATSCR-NEXT: ;;#ASMEND
@@ -423,24 +424,23 @@ define void @callee_func_sgpr_spill_no_calls(i32 %in) #0 {
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; use s[0:15]
; FLATSCR-NEXT: ;;#ASMEND
-; FLATSCR-NEXT: v_readlane_b32 s67, v40, 17
-; FLATSCR-NEXT: v_readlane_b32 s66, v40, 16
-; FLATSCR-NEXT: v_readlane_b32 s65, v40, 15
-; FLATSCR-NEXT: v_readlane_b32 s64, v40, 14
-; FLATSCR-NEXT: v_readlane_b32 s55, v40, 13
-; FLATSCR-NEXT: v_readlane_b32 s54, v40, 12
-; FLATSCR-NEXT: v_readlane_b32 s53, v40, 11
-; FLATSCR-NEXT: v_readlane_b32 s52, v40, 10
-; FLATSCR-NEXT: v_readlane_b32 s51, v40, 9
-; FLATSCR-NEXT: v_readlane_b32 s50, v40, 8
-; FLATSCR-NEXT: v_readlane_b32 s49, v40, 7
-; FLATSCR-NEXT: v_readlane_b32 s48, v40, 6
-; FLATSCR-NEXT: v_readlane_b32 s39, v40, 5
-; FLATSCR-NEXT: v_readlane_b32 s38, v40, 4
-; FLATSCR-NEXT: v_readlane_b32 s37, v40, 3
-; FLATSCR-NEXT: v_readlane_b32 s36, v40, 2
-; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
-; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
+; FLATSCR-NEXT: v_readlane_b32 s31, v40, 17
+; FLATSCR-NEXT: v_readlane_b32 s67, v40, 15
+; FLATSCR-NEXT: v_readlane_b32 s66, v40, 14
+; FLATSCR-NEXT: v_readlane_b32 s65, v40, 13
+; FLATSCR-NEXT: v_readlane_b32 s64, v40, 12
+; FLATSCR-NEXT: v_readlane_b32 s55, v40, 11
+; FLATSCR-NEXT: v_readlane_b32 s54, v40, 10
+; FLATSCR-NEXT: v_readlane_b32 s53, v40, 9
+; FLATSCR-NEXT: v_readlane_b32 s52, v40, 8
+; FLATSCR-NEXT: v_readlane_b32 s51, v40, 7
+; FLATSCR-NEXT: v_readlane_b32 s50, v40, 6
+; FLATSCR-NEXT: v_readlane_b32 s49, v40, 5
+; FLATSCR-NEXT: v_readlane_b32 s48, v40, 4
+; FLATSCR-NEXT: v_readlane_b32 s39, v40, 3
+; FLATSCR-NEXT: v_readlane_b32 s38, v40, 2
+; FLATSCR-NEXT: v_readlane_b32 s37, v40, 1
+; FLATSCR-NEXT: v_readlane_b32 s36, v40, 0
; FLATSCR-NEXT: s_or_saveexec_b64 s[0:1], -1
; FLATSCR-NEXT: scratch_load_dword v40, off, s32 ; 4-byte Folded Reload
; FLATSCR-NEXT: s_mov_b64 exec, s[0:1]
@@ -971,14 +971,14 @@ define void @no_unused_non_csr_sgpr_for_fp() #1 {
; MUBUF-NEXT: s_mov_b64 exec, s[4:5]
; MUBUF-NEXT: v_writelane_b32 v1, s30, 0
; MUBUF-NEXT: v_mov_b32_e32 v0, 0
-; MUBUF-NEXT: s_addk_i32 s32, 0x300
; MUBUF-NEXT: v_writelane_b32 v1, s31, 1
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ;;#ASMEND
-; MUBUF-NEXT: v_readlane_b32 s31, v1, 1
+; MUBUF-NEXT: s_addk_i32 s32, 0x300
; MUBUF-NEXT: v_readlane_b32 s30, v1, 0
+; MUBUF-NEXT: v_readlane_b32 s31, v1, 1
; MUBUF-NEXT: s_mov_b32 s32, s33
; MUBUF-NEXT: s_xor_saveexec_b64 s[4:5], -1
; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
@@ -997,14 +997,14 @@ define void @no_unused_non_csr_sgpr_for_fp() #1 {
; FLATSCR-NEXT: s_mov_b64 exec, s[0:1]
; FLATSCR-NEXT: v_writelane_b32 v1, s30, 0
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
-; FLATSCR-NEXT: s_add_i32 s32, s32, 12
; FLATSCR-NEXT: v_writelane_b32 v1, s31, 1
; FLATSCR-NEXT: scratch_store_dword off, v0, s33
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ;;#ASMEND
-; FLATSCR-NEXT: v_readlane_b32 s31, v1, 1
+; FLATSCR-NEXT: s_add_i32 s32, s32, 12
; FLATSCR-NEXT: v_readlane_b32 s30, v1, 0
+; FLATSCR-NEXT: v_readlane_b32 s31, v1, 1
; FLATSCR-NEXT: s_mov_b32 s32, s33
; FLATSCR-NEXT: s_xor_saveexec_b64 s[0:1], -1
; FLATSCR-NEXT: scratch_load_dword v1, off, s33 offset:4 ; 4-byte Folded Reload
@@ -1037,17 +1037,17 @@ define void @no_unused_non_csr_sgpr_for_fp_no_scratch_vgpr() #1 {
; MUBUF-NEXT: s_mov_b64 exec, s[4:5]
; MUBUF-NEXT: v_writelane_b32 v40, s30, 0
; MUBUF-NEXT: v_mov_b32_e32 v0, 0
-; MUBUF-NEXT: s_addk_i32 s32, 0x300
; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ;;#ASMEND
+; MUBUF-NEXT: s_addk_i32 s32, 0x300
+; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; clobber nonpreserved initial VGPRs
; MUBUF-NEXT: ;;#ASMEND
; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
-; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
; MUBUF-NEXT: s_mov_b32 s32, s33
; MUBUF-NEXT: s_or_saveexec_b64 s[4:5], -1
; MUBUF-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
@@ -1066,17 +1066,17 @@ define void @no_unused_non_csr_sgpr_for_fp_no_scratch_vgpr() #1 {
; FLATSCR-NEXT: s_mov_b64 exec, s[0:1]
; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
-; FLATSCR-NEXT: s_add_i32 s32, s32, 12
; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
; FLATSCR-NEXT: scratch_store_dword off, v0, s33
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ;;#ASMEND
+; FLATSCR-NEXT: s_add_i32 s32, s32, 12
+; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; clobber nonpreserved initial VGPRs
; FLATSCR-NEXT: ;;#ASMEND
; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
-; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
; FLATSCR-NEXT: s_mov_b32 s32, s33
; FLATSCR-NEXT: s_or_saveexec_b64 s[0:1], -1
; FLATSCR-NEXT: scratch_load_dword v40, off, s33 offset:4 ; 4-byte Folded Reload
@@ -1118,18 +1118,18 @@ define void @scratch_reg_needed_mubuf_offset(ptr addrspace(5) byval([4096 x i8])
; MUBUF-NEXT: v_writelane_b32 v40, s30, 0
; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: v_mov_b32_e32 v1, 0x1000
-; MUBUF-NEXT: s_add_i32 s32, s32, 0x40300
; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], s33 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; clobber nonpreserved SGPRs
; MUBUF-NEXT: ;;#ASMEND
+; MUBUF-NEXT: s_add_i32 s32, s32, 0x40300
+; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; clobber nonpreserved VGPRs
; MUBUF-NEXT: ;;#ASMEND
; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
-; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
; MUBUF-NEXT: s_mov_b32 s32, s33
; MUBUF-NEXT: s_or_saveexec_b64 s[4:5], -1
; MUBUF-NEXT: s_add_i32 s6, s33, 0x40100
@@ -1158,11 +1158,11 @@ define void @scratch_reg_needed_mubuf_offset(ptr addrspace(5) byval([4096 x i8])
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; clobber nonpreserved SGPRs
; FLATSCR-NEXT: ;;#ASMEND
+; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; clobber nonpreserved VGPRs
; FLATSCR-NEXT: ;;#ASMEND
; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
-; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
; FLATSCR-NEXT: s_mov_b32 s32, s33
; FLATSCR-NEXT: s_or_saveexec_b64 s[0:1], -1
; FLATSCR-NEXT: s_add_i32 s2, s33, 0x1004
@@ -1220,8 +1220,8 @@ define void @ipra_call_with_stack() #0 {
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; MUBUF-NEXT: v_readlane_b32 s31, v1, 1
; MUBUF-NEXT: v_readlane_b32 s30, v1, 0
+; MUBUF-NEXT: v_readlane_b32 s31, v1, 1
; MUBUF-NEXT: s_mov_b32 s32, s33
; MUBUF-NEXT: s_xor_saveexec_b64 s[4:5], -1
; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
@@ -1248,8 +1248,8 @@ define void @ipra_call_with_stack() #0 {
; FLATSCR-NEXT: scratch_store_dword off, v0, s33
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; FLATSCR-NEXT: v_readlane_b32 s31, v1, 1
; FLATSCR-NEXT: v_readlane_b32 s30, v1, 0
+; FLATSCR-NEXT: v_readlane_b32 s31, v1, 1
; FLATSCR-NEXT: s_mov_b32 s32, s33
; FLATSCR-NEXT: s_xor_saveexec_b64 s[0:1], -1
; FLATSCR-NEXT: scratch_load_dword v1, off, s33 offset:4 ; 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
index fccee3da6d77e..ce2ce4380d3b7 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
@@ -430,8 +430,8 @@ define void @func_indirect_use_workitem_id_x() #1 {
; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -463,8 +463,8 @@ define void @func_indirect_use_workitem_id_y() #1 {
; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -496,8 +496,8 @@ define void @func_indirect_use_workitem_id_z() #1 {
; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -984,8 +984,8 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
; GFX7-NEXT: v_writelane_b32 v40, s31, 1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GFX7-NEXT: v_readlane_b32 s31, v40, 1
; GFX7-NEXT: v_readlane_b32 s30, v40, 0
+; GFX7-NEXT: v_readlane_b32 s31, v40, 1
; GFX7-NEXT: s_mov_b32 s32, s33
; GFX7-NEXT: v_readlane_b32 s4, v40, 2
; GFX7-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -1048,8 +1048,8 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
; GFX90A-NEXT: v_writelane_b32 v40, s31, 1
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GFX90A-NEXT: v_readlane_b32 s31, v40, 1
; GFX90A-NEXT: v_readlane_b32 s30, v40, 0
+; GFX90A-NEXT: v_readlane_b32 s31, v40, 1
; GFX90A-NEXT: s_mov_b32 s32, s33
; GFX90A-NEXT: v_readlane_b32 s4, v40, 2
; GFX90A-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -1094,8 +1094,8 @@ define void @too_many_args_call_too_many_args_use_workitem_id_x(
; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s32
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -1445,8 +1445,8 @@ define void @func_call_too_many_args_use_workitem_id_x_byval() #1 {
; GCN-NEXT: v_mov_b32_e32 v0, 10
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
index bb2f06bfe83f8..f20be656f3af0 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
@@ -275,8 +275,8 @@ define void @func_indirect_use_workitem_id_x() #1 {
; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -308,8 +308,8 @@ define void @func_indirect_use_workitem_id_y() #1 {
; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -341,8 +341,8 @@ define void @func_indirect_use_workitem_id_z() #1 {
; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -696,8 +696,8 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -742,8 +742,8 @@ define void @too_many_args_call_too_many_args_use_workitem_id_x(
; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s32
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -1019,8 +1019,8 @@ define void @func_call_too_many_args_use_workitem_id_x_byval() #1 {
; GCN-NEXT: v_mov_b32_e32 v0, 10
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -1469,8 +1469,8 @@ define void @func_call_no_workitem_id_hints() #2 {
; GCN-NEXT: v_mov_b32_e32 v0, 9
; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll b/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
index 38c20c7cf62d6..0cab17c9bfcfc 100644
--- a/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
+++ b/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
@@ -40,8 +40,8 @@ define float @call_split_type_used_outside_block_v2f32() #0 {
; GCN-NEXT: s_addc_u32 s17, s17, func_v2f32 at rel32@hi+12
; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -76,8 +76,8 @@ define float @call_split_type_used_outside_block_v3f32() #0 {
; GCN-NEXT: s_addc_u32 s17, s17, func_v3f32 at rel32@hi+12
; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -112,8 +112,8 @@ define half @call_split_type_used_outside_block_v4f16() #0 {
; GCN-NEXT: s_addc_u32 s17, s17, func_v4f16 at rel32@hi+12
; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -148,8 +148,8 @@ define { i32, half } @call_split_type_used_outside_block_struct() #0 {
; GCN-NEXT: s_addc_u32 s17, s17, func_struct at rel32@hi+12
; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_mov_b32_e32 v1, v4
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
diff --git a/llvm/test/CodeGen/AMDGPU/debug-frame.ll b/llvm/test/CodeGen/AMDGPU/debug-frame.ll
index 676144e65c10f..7d38cea998256 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-frame.ll
+++ b/llvm/test/CodeGen/AMDGPU/debug-frame.ll
@@ -2005,8 +2005,8 @@ define hidden void @func_call_clobber() #0 {
; GFX900-NEXT: s_addc_u32 s17, s17, ex at rel32@hi+12
; GFX900-NEXT: v_writelane_b32 v40, s31, 1
; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX900-NEXT: v_readlane_b32 s31, v40, 1
; GFX900-NEXT: v_readlane_b32 s30, v40, 0
+; GFX900-NEXT: v_readlane_b32 s31, v40, 1
; GFX900-NEXT: s_mov_b32 s32, s33
; GFX900-NEXT: v_readlane_b32 s4, v40, 2
; GFX900-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -2278,8 +2278,8 @@ define hidden void @func_call_clobber() #0 {
; GFX90A-V2A-DIS-NEXT: s_addc_u32 s17, s17, ex at rel32@hi+12
; GFX90A-V2A-DIS-NEXT: v_writelane_b32 v40, s31, 1
; GFX90A-V2A-DIS-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX90A-V2A-DIS-NEXT: v_readlane_b32 s31, v40, 1
; GFX90A-V2A-DIS-NEXT: v_readlane_b32 s30, v40, 0
+; GFX90A-V2A-DIS-NEXT: v_readlane_b32 s31, v40, 1
; GFX90A-V2A-DIS-NEXT: s_mov_b32 s32, s33
; GFX90A-V2A-DIS-NEXT: v_readlane_b32 s4, v40, 2
; GFX90A-V2A-DIS-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -2551,8 +2551,8 @@ define hidden void @func_call_clobber() #0 {
; GFX90A-V2A-EN-NEXT: s_addc_u32 s17, s17, ex at rel32@hi+12
; GFX90A-V2A-EN-NEXT: v_writelane_b32 v40, s31, 1
; GFX90A-V2A-EN-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX90A-V2A-EN-NEXT: v_readlane_b32 s31, v40, 1
; GFX90A-V2A-EN-NEXT: v_readlane_b32 s30, v40, 0
+; GFX90A-V2A-EN-NEXT: v_readlane_b32 s31, v40, 1
; GFX90A-V2A-EN-NEXT: s_mov_b32 s32, s33
; GFX90A-V2A-EN-NEXT: v_readlane_b32 s4, v40, 2
; GFX90A-V2A-EN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -2793,8 +2793,8 @@ define hidden void @func_call_clobber() #0 {
; WAVE32-NEXT: s_addc_u32 s17, s17, ex at rel32@hi+12
; WAVE32-NEXT: v_writelane_b32 v40, s31, 1
; WAVE32-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; WAVE32-NEXT: v_readlane_b32 s31, v40, 1
; WAVE32-NEXT: v_readlane_b32 s30, v40, 0
+; WAVE32-NEXT: v_readlane_b32 s31, v40, 1
; WAVE32-NEXT: s_mov_b32 s32, s33
; WAVE32-NEXT: v_readlane_b32 s4, v40, 2
; WAVE32-NEXT: s_or_saveexec_b32 s5, -1
diff --git a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
index a0c25b2a0beb3..705d403764503 100644
--- a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
@@ -489,22 +489,20 @@ define weak_odr void @test(i32 %0) !dbg !34 {
; CHECK-NEXT: v_writelane_b32 v41, s16, 16
; CHECK-NEXT: .cfi_llvm_vector_registers 65, 2601, 16, 32
; CHECK-NEXT: .cfi_def_cfa_register 65
-; CHECK-NEXT: v_writelane_b32 v41, s30, 0
-; CHECK-NEXT: v_writelane_b32 v41, s31, 1
-; CHECK-NEXT: v_writelane_b32 v41, s34, 2
-; CHECK-NEXT: v_writelane_b32 v41, s35, 3
-; CHECK-NEXT: v_writelane_b32 v41, s36, 4
-; CHECK-NEXT: v_writelane_b32 v41, s37, 5
-; CHECK-NEXT: v_writelane_b32 v41, s38, 6
-; CHECK-NEXT: v_writelane_b32 v41, s39, 7
-; CHECK-NEXT: v_writelane_b32 v41, s48, 8
-; CHECK-NEXT: v_writelane_b32 v41, s49, 9
-; CHECK-NEXT: v_writelane_b32 v41, s50, 10
-; CHECK-NEXT: v_writelane_b32 v41, s51, 11
-; CHECK-NEXT: v_writelane_b32 v41, s52, 12
+; CHECK-NEXT: v_writelane_b32 v41, s34, 0
+; CHECK-NEXT: v_writelane_b32 v41, s35, 1
+; CHECK-NEXT: v_writelane_b32 v41, s36, 2
+; CHECK-NEXT: v_writelane_b32 v41, s37, 3
+; CHECK-NEXT: v_writelane_b32 v41, s38, 4
+; CHECK-NEXT: v_writelane_b32 v41, s39, 5
+; CHECK-NEXT: v_writelane_b32 v41, s48, 6
+; CHECK-NEXT: v_writelane_b32 v41, s49, 7
+; CHECK-NEXT: v_writelane_b32 v41, s50, 8
+; CHECK-NEXT: v_writelane_b32 v41, s51, 9
+; CHECK-NEXT: v_writelane_b32 v41, s52, 10
; CHECK-NEXT: s_addk_i32 s32, 0x400
-; CHECK-NEXT: v_writelane_b32 v41, s53, 13
-; CHECK-NEXT: v_writelane_b32 v41, s54, 14
+; CHECK-NEXT: v_writelane_b32 v41, s53, 11
+; CHECK-NEXT: v_writelane_b32 v41, s54, 12
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
; CHECK-NEXT: ;DEBUG_VALUE: dummy:dummy <- undef
; CHECK-NEXT: .Ltmp0:
@@ -512,10 +510,12 @@ define weak_odr void @test(i32 %0) !dbg !34 {
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, __kmpc_alloc_shared at gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s5, s5, __kmpc_alloc_shared at gotpcrel32@hi+12
-; CHECK-NEXT: v_writelane_b32 v41, s55, 15
+; CHECK-NEXT: v_writelane_b32 v41, s55, 13
; CHECK-NEXT: s_load_dwordx2 s[54:55], s[4:5], 0x0
+; CHECK-NEXT: v_writelane_b32 v41, s30, 14
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
+; CHECK-NEXT: v_writelane_b32 v41, s31, 15
; CHECK-NEXT: v_mov_b32_e32 v40, v31
; CHECK-NEXT: s_mov_b32 s50, s15
; CHECK-NEXT: s_mov_b32 s51, s14
@@ -541,23 +541,23 @@ define weak_odr void @test(i32 %0) !dbg !34 {
; CHECK-NEXT: .loc 1 0 9 is_stmt 0 ; dummy:0:9
; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; CHECK-NEXT: v_mov_b32_e32 v2, 0
+; CHECK-NEXT: v_readlane_b32 s30, v41, 14
; CHECK-NEXT: flat_store_dword v[0:1], v2
-; CHECK-NEXT: v_readlane_b32 s55, v41, 15
-; CHECK-NEXT: v_readlane_b32 s54, v41, 14
-; CHECK-NEXT: v_readlane_b32 s53, v41, 13
-; CHECK-NEXT: v_readlane_b32 s52, v41, 12
-; CHECK-NEXT: v_readlane_b32 s51, v41, 11
-; CHECK-NEXT: v_readlane_b32 s50, v41, 10
-; CHECK-NEXT: v_readlane_b32 s49, v41, 9
-; CHECK-NEXT: v_readlane_b32 s48, v41, 8
-; CHECK-NEXT: v_readlane_b32 s39, v41, 7
-; CHECK-NEXT: v_readlane_b32 s38, v41, 6
-; CHECK-NEXT: v_readlane_b32 s37, v41, 5
-; CHECK-NEXT: v_readlane_b32 s36, v41, 4
-; CHECK-NEXT: v_readlane_b32 s35, v41, 3
-; CHECK-NEXT: v_readlane_b32 s34, v41, 2
-; CHECK-NEXT: v_readlane_b32 s31, v41, 1
-; CHECK-NEXT: v_readlane_b32 s30, v41, 0
+; CHECK-NEXT: v_readlane_b32 s31, v41, 15
+; CHECK-NEXT: v_readlane_b32 s55, v41, 13
+; CHECK-NEXT: v_readlane_b32 s54, v41, 12
+; CHECK-NEXT: v_readlane_b32 s53, v41, 11
+; CHECK-NEXT: v_readlane_b32 s52, v41, 10
+; CHECK-NEXT: v_readlane_b32 s51, v41, 9
+; CHECK-NEXT: v_readlane_b32 s50, v41, 8
+; CHECK-NEXT: v_readlane_b32 s49, v41, 7
+; CHECK-NEXT: v_readlane_b32 s48, v41, 6
+; CHECK-NEXT: v_readlane_b32 s39, v41, 5
+; CHECK-NEXT: v_readlane_b32 s38, v41, 4
+; CHECK-NEXT: v_readlane_b32 s37, v41, 3
+; CHECK-NEXT: v_readlane_b32 s36, v41, 2
+; CHECK-NEXT: v_readlane_b32 s35, v41, 1
+; CHECK-NEXT: v_readlane_b32 s34, v41, 0
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: v_readlane_b32 s4, v41, 16
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll b/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
index bcccf50e3805c..db48100aa7caf 100644
--- a/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
+++ b/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
@@ -299,8 +299,8 @@ define amdgpu_gfx void @amdgpu_gfx() #0 {
; CHECK-TRUE16-NEXT: s_wait_alu 0xfffe
; CHECK-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; CHECK-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; CHECK-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; CHECK-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-TRUE16-NEXT: s_mov_b32 s32, s33
; CHECK-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; CHECK-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -339,8 +339,8 @@ define amdgpu_gfx void @amdgpu_gfx() #0 {
; CHECK-FAKE16-NEXT: s_wait_alu 0xfffe
; CHECK-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; CHECK-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; CHECK-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; CHECK-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-FAKE16-NEXT: s_mov_b32 s32, s33
; CHECK-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
; CHECK-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
diff --git a/llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll b/llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll
index 76a2114a000cf..cba5aa8ef3672 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll
+++ b/llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll
@@ -55,8 +55,8 @@ define void @test_stack_realign(<8 x i32> %val, i32 %idx) #0 {
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GCN-NEXT: v_readlane_b32 s31, v42, 1
; GCN-NEXT: v_readlane_b32 s30, v42, 0
+; GCN-NEXT: v_readlane_b32 s31, v42, 1
; GCN-NEXT: s_mov_b32 s32, s34
; GCN-NEXT: v_readlane_b32 s4, v42, 2
; GCN-NEXT: v_readlane_b32 s34, v42, 3
diff --git a/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll b/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
index 2e88da142bb41..6abe5998d6767 100644
--- a/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
+++ b/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
@@ -26,8 +26,8 @@ define void @callee_with_stack_and_call() #0 {
; SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33
; SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
; SPILL-TO-VGPR-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; SPILL-TO-VGPR-NEXT: v_readlane_b32 s31, v40, 1
; SPILL-TO-VGPR-NEXT: v_readlane_b32 s30, v40, 0
+; SPILL-TO-VGPR-NEXT: v_readlane_b32 s31, v40, 1
; SPILL-TO-VGPR-NEXT: s_mov_b32 s32, s33
; SPILL-TO-VGPR-NEXT: v_readlane_b32 s4, v40, 2
; SPILL-TO-VGPR-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -46,21 +46,14 @@ define void @callee_with_stack_and_call() #0 {
; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; NO-SPILL-TO-VGPR-NEXT: s_addk_i32 s32, 0x800
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec
-; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 1
+; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 3
; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:16
; NO-SPILL-TO-VGPR-NEXT: v_writelane_b32 v0, s30, 0
+; NO-SPILL-TO-VGPR-NEXT: v_writelane_b32 v0, s31, 1
; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:16
; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5]
-; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec
-; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 1
-; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:16
-; NO-SPILL-TO-VGPR-NEXT: v_writelane_b32 v0, s31, 0
-; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:16
-; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
-; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5]
; NO-SPILL-TO-VGPR-NEXT: v_mov_b32_e32 v0, 0
; NO-SPILL-TO-VGPR-NEXT: s_getpc_b64 s[4:5]
; NO-SPILL-TO-VGPR-NEXT: s_add_u32 s4, s4, external_void_func_void at rel32@lo+4
@@ -69,20 +62,12 @@ define void @callee_with_stack_and_call() #0 {
; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
; NO-SPILL-TO-VGPR-NEXT: s_swappc_b64 s[30:31], s[4:5]
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec
-; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 1
-; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:16
-; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
-; NO-SPILL-TO-VGPR-NEXT: v_readlane_b32 s31, v0, 0
-; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:16
-; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
-; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5]
-; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec
-; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 1
+; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 3
; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:16
; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
; NO-SPILL-TO-VGPR-NEXT: v_readlane_b32 s30, v0, 0
+; NO-SPILL-TO-VGPR-NEXT: v_readlane_b32 s31, v0, 1
; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:16
; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
index 0f535c3a3bdbc..6dd683e6fca53 100644
--- a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
@@ -1740,8 +1740,8 @@ define void @caller_void_func_i32_v2float_inreg(i32 inreg %arg0, <2 x float> inr
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_swappc_b64 s[30:31], s[20:21]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -1770,8 +1770,8 @@ define void @caller_void_func_i32_v2float_inreg(i32 inreg %arg0, <2 x float> inr
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -2159,8 +2159,8 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p
; GFX9-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -2201,8 +2201,8 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll b/llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
index 9d137fb4101e4..a2f203a111e18 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
@@ -39,47 +39,47 @@ define amdgpu_gfx void @gfx_func() {
; SDAG-NEXT: v_writelane_b32 v40, s27, 23
; SDAG-NEXT: v_writelane_b32 v40, s28, 24
; SDAG-NEXT: v_writelane_b32 v40, s29, 25
-; SDAG-NEXT: v_writelane_b32 v40, s30, 26
-; SDAG-NEXT: v_writelane_b32 v40, s31, 27
-; SDAG-NEXT: v_writelane_b32 v40, s72, 28
-; SDAG-NEXT: v_writelane_b32 v40, s73, 29
-; SDAG-NEXT: v_writelane_b32 v40, s74, 30
-; SDAG-NEXT: v_writelane_b32 v40, s75, 31
-; SDAG-NEXT: v_writelane_b32 v40, s76, 32
-; SDAG-NEXT: v_writelane_b32 v40, s77, 33
-; SDAG-NEXT: v_writelane_b32 v40, s78, 34
-; SDAG-NEXT: v_writelane_b32 v40, s79, 35
-; SDAG-NEXT: v_writelane_b32 v40, s88, 36
-; SDAG-NEXT: v_writelane_b32 v40, s89, 37
-; SDAG-NEXT: v_writelane_b32 v40, s90, 38
-; SDAG-NEXT: v_writelane_b32 v40, s91, 39
-; SDAG-NEXT: v_writelane_b32 v40, s92, 40
-; SDAG-NEXT: v_writelane_b32 v40, s93, 41
-; SDAG-NEXT: v_writelane_b32 v40, s94, 42
+; SDAG-NEXT: v_writelane_b32 v40, s72, 26
+; SDAG-NEXT: v_writelane_b32 v40, s73, 27
+; SDAG-NEXT: v_writelane_b32 v40, s74, 28
+; SDAG-NEXT: v_writelane_b32 v40, s75, 29
+; SDAG-NEXT: v_writelane_b32 v40, s76, 30
+; SDAG-NEXT: v_writelane_b32 v40, s77, 31
+; SDAG-NEXT: v_writelane_b32 v40, s78, 32
+; SDAG-NEXT: v_writelane_b32 v40, s79, 33
+; SDAG-NEXT: v_writelane_b32 v40, s88, 34
+; SDAG-NEXT: v_writelane_b32 v40, s89, 35
+; SDAG-NEXT: v_writelane_b32 v40, s90, 36
+; SDAG-NEXT: v_writelane_b32 v40, s91, 37
+; SDAG-NEXT: v_writelane_b32 v40, s92, 38
+; SDAG-NEXT: v_writelane_b32 v40, s93, 39
+; SDAG-NEXT: v_writelane_b32 v40, s94, 40
+; SDAG-NEXT: v_writelane_b32 v40, s95, 41
+; SDAG-NEXT: v_writelane_b32 v40, s30, 42
; SDAG-NEXT: s_mov_b32 s35, extern_c_func at abs32@hi
; SDAG-NEXT: s_mov_b32 s34, extern_c_func at abs32@lo
; SDAG-NEXT: s_mov_b64 s[8:9], 0
; SDAG-NEXT: s_addk_i32 s32, 0x400
-; SDAG-NEXT: v_writelane_b32 v40, s95, 43
+; SDAG-NEXT: v_writelane_b32 v40, s31, 43
; SDAG-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; SDAG-NEXT: v_readlane_b32 s95, v40, 43
-; SDAG-NEXT: v_readlane_b32 s94, v40, 42
-; SDAG-NEXT: v_readlane_b32 s93, v40, 41
-; SDAG-NEXT: v_readlane_b32 s92, v40, 40
-; SDAG-NEXT: v_readlane_b32 s91, v40, 39
-; SDAG-NEXT: v_readlane_b32 s90, v40, 38
-; SDAG-NEXT: v_readlane_b32 s89, v40, 37
-; SDAG-NEXT: v_readlane_b32 s88, v40, 36
-; SDAG-NEXT: v_readlane_b32 s79, v40, 35
-; SDAG-NEXT: v_readlane_b32 s78, v40, 34
-; SDAG-NEXT: v_readlane_b32 s77, v40, 33
-; SDAG-NEXT: v_readlane_b32 s76, v40, 32
-; SDAG-NEXT: v_readlane_b32 s75, v40, 31
-; SDAG-NEXT: v_readlane_b32 s74, v40, 30
-; SDAG-NEXT: v_readlane_b32 s73, v40, 29
-; SDAG-NEXT: v_readlane_b32 s72, v40, 28
-; SDAG-NEXT: v_readlane_b32 s31, v40, 27
-; SDAG-NEXT: v_readlane_b32 s30, v40, 26
+; SDAG-NEXT: v_readlane_b32 s30, v40, 42
+; SDAG-NEXT: v_readlane_b32 s31, v40, 43
+; SDAG-NEXT: v_readlane_b32 s95, v40, 41
+; SDAG-NEXT: v_readlane_b32 s94, v40, 40
+; SDAG-NEXT: v_readlane_b32 s93, v40, 39
+; SDAG-NEXT: v_readlane_b32 s92, v40, 38
+; SDAG-NEXT: v_readlane_b32 s91, v40, 37
+; SDAG-NEXT: v_readlane_b32 s90, v40, 36
+; SDAG-NEXT: v_readlane_b32 s89, v40, 35
+; SDAG-NEXT: v_readlane_b32 s88, v40, 34
+; SDAG-NEXT: v_readlane_b32 s79, v40, 33
+; SDAG-NEXT: v_readlane_b32 s78, v40, 32
+; SDAG-NEXT: v_readlane_b32 s77, v40, 31
+; SDAG-NEXT: v_readlane_b32 s76, v40, 30
+; SDAG-NEXT: v_readlane_b32 s75, v40, 29
+; SDAG-NEXT: v_readlane_b32 s74, v40, 28
+; SDAG-NEXT: v_readlane_b32 s73, v40, 27
+; SDAG-NEXT: v_readlane_b32 s72, v40, 26
; SDAG-NEXT: v_readlane_b32 s29, v40, 25
; SDAG-NEXT: v_readlane_b32 s28, v40, 24
; SDAG-NEXT: v_readlane_b32 s27, v40, 23
@@ -148,47 +148,47 @@ define amdgpu_gfx void @gfx_func() {
; GISEL-NEXT: v_writelane_b32 v40, s27, 23
; GISEL-NEXT: v_writelane_b32 v40, s28, 24
; GISEL-NEXT: v_writelane_b32 v40, s29, 25
-; GISEL-NEXT: v_writelane_b32 v40, s30, 26
-; GISEL-NEXT: v_writelane_b32 v40, s31, 27
-; GISEL-NEXT: v_writelane_b32 v40, s72, 28
-; GISEL-NEXT: v_writelane_b32 v40, s73, 29
-; GISEL-NEXT: v_writelane_b32 v40, s74, 30
-; GISEL-NEXT: v_writelane_b32 v40, s75, 31
-; GISEL-NEXT: v_writelane_b32 v40, s76, 32
-; GISEL-NEXT: v_writelane_b32 v40, s77, 33
-; GISEL-NEXT: v_writelane_b32 v40, s78, 34
-; GISEL-NEXT: v_writelane_b32 v40, s79, 35
-; GISEL-NEXT: v_writelane_b32 v40, s88, 36
-; GISEL-NEXT: v_writelane_b32 v40, s89, 37
-; GISEL-NEXT: v_writelane_b32 v40, s90, 38
-; GISEL-NEXT: v_writelane_b32 v40, s91, 39
-; GISEL-NEXT: v_writelane_b32 v40, s92, 40
-; GISEL-NEXT: v_writelane_b32 v40, s93, 41
-; GISEL-NEXT: v_writelane_b32 v40, s94, 42
+; GISEL-NEXT: v_writelane_b32 v40, s72, 26
+; GISEL-NEXT: v_writelane_b32 v40, s73, 27
+; GISEL-NEXT: v_writelane_b32 v40, s74, 28
+; GISEL-NEXT: v_writelane_b32 v40, s75, 29
+; GISEL-NEXT: v_writelane_b32 v40, s76, 30
+; GISEL-NEXT: v_writelane_b32 v40, s77, 31
+; GISEL-NEXT: v_writelane_b32 v40, s78, 32
+; GISEL-NEXT: v_writelane_b32 v40, s79, 33
+; GISEL-NEXT: v_writelane_b32 v40, s88, 34
+; GISEL-NEXT: v_writelane_b32 v40, s89, 35
+; GISEL-NEXT: v_writelane_b32 v40, s90, 36
+; GISEL-NEXT: v_writelane_b32 v40, s91, 37
+; GISEL-NEXT: v_writelane_b32 v40, s92, 38
+; GISEL-NEXT: v_writelane_b32 v40, s93, 39
+; GISEL-NEXT: v_writelane_b32 v40, s94, 40
+; GISEL-NEXT: v_writelane_b32 v40, s95, 41
+; GISEL-NEXT: v_writelane_b32 v40, s30, 42
; GISEL-NEXT: s_mov_b32 s34, extern_c_func at abs32@lo
; GISEL-NEXT: s_mov_b32 s35, extern_c_func at abs32@hi
; GISEL-NEXT: s_mov_b64 s[8:9], 0
; GISEL-NEXT: s_addk_i32 s32, 0x400
-; GISEL-NEXT: v_writelane_b32 v40, s95, 43
+; GISEL-NEXT: v_writelane_b32 v40, s31, 43
; GISEL-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GISEL-NEXT: v_readlane_b32 s95, v40, 43
-; GISEL-NEXT: v_readlane_b32 s94, v40, 42
-; GISEL-NEXT: v_readlane_b32 s93, v40, 41
-; GISEL-NEXT: v_readlane_b32 s92, v40, 40
-; GISEL-NEXT: v_readlane_b32 s91, v40, 39
-; GISEL-NEXT: v_readlane_b32 s90, v40, 38
-; GISEL-NEXT: v_readlane_b32 s89, v40, 37
-; GISEL-NEXT: v_readlane_b32 s88, v40, 36
-; GISEL-NEXT: v_readlane_b32 s79, v40, 35
-; GISEL-NEXT: v_readlane_b32 s78, v40, 34
-; GISEL-NEXT: v_readlane_b32 s77, v40, 33
-; GISEL-NEXT: v_readlane_b32 s76, v40, 32
-; GISEL-NEXT: v_readlane_b32 s75, v40, 31
-; GISEL-NEXT: v_readlane_b32 s74, v40, 30
-; GISEL-NEXT: v_readlane_b32 s73, v40, 29
-; GISEL-NEXT: v_readlane_b32 s72, v40, 28
-; GISEL-NEXT: v_readlane_b32 s31, v40, 27
-; GISEL-NEXT: v_readlane_b32 s30, v40, 26
+; GISEL-NEXT: v_readlane_b32 s30, v40, 42
+; GISEL-NEXT: v_readlane_b32 s31, v40, 43
+; GISEL-NEXT: v_readlane_b32 s95, v40, 41
+; GISEL-NEXT: v_readlane_b32 s94, v40, 40
+; GISEL-NEXT: v_readlane_b32 s93, v40, 39
+; GISEL-NEXT: v_readlane_b32 s92, v40, 38
+; GISEL-NEXT: v_readlane_b32 s91, v40, 37
+; GISEL-NEXT: v_readlane_b32 s90, v40, 36
+; GISEL-NEXT: v_readlane_b32 s89, v40, 35
+; GISEL-NEXT: v_readlane_b32 s88, v40, 34
+; GISEL-NEXT: v_readlane_b32 s79, v40, 33
+; GISEL-NEXT: v_readlane_b32 s78, v40, 32
+; GISEL-NEXT: v_readlane_b32 s77, v40, 31
+; GISEL-NEXT: v_readlane_b32 s76, v40, 30
+; GISEL-NEXT: v_readlane_b32 s75, v40, 29
+; GISEL-NEXT: v_readlane_b32 s74, v40, 28
+; GISEL-NEXT: v_readlane_b32 s73, v40, 27
+; GISEL-NEXT: v_readlane_b32 s72, v40, 26
; GISEL-NEXT: v_readlane_b32 s29, v40, 25
; GISEL-NEXT: v_readlane_b32 s28, v40, 24
; GISEL-NEXT: v_readlane_b32 s27, v40, 23
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
index 234eaa8af7edf..39231558934a7 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
@@ -141,8 +141,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 {
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -170,8 +170,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 {
; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -200,8 +200,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -229,8 +229,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -264,8 +264,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 {
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -295,8 +295,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 {
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -326,8 +326,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 {
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-NEXT: scratch_store_b8 off, v0, s32
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -357,8 +357,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 {
; GFX10-SCRATCH-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -393,8 +393,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 {
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -424,8 +424,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 {
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -455,8 +455,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 {
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-NEXT: scratch_store_b8 off, v0, s32
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -486,8 +486,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 {
; GFX10-SCRATCH-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -519,8 +519,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -547,8 +547,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -576,8 +576,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 {
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -604,8 +604,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 {
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -632,8 +632,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -665,8 +665,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -694,8 +694,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -724,8 +724,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -753,8 +753,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -782,8 +782,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -816,8 +816,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -845,8 +845,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -875,8 +875,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -904,8 +904,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -933,8 +933,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -966,8 +966,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -994,8 +994,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -1023,8 +1023,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 {
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -1051,8 +1051,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 {
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -1079,8 +1079,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -1112,8 +1112,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -1141,8 +1141,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -1171,8 +1171,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -1200,8 +1200,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -1229,8 +1229,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -1263,8 +1263,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -1292,8 +1292,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -1322,8 +1322,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -1351,8 +1351,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -1380,8 +1380,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -1413,8 +1413,8 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -1441,8 +1441,8 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -1470,8 +1470,8 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -1498,8 +1498,8 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -1531,8 +1531,8 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -1560,8 +1560,8 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -1589,8 +1589,8 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -1618,8 +1618,8 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -1652,8 +1652,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -1682,8 +1682,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -1713,8 +1713,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -1743,8 +1743,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -1779,8 +1779,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -1810,8 +1810,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -1840,8 +1840,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -1871,8 +1871,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -1907,8 +1907,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -1939,8 +1939,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -1970,8 +1970,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -2002,8 +2002,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -2043,8 +2043,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -2077,8 +2077,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -2109,8 +2109,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -2143,8 +2143,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -2177,8 +2177,8 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -2205,8 +2205,8 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -2234,8 +2234,8 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 {
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -2262,8 +2262,8 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 {
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -2290,8 +2290,8 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -2322,8 +2322,8 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -2350,8 +2350,8 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -2379,8 +2379,8 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -2407,8 +2407,8 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -2440,8 +2440,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -2469,8 +2469,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -2498,8 +2498,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -2527,8 +2527,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -2561,8 +2561,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -2591,8 +2591,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -2621,8 +2621,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -2651,8 +2651,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -2687,8 +2687,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -2719,8 +2719,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -2750,8 +2750,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -2782,8 +2782,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -2815,8 +2815,8 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -2844,8 +2844,8 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -2873,8 +2873,8 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -2902,8 +2902,8 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -2937,8 +2937,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -2968,8 +2968,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -2998,8 +2998,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -3029,8 +3029,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -3066,8 +3066,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -3099,8 +3099,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -3130,8 +3130,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -3163,8 +3163,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -3200,8 +3200,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -3233,8 +3233,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 {
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -3267,8 +3267,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -3300,8 +3300,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -3333,8 +3333,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -3371,8 +3371,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 {
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -3404,8 +3404,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -3437,8 +3437,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 {
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -3470,8 +3470,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 {
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -3509,8 +3509,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 {
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -3543,8 +3543,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 24, v0
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -3577,8 +3577,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 {
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 24, v0
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -3611,8 +3611,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 {
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v3, 24, v0
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -3652,8 +3652,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 {
; GFX9-NEXT: v_mov_b32_e32 v0, v5
; GFX9-NEXT: v_mov_b32_e32 v4, v6
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -3688,8 +3688,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 {
; GFX10-NEXT: v_mov_b32_e32 v0, v5
; GFX10-NEXT: v_mov_b32_e32 v4, v6
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -3724,8 +3724,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 {
; GFX11-NEXT: v_mov_b32_e32 v0, v5
; GFX11-NEXT: v_mov_b32_e32 v4, v6
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -3760,8 +3760,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 {
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, v5
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, v6
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -3804,8 +3804,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 {
; GFX9-NEXT: v_mov_b32_e32 v4, v1
; GFX9-NEXT: v_mov_b32_e32 v1, v8
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -3843,8 +3843,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 {
; GFX10-NEXT: v_mov_b32_e32 v4, v1
; GFX10-NEXT: v_mov_b32_e32 v1, v8
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -3881,8 +3881,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 {
; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX11-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, v8
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -3920,8 +3920,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 {
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, v1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, v8
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -3996,8 +3996,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 {
; GFX9-NEXT: v_mov_b32_e32 v18, v33
; GFX9-NEXT: v_mov_b32_e32 v19, v34
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -4068,8 +4068,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 {
; GFX10-NEXT: v_mov_b32_e32 v18, v33
; GFX10-NEXT: v_mov_b32_e32 v19, v34
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -4135,8 +4135,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 {
; GFX11-NEXT: v_dual_mov_b32 v17, v32 :: v_dual_mov_b32 v18, v33
; GFX11-NEXT: v_mov_b32_e32 v19, v34
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -4207,8 +4207,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 {
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v18, v33
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v19, v34
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -4249,8 +4249,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s31, v42, 1
; GFX9-NEXT: v_readlane_b32 s30, v42, 0
+; GFX9-NEXT: v_readlane_b32 s31, v42, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v42, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -4285,8 +4285,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
-; GFX10-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-NEXT: v_readlane_b32 s30, v42, 0
+; GFX10-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v42, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -4322,8 +4322,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -4358,8 +4358,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v42, 2
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -4394,8 +4394,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_clause 0x1
; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -4442,8 +4442,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s31, v42, 1
; GFX9-NEXT: v_readlane_b32 s30, v42, 0
+; GFX9-NEXT: v_readlane_b32 s31, v42, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v42, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -4478,8 +4478,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX10-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1
-; GFX10-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-NEXT: v_readlane_b32 s30, v42, 0
+; GFX10-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v42, 2
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -4522,8 +4522,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
@@ -4566,8 +4566,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v42, 2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
@@ -4607,8 +4607,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v1, 8, v1
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -4663,8 +4663,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s31, v42, 1
; GFX9-NEXT: v_readlane_b32 s30, v42, 0
+; GFX9-NEXT: v_readlane_b32 s31, v42, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v42, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -4701,8 +4701,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX10-NEXT: v_mov_b32_e32 v3, 2
; GFX10-NEXT: v_mov_b32_e32 v4, 0
-; GFX10-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-NEXT: v_readlane_b32 s30, v42, 0
+; GFX10-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v42, 2
@@ -4743,20 +4743,20 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 2
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: global_store_b8 v[3:4], v2, off
; GFX11-TRUE16-NEXT: global_store_b16 v[40:41], v0, off
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
-; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -4795,8 +4795,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v0
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 2
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v42, 2
@@ -4840,8 +4840,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 0
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
@@ -4898,8 +4898,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s31, v42, 1
; GFX9-NEXT: v_readlane_b32 s30, v42, 0
+; GFX9-NEXT: v_readlane_b32 s31, v42, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v42, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -4936,8 +4936,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX10-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX10-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-NEXT: v_readlane_b32 s30, v42, 0
+; GFX10-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -4985,11 +4985,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
-; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: global_store_b32 v[40:41], v0, off
; GFX11-TRUE16-NEXT: s_clause 0x1
@@ -5033,8 +5033,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
@@ -5082,8 +5082,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -5146,8 +5146,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s31, v42, 1
; GFX9-NEXT: v_readlane_b32 s30, v42, 0
+; GFX9-NEXT: v_readlane_b32 s31, v42, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v42, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -5186,8 +5186,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX10-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX10-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-NEXT: v_readlane_b32 s30, v42, 0
+; GFX10-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_or_b32_sdwa v5, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -5242,7 +5242,7 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 4
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: global_store_b8 v[2:3], v4, off
@@ -5251,7 +5251,6 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
-; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -5293,8 +5292,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
@@ -5347,8 +5346,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v5, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
@@ -5419,8 +5418,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s31, v42, 1
; GFX9-NEXT: v_readlane_b32 s30, v42, 0
+; GFX9-NEXT: v_readlane_b32 s31, v42, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v42, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -5464,12 +5463,12 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX10-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX10-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX10-NEXT: v_readlane_b32 s31, v42, 1
+; GFX10-NEXT: v_readlane_b32 s30, v42, 0
; GFX10-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v5, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_readlane_b32 s30, v42, 0
+; GFX10-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-NEXT: v_readlane_b32 s34, v42, 2
@@ -5527,14 +5526,13 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v1.h, v0.h
; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v3.h, v2.h
; GFX11-TRUE16-NEXT: v_or_b16 v3.h, v2.l, v3.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v0.l, v1.l
; GFX11-TRUE16-NEXT: global_store_b64 v[40:41], v[3:4], off
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33
; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:4
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v42, 1
-; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v42, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v42, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -5585,12 +5583,12 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
+; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v42, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
@@ -5642,12 +5640,12 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX10-SCRATCH-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v5, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_or_b32_sdwa v1, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
@@ -5781,8 +5779,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s31, v44, 1
; GFX9-NEXT: v_readlane_b32 s30, v44, 0
+; GFX9-NEXT: v_readlane_b32 s31, v44, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v44, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -5904,8 +5902,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:4
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:8
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:12
-; GFX10-NEXT: v_readlane_b32 s31, v44, 1
; GFX10-NEXT: v_readlane_b32 s30, v44, 0
+; GFX10-NEXT: v_readlane_b32 s31, v44, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v44, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -6032,8 +6030,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s33 offset:4
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s33 offset:8
; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s33 offset:12
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v44, 1
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v44, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v44, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v44, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -6183,8 +6181,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s33 offset:4
; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s33 offset:8
; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s33 offset:12
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v44, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v44, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v44, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v44, 2
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -6306,8 +6304,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX10-SCRATCH-NEXT: scratch_load_dword v42, off, s33 offset:4
; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33 offset:8
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:12
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v44, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v44, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v44, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v44, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -6342,8 +6340,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -6370,8 +6368,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -6399,8 +6397,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -6427,8 +6425,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -6460,8 +6458,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -6488,8 +6486,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -6517,8 +6515,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -6545,8 +6543,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -6578,8 +6576,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -6606,8 +6604,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -6635,8 +6633,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -6663,8 +6661,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -6697,8 +6695,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -6726,8 +6724,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -6755,8 +6753,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -6784,8 +6782,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -6817,8 +6815,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -6846,8 +6844,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -6876,8 +6874,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -6905,8 +6903,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -6937,8 +6935,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -6965,8 +6963,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -6994,8 +6992,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -7022,8 +7020,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -7056,8 +7054,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -7085,8 +7083,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -7115,8 +7113,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -7144,8 +7142,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -7176,8 +7174,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -7204,8 +7202,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -7233,8 +7231,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -7261,8 +7259,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -7294,8 +7292,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -7322,8 +7320,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -7351,8 +7349,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -7379,8 +7377,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -7413,8 +7411,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -7442,8 +7440,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -7471,8 +7469,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -7500,8 +7498,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -7534,8 +7532,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -7564,8 +7562,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -7594,8 +7592,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -7624,8 +7622,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -7659,8 +7657,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -7690,8 +7688,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -7720,8 +7718,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -7751,8 +7749,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -7783,8 +7781,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -7811,8 +7809,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -7840,8 +7838,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -7868,8 +7866,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -7904,8 +7902,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -7935,8 +7933,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -7965,8 +7963,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -7996,8 +7994,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -8032,8 +8030,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -8064,8 +8062,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -8095,8 +8093,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -8127,8 +8125,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -8163,8 +8161,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 {
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i32 at abs32@lo
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -8196,8 +8194,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 {
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i32 at abs32@lo
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -8230,8 +8228,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -8263,8 +8261,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i32 at abs32@lo
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -8304,8 +8302,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -8339,8 +8337,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -8371,8 +8369,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -8406,8 +8404,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -8444,8 +8442,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 {
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v16i32 at abs32@lo
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -8479,8 +8477,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 {
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16i32 at abs32@lo
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -8515,8 +8513,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -8550,8 +8548,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16i32 at abs32@lo
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -8595,8 +8593,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i32 at abs32@lo
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -8634,8 +8632,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v32i32 at abs32@lo
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -8674,8 +8672,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -8713,8 +8711,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v32i32 at abs32@lo
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -8761,8 +8759,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -8803,8 +8801,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX10-NEXT: s_waitcnt vmcnt(8)
; GFX10-NEXT: buffer_store_dword v33, off, s[0:3], s32
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -8845,8 +8843,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX11-NEXT: s_waitcnt vmcnt(8)
; GFX11-NEXT: scratch_store_b32 off, v32, s32
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -8887,8 +8885,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(8)
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v33, s32
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -8930,8 +8928,8 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s31, v42, 1
; GFX9-NEXT: v_readlane_b32 s30, v42, 0
+; GFX9-NEXT: v_readlane_b32 s31, v42, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v42, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -8967,8 +8965,8 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
-; GFX10-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-NEXT: v_readlane_b32 s30, v42, 0
+; GFX10-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v42, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -9004,8 +9002,8 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_load_b32 v41, off, s33
; GFX11-NEXT: scratch_load_b32 v40, off, s33 offset:4
-; GFX11-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-NEXT: v_readlane_b32 s30, v42, 0
+; GFX11-NEXT: v_readlane_b32 s31, v42, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v42, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -9041,8 +9039,8 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX10-SCRATCH-NEXT: s_clause 0x1
; GFX10-SCRATCH-NEXT: scratch_load_dword v41, off, s33
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:4
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v42, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v42, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v42, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -9078,8 +9076,8 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
; GFX9-NEXT: s_mov_b32 s34, external_void_func_struct_i8_i32 at abs32@lo
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -9111,8 +9109,8 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
; GFX10-NEXT: s_mov_b32 s34, external_void_func_struct_i8_i32 at abs32@lo
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -9145,8 +9143,8 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -9178,8 +9176,8 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -9211,8 +9209,8 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_struct_i8_i32 at abs32@lo
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -9249,8 +9247,8 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -9281,8 +9279,8 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -9315,8 +9313,8 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -9347,8 +9345,8 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
@@ -9379,8 +9377,8 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -9424,8 +9422,8 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: buffer_load_ubyte v0, off, s[0:3], s33 offset:8
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:12
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -9466,8 +9464,8 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: buffer_load_ubyte v0, off, s[0:3], s33 offset:8
; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:12
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -9508,8 +9506,8 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v0, off, s33 offset:8
; GFX11-TRUE16-NEXT: scratch_load_b32 v1, off, s33 offset:12
-; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -9548,8 +9546,8 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_load_u8 v0, off, s33 offset:8
; GFX11-FAKE16-NEXT: scratch_load_b32 v1, off, s33 offset:12
-; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
@@ -9590,8 +9588,8 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st
; GFX10-SCRATCH-NEXT: s_clause 0x1
; GFX10-SCRATCH-NEXT: scratch_load_ubyte v0, off, s33 offset:8
; GFX10-SCRATCH-NEXT: scratch_load_dword v1, off, s33 offset:12
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
@@ -9662,8 +9660,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 {
; GFX9-NEXT: v_mov_b32_e32 v2, v17
; GFX9-NEXT: v_mov_b32_e32 v3, v18
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -9713,8 +9711,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 {
; GFX10-NEXT: v_mov_b32_e32 v2, v17
; GFX10-NEXT: v_mov_b32_e32 v3, v18
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -9761,8 +9759,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 {
; GFX11-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v1, v16
; GFX11-NEXT: v_dual_mov_b32 v2, v17 :: v_dual_mov_b32 v3, v18
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -9812,8 +9810,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 {
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, v17
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, v18
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -9841,46 +9839,46 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:16
; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:20
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s33
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: v_writelane_b32 v40, s35, 3
-; GFX9-NEXT: v_writelane_b32 v40, s36, 4
-; GFX9-NEXT: v_writelane_b32 v40, s37, 5
-; GFX9-NEXT: v_writelane_b32 v40, s38, 6
-; GFX9-NEXT: v_writelane_b32 v40, s39, 7
-; GFX9-NEXT: v_writelane_b32 v40, s48, 8
-; GFX9-NEXT: v_writelane_b32 v40, s49, 9
-; GFX9-NEXT: v_writelane_b32 v40, s50, 10
-; GFX9-NEXT: v_writelane_b32 v40, s51, 11
-; GFX9-NEXT: v_writelane_b32 v40, s52, 12
-; GFX9-NEXT: v_writelane_b32 v40, s53, 13
+; GFX9-NEXT: v_writelane_b32 v40, s34, 0
+; GFX9-NEXT: v_writelane_b32 v40, s35, 1
+; GFX9-NEXT: v_writelane_b32 v40, s36, 2
+; GFX9-NEXT: v_writelane_b32 v40, s37, 3
+; GFX9-NEXT: v_writelane_b32 v40, s38, 4
+; GFX9-NEXT: v_writelane_b32 v40, s39, 5
+; GFX9-NEXT: v_writelane_b32 v40, s48, 6
+; GFX9-NEXT: v_writelane_b32 v40, s49, 7
+; GFX9-NEXT: v_writelane_b32 v40, s50, 8
+; GFX9-NEXT: v_writelane_b32 v40, s51, 9
+; GFX9-NEXT: v_writelane_b32 v40, s52, 10
+; GFX9-NEXT: v_writelane_b32 v40, s53, 11
+; GFX9-NEXT: v_writelane_b32 v40, s54, 12
+; GFX9-NEXT: v_writelane_b32 v40, s55, 13
; GFX9-NEXT: s_addk_i32 s32, 0x800
-; GFX9-NEXT: v_writelane_b32 v40, s54, 14
+; GFX9-NEXT: v_writelane_b32 v40, s30, 14
; GFX9-NEXT: s_mov_b32 s5, byval_align16_f64_arg at abs32@hi
; GFX9-NEXT: s_mov_b32 s4, byval_align16_f64_arg at abs32@lo
-; GFX9-NEXT: v_writelane_b32 v40, s55, 15
+; GFX9-NEXT: v_writelane_b32 v40, s31, 15
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GFX9-NEXT: v_readlane_b32 s55, v40, 15
-; GFX9-NEXT: v_readlane_b32 s54, v40, 14
-; GFX9-NEXT: v_readlane_b32 s53, v40, 13
-; GFX9-NEXT: v_readlane_b32 s52, v40, 12
-; GFX9-NEXT: v_readlane_b32 s51, v40, 11
-; GFX9-NEXT: v_readlane_b32 s50, v40, 10
-; GFX9-NEXT: v_readlane_b32 s49, v40, 9
-; GFX9-NEXT: v_readlane_b32 s48, v40, 8
-; GFX9-NEXT: v_readlane_b32 s39, v40, 7
-; GFX9-NEXT: v_readlane_b32 s38, v40, 6
-; GFX9-NEXT: v_readlane_b32 s37, v40, 5
-; GFX9-NEXT: v_readlane_b32 s36, v40, 4
-; GFX9-NEXT: v_readlane_b32 s35, v40, 3
-; GFX9-NEXT: v_readlane_b32 s34, v40, 2
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
-; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s30, v40, 14
+; GFX9-NEXT: v_readlane_b32 s31, v40, 15
+; GFX9-NEXT: v_readlane_b32 s55, v40, 13
+; GFX9-NEXT: v_readlane_b32 s54, v40, 12
+; GFX9-NEXT: v_readlane_b32 s53, v40, 11
+; GFX9-NEXT: v_readlane_b32 s52, v40, 10
+; GFX9-NEXT: v_readlane_b32 s51, v40, 9
+; GFX9-NEXT: v_readlane_b32 s50, v40, 8
+; GFX9-NEXT: v_readlane_b32 s49, v40, 7
+; GFX9-NEXT: v_readlane_b32 s48, v40, 6
+; GFX9-NEXT: v_readlane_b32 s39, v40, 5
+; GFX9-NEXT: v_readlane_b32 s38, v40, 4
+; GFX9-NEXT: v_readlane_b32 s37, v40, 3
+; GFX9-NEXT: v_readlane_b32 s36, v40, 2
+; GFX9-NEXT: v_readlane_b32 s35, v40, 1
+; GFX9-NEXT: v_readlane_b32 s34, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
@@ -9902,7 +9900,7 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:16
; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:20
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s33
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s34, 0
; GFX10-NEXT: s_addk_i32 s32, 0x400
; GFX10-NEXT: s_mov_b32 s5, byval_align16_f64_arg at abs32@hi
; GFX10-NEXT: s_mov_b32 s4, byval_align16_f64_arg at abs32@lo
@@ -9910,38 +9908,38 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX10-NEXT: buffer_store_dword v32, off, s[0:3], s32
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
-; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: v_writelane_b32 v40, s35, 3
-; GFX10-NEXT: v_writelane_b32 v40, s36, 4
-; GFX10-NEXT: v_writelane_b32 v40, s37, 5
-; GFX10-NEXT: v_writelane_b32 v40, s38, 6
-; GFX10-NEXT: v_writelane_b32 v40, s39, 7
-; GFX10-NEXT: v_writelane_b32 v40, s48, 8
-; GFX10-NEXT: v_writelane_b32 v40, s49, 9
-; GFX10-NEXT: v_writelane_b32 v40, s50, 10
-; GFX10-NEXT: v_writelane_b32 v40, s51, 11
-; GFX10-NEXT: v_writelane_b32 v40, s52, 12
-; GFX10-NEXT: v_writelane_b32 v40, s53, 13
-; GFX10-NEXT: v_writelane_b32 v40, s54, 14
-; GFX10-NEXT: v_writelane_b32 v40, s55, 15
+; GFX10-NEXT: v_writelane_b32 v40, s35, 1
+; GFX10-NEXT: v_writelane_b32 v40, s36, 2
+; GFX10-NEXT: v_writelane_b32 v40, s37, 3
+; GFX10-NEXT: v_writelane_b32 v40, s38, 4
+; GFX10-NEXT: v_writelane_b32 v40, s39, 5
+; GFX10-NEXT: v_writelane_b32 v40, s48, 6
+; GFX10-NEXT: v_writelane_b32 v40, s49, 7
+; GFX10-NEXT: v_writelane_b32 v40, s50, 8
+; GFX10-NEXT: v_writelane_b32 v40, s51, 9
+; GFX10-NEXT: v_writelane_b32 v40, s52, 10
+; GFX10-NEXT: v_writelane_b32 v40, s53, 11
+; GFX10-NEXT: v_writelane_b32 v40, s54, 12
+; GFX10-NEXT: v_writelane_b32 v40, s55, 13
+; GFX10-NEXT: v_writelane_b32 v40, s30, 14
+; GFX10-NEXT: v_writelane_b32 v40, s31, 15
; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GFX10-NEXT: v_readlane_b32 s55, v40, 15
-; GFX10-NEXT: v_readlane_b32 s54, v40, 14
-; GFX10-NEXT: v_readlane_b32 s53, v40, 13
-; GFX10-NEXT: v_readlane_b32 s52, v40, 12
-; GFX10-NEXT: v_readlane_b32 s51, v40, 11
-; GFX10-NEXT: v_readlane_b32 s50, v40, 10
-; GFX10-NEXT: v_readlane_b32 s49, v40, 9
-; GFX10-NEXT: v_readlane_b32 s48, v40, 8
-; GFX10-NEXT: v_readlane_b32 s39, v40, 7
-; GFX10-NEXT: v_readlane_b32 s38, v40, 6
-; GFX10-NEXT: v_readlane_b32 s37, v40, 5
-; GFX10-NEXT: v_readlane_b32 s36, v40, 4
-; GFX10-NEXT: v_readlane_b32 s35, v40, 3
-; GFX10-NEXT: v_readlane_b32 s34, v40, 2
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
-; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s30, v40, 14
+; GFX10-NEXT: v_readlane_b32 s31, v40, 15
+; GFX10-NEXT: v_readlane_b32 s55, v40, 13
+; GFX10-NEXT: v_readlane_b32 s54, v40, 12
+; GFX10-NEXT: v_readlane_b32 s53, v40, 11
+; GFX10-NEXT: v_readlane_b32 s52, v40, 10
+; GFX10-NEXT: v_readlane_b32 s51, v40, 9
+; GFX10-NEXT: v_readlane_b32 s50, v40, 8
+; GFX10-NEXT: v_readlane_b32 s49, v40, 7
+; GFX10-NEXT: v_readlane_b32 s48, v40, 6
+; GFX10-NEXT: v_readlane_b32 s39, v40, 5
+; GFX10-NEXT: v_readlane_b32 s38, v40, 4
+; GFX10-NEXT: v_readlane_b32 s37, v40, 3
+; GFX10-NEXT: v_readlane_b32 s36, v40, 2
+; GFX10-NEXT: v_readlane_b32 s35, v40, 1
+; GFX10-NEXT: v_readlane_b32 s34, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_or_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
@@ -9962,44 +9960,44 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_load_b64 v[32:33], off, s33 offset:16
; GFX11-NEXT: scratch_load_b32 v31, off, s33
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s34, 0
; GFX11-NEXT: s_add_i32 s32, s32, 32
; GFX11-NEXT: s_mov_b32 s1, byval_align16_f64_arg at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, byval_align16_f64_arg at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
-; GFX11-NEXT: v_writelane_b32 v40, s34, 2
-; GFX11-NEXT: v_writelane_b32 v40, s35, 3
-; GFX11-NEXT: v_writelane_b32 v40, s36, 4
-; GFX11-NEXT: v_writelane_b32 v40, s37, 5
-; GFX11-NEXT: v_writelane_b32 v40, s38, 6
-; GFX11-NEXT: v_writelane_b32 v40, s39, 7
-; GFX11-NEXT: v_writelane_b32 v40, s48, 8
-; GFX11-NEXT: v_writelane_b32 v40, s49, 9
-; GFX11-NEXT: v_writelane_b32 v40, s50, 10
-; GFX11-NEXT: v_writelane_b32 v40, s51, 11
-; GFX11-NEXT: v_writelane_b32 v40, s52, 12
-; GFX11-NEXT: v_writelane_b32 v40, s53, 13
-; GFX11-NEXT: v_writelane_b32 v40, s54, 14
-; GFX11-NEXT: v_writelane_b32 v40, s55, 15
+; GFX11-NEXT: v_writelane_b32 v40, s35, 1
+; GFX11-NEXT: v_writelane_b32 v40, s36, 2
+; GFX11-NEXT: v_writelane_b32 v40, s37, 3
+; GFX11-NEXT: v_writelane_b32 v40, s38, 4
+; GFX11-NEXT: v_writelane_b32 v40, s39, 5
+; GFX11-NEXT: v_writelane_b32 v40, s48, 6
+; GFX11-NEXT: v_writelane_b32 v40, s49, 7
+; GFX11-NEXT: v_writelane_b32 v40, s50, 8
+; GFX11-NEXT: v_writelane_b32 v40, s51, 9
+; GFX11-NEXT: v_writelane_b32 v40, s52, 10
+; GFX11-NEXT: v_writelane_b32 v40, s53, 11
+; GFX11-NEXT: v_writelane_b32 v40, s54, 12
+; GFX11-NEXT: v_writelane_b32 v40, s55, 13
+; GFX11-NEXT: v_writelane_b32 v40, s30, 14
+; GFX11-NEXT: v_writelane_b32 v40, s31, 15
; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: scratch_store_b64 off, v[32:33], s32
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: v_readlane_b32 s55, v40, 15
-; GFX11-NEXT: v_readlane_b32 s54, v40, 14
-; GFX11-NEXT: v_readlane_b32 s53, v40, 13
-; GFX11-NEXT: v_readlane_b32 s52, v40, 12
-; GFX11-NEXT: v_readlane_b32 s51, v40, 11
-; GFX11-NEXT: v_readlane_b32 s50, v40, 10
-; GFX11-NEXT: v_readlane_b32 s49, v40, 9
-; GFX11-NEXT: v_readlane_b32 s48, v40, 8
-; GFX11-NEXT: v_readlane_b32 s39, v40, 7
-; GFX11-NEXT: v_readlane_b32 s38, v40, 6
-; GFX11-NEXT: v_readlane_b32 s37, v40, 5
-; GFX11-NEXT: v_readlane_b32 s36, v40, 4
-; GFX11-NEXT: v_readlane_b32 s35, v40, 3
-; GFX11-NEXT: v_readlane_b32 s34, v40, 2
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
-; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s30, v40, 14
+; GFX11-NEXT: v_readlane_b32 s31, v40, 15
+; GFX11-NEXT: v_readlane_b32 s55, v40, 13
+; GFX11-NEXT: v_readlane_b32 s54, v40, 12
+; GFX11-NEXT: v_readlane_b32 s53, v40, 11
+; GFX11-NEXT: v_readlane_b32 s52, v40, 10
+; GFX11-NEXT: v_readlane_b32 s51, v40, 9
+; GFX11-NEXT: v_readlane_b32 s50, v40, 8
+; GFX11-NEXT: v_readlane_b32 s49, v40, 7
+; GFX11-NEXT: v_readlane_b32 s48, v40, 6
+; GFX11-NEXT: v_readlane_b32 s39, v40, 5
+; GFX11-NEXT: v_readlane_b32 s38, v40, 4
+; GFX11-NEXT: v_readlane_b32 s37, v40, 3
+; GFX11-NEXT: v_readlane_b32 s36, v40, 2
+; GFX11-NEXT: v_readlane_b32 s35, v40, 1
+; GFX11-NEXT: v_readlane_b32 s34, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v40, off, s33 offset:24 ; 4-byte Folded Reload
@@ -10020,44 +10018,44 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX10-SCRATCH-NEXT: s_clause 0x1
; GFX10-SCRATCH-NEXT: scratch_load_dwordx2 v[32:33], off, s33 offset:16
; GFX10-SCRATCH-NEXT: scratch_load_dword v31, off, s33
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s34, 0
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, byval_align16_f64_arg at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, byval_align16_f64_arg at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s35, 3
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s36, 4
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s37, 5
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s38, 6
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s39, 7
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s48, 8
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s49, 9
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s50, 10
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s51, 11
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s52, 12
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s53, 13
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s54, 14
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s55, 15
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s35, 1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s36, 2
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s37, 3
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s38, 4
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s39, 5
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s48, 6
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s49, 7
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s50, 8
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s51, 9
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s52, 10
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s53, 11
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s54, 12
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s55, 13
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 14
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 15
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(1)
; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[32:33], s32
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s55, v40, 15
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s54, v40, 14
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s53, v40, 13
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s52, v40, 12
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s51, v40, 11
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s50, v40, 10
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s49, v40, 9
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s48, v40, 8
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s39, v40, 7
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s38, v40, 6
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s37, v40, 5
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s36, v40, 4
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s35, v40, 3
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s34, v40, 2
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 14
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 15
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s55, v40, 13
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s54, v40, 12
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s53, v40, 11
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s52, v40, 10
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s51, v40, 9
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s50, v40, 8
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s49, v40, 7
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s48, v40, 6
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s39, v40, 5
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s38, v40, 4
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s37, v40, 3
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s36, v40, 2
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s35, v40, 1
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s34, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s0, -1
; GFX10-SCRATCH-NEXT: scratch_load_dword v40, off, s33 offset:24 ; 4-byte Folded Reload
@@ -10091,8 +10089,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 {
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -10120,8 +10118,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 {
; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -10150,8 +10148,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -10179,8 +10177,8 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -10212,8 +10210,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
+; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 3
@@ -10242,8 +10240,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
+; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
@@ -10273,8 +10271,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
+; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 3
@@ -10303,8 +10301,8 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3
@@ -10337,8 +10335,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
+; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 3
@@ -10367,8 +10365,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
+; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
@@ -10398,8 +10396,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
+; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 3
@@ -10428,8 +10426,8 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3
@@ -10462,8 +10460,8 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
+; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 3
@@ -10492,8 +10490,8 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
+; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
@@ -10523,8 +10521,8 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
+; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 3
@@ -10553,8 +10551,8 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3
@@ -10589,8 +10587,8 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
+; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
@@ -10622,8 +10620,8 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
@@ -10656,8 +10654,8 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
+; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -10689,8 +10687,8 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
@@ -10728,8 +10726,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 5
; GFX9-NEXT: v_readlane_b32 s30, v40, 4
+; GFX9-NEXT: v_readlane_b32 s31, v40, 5
; GFX9-NEXT: v_readlane_b32 s7, v40, 3
; GFX9-NEXT: v_readlane_b32 s6, v40, 2
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
@@ -10765,8 +10763,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-NEXT: v_readlane_b32 s30, v40, 4
+; GFX10-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
@@ -10803,8 +10801,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 5
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s30, v40, 4
+; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
; GFX11-NEXT: v_readlane_b32 s6, v40, 2
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -10840,8 +10838,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
@@ -10884,8 +10882,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 5
; GFX9-NEXT: v_readlane_b32 s30, v40, 4
+; GFX9-NEXT: v_readlane_b32 s31, v40, 5
; GFX9-NEXT: v_readlane_b32 s7, v40, 3
; GFX9-NEXT: v_readlane_b32 s6, v40, 2
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
@@ -10923,8 +10921,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-NEXT: v_readlane_b32 s30, v40, 4
+; GFX10-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
@@ -10963,8 +10961,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 5
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s30, v40, 4
+; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
; GFX11-NEXT: v_readlane_b32 s6, v40, 2
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -11002,8 +11000,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
@@ -11047,8 +11045,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 7
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 7
; GFX9-NEXT: v_readlane_b32 s30, v40, 6
+; GFX9-NEXT: v_readlane_b32 s31, v40, 7
; GFX9-NEXT: v_readlane_b32 s9, v40, 5
; GFX9-NEXT: v_readlane_b32 s8, v40, 4
; GFX9-NEXT: v_readlane_b32 s7, v40, 3
@@ -11090,8 +11088,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 6
; GFX10-NEXT: v_writelane_b32 v40, s31, 7
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 7
; GFX10-NEXT: v_readlane_b32 s30, v40, 6
+; GFX10-NEXT: v_readlane_b32 s31, v40, 7
; GFX10-NEXT: v_readlane_b32 s9, v40, 5
; GFX10-NEXT: v_readlane_b32 s8, v40, 4
; GFX10-NEXT: v_readlane_b32 s7, v40, 3
@@ -11134,8 +11132,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 7
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 7
; GFX11-NEXT: v_readlane_b32 s30, v40, 6
+; GFX11-NEXT: v_readlane_b32 s31, v40, 7
; GFX11-NEXT: v_readlane_b32 s9, v40, 5
; GFX11-NEXT: v_readlane_b32 s8, v40, 4
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
@@ -11177,8 +11175,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 6
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 7
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 7
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 6
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 7
; GFX10-SCRATCH-NEXT: v_readlane_b32 s9, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s8, v40, 4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3
@@ -11231,8 +11229,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 9
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 9
; GFX9-NEXT: v_readlane_b32 s30, v40, 8
+; GFX9-NEXT: v_readlane_b32 s31, v40, 9
; GFX9-NEXT: v_readlane_b32 s11, v40, 7
; GFX9-NEXT: v_readlane_b32 s10, v40, 6
; GFX9-NEXT: v_readlane_b32 s9, v40, 5
@@ -11280,8 +11278,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 8
; GFX10-NEXT: v_writelane_b32 v40, s31, 9
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 9
; GFX10-NEXT: v_readlane_b32 s30, v40, 8
+; GFX10-NEXT: v_readlane_b32 s31, v40, 9
; GFX10-NEXT: v_readlane_b32 s11, v40, 7
; GFX10-NEXT: v_readlane_b32 s10, v40, 6
; GFX10-NEXT: v_readlane_b32 s9, v40, 5
@@ -11330,8 +11328,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 9
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 9
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
+; GFX11-NEXT: v_readlane_b32 s31, v40, 9
; GFX11-NEXT: v_readlane_b32 s11, v40, 7
; GFX11-NEXT: v_readlane_b32 s10, v40, 6
; GFX11-NEXT: v_readlane_b32 s9, v40, 5
@@ -11379,8 +11377,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 8
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 9
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 9
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 8
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 9
; GFX10-SCRATCH-NEXT: v_readlane_b32 s11, v40, 7
; GFX10-SCRATCH-NEXT: v_readlane_b32 s10, v40, 6
; GFX10-SCRATCH-NEXT: v_readlane_b32 s9, v40, 5
@@ -11422,8 +11420,8 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
+; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 3
@@ -11452,8 +11450,8 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
+; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
@@ -11483,8 +11481,8 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
+; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 3
@@ -11513,8 +11511,8 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3
@@ -11547,8 +11545,8 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
+; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 3
@@ -11577,8 +11575,8 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
+; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
@@ -11608,8 +11606,8 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
+; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 3
@@ -11638,8 +11636,8 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3
@@ -11674,8 +11672,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
+; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
@@ -11707,8 +11705,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
@@ -11741,8 +11739,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
+; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -11774,8 +11772,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
@@ -11813,8 +11811,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 4
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 4
; GFX9-NEXT: v_readlane_b32 s30, v40, 3
+; GFX9-NEXT: v_readlane_b32 s31, v40, 4
; GFX9-NEXT: v_readlane_b32 s6, v40, 2
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
@@ -11849,8 +11847,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 3
; GFX10-NEXT: v_writelane_b32 v40, s31, 4
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 4
; GFX10-NEXT: v_readlane_b32 s30, v40, 3
+; GFX10-NEXT: v_readlane_b32 s31, v40, 4
; GFX10-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
@@ -11886,8 +11884,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 4
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 4
; GFX11-NEXT: v_readlane_b32 s30, v40, 3
+; GFX11-NEXT: v_readlane_b32 s31, v40, 4
; GFX11-NEXT: v_readlane_b32 s6, v40, 2
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
@@ -11922,8 +11920,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 3
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 4
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 3
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
@@ -11966,8 +11964,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 6
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 6
; GFX9-NEXT: v_readlane_b32 s30, v40, 5
+; GFX9-NEXT: v_readlane_b32 s31, v40, 6
; GFX9-NEXT: v_readlane_b32 s8, v40, 4
; GFX9-NEXT: v_readlane_b32 s7, v40, 3
; GFX9-NEXT: v_readlane_b32 s6, v40, 2
@@ -12008,8 +12006,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 5
; GFX10-NEXT: v_writelane_b32 v40, s31, 6
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 6
; GFX10-NEXT: v_readlane_b32 s30, v40, 5
+; GFX10-NEXT: v_readlane_b32 s31, v40, 6
; GFX10-NEXT: v_readlane_b32 s8, v40, 4
; GFX10-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-NEXT: v_readlane_b32 s6, v40, 2
@@ -12051,8 +12049,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 6
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 6
; GFX11-NEXT: v_readlane_b32 s30, v40, 5
+; GFX11-NEXT: v_readlane_b32 s31, v40, 6
; GFX11-NEXT: v_readlane_b32 s8, v40, 4
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
; GFX11-NEXT: v_readlane_b32 s6, v40, 2
@@ -12093,8 +12091,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 5
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 6
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 6
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 5
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 6
; GFX10-SCRATCH-NEXT: v_readlane_b32 s8, v40, 4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2
@@ -12133,8 +12131,8 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
+; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
@@ -12166,8 +12164,8 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
@@ -12200,8 +12198,8 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
+; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -12233,8 +12231,8 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
@@ -12274,8 +12272,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 5
; GFX9-NEXT: v_readlane_b32 s30, v40, 4
+; GFX9-NEXT: v_readlane_b32 s31, v40, 5
; GFX9-NEXT: v_readlane_b32 s7, v40, 3
; GFX9-NEXT: v_readlane_b32 s6, v40, 2
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
@@ -12313,8 +12311,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-NEXT: v_readlane_b32 s30, v40, 4
+; GFX10-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
@@ -12353,8 +12351,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 5
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s30, v40, 4
+; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
; GFX11-NEXT: v_readlane_b32 s6, v40, 2
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -12392,8 +12390,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
@@ -12439,8 +12437,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 7
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 7
; GFX9-NEXT: v_readlane_b32 s30, v40, 6
+; GFX9-NEXT: v_readlane_b32 s31, v40, 7
; GFX9-NEXT: v_readlane_b32 s9, v40, 5
; GFX9-NEXT: v_readlane_b32 s8, v40, 4
; GFX9-NEXT: v_readlane_b32 s7, v40, 3
@@ -12484,8 +12482,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 6
; GFX10-NEXT: v_writelane_b32 v40, s31, 7
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 7
; GFX10-NEXT: v_readlane_b32 s30, v40, 6
+; GFX10-NEXT: v_readlane_b32 s31, v40, 7
; GFX10-NEXT: v_readlane_b32 s9, v40, 5
; GFX10-NEXT: v_readlane_b32 s8, v40, 4
; GFX10-NEXT: v_readlane_b32 s7, v40, 3
@@ -12530,8 +12528,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 7
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 7
; GFX11-NEXT: v_readlane_b32 s30, v40, 6
+; GFX11-NEXT: v_readlane_b32 s31, v40, 7
; GFX11-NEXT: v_readlane_b32 s9, v40, 5
; GFX11-NEXT: v_readlane_b32 s8, v40, 4
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
@@ -12575,8 +12573,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 6
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 7
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 7
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 6
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 7
; GFX10-SCRATCH-NEXT: v_readlane_b32 s9, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s8, v40, 4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3
@@ -12614,8 +12612,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
+; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 3
@@ -12644,8 +12642,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
+; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
@@ -12675,8 +12673,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
+; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 3
@@ -12705,8 +12703,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3
@@ -12741,8 +12739,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
+; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
@@ -12773,8 +12771,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
@@ -12806,8 +12804,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
+; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -12838,8 +12836,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
@@ -12875,8 +12873,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
+; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
@@ -12907,8 +12905,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
@@ -12940,8 +12938,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
+; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -12972,8 +12970,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
@@ -13010,8 +13008,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
+; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
@@ -13043,8 +13041,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
@@ -13077,8 +13075,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
+; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -13110,8 +13108,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
@@ -13147,8 +13145,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
+; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
@@ -13180,8 +13178,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
@@ -13214,8 +13212,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
+; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -13247,8 +13245,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
@@ -13283,8 +13281,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
+; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
@@ -13315,8 +13313,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
@@ -13348,8 +13346,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
+; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -13380,8 +13378,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
@@ -13418,8 +13416,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
+; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
@@ -13451,8 +13449,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
@@ -13485,8 +13483,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
+; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -13518,8 +13516,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
@@ -13553,8 +13551,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
+; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 3
@@ -13583,8 +13581,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
+; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
@@ -13614,8 +13612,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
+; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 3
@@ -13644,8 +13642,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 3
@@ -13680,8 +13678,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
+; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
@@ -13712,8 +13710,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
@@ -13745,8 +13743,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
+; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -13777,8 +13775,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
@@ -13815,8 +13813,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
+; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
@@ -13848,8 +13846,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
@@ -13882,8 +13880,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
+; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -13915,8 +13913,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
@@ -13954,8 +13952,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 4
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 4
; GFX9-NEXT: v_readlane_b32 s30, v40, 3
+; GFX9-NEXT: v_readlane_b32 s31, v40, 4
; GFX9-NEXT: v_readlane_b32 s6, v40, 2
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
@@ -13990,8 +13988,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 3
; GFX10-NEXT: v_writelane_b32 v40, s31, 4
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 4
; GFX10-NEXT: v_readlane_b32 s30, v40, 3
+; GFX10-NEXT: v_readlane_b32 s31, v40, 4
; GFX10-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
@@ -14027,8 +14025,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 4
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 4
; GFX11-NEXT: v_readlane_b32 s30, v40, 3
+; GFX11-NEXT: v_readlane_b32 s31, v40, 4
; GFX11-NEXT: v_readlane_b32 s6, v40, 2
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
@@ -14063,8 +14061,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 3
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 4
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 3
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s4, v40, 0
@@ -14105,8 +14103,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 5
; GFX9-NEXT: v_readlane_b32 s30, v40, 4
+; GFX9-NEXT: v_readlane_b32 s31, v40, 5
; GFX9-NEXT: v_readlane_b32 s7, v40, 3
; GFX9-NEXT: v_readlane_b32 s6, v40, 2
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
@@ -14144,8 +14142,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-NEXT: v_readlane_b32 s30, v40, 4
+; GFX10-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
@@ -14184,8 +14182,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 5
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s30, v40, 4
+; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
; GFX11-NEXT: v_readlane_b32 s6, v40, 2
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -14223,8 +14221,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
@@ -14263,8 +14261,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 5
; GFX9-NEXT: v_readlane_b32 s30, v40, 4
+; GFX9-NEXT: v_readlane_b32 s31, v40, 5
; GFX9-NEXT: v_readlane_b32 s7, v40, 3
; GFX9-NEXT: v_readlane_b32 s6, v40, 2
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
@@ -14299,8 +14297,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-NEXT: v_readlane_b32 s30, v40, 4
+; GFX10-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
@@ -14336,8 +14334,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 5
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s30, v40, 4
+; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
; GFX11-NEXT: v_readlane_b32 s6, v40, 2
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -14372,8 +14370,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
@@ -14416,8 +14414,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 5
; GFX9-NEXT: v_readlane_b32 s30, v40, 4
+; GFX9-NEXT: v_readlane_b32 s31, v40, 5
; GFX9-NEXT: v_readlane_b32 s7, v40, 3
; GFX9-NEXT: v_readlane_b32 s6, v40, 2
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
@@ -14455,8 +14453,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-NEXT: v_readlane_b32 s30, v40, 4
+; GFX10-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
@@ -14495,8 +14493,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 5
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s30, v40, 4
+; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
; GFX11-NEXT: v_readlane_b32 s6, v40, 2
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -14534,8 +14532,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s5, v40, 1
@@ -14579,8 +14577,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 6
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 6
; GFX9-NEXT: v_readlane_b32 s30, v40, 5
+; GFX9-NEXT: v_readlane_b32 s31, v40, 6
; GFX9-NEXT: v_readlane_b32 s8, v40, 4
; GFX9-NEXT: v_readlane_b32 s7, v40, 3
; GFX9-NEXT: v_readlane_b32 s6, v40, 2
@@ -14621,8 +14619,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 5
; GFX10-NEXT: v_writelane_b32 v40, s31, 6
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 6
; GFX10-NEXT: v_readlane_b32 s30, v40, 5
+; GFX10-NEXT: v_readlane_b32 s31, v40, 6
; GFX10-NEXT: v_readlane_b32 s8, v40, 4
; GFX10-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-NEXT: v_readlane_b32 s6, v40, 2
@@ -14664,8 +14662,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 6
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 6
; GFX11-NEXT: v_readlane_b32 s30, v40, 5
+; GFX11-NEXT: v_readlane_b32 s31, v40, 6
; GFX11-NEXT: v_readlane_b32 s8, v40, 4
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
; GFX11-NEXT: v_readlane_b32 s6, v40, 2
@@ -14706,8 +14704,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 5
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 6
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 6
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 5
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 6
; GFX10-SCRATCH-NEXT: v_readlane_b32 s8, v40, 4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s7, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s6, v40, 2
@@ -14753,8 +14751,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 9
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 9
; GFX9-NEXT: v_readlane_b32 s30, v40, 8
+; GFX9-NEXT: v_readlane_b32 s31, v40, 9
; GFX9-NEXT: v_readlane_b32 s11, v40, 7
; GFX9-NEXT: v_readlane_b32 s10, v40, 6
; GFX9-NEXT: v_readlane_b32 s9, v40, 5
@@ -14799,8 +14797,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 8
; GFX10-NEXT: v_writelane_b32 v40, s31, 9
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 9
; GFX10-NEXT: v_readlane_b32 s30, v40, 8
+; GFX10-NEXT: v_readlane_b32 s31, v40, 9
; GFX10-NEXT: v_readlane_b32 s11, v40, 7
; GFX10-NEXT: v_readlane_b32 s10, v40, 6
; GFX10-NEXT: v_readlane_b32 s9, v40, 5
@@ -14846,8 +14844,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 9
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 9
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
+; GFX11-NEXT: v_readlane_b32 s31, v40, 9
; GFX11-NEXT: v_readlane_b32 s11, v40, 7
; GFX11-NEXT: v_readlane_b32 s10, v40, 6
; GFX11-NEXT: v_readlane_b32 s9, v40, 5
@@ -14892,8 +14890,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 8
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 9
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 9
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 8
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 9
; GFX10-SCRATCH-NEXT: v_readlane_b32 s11, v40, 7
; GFX10-SCRATCH-NEXT: v_readlane_b32 s10, v40, 6
; GFX10-SCRATCH-NEXT: v_readlane_b32 s9, v40, 5
@@ -14949,8 +14947,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 9
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 9
; GFX9-NEXT: v_readlane_b32 s30, v40, 8
+; GFX9-NEXT: v_readlane_b32 s31, v40, 9
; GFX9-NEXT: v_readlane_b32 s11, v40, 7
; GFX9-NEXT: v_readlane_b32 s10, v40, 6
; GFX9-NEXT: v_readlane_b32 s9, v40, 5
@@ -15000,8 +14998,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 8
; GFX10-NEXT: v_writelane_b32 v40, s31, 9
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 9
; GFX10-NEXT: v_readlane_b32 s30, v40, 8
+; GFX10-NEXT: v_readlane_b32 s31, v40, 9
; GFX10-NEXT: v_readlane_b32 s11, v40, 7
; GFX10-NEXT: v_readlane_b32 s10, v40, 6
; GFX10-NEXT: v_readlane_b32 s9, v40, 5
@@ -15052,8 +15050,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 9
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 9
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
+; GFX11-NEXT: v_readlane_b32 s31, v40, 9
; GFX11-NEXT: v_readlane_b32 s11, v40, 7
; GFX11-NEXT: v_readlane_b32 s10, v40, 6
; GFX11-NEXT: v_readlane_b32 s9, v40, 5
@@ -15103,8 +15101,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 8
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 9
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 9
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 8
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 9
; GFX10-SCRATCH-NEXT: v_readlane_b32 s11, v40, 7
; GFX10-SCRATCH-NEXT: v_readlane_b32 s10, v40, 6
; GFX10-SCRATCH-NEXT: v_readlane_b32 s9, v40, 5
@@ -15161,8 +15159,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 17
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 17
; GFX9-NEXT: v_readlane_b32 s30, v40, 16
+; GFX9-NEXT: v_readlane_b32 s31, v40, 17
; GFX9-NEXT: v_readlane_b32 s19, v40, 15
; GFX9-NEXT: v_readlane_b32 s18, v40, 14
; GFX9-NEXT: v_readlane_b32 s17, v40, 13
@@ -15223,8 +15221,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 16
; GFX10-NEXT: v_writelane_b32 v40, s31, 17
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 17
; GFX10-NEXT: v_readlane_b32 s30, v40, 16
+; GFX10-NEXT: v_readlane_b32 s31, v40, 17
; GFX10-NEXT: v_readlane_b32 s19, v40, 15
; GFX10-NEXT: v_readlane_b32 s18, v40, 14
; GFX10-NEXT: v_readlane_b32 s17, v40, 13
@@ -15286,8 +15284,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 17
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 17
; GFX11-NEXT: v_readlane_b32 s30, v40, 16
+; GFX11-NEXT: v_readlane_b32 s31, v40, 17
; GFX11-NEXT: v_readlane_b32 s19, v40, 15
; GFX11-NEXT: v_readlane_b32 s18, v40, 14
; GFX11-NEXT: v_readlane_b32 s17, v40, 13
@@ -15348,8 +15346,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 17
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 17
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 16
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 17
; GFX10-SCRATCH-NEXT: v_readlane_b32 s19, v40, 15
; GFX10-SCRATCH-NEXT: v_readlane_b32 s18, v40, 14
; GFX10-SCRATCH-NEXT: v_readlane_b32 s17, v40, 13
@@ -15450,8 +15448,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX9-NEXT: v_writelane_b32 v40, s31, 27
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 27
; GFX9-NEXT: v_readlane_b32 s30, v40, 26
+; GFX9-NEXT: v_readlane_b32 s31, v40, 27
; GFX9-NEXT: v_readlane_b32 s29, v40, 25
; GFX9-NEXT: v_readlane_b32 s28, v40, 24
; GFX9-NEXT: v_readlane_b32 s27, v40, 23
@@ -15557,8 +15555,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 26
; GFX10-NEXT: v_writelane_b32 v40, s31, 27
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 27
; GFX10-NEXT: v_readlane_b32 s30, v40, 26
+; GFX10-NEXT: v_readlane_b32 s31, v40, 27
; GFX10-NEXT: v_readlane_b32 s29, v40, 25
; GFX10-NEXT: v_readlane_b32 s28, v40, 24
; GFX10-NEXT: v_readlane_b32 s27, v40, 23
@@ -15660,8 +15658,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 27
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 27
; GFX11-NEXT: v_readlane_b32 s30, v40, 26
+; GFX11-NEXT: v_readlane_b32 s31, v40, 27
; GFX11-NEXT: v_readlane_b32 s29, v40, 25
; GFX11-NEXT: v_readlane_b32 s28, v40, 24
; GFX11-NEXT: v_readlane_b32 s27, v40, 23
@@ -15764,8 +15762,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 26
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 27
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 27
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 26
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 27
; GFX10-SCRATCH-NEXT: v_readlane_b32 s29, v40, 25
; GFX10-SCRATCH-NEXT: v_readlane_b32 s28, v40, 24
; GFX10-SCRATCH-NEXT: v_readlane_b32 s27, v40, 23
@@ -15881,8 +15879,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX9-NEXT: v_writelane_b32 v40, s31, 27
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 27
; GFX9-NEXT: v_readlane_b32 s30, v40, 26
+; GFX9-NEXT: v_readlane_b32 s31, v40, 27
; GFX9-NEXT: v_readlane_b32 s29, v40, 25
; GFX9-NEXT: v_readlane_b32 s28, v40, 24
; GFX9-NEXT: v_readlane_b32 s27, v40, 23
@@ -15993,8 +15991,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 26
; GFX10-NEXT: v_writelane_b32 v40, s31, 27
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 27
; GFX10-NEXT: v_readlane_b32 s30, v40, 26
+; GFX10-NEXT: v_readlane_b32 s31, v40, 27
; GFX10-NEXT: v_readlane_b32 s29, v40, 25
; GFX10-NEXT: v_readlane_b32 s28, v40, 24
; GFX10-NEXT: v_readlane_b32 s27, v40, 23
@@ -16100,8 +16098,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 27
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 27
; GFX11-NEXT: v_readlane_b32 s30, v40, 26
+; GFX11-NEXT: v_readlane_b32 s31, v40, 27
; GFX11-NEXT: v_readlane_b32 s29, v40, 25
; GFX11-NEXT: v_readlane_b32 s28, v40, 24
; GFX11-NEXT: v_readlane_b32 s27, v40, 23
@@ -16210,8 +16208,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 26
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 27
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 27
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 26
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 27
; GFX10-SCRATCH-NEXT: v_readlane_b32 s29, v40, 25
; GFX10-SCRATCH-NEXT: v_readlane_b32 s28, v40, 24
; GFX10-SCRATCH-NEXT: v_readlane_b32 s27, v40, 23
@@ -16276,8 +16274,8 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -16310,8 +16308,8 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -16340,8 +16338,8 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: scratch_store_b64 off, v[32:33], s32
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -16370,8 +16368,8 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[32:33], s32
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -16442,8 +16440,8 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v31, 11
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -16509,8 +16507,8 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX10-NEXT: s_mov_b32 s34, external_void_func_12xv3i32 at abs32@lo
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -16556,8 +16554,8 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -16620,8 +16618,8 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_12xv3i32 at abs32@lo
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -16712,8 +16710,8 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v31, 7
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -16787,8 +16785,8 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX10-NEXT: s_mov_b32 s34, external_void_func_8xv5i32 at abs32@lo
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -16838,8 +16836,8 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -16908,8 +16906,8 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_8xv5i32 at abs32@lo
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -16996,8 +16994,8 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v31, 0x40e00000
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -17071,8 +17069,8 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX10-NEXT: s_mov_b32 s34, external_void_func_8xv5f32 at abs32@lo
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -17127,8 +17125,8 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -17197,8 +17195,8 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_8xv5f32 at abs32@lo
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -17237,8 +17235,8 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -17264,8 +17262,8 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -17292,8 +17290,8 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -17319,8 +17317,8 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -17351,8 +17349,8 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -17378,8 +17376,8 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -17406,8 +17404,8 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -17433,8 +17431,8 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -17465,8 +17463,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -17492,8 +17490,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -17520,8 +17518,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -17547,8 +17545,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -17579,8 +17577,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -17606,8 +17604,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -17634,8 +17632,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -17661,8 +17659,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -17693,8 +17691,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -17720,8 +17718,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -17748,8 +17746,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -17775,8 +17773,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -17807,8 +17805,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -17834,8 +17832,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -17862,8 +17860,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -17889,8 +17887,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -17921,8 +17919,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -17948,8 +17946,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -17976,8 +17974,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -18003,8 +18001,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -18035,8 +18033,8 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg)
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -18062,8 +18060,8 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg)
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -18090,8 +18088,8 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg)
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -18117,8 +18115,8 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg)
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -18149,8 +18147,8 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -18176,8 +18174,8 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -18204,8 +18202,8 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -18231,8 +18229,8 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -18263,8 +18261,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -18290,8 +18288,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -18318,8 +18316,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -18345,8 +18343,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -18377,8 +18375,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -18404,8 +18402,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -18432,8 +18430,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -18459,8 +18457,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -18491,8 +18489,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -18518,8 +18516,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -18546,8 +18544,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -18573,8 +18571,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -18605,8 +18603,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -18632,8 +18630,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -18660,8 +18658,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -18687,8 +18685,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
@@ -18719,8 +18717,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -18746,8 +18744,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -18774,8 +18772,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -18801,8 +18799,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s32, s33
; GFX10-SCRATCH-NEXT: v_readlane_b32 s0, v40, 2
; GFX10-SCRATCH-NEXT: s_or_saveexec_b32 s1, -1
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
index 124de7e00f020..ecf2b33841076 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
@@ -26,8 +26,8 @@ define amdgpu_gfx void @test_call_external_void_func_void_clobber_s30_s31_call_e
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
+; GFX9-NEXT: v_readlane_b32 s31, v40, 3
; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
@@ -60,8 +60,8 @@ define amdgpu_gfx void @test_call_external_void_func_void_clobber_s30_s31_call_e
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
+; GFX10-NEXT: v_readlane_b32 s31, v40, 3
; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
@@ -95,8 +95,8 @@ define amdgpu_gfx void @test_call_external_void_func_void_clobber_s30_s31_call_e
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
+; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -130,8 +130,8 @@ define amdgpu_gfx void @void_func_void_clobber_s28_s29() #1 {
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; clobber
; GFX9-NEXT: ;;#ASMEND
-; GFX9-NEXT: v_readlane_b32 s31, v0, 3
; GFX9-NEXT: v_readlane_b32 s30, v0, 2
+; GFX9-NEXT: v_readlane_b32 s31, v0, 3
; GFX9-NEXT: v_readlane_b32 s29, v0, 1
; GFX9-NEXT: v_readlane_b32 s28, v0, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[34:35], -1
@@ -157,8 +157,8 @@ define amdgpu_gfx void @void_func_void_clobber_s28_s29() #1 {
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; clobber
; GFX10-NEXT: ;;#ASMEND
-; GFX10-NEXT: v_readlane_b32 s31, v0, 3
; GFX10-NEXT: v_readlane_b32 s30, v0, 2
+; GFX10-NEXT: v_readlane_b32 s31, v0, 3
; GFX10-NEXT: v_readlane_b32 s29, v0, 1
; GFX10-NEXT: v_readlane_b32 s28, v0, 0
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
@@ -185,8 +185,8 @@ define amdgpu_gfx void @void_func_void_clobber_s28_s29() #1 {
; GFX11-NEXT: ; clobber
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v0, 3
; GFX11-NEXT: v_readlane_b32 s30, v0, 2
+; GFX11-NEXT: v_readlane_b32 s31, v0, 3
; GFX11-NEXT: v_readlane_b32 s29, v0, 1
; GFX11-NEXT: v_readlane_b32 s28, v0, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
@@ -224,8 +224,8 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1)
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s31
; GFX9-NEXT: ;;#ASMEND
-; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
+; GFX9-NEXT: v_readlane_b32 s31, v40, 2
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 3
@@ -261,8 +261,8 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1)
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; use s31
; GFX10-NEXT: ;;#ASMEND
-; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
+; GFX10-NEXT: v_readlane_b32 s31, v40, 2
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
@@ -298,8 +298,8 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1)
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s31
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
+; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 3
@@ -341,8 +341,8 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_v31(ptr addrspace(1)
; GFX9-NEXT: ; use v31
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s31, v41, 1
; GFX9-NEXT: v_readlane_b32 s30, v41, 0
+; GFX9-NEXT: v_readlane_b32 s31, v41, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v41, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -378,8 +378,8 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_v31(ptr addrspace(1)
; GFX10-NEXT: ; use v31
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: v_readlane_b32 s31, v41, 1
; GFX10-NEXT: v_readlane_b32 s30, v41, 0
+; GFX10-NEXT: v_readlane_b32 s31, v41, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v41, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -416,8 +416,8 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_v31(ptr addrspace(1)
; GFX11-NEXT: ; use v31
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT: v_readlane_b32 s31, v41, 1
; GFX11-NEXT: v_readlane_b32 s30, v41, 0
+; GFX11-NEXT: v_readlane_b32 s31, v41, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v41, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -455,11 +455,11 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s33(ptr addrspace(1)
; GFX9-NEXT: s_mov_b32 s4, s33
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: s_mov_b32 s33, s4
+; GFX9-NEXT: v_readlane_b32 s30, v40, 1
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s33
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: v_readlane_b32 s31, v40, 2
-; GFX9-NEXT: v_readlane_b32 s30, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 3
@@ -492,11 +492,11 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s33(ptr addrspace(1)
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: s_mov_b32 s33, s4
+; GFX10-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; use s33
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: v_readlane_b32 s31, v40, 2
-; GFX10-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
@@ -529,12 +529,12 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s33(ptr addrspace(1)
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_mov_b32 s33, s4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s33
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s31, v40, 2
-; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 3
@@ -572,11 +572,11 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s34(ptr addrspace(1)
; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: s_mov_b32 s34, s4
+; GFX9-NEXT: v_readlane_b32 s30, v40, 1
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s34
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: v_readlane_b32 s31, v40, 2
-; GFX9-NEXT: v_readlane_b32 s30, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 3
@@ -609,11 +609,11 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s34(ptr addrspace(1)
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: s_mov_b32 s34, s4
+; GFX10-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; use s34
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: v_readlane_b32 s31, v40, 2
-; GFX10-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
@@ -645,13 +645,13 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s34(ptr addrspace(1)
; GFX11-NEXT: v_writelane_b32 v40, s30, 1
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: s_mov_b32 s34, s4
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s34
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s31, v40, 2
-; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 3
@@ -691,8 +691,8 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_v40(ptr addrspace(1)
; GFX9-NEXT: ; use v40
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s31, v41, 1
; GFX9-NEXT: v_readlane_b32 s30, v41, 0
+; GFX9-NEXT: v_readlane_b32 s31, v41, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v41, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -726,8 +726,8 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_v40(ptr addrspace(1)
; GFX10-NEXT: ; use v40
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: v_readlane_b32 s31, v41, 1
; GFX10-NEXT: v_readlane_b32 s30, v41, 0
+; GFX10-NEXT: v_readlane_b32 s31, v41, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v41, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -761,8 +761,8 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_v40(ptr addrspace(1)
; GFX11-NEXT: ; use v40
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT: v_readlane_b32 s31, v41, 1
; GFX11-NEXT: v_readlane_b32 s30, v41, 0
+; GFX11-NEXT: v_readlane_b32 s31, v41, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v41, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -849,8 +849,8 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s33() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -876,8 +876,8 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s33() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -904,8 +904,8 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s33() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -934,8 +934,8 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s34() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -961,8 +961,8 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s34() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
+; GFX10-NEXT: v_readlane_b32 s31, v40, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s35, -1
@@ -989,8 +989,8 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s34() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
+; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -1024,11 +1024,11 @@ define amdgpu_gfx void @callee_saved_sgpr_kernel() #1 {
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: s_mov_b32 s4, s40
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
+; GFX9-NEXT: v_readlane_b32 s30, v40, 1
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; use s4
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: v_readlane_b32 s31, v40, 2
-; GFX9-NEXT: v_readlane_b32 s30, v40, 1
; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v40, 3
@@ -1060,11 +1060,11 @@ define amdgpu_gfx void @callee_saved_sgpr_kernel() #1 {
; GFX10-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
+; GFX10-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; use s4
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: v_readlane_b32 s31, v40, 2
-; GFX10-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v40, 3
@@ -1096,12 +1096,12 @@ define amdgpu_gfx void @callee_saved_sgpr_kernel() #1 {
; GFX11-NEXT: v_writelane_b32 v40, s30, 1
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s4
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s31, v40, 2
-; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v40, 3
@@ -1150,8 +1150,8 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 {
; GFX9-NEXT: ; use v40
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s31, v41, 2
; GFX9-NEXT: v_readlane_b32 s30, v41, 1
+; GFX9-NEXT: v_readlane_b32 s31, v41, 2
; GFX9-NEXT: v_readlane_b32 s4, v41, 0
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s34, v41, 3
@@ -1195,8 +1195,8 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 {
; GFX10-NEXT: ; use v40
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
-; GFX10-NEXT: v_readlane_b32 s31, v41, 2
; GFX10-NEXT: v_readlane_b32 s30, v41, 1
+; GFX10-NEXT: v_readlane_b32 s31, v41, 2
; GFX10-NEXT: v_readlane_b32 s4, v41, 0
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s34, v41, 3
@@ -1240,8 +1240,8 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 {
; GFX11-NEXT: ; use v40
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
-; GFX11-NEXT: v_readlane_b32 s31, v41, 2
; GFX11-NEXT: v_readlane_b32 s30, v41, 1
+; GFX11-NEXT: v_readlane_b32 s31, v41, 2
; GFX11-NEXT: v_readlane_b32 s4, v41, 0
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v41, 3
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
index b750d28ffa7d3..036c39ce51658 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
@@ -34,8 +34,8 @@ define amdgpu_gfx void @call_i1() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v1, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v1, 1
; GFX9-NEXT: v_readlane_b32 s30, v1, 0
+; GFX9-NEXT: v_readlane_b32 s31, v1, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: s_xor_saveexec_b64 s[34:35], -1
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -59,8 +59,8 @@ define amdgpu_gfx void @call_i1() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v1, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v1, 1
; GFX10-NEXT: v_readlane_b32 s30, v1, 0
+; GFX10-NEXT: v_readlane_b32 s31, v1, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -85,8 +85,8 @@ define amdgpu_gfx void @call_i1() #0 {
; GFX11-NEXT: v_writelane_b32 v1, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v1, 1
; GFX11-NEXT: v_readlane_b32 s30, v1, 0
+; GFX11-NEXT: v_readlane_b32 s31, v1, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v1, off, s33 ; 4-byte Folded Reload
@@ -136,8 +136,8 @@ define amdgpu_gfx void @call_i16() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v1, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v1, 1
; GFX9-NEXT: v_readlane_b32 s30, v1, 0
+; GFX9-NEXT: v_readlane_b32 s31, v1, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: s_xor_saveexec_b64 s[34:35], -1
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -161,8 +161,8 @@ define amdgpu_gfx void @call_i16() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v1, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v1, 1
; GFX10-NEXT: v_readlane_b32 s30, v1, 0
+; GFX10-NEXT: v_readlane_b32 s31, v1, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -187,8 +187,8 @@ define amdgpu_gfx void @call_i16() #0 {
; GFX11-NEXT: v_writelane_b32 v1, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v1, 1
; GFX11-NEXT: v_readlane_b32 s30, v1, 0
+; GFX11-NEXT: v_readlane_b32 s31, v1, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v1, off, s33 ; 4-byte Folded Reload
@@ -232,8 +232,8 @@ define amdgpu_gfx void @call_2xi16() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v1, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v1, 1
; GFX9-NEXT: v_readlane_b32 s30, v1, 0
+; GFX9-NEXT: v_readlane_b32 s31, v1, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: s_xor_saveexec_b64 s[34:35], -1
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -257,8 +257,8 @@ define amdgpu_gfx void @call_2xi16() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v1, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v1, 1
; GFX10-NEXT: v_readlane_b32 s30, v1, 0
+; GFX10-NEXT: v_readlane_b32 s31, v1, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -283,8 +283,8 @@ define amdgpu_gfx void @call_2xi16() #0 {
; GFX11-NEXT: v_writelane_b32 v1, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v1, 1
; GFX11-NEXT: v_readlane_b32 s30, v1, 0
+; GFX11-NEXT: v_readlane_b32 s31, v1, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v1, off, s33 ; 4-byte Folded Reload
@@ -336,8 +336,8 @@ define amdgpu_gfx void @call_3xi16() #0 {
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v2, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX9-NEXT: v_readlane_b32 s31, v2, 1
; GFX9-NEXT: v_readlane_b32 s30, v2, 0
+; GFX9-NEXT: v_readlane_b32 s31, v2, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: s_xor_saveexec_b64 s[34:35], -1
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -361,8 +361,8 @@ define amdgpu_gfx void @call_3xi16() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v2, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
-; GFX10-NEXT: v_readlane_b32 s31, v2, 1
; GFX10-NEXT: v_readlane_b32 s30, v2, 0
+; GFX10-NEXT: v_readlane_b32 s31, v2, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -387,8 +387,8 @@ define amdgpu_gfx void @call_3xi16() #0 {
; GFX11-NEXT: v_writelane_b32 v2, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v2, 1
; GFX11-NEXT: v_readlane_b32 s30, v2, 0
+; GFX11-NEXT: v_readlane_b32 s31, v2, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v2, off, s33 ; 4-byte Folded Reload
@@ -750,8 +750,8 @@ define amdgpu_gfx void @call_100xi32() #0 {
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:120 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:124 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s31, v100, 1
; GFX9-NEXT: v_readlane_b32 s30, v100, 0
+; GFX9-NEXT: v_readlane_b32 s31, v100, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: s_xor_saveexec_b64 s[34:35], -1
; GFX9-NEXT: buffer_load_dword v100, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload
@@ -840,8 +840,8 @@ define amdgpu_gfx void @call_100xi32() #0 {
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:116
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:120
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:124
-; GFX10-NEXT: v_readlane_b32 s31, v100, 1
; GFX10-NEXT: v_readlane_b32 s30, v100, 0
+; GFX10-NEXT: v_readlane_b32 s31, v100, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: s_xor_saveexec_b32 s34, -1
; GFX10-NEXT: buffer_load_dword v100, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload
@@ -931,8 +931,8 @@ define amdgpu_gfx void @call_100xi32() #0 {
; GFX11-NEXT: scratch_load_b32 v42, off, s33 offset:116
; GFX11-NEXT: scratch_load_b32 v41, off, s33 offset:120
; GFX11-NEXT: scratch_load_b32 v40, off, s33 offset:124
-; GFX11-NEXT: v_readlane_b32 s31, v100, 1
; GFX11-NEXT: v_readlane_b32 s30, v100, 0
+; GFX11-NEXT: v_readlane_b32 s31, v100, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v100, off, s33 offset:128 ; 4-byte Folded Reload
@@ -2151,8 +2151,8 @@ define amdgpu_gfx void @call_512xi32() #0 {
; GFX9-NEXT: s_add_i32 s32, s32, 0x60000
; GFX9-NEXT: v_writelane_b32 v2, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[36:37]
-; GFX9-NEXT: v_readlane_b32 s31, v2, 1
; GFX9-NEXT: v_readlane_b32 s30, v2, 0
+; GFX9-NEXT: v_readlane_b32 s31, v2, 1
; GFX9-NEXT: s_mov_b32 s32, s34
; GFX9-NEXT: s_mov_b32 s34, s38
; GFX9-NEXT: s_xor_saveexec_b64 s[36:37], -1
@@ -2181,8 +2181,8 @@ define amdgpu_gfx void @call_512xi32() #0 {
; GFX10-NEXT: s_add_i32 s32, s32, 0x30000
; GFX10-NEXT: v_writelane_b32 v2, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[36:37]
-; GFX10-NEXT: v_readlane_b32 s31, v2, 1
; GFX10-NEXT: v_readlane_b32 s30, v2, 0
+; GFX10-NEXT: v_readlane_b32 s31, v2, 1
; GFX10-NEXT: s_mov_b32 s32, s34
; GFX10-NEXT: s_mov_b32 s34, s38
; GFX10-NEXT: s_xor_saveexec_b32 s36, -1
@@ -2213,8 +2213,8 @@ define amdgpu_gfx void @call_512xi32() #0 {
; GFX11-NEXT: v_writelane_b32 v5, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v5, 1
; GFX11-NEXT: v_readlane_b32 s30, v5, 0
+; GFX11-NEXT: v_readlane_b32 s31, v5, 1
; GFX11-NEXT: s_mov_b32 s32, s34
; GFX11-NEXT: s_mov_b32 s34, s36
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
@@ -2889,8 +2889,8 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s31, v63, 1
; GFX9-NEXT: v_readlane_b32 s30, v63, 0
+; GFX9-NEXT: v_readlane_b32 s31, v63, 1
; GFX9-NEXT: s_mov_b32 s32, s34
; GFX9-NEXT: s_mov_b32 s34, s38
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
@@ -3167,8 +3167,8 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:48
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:52
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:56
-; GFX10-NEXT: v_readlane_b32 s31, v63, 1
; GFX10-NEXT: v_readlane_b32 s30, v63, 0
+; GFX10-NEXT: v_readlane_b32 s31, v63, 1
; GFX10-NEXT: s_mov_b32 s32, s34
; GFX10-NEXT: s_mov_b32 s34, s38
; GFX10-NEXT: s_or_saveexec_b32 s36, -1
@@ -3365,8 +3365,8 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX11-NEXT: scratch_load_b32 v42, off, s33 offset:36
; GFX11-NEXT: scratch_load_b32 v41, off, s33 offset:40
; GFX11-NEXT: scratch_load_b32 v40, off, s33 offset:44
-; GFX11-NEXT: v_readlane_b32 s31, v60, 1
; GFX11-NEXT: v_readlane_b32 s30, v60, 0
+; GFX11-NEXT: v_readlane_b32 s31, v60, 1
; GFX11-NEXT: s_mov_b32 s32, s34
; GFX11-NEXT: s_mov_b32 s34, s36
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
diff --git a/llvm/test/CodeGen/AMDGPU/global-alias.ll b/llvm/test/CodeGen/AMDGPU/global-alias.ll
index d8df20eb69452..4c7bef4aec091 100644
--- a/llvm/test/CodeGen/AMDGPU/global-alias.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-alias.ll
@@ -35,8 +35,8 @@ define void @bar() {
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; CHECK-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-NEXT: v_readlane_b32 s30, v40, 0
+; CHECK-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: v_readlane_b32 s4, v40, 2
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
index 10d61deed71cc..0bbe2b6a0caa7 100644
--- a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
+++ b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
@@ -9,28 +9,30 @@ define void @main(i1 %arg) #0 {
; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[4:5]
-; CHECK-NEXT: v_writelane_b32 v6, s30, 0
-; CHECK-NEXT: v_writelane_b32 v6, s31, 1
-; CHECK-NEXT: v_writelane_b32 v6, s36, 2
-; CHECK-NEXT: v_writelane_b32 v6, s37, 3
-; CHECK-NEXT: v_writelane_b32 v6, s38, 4
-; CHECK-NEXT: v_writelane_b32 v6, s39, 5
-; CHECK-NEXT: v_writelane_b32 v6, s48, 6
-; CHECK-NEXT: v_writelane_b32 v6, s49, 7
-; CHECK-NEXT: v_writelane_b32 v6, s50, 8
-; CHECK-NEXT: v_writelane_b32 v6, s51, 9
-; CHECK-NEXT: v_writelane_b32 v6, s52, 10
-; CHECK-NEXT: v_writelane_b32 v6, s53, 11
-; CHECK-NEXT: v_writelane_b32 v6, s54, 12
-; CHECK-NEXT: v_writelane_b32 v6, s55, 13
-; CHECK-NEXT: v_writelane_b32 v6, s64, 14
-; CHECK-NEXT: v_writelane_b32 v6, s65, 15
-; CHECK-NEXT: v_writelane_b32 v6, s66, 16
-; CHECK-NEXT: v_writelane_b32 v6, s67, 17
-; CHECK-NEXT: v_writelane_b32 v6, s68, 18
+; CHECK-NEXT: v_writelane_b32 v6, s36, 0
+; CHECK-NEXT: v_writelane_b32 v6, s37, 1
+; CHECK-NEXT: v_writelane_b32 v6, s38, 2
+; CHECK-NEXT: v_writelane_b32 v6, s39, 3
+; CHECK-NEXT: v_writelane_b32 v6, s48, 4
+; CHECK-NEXT: v_writelane_b32 v6, s49, 5
+; CHECK-NEXT: v_writelane_b32 v6, s50, 6
+; CHECK-NEXT: v_writelane_b32 v6, s51, 7
+; CHECK-NEXT: v_writelane_b32 v6, s52, 8
+; CHECK-NEXT: v_writelane_b32 v6, s53, 9
+; CHECK-NEXT: v_writelane_b32 v6, s54, 10
+; CHECK-NEXT: v_writelane_b32 v6, s55, 11
+; CHECK-NEXT: v_writelane_b32 v6, s64, 12
+; CHECK-NEXT: v_writelane_b32 v6, s65, 13
+; CHECK-NEXT: v_writelane_b32 v6, s66, 14
+; CHECK-NEXT: v_writelane_b32 v6, s67, 15
+; CHECK-NEXT: v_writelane_b32 v6, s68, 16
+; CHECK-NEXT: v_writelane_b32 v6, s69, 17
+; CHECK-NEXT: v_writelane_b32 v6, s70, 18
+; CHECK-NEXT: v_writelane_b32 v6, s71, 19
+; CHECK-NEXT: v_writelane_b32 v6, s30, 20
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_mov_b64 s[8:9], 0
-; CHECK-NEXT: v_writelane_b32 v6, s69, 19
+; CHECK-NEXT: v_writelane_b32 v6, s31, 21
; CHECK-NEXT: s_mov_b32 s68, 0
; CHECK-NEXT: s_mov_b32 s69, s4
; CHECK-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x0
@@ -40,11 +42,11 @@ define void @main(i1 %arg) #0 {
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: s_load_dwordx16 s[8:23], s[68:69], 0x130
; CHECK-NEXT: ; implicit-def: $vgpr7 : SGPR spill to VGPR lane
-; CHECK-NEXT: v_writelane_b32 v6, s70, 20
-; CHECK-NEXT: v_writelane_b32 v6, s71, 21
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v1, s4
; CHECK-NEXT: v_mov_b32_e32 v2, 0
+; CHECK-NEXT: s_load_dwordx16 s[36:51], s[68:69], 0x2f0
+; CHECK-NEXT: s_mov_b32 s70, s68
; CHECK-NEXT: v_writelane_b32 v7, s8, 0
; CHECK-NEXT: v_writelane_b32 v7, s9, 1
; CHECK-NEXT: v_writelane_b32 v7, s10, 2
@@ -77,9 +79,7 @@ define void @main(i1 %arg) #0 {
; CHECK-NEXT: v_writelane_b32 v7, s65, 29
; CHECK-NEXT: v_writelane_b32 v7, s66, 30
; CHECK-NEXT: s_load_dwordx16 s[8:23], s[68:69], 0x1f0
-; CHECK-NEXT: s_load_dwordx16 s[36:51], s[68:69], 0x2f0
; CHECK-NEXT: s_mov_b32 s69, s68
-; CHECK-NEXT: s_mov_b32 s70, s68
; CHECK-NEXT: s_mov_b32 s71, s68
; CHECK-NEXT: v_writelane_b32 v7, s67, 31
; CHECK-NEXT: image_sample_lz v3, v[1:2], s[60:67], s[68:71] dmask:0x1
@@ -225,29 +225,29 @@ define void @main(i1 %arg) #0 {
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: .LBB0_10: ; %UnifiedReturnBlock
; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
-; CHECK-NEXT: v_readlane_b32 s71, v6, 21
-; CHECK-NEXT: v_readlane_b32 s70, v6, 20
-; CHECK-NEXT: v_readlane_b32 s69, v6, 19
-; CHECK-NEXT: v_readlane_b32 s68, v6, 18
-; CHECK-NEXT: v_readlane_b32 s67, v6, 17
-; CHECK-NEXT: v_readlane_b32 s66, v6, 16
-; CHECK-NEXT: v_readlane_b32 s65, v6, 15
-; CHECK-NEXT: v_readlane_b32 s64, v6, 14
-; CHECK-NEXT: v_readlane_b32 s55, v6, 13
-; CHECK-NEXT: v_readlane_b32 s54, v6, 12
-; CHECK-NEXT: v_readlane_b32 s53, v6, 11
-; CHECK-NEXT: v_readlane_b32 s52, v6, 10
+; CHECK-NEXT: v_readlane_b32 s30, v6, 20
+; CHECK-NEXT: v_readlane_b32 s31, v6, 21
+; CHECK-NEXT: v_readlane_b32 s71, v6, 19
+; CHECK-NEXT: v_readlane_b32 s70, v6, 18
+; CHECK-NEXT: v_readlane_b32 s69, v6, 17
+; CHECK-NEXT: v_readlane_b32 s68, v6, 16
+; CHECK-NEXT: v_readlane_b32 s67, v6, 15
+; CHECK-NEXT: v_readlane_b32 s66, v6, 14
+; CHECK-NEXT: v_readlane_b32 s65, v6, 13
+; CHECK-NEXT: v_readlane_b32 s64, v6, 12
+; CHECK-NEXT: v_readlane_b32 s55, v6, 11
+; CHECK-NEXT: v_readlane_b32 s54, v6, 10
+; CHECK-NEXT: v_readlane_b32 s53, v6, 9
+; CHECK-NEXT: v_readlane_b32 s52, v6, 8
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: v_readlane_b32 s51, v6, 9
-; CHECK-NEXT: v_readlane_b32 s50, v6, 8
-; CHECK-NEXT: v_readlane_b32 s49, v6, 7
-; CHECK-NEXT: v_readlane_b32 s48, v6, 6
-; CHECK-NEXT: v_readlane_b32 s39, v6, 5
-; CHECK-NEXT: v_readlane_b32 s38, v6, 4
-; CHECK-NEXT: v_readlane_b32 s37, v6, 3
-; CHECK-NEXT: v_readlane_b32 s36, v6, 2
-; CHECK-NEXT: v_readlane_b32 s31, v6, 1
-; CHECK-NEXT: v_readlane_b32 s30, v6, 0
+; CHECK-NEXT: v_readlane_b32 s51, v6, 7
+; CHECK-NEXT: v_readlane_b32 s50, v6, 6
+; CHECK-NEXT: v_readlane_b32 s49, v6, 5
+; CHECK-NEXT: v_readlane_b32 s48, v6, 4
+; CHECK-NEXT: v_readlane_b32 s39, v6, 3
+; CHECK-NEXT: v_readlane_b32 s38, v6, 2
+; CHECK-NEXT: v_readlane_b32 s37, v6, 1
+; CHECK-NEXT: v_readlane_b32 s36, v6, 0
; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-call.ll b/llvm/test/CodeGen/AMDGPU/indirect-call.ll
index a208cfdb197af..2aaaff1ecc407 100644
--- a/llvm/test/CodeGen/AMDGPU/indirect-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/indirect-call.ll
@@ -128,24 +128,24 @@ define void @test_indirect_call_vgpr_ptr(ptr %fptr) {
; GCN-NEXT: s_mov_b64 exec, s[18:19]
; GCN-NEXT: v_writelane_b32 v40, s16, 18
; GCN-NEXT: s_addk_i32 s32, 0x400
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
-; GCN-NEXT: v_writelane_b32 v40, s34, 2
-; GCN-NEXT: v_writelane_b32 v40, s35, 3
-; GCN-NEXT: v_writelane_b32 v40, s36, 4
-; GCN-NEXT: v_writelane_b32 v40, s37, 5
-; GCN-NEXT: v_writelane_b32 v40, s38, 6
-; GCN-NEXT: v_writelane_b32 v40, s39, 7
-; GCN-NEXT: v_writelane_b32 v40, s48, 8
-; GCN-NEXT: v_writelane_b32 v40, s49, 9
-; GCN-NEXT: v_writelane_b32 v40, s50, 10
-; GCN-NEXT: v_writelane_b32 v40, s51, 11
-; GCN-NEXT: v_writelane_b32 v40, s52, 12
-; GCN-NEXT: v_writelane_b32 v40, s53, 13
-; GCN-NEXT: v_writelane_b32 v40, s54, 14
-; GCN-NEXT: v_writelane_b32 v40, s55, 15
-; GCN-NEXT: v_writelane_b32 v40, s64, 16
-; GCN-NEXT: v_writelane_b32 v40, s65, 17
+; GCN-NEXT: v_writelane_b32 v40, s34, 0
+; GCN-NEXT: v_writelane_b32 v40, s35, 1
+; GCN-NEXT: v_writelane_b32 v40, s36, 2
+; GCN-NEXT: v_writelane_b32 v40, s37, 3
+; GCN-NEXT: v_writelane_b32 v40, s38, 4
+; GCN-NEXT: v_writelane_b32 v40, s39, 5
+; GCN-NEXT: v_writelane_b32 v40, s48, 6
+; GCN-NEXT: v_writelane_b32 v40, s49, 7
+; GCN-NEXT: v_writelane_b32 v40, s50, 8
+; GCN-NEXT: v_writelane_b32 v40, s51, 9
+; GCN-NEXT: v_writelane_b32 v40, s52, 10
+; GCN-NEXT: v_writelane_b32 v40, s53, 11
+; GCN-NEXT: v_writelane_b32 v40, s54, 12
+; GCN-NEXT: v_writelane_b32 v40, s55, 13
+; GCN-NEXT: v_writelane_b32 v40, s64, 14
+; GCN-NEXT: v_writelane_b32 v40, s65, 15
+; GCN-NEXT: v_writelane_b32 v40, s30, 16
+; GCN-NEXT: v_writelane_b32 v40, s31, 17
; GCN-NEXT: s_mov_b32 s50, s15
; GCN-NEXT: s_mov_b32 s51, s14
; GCN-NEXT: s_mov_b32 s52, s13
@@ -175,24 +175,24 @@ define void @test_indirect_call_vgpr_ptr(ptr %fptr) {
; GCN-NEXT: s_cbranch_execnz .LBB2_1
; GCN-NEXT: ; %bb.2:
; GCN-NEXT: s_mov_b64 exec, s[54:55]
-; GCN-NEXT: v_readlane_b32 s65, v40, 17
-; GCN-NEXT: v_readlane_b32 s64, v40, 16
-; GCN-NEXT: v_readlane_b32 s55, v40, 15
-; GCN-NEXT: v_readlane_b32 s54, v40, 14
-; GCN-NEXT: v_readlane_b32 s53, v40, 13
-; GCN-NEXT: v_readlane_b32 s52, v40, 12
-; GCN-NEXT: v_readlane_b32 s51, v40, 11
-; GCN-NEXT: v_readlane_b32 s50, v40, 10
-; GCN-NEXT: v_readlane_b32 s49, v40, 9
-; GCN-NEXT: v_readlane_b32 s48, v40, 8
-; GCN-NEXT: v_readlane_b32 s39, v40, 7
-; GCN-NEXT: v_readlane_b32 s38, v40, 6
-; GCN-NEXT: v_readlane_b32 s37, v40, 5
-; GCN-NEXT: v_readlane_b32 s36, v40, 4
-; GCN-NEXT: v_readlane_b32 s35, v40, 3
-; GCN-NEXT: v_readlane_b32 s34, v40, 2
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
-; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s30, v40, 16
+; GCN-NEXT: v_readlane_b32 s31, v40, 17
+; GCN-NEXT: v_readlane_b32 s65, v40, 15
+; GCN-NEXT: v_readlane_b32 s64, v40, 14
+; GCN-NEXT: v_readlane_b32 s55, v40, 13
+; GCN-NEXT: v_readlane_b32 s54, v40, 12
+; GCN-NEXT: v_readlane_b32 s53, v40, 11
+; GCN-NEXT: v_readlane_b32 s52, v40, 10
+; GCN-NEXT: v_readlane_b32 s51, v40, 9
+; GCN-NEXT: v_readlane_b32 s50, v40, 8
+; GCN-NEXT: v_readlane_b32 s49, v40, 7
+; GCN-NEXT: v_readlane_b32 s48, v40, 6
+; GCN-NEXT: v_readlane_b32 s39, v40, 5
+; GCN-NEXT: v_readlane_b32 s38, v40, 4
+; GCN-NEXT: v_readlane_b32 s37, v40, 3
+; GCN-NEXT: v_readlane_b32 s36, v40, 2
+; GCN-NEXT: v_readlane_b32 s35, v40, 1
+; GCN-NEXT: v_readlane_b32 s34, v40, 0
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 18
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -212,24 +212,24 @@ define void @test_indirect_call_vgpr_ptr(ptr %fptr) {
; GISEL-NEXT: s_mov_b64 exec, s[18:19]
; GISEL-NEXT: v_writelane_b32 v40, s16, 18
; GISEL-NEXT: s_addk_i32 s32, 0x400
-; GISEL-NEXT: v_writelane_b32 v40, s30, 0
-; GISEL-NEXT: v_writelane_b32 v40, s31, 1
-; GISEL-NEXT: v_writelane_b32 v40, s34, 2
-; GISEL-NEXT: v_writelane_b32 v40, s35, 3
-; GISEL-NEXT: v_writelane_b32 v40, s36, 4
-; GISEL-NEXT: v_writelane_b32 v40, s37, 5
-; GISEL-NEXT: v_writelane_b32 v40, s38, 6
-; GISEL-NEXT: v_writelane_b32 v40, s39, 7
-; GISEL-NEXT: v_writelane_b32 v40, s48, 8
-; GISEL-NEXT: v_writelane_b32 v40, s49, 9
-; GISEL-NEXT: v_writelane_b32 v40, s50, 10
-; GISEL-NEXT: v_writelane_b32 v40, s51, 11
-; GISEL-NEXT: v_writelane_b32 v40, s52, 12
-; GISEL-NEXT: v_writelane_b32 v40, s53, 13
-; GISEL-NEXT: v_writelane_b32 v40, s54, 14
-; GISEL-NEXT: v_writelane_b32 v40, s55, 15
-; GISEL-NEXT: v_writelane_b32 v40, s64, 16
-; GISEL-NEXT: v_writelane_b32 v40, s65, 17
+; GISEL-NEXT: v_writelane_b32 v40, s34, 0
+; GISEL-NEXT: v_writelane_b32 v40, s35, 1
+; GISEL-NEXT: v_writelane_b32 v40, s36, 2
+; GISEL-NEXT: v_writelane_b32 v40, s37, 3
+; GISEL-NEXT: v_writelane_b32 v40, s38, 4
+; GISEL-NEXT: v_writelane_b32 v40, s39, 5
+; GISEL-NEXT: v_writelane_b32 v40, s48, 6
+; GISEL-NEXT: v_writelane_b32 v40, s49, 7
+; GISEL-NEXT: v_writelane_b32 v40, s50, 8
+; GISEL-NEXT: v_writelane_b32 v40, s51, 9
+; GISEL-NEXT: v_writelane_b32 v40, s52, 10
+; GISEL-NEXT: v_writelane_b32 v40, s53, 11
+; GISEL-NEXT: v_writelane_b32 v40, s54, 12
+; GISEL-NEXT: v_writelane_b32 v40, s55, 13
+; GISEL-NEXT: v_writelane_b32 v40, s64, 14
+; GISEL-NEXT: v_writelane_b32 v40, s65, 15
+; GISEL-NEXT: v_writelane_b32 v40, s30, 16
+; GISEL-NEXT: v_writelane_b32 v40, s31, 17
; GISEL-NEXT: s_mov_b32 s50, s15
; GISEL-NEXT: s_mov_b32 s51, s14
; GISEL-NEXT: s_mov_b32 s52, s13
@@ -259,24 +259,24 @@ define void @test_indirect_call_vgpr_ptr(ptr %fptr) {
; GISEL-NEXT: s_cbranch_execnz .LBB2_1
; GISEL-NEXT: ; %bb.2:
; GISEL-NEXT: s_mov_b64 exec, s[54:55]
-; GISEL-NEXT: v_readlane_b32 s65, v40, 17
-; GISEL-NEXT: v_readlane_b32 s64, v40, 16
-; GISEL-NEXT: v_readlane_b32 s55, v40, 15
-; GISEL-NEXT: v_readlane_b32 s54, v40, 14
-; GISEL-NEXT: v_readlane_b32 s53, v40, 13
-; GISEL-NEXT: v_readlane_b32 s52, v40, 12
-; GISEL-NEXT: v_readlane_b32 s51, v40, 11
-; GISEL-NEXT: v_readlane_b32 s50, v40, 10
-; GISEL-NEXT: v_readlane_b32 s49, v40, 9
-; GISEL-NEXT: v_readlane_b32 s48, v40, 8
-; GISEL-NEXT: v_readlane_b32 s39, v40, 7
-; GISEL-NEXT: v_readlane_b32 s38, v40, 6
-; GISEL-NEXT: v_readlane_b32 s37, v40, 5
-; GISEL-NEXT: v_readlane_b32 s36, v40, 4
-; GISEL-NEXT: v_readlane_b32 s35, v40, 3
-; GISEL-NEXT: v_readlane_b32 s34, v40, 2
-; GISEL-NEXT: v_readlane_b32 s31, v40, 1
-; GISEL-NEXT: v_readlane_b32 s30, v40, 0
+; GISEL-NEXT: v_readlane_b32 s30, v40, 16
+; GISEL-NEXT: v_readlane_b32 s31, v40, 17
+; GISEL-NEXT: v_readlane_b32 s65, v40, 15
+; GISEL-NEXT: v_readlane_b32 s64, v40, 14
+; GISEL-NEXT: v_readlane_b32 s55, v40, 13
+; GISEL-NEXT: v_readlane_b32 s54, v40, 12
+; GISEL-NEXT: v_readlane_b32 s53, v40, 11
+; GISEL-NEXT: v_readlane_b32 s52, v40, 10
+; GISEL-NEXT: v_readlane_b32 s51, v40, 9
+; GISEL-NEXT: v_readlane_b32 s50, v40, 8
+; GISEL-NEXT: v_readlane_b32 s49, v40, 7
+; GISEL-NEXT: v_readlane_b32 s48, v40, 6
+; GISEL-NEXT: v_readlane_b32 s39, v40, 5
+; GISEL-NEXT: v_readlane_b32 s38, v40, 4
+; GISEL-NEXT: v_readlane_b32 s37, v40, 3
+; GISEL-NEXT: v_readlane_b32 s36, v40, 2
+; GISEL-NEXT: v_readlane_b32 s35, v40, 1
+; GISEL-NEXT: v_readlane_b32 s34, v40, 0
; GISEL-NEXT: s_mov_b32 s32, s33
; GISEL-NEXT: v_readlane_b32 s4, v40, 18
; GISEL-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -300,24 +300,24 @@ define void @test_indirect_call_vgpr_ptr_arg(ptr %fptr) {
; GCN-NEXT: s_mov_b64 exec, s[18:19]
; GCN-NEXT: v_writelane_b32 v40, s16, 18
; GCN-NEXT: s_addk_i32 s32, 0x400
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
-; GCN-NEXT: v_writelane_b32 v40, s34, 2
-; GCN-NEXT: v_writelane_b32 v40, s35, 3
-; GCN-NEXT: v_writelane_b32 v40, s36, 4
-; GCN-NEXT: v_writelane_b32 v40, s37, 5
-; GCN-NEXT: v_writelane_b32 v40, s38, 6
-; GCN-NEXT: v_writelane_b32 v40, s39, 7
-; GCN-NEXT: v_writelane_b32 v40, s48, 8
-; GCN-NEXT: v_writelane_b32 v40, s49, 9
-; GCN-NEXT: v_writelane_b32 v40, s50, 10
-; GCN-NEXT: v_writelane_b32 v40, s51, 11
-; GCN-NEXT: v_writelane_b32 v40, s52, 12
-; GCN-NEXT: v_writelane_b32 v40, s53, 13
-; GCN-NEXT: v_writelane_b32 v40, s54, 14
-; GCN-NEXT: v_writelane_b32 v40, s55, 15
-; GCN-NEXT: v_writelane_b32 v40, s64, 16
-; GCN-NEXT: v_writelane_b32 v40, s65, 17
+; GCN-NEXT: v_writelane_b32 v40, s34, 0
+; GCN-NEXT: v_writelane_b32 v40, s35, 1
+; GCN-NEXT: v_writelane_b32 v40, s36, 2
+; GCN-NEXT: v_writelane_b32 v40, s37, 3
+; GCN-NEXT: v_writelane_b32 v40, s38, 4
+; GCN-NEXT: v_writelane_b32 v40, s39, 5
+; GCN-NEXT: v_writelane_b32 v40, s48, 6
+; GCN-NEXT: v_writelane_b32 v40, s49, 7
+; GCN-NEXT: v_writelane_b32 v40, s50, 8
+; GCN-NEXT: v_writelane_b32 v40, s51, 9
+; GCN-NEXT: v_writelane_b32 v40, s52, 10
+; GCN-NEXT: v_writelane_b32 v40, s53, 11
+; GCN-NEXT: v_writelane_b32 v40, s54, 12
+; GCN-NEXT: v_writelane_b32 v40, s55, 13
+; GCN-NEXT: v_writelane_b32 v40, s64, 14
+; GCN-NEXT: v_writelane_b32 v40, s65, 15
+; GCN-NEXT: v_writelane_b32 v40, s30, 16
+; GCN-NEXT: v_writelane_b32 v40, s31, 17
; GCN-NEXT: s_mov_b32 s50, s15
; GCN-NEXT: s_mov_b32 s51, s14
; GCN-NEXT: s_mov_b32 s52, s13
@@ -350,24 +350,24 @@ define void @test_indirect_call_vgpr_ptr_arg(ptr %fptr) {
; GCN-NEXT: s_cbranch_execnz .LBB3_1
; GCN-NEXT: ; %bb.2:
; GCN-NEXT: s_mov_b64 exec, s[54:55]
-; GCN-NEXT: v_readlane_b32 s65, v40, 17
-; GCN-NEXT: v_readlane_b32 s64, v40, 16
-; GCN-NEXT: v_readlane_b32 s55, v40, 15
-; GCN-NEXT: v_readlane_b32 s54, v40, 14
-; GCN-NEXT: v_readlane_b32 s53, v40, 13
-; GCN-NEXT: v_readlane_b32 s52, v40, 12
-; GCN-NEXT: v_readlane_b32 s51, v40, 11
-; GCN-NEXT: v_readlane_b32 s50, v40, 10
-; GCN-NEXT: v_readlane_b32 s49, v40, 9
-; GCN-NEXT: v_readlane_b32 s48, v40, 8
-; GCN-NEXT: v_readlane_b32 s39, v40, 7
-; GCN-NEXT: v_readlane_b32 s38, v40, 6
-; GCN-NEXT: v_readlane_b32 s37, v40, 5
-; GCN-NEXT: v_readlane_b32 s36, v40, 4
-; GCN-NEXT: v_readlane_b32 s35, v40, 3
-; GCN-NEXT: v_readlane_b32 s34, v40, 2
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
-; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s30, v40, 16
+; GCN-NEXT: v_readlane_b32 s31, v40, 17
+; GCN-NEXT: v_readlane_b32 s65, v40, 15
+; GCN-NEXT: v_readlane_b32 s64, v40, 14
+; GCN-NEXT: v_readlane_b32 s55, v40, 13
+; GCN-NEXT: v_readlane_b32 s54, v40, 12
+; GCN-NEXT: v_readlane_b32 s53, v40, 11
+; GCN-NEXT: v_readlane_b32 s52, v40, 10
+; GCN-NEXT: v_readlane_b32 s51, v40, 9
+; GCN-NEXT: v_readlane_b32 s50, v40, 8
+; GCN-NEXT: v_readlane_b32 s49, v40, 7
+; GCN-NEXT: v_readlane_b32 s48, v40, 6
+; GCN-NEXT: v_readlane_b32 s39, v40, 5
+; GCN-NEXT: v_readlane_b32 s38, v40, 4
+; GCN-NEXT: v_readlane_b32 s37, v40, 3
+; GCN-NEXT: v_readlane_b32 s36, v40, 2
+; GCN-NEXT: v_readlane_b32 s35, v40, 1
+; GCN-NEXT: v_readlane_b32 s34, v40, 0
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 18
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -387,24 +387,24 @@ define void @test_indirect_call_vgpr_ptr_arg(ptr %fptr) {
; GISEL-NEXT: s_mov_b64 exec, s[18:19]
; GISEL-NEXT: v_writelane_b32 v40, s16, 18
; GISEL-NEXT: s_addk_i32 s32, 0x400
-; GISEL-NEXT: v_writelane_b32 v40, s30, 0
-; GISEL-NEXT: v_writelane_b32 v40, s31, 1
-; GISEL-NEXT: v_writelane_b32 v40, s34, 2
-; GISEL-NEXT: v_writelane_b32 v40, s35, 3
-; GISEL-NEXT: v_writelane_b32 v40, s36, 4
-; GISEL-NEXT: v_writelane_b32 v40, s37, 5
-; GISEL-NEXT: v_writelane_b32 v40, s38, 6
-; GISEL-NEXT: v_writelane_b32 v40, s39, 7
-; GISEL-NEXT: v_writelane_b32 v40, s48, 8
-; GISEL-NEXT: v_writelane_b32 v40, s49, 9
-; GISEL-NEXT: v_writelane_b32 v40, s50, 10
-; GISEL-NEXT: v_writelane_b32 v40, s51, 11
-; GISEL-NEXT: v_writelane_b32 v40, s52, 12
-; GISEL-NEXT: v_writelane_b32 v40, s53, 13
-; GISEL-NEXT: v_writelane_b32 v40, s54, 14
-; GISEL-NEXT: v_writelane_b32 v40, s55, 15
-; GISEL-NEXT: v_writelane_b32 v40, s64, 16
-; GISEL-NEXT: v_writelane_b32 v40, s65, 17
+; GISEL-NEXT: v_writelane_b32 v40, s34, 0
+; GISEL-NEXT: v_writelane_b32 v40, s35, 1
+; GISEL-NEXT: v_writelane_b32 v40, s36, 2
+; GISEL-NEXT: v_writelane_b32 v40, s37, 3
+; GISEL-NEXT: v_writelane_b32 v40, s38, 4
+; GISEL-NEXT: v_writelane_b32 v40, s39, 5
+; GISEL-NEXT: v_writelane_b32 v40, s48, 6
+; GISEL-NEXT: v_writelane_b32 v40, s49, 7
+; GISEL-NEXT: v_writelane_b32 v40, s50, 8
+; GISEL-NEXT: v_writelane_b32 v40, s51, 9
+; GISEL-NEXT: v_writelane_b32 v40, s52, 10
+; GISEL-NEXT: v_writelane_b32 v40, s53, 11
+; GISEL-NEXT: v_writelane_b32 v40, s54, 12
+; GISEL-NEXT: v_writelane_b32 v40, s55, 13
+; GISEL-NEXT: v_writelane_b32 v40, s64, 14
+; GISEL-NEXT: v_writelane_b32 v40, s65, 15
+; GISEL-NEXT: v_writelane_b32 v40, s30, 16
+; GISEL-NEXT: v_writelane_b32 v40, s31, 17
; GISEL-NEXT: s_mov_b32 s50, s15
; GISEL-NEXT: s_mov_b32 s51, s14
; GISEL-NEXT: s_mov_b32 s52, s13
@@ -435,24 +435,24 @@ define void @test_indirect_call_vgpr_ptr_arg(ptr %fptr) {
; GISEL-NEXT: s_cbranch_execnz .LBB3_1
; GISEL-NEXT: ; %bb.2:
; GISEL-NEXT: s_mov_b64 exec, s[54:55]
-; GISEL-NEXT: v_readlane_b32 s65, v40, 17
-; GISEL-NEXT: v_readlane_b32 s64, v40, 16
-; GISEL-NEXT: v_readlane_b32 s55, v40, 15
-; GISEL-NEXT: v_readlane_b32 s54, v40, 14
-; GISEL-NEXT: v_readlane_b32 s53, v40, 13
-; GISEL-NEXT: v_readlane_b32 s52, v40, 12
-; GISEL-NEXT: v_readlane_b32 s51, v40, 11
-; GISEL-NEXT: v_readlane_b32 s50, v40, 10
-; GISEL-NEXT: v_readlane_b32 s49, v40, 9
-; GISEL-NEXT: v_readlane_b32 s48, v40, 8
-; GISEL-NEXT: v_readlane_b32 s39, v40, 7
-; GISEL-NEXT: v_readlane_b32 s38, v40, 6
-; GISEL-NEXT: v_readlane_b32 s37, v40, 5
-; GISEL-NEXT: v_readlane_b32 s36, v40, 4
-; GISEL-NEXT: v_readlane_b32 s35, v40, 3
-; GISEL-NEXT: v_readlane_b32 s34, v40, 2
-; GISEL-NEXT: v_readlane_b32 s31, v40, 1
-; GISEL-NEXT: v_readlane_b32 s30, v40, 0
+; GISEL-NEXT: v_readlane_b32 s30, v40, 16
+; GISEL-NEXT: v_readlane_b32 s31, v40, 17
+; GISEL-NEXT: v_readlane_b32 s65, v40, 15
+; GISEL-NEXT: v_readlane_b32 s64, v40, 14
+; GISEL-NEXT: v_readlane_b32 s55, v40, 13
+; GISEL-NEXT: v_readlane_b32 s54, v40, 12
+; GISEL-NEXT: v_readlane_b32 s53, v40, 11
+; GISEL-NEXT: v_readlane_b32 s52, v40, 10
+; GISEL-NEXT: v_readlane_b32 s51, v40, 9
+; GISEL-NEXT: v_readlane_b32 s50, v40, 8
+; GISEL-NEXT: v_readlane_b32 s49, v40, 7
+; GISEL-NEXT: v_readlane_b32 s48, v40, 6
+; GISEL-NEXT: v_readlane_b32 s39, v40, 5
+; GISEL-NEXT: v_readlane_b32 s38, v40, 4
+; GISEL-NEXT: v_readlane_b32 s37, v40, 3
+; GISEL-NEXT: v_readlane_b32 s36, v40, 2
+; GISEL-NEXT: v_readlane_b32 s35, v40, 1
+; GISEL-NEXT: v_readlane_b32 s34, v40, 0
; GISEL-NEXT: s_mov_b32 s32, s33
; GISEL-NEXT: v_readlane_b32 s4, v40, 18
; GISEL-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -476,24 +476,24 @@ define i32 @test_indirect_call_vgpr_ptr_ret(ptr %fptr) {
; GCN-NEXT: s_mov_b64 exec, s[18:19]
; GCN-NEXT: v_writelane_b32 v40, s16, 18
; GCN-NEXT: s_addk_i32 s32, 0x400
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
-; GCN-NEXT: v_writelane_b32 v40, s34, 2
-; GCN-NEXT: v_writelane_b32 v40, s35, 3
-; GCN-NEXT: v_writelane_b32 v40, s36, 4
-; GCN-NEXT: v_writelane_b32 v40, s37, 5
-; GCN-NEXT: v_writelane_b32 v40, s38, 6
-; GCN-NEXT: v_writelane_b32 v40, s39, 7
-; GCN-NEXT: v_writelane_b32 v40, s48, 8
-; GCN-NEXT: v_writelane_b32 v40, s49, 9
-; GCN-NEXT: v_writelane_b32 v40, s50, 10
-; GCN-NEXT: v_writelane_b32 v40, s51, 11
-; GCN-NEXT: v_writelane_b32 v40, s52, 12
-; GCN-NEXT: v_writelane_b32 v40, s53, 13
-; GCN-NEXT: v_writelane_b32 v40, s54, 14
-; GCN-NEXT: v_writelane_b32 v40, s55, 15
-; GCN-NEXT: v_writelane_b32 v40, s64, 16
-; GCN-NEXT: v_writelane_b32 v40, s65, 17
+; GCN-NEXT: v_writelane_b32 v40, s34, 0
+; GCN-NEXT: v_writelane_b32 v40, s35, 1
+; GCN-NEXT: v_writelane_b32 v40, s36, 2
+; GCN-NEXT: v_writelane_b32 v40, s37, 3
+; GCN-NEXT: v_writelane_b32 v40, s38, 4
+; GCN-NEXT: v_writelane_b32 v40, s39, 5
+; GCN-NEXT: v_writelane_b32 v40, s48, 6
+; GCN-NEXT: v_writelane_b32 v40, s49, 7
+; GCN-NEXT: v_writelane_b32 v40, s50, 8
+; GCN-NEXT: v_writelane_b32 v40, s51, 9
+; GCN-NEXT: v_writelane_b32 v40, s52, 10
+; GCN-NEXT: v_writelane_b32 v40, s53, 11
+; GCN-NEXT: v_writelane_b32 v40, s54, 12
+; GCN-NEXT: v_writelane_b32 v40, s55, 13
+; GCN-NEXT: v_writelane_b32 v40, s64, 14
+; GCN-NEXT: v_writelane_b32 v40, s65, 15
+; GCN-NEXT: v_writelane_b32 v40, s30, 16
+; GCN-NEXT: v_writelane_b32 v40, s31, 17
; GCN-NEXT: s_mov_b32 s50, s15
; GCN-NEXT: s_mov_b32 s51, s14
; GCN-NEXT: s_mov_b32 s52, s13
@@ -525,24 +525,24 @@ define i32 @test_indirect_call_vgpr_ptr_ret(ptr %fptr) {
; GCN-NEXT: ; %bb.2:
; GCN-NEXT: s_mov_b64 exec, s[54:55]
; GCN-NEXT: v_add_i32_e32 v0, vcc, 1, v2
-; GCN-NEXT: v_readlane_b32 s65, v40, 17
-; GCN-NEXT: v_readlane_b32 s64, v40, 16
-; GCN-NEXT: v_readlane_b32 s55, v40, 15
-; GCN-NEXT: v_readlane_b32 s54, v40, 14
-; GCN-NEXT: v_readlane_b32 s53, v40, 13
-; GCN-NEXT: v_readlane_b32 s52, v40, 12
-; GCN-NEXT: v_readlane_b32 s51, v40, 11
-; GCN-NEXT: v_readlane_b32 s50, v40, 10
-; GCN-NEXT: v_readlane_b32 s49, v40, 9
-; GCN-NEXT: v_readlane_b32 s48, v40, 8
-; GCN-NEXT: v_readlane_b32 s39, v40, 7
-; GCN-NEXT: v_readlane_b32 s38, v40, 6
-; GCN-NEXT: v_readlane_b32 s37, v40, 5
-; GCN-NEXT: v_readlane_b32 s36, v40, 4
-; GCN-NEXT: v_readlane_b32 s35, v40, 3
-; GCN-NEXT: v_readlane_b32 s34, v40, 2
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
-; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s30, v40, 16
+; GCN-NEXT: v_readlane_b32 s31, v40, 17
+; GCN-NEXT: v_readlane_b32 s65, v40, 15
+; GCN-NEXT: v_readlane_b32 s64, v40, 14
+; GCN-NEXT: v_readlane_b32 s55, v40, 13
+; GCN-NEXT: v_readlane_b32 s54, v40, 12
+; GCN-NEXT: v_readlane_b32 s53, v40, 11
+; GCN-NEXT: v_readlane_b32 s52, v40, 10
+; GCN-NEXT: v_readlane_b32 s51, v40, 9
+; GCN-NEXT: v_readlane_b32 s50, v40, 8
+; GCN-NEXT: v_readlane_b32 s49, v40, 7
+; GCN-NEXT: v_readlane_b32 s48, v40, 6
+; GCN-NEXT: v_readlane_b32 s39, v40, 5
+; GCN-NEXT: v_readlane_b32 s38, v40, 4
+; GCN-NEXT: v_readlane_b32 s37, v40, 3
+; GCN-NEXT: v_readlane_b32 s36, v40, 2
+; GCN-NEXT: v_readlane_b32 s35, v40, 1
+; GCN-NEXT: v_readlane_b32 s34, v40, 0
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 18
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -562,24 +562,24 @@ define i32 @test_indirect_call_vgpr_ptr_ret(ptr %fptr) {
; GISEL-NEXT: s_mov_b64 exec, s[18:19]
; GISEL-NEXT: v_writelane_b32 v40, s16, 18
; GISEL-NEXT: s_addk_i32 s32, 0x400
-; GISEL-NEXT: v_writelane_b32 v40, s30, 0
-; GISEL-NEXT: v_writelane_b32 v40, s31, 1
-; GISEL-NEXT: v_writelane_b32 v40, s34, 2
-; GISEL-NEXT: v_writelane_b32 v40, s35, 3
-; GISEL-NEXT: v_writelane_b32 v40, s36, 4
-; GISEL-NEXT: v_writelane_b32 v40, s37, 5
-; GISEL-NEXT: v_writelane_b32 v40, s38, 6
-; GISEL-NEXT: v_writelane_b32 v40, s39, 7
-; GISEL-NEXT: v_writelane_b32 v40, s48, 8
-; GISEL-NEXT: v_writelane_b32 v40, s49, 9
-; GISEL-NEXT: v_writelane_b32 v40, s50, 10
-; GISEL-NEXT: v_writelane_b32 v40, s51, 11
-; GISEL-NEXT: v_writelane_b32 v40, s52, 12
-; GISEL-NEXT: v_writelane_b32 v40, s53, 13
-; GISEL-NEXT: v_writelane_b32 v40, s54, 14
-; GISEL-NEXT: v_writelane_b32 v40, s55, 15
-; GISEL-NEXT: v_writelane_b32 v40, s64, 16
-; GISEL-NEXT: v_writelane_b32 v40, s65, 17
+; GISEL-NEXT: v_writelane_b32 v40, s34, 0
+; GISEL-NEXT: v_writelane_b32 v40, s35, 1
+; GISEL-NEXT: v_writelane_b32 v40, s36, 2
+; GISEL-NEXT: v_writelane_b32 v40, s37, 3
+; GISEL-NEXT: v_writelane_b32 v40, s38, 4
+; GISEL-NEXT: v_writelane_b32 v40, s39, 5
+; GISEL-NEXT: v_writelane_b32 v40, s48, 6
+; GISEL-NEXT: v_writelane_b32 v40, s49, 7
+; GISEL-NEXT: v_writelane_b32 v40, s50, 8
+; GISEL-NEXT: v_writelane_b32 v40, s51, 9
+; GISEL-NEXT: v_writelane_b32 v40, s52, 10
+; GISEL-NEXT: v_writelane_b32 v40, s53, 11
+; GISEL-NEXT: v_writelane_b32 v40, s54, 12
+; GISEL-NEXT: v_writelane_b32 v40, s55, 13
+; GISEL-NEXT: v_writelane_b32 v40, s64, 14
+; GISEL-NEXT: v_writelane_b32 v40, s65, 15
+; GISEL-NEXT: v_writelane_b32 v40, s30, 16
+; GISEL-NEXT: v_writelane_b32 v40, s31, 17
; GISEL-NEXT: s_mov_b32 s50, s15
; GISEL-NEXT: s_mov_b32 s51, s14
; GISEL-NEXT: s_mov_b32 s52, s13
@@ -611,24 +611,24 @@ define i32 @test_indirect_call_vgpr_ptr_ret(ptr %fptr) {
; GISEL-NEXT: ; %bb.2:
; GISEL-NEXT: s_mov_b64 exec, s[54:55]
; GISEL-NEXT: v_add_i32_e32 v0, vcc, 1, v1
-; GISEL-NEXT: v_readlane_b32 s65, v40, 17
-; GISEL-NEXT: v_readlane_b32 s64, v40, 16
-; GISEL-NEXT: v_readlane_b32 s55, v40, 15
-; GISEL-NEXT: v_readlane_b32 s54, v40, 14
-; GISEL-NEXT: v_readlane_b32 s53, v40, 13
-; GISEL-NEXT: v_readlane_b32 s52, v40, 12
-; GISEL-NEXT: v_readlane_b32 s51, v40, 11
-; GISEL-NEXT: v_readlane_b32 s50, v40, 10
-; GISEL-NEXT: v_readlane_b32 s49, v40, 9
-; GISEL-NEXT: v_readlane_b32 s48, v40, 8
-; GISEL-NEXT: v_readlane_b32 s39, v40, 7
-; GISEL-NEXT: v_readlane_b32 s38, v40, 6
-; GISEL-NEXT: v_readlane_b32 s37, v40, 5
-; GISEL-NEXT: v_readlane_b32 s36, v40, 4
-; GISEL-NEXT: v_readlane_b32 s35, v40, 3
-; GISEL-NEXT: v_readlane_b32 s34, v40, 2
-; GISEL-NEXT: v_readlane_b32 s31, v40, 1
-; GISEL-NEXT: v_readlane_b32 s30, v40, 0
+; GISEL-NEXT: v_readlane_b32 s30, v40, 16
+; GISEL-NEXT: v_readlane_b32 s31, v40, 17
+; GISEL-NEXT: v_readlane_b32 s65, v40, 15
+; GISEL-NEXT: v_readlane_b32 s64, v40, 14
+; GISEL-NEXT: v_readlane_b32 s55, v40, 13
+; GISEL-NEXT: v_readlane_b32 s54, v40, 12
+; GISEL-NEXT: v_readlane_b32 s53, v40, 11
+; GISEL-NEXT: v_readlane_b32 s52, v40, 10
+; GISEL-NEXT: v_readlane_b32 s51, v40, 9
+; GISEL-NEXT: v_readlane_b32 s50, v40, 8
+; GISEL-NEXT: v_readlane_b32 s49, v40, 7
+; GISEL-NEXT: v_readlane_b32 s48, v40, 6
+; GISEL-NEXT: v_readlane_b32 s39, v40, 5
+; GISEL-NEXT: v_readlane_b32 s38, v40, 4
+; GISEL-NEXT: v_readlane_b32 s37, v40, 3
+; GISEL-NEXT: v_readlane_b32 s36, v40, 2
+; GISEL-NEXT: v_readlane_b32 s35, v40, 1
+; GISEL-NEXT: v_readlane_b32 s34, v40, 0
; GISEL-NEXT: s_mov_b32 s32, s33
; GISEL-NEXT: v_readlane_b32 s4, v40, 18
; GISEL-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -653,26 +653,26 @@ define void @test_indirect_call_vgpr_ptr_in_branch(ptr %fptr, i1 %cond) {
; GCN-NEXT: s_mov_b64 exec, s[18:19]
; GCN-NEXT: v_writelane_b32 v40, s16, 20
; GCN-NEXT: s_addk_i32 s32, 0x400
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
-; GCN-NEXT: v_writelane_b32 v40, s34, 2
-; GCN-NEXT: v_writelane_b32 v40, s35, 3
-; GCN-NEXT: v_writelane_b32 v40, s36, 4
-; GCN-NEXT: v_writelane_b32 v40, s37, 5
-; GCN-NEXT: v_writelane_b32 v40, s38, 6
-; GCN-NEXT: v_writelane_b32 v40, s39, 7
-; GCN-NEXT: v_writelane_b32 v40, s48, 8
-; GCN-NEXT: v_writelane_b32 v40, s49, 9
-; GCN-NEXT: v_writelane_b32 v40, s50, 10
-; GCN-NEXT: v_writelane_b32 v40, s51, 11
-; GCN-NEXT: v_writelane_b32 v40, s52, 12
-; GCN-NEXT: v_writelane_b32 v40, s53, 13
-; GCN-NEXT: v_writelane_b32 v40, s54, 14
-; GCN-NEXT: v_writelane_b32 v40, s55, 15
-; GCN-NEXT: v_writelane_b32 v40, s64, 16
-; GCN-NEXT: v_writelane_b32 v40, s65, 17
-; GCN-NEXT: v_writelane_b32 v40, s66, 18
-; GCN-NEXT: v_writelane_b32 v40, s67, 19
+; GCN-NEXT: v_writelane_b32 v40, s34, 0
+; GCN-NEXT: v_writelane_b32 v40, s35, 1
+; GCN-NEXT: v_writelane_b32 v40, s36, 2
+; GCN-NEXT: v_writelane_b32 v40, s37, 3
+; GCN-NEXT: v_writelane_b32 v40, s38, 4
+; GCN-NEXT: v_writelane_b32 v40, s39, 5
+; GCN-NEXT: v_writelane_b32 v40, s48, 6
+; GCN-NEXT: v_writelane_b32 v40, s49, 7
+; GCN-NEXT: v_writelane_b32 v40, s50, 8
+; GCN-NEXT: v_writelane_b32 v40, s51, 9
+; GCN-NEXT: v_writelane_b32 v40, s52, 10
+; GCN-NEXT: v_writelane_b32 v40, s53, 11
+; GCN-NEXT: v_writelane_b32 v40, s54, 12
+; GCN-NEXT: v_writelane_b32 v40, s55, 13
+; GCN-NEXT: v_writelane_b32 v40, s64, 14
+; GCN-NEXT: v_writelane_b32 v40, s65, 15
+; GCN-NEXT: v_writelane_b32 v40, s66, 16
+; GCN-NEXT: v_writelane_b32 v40, s67, 17
+; GCN-NEXT: v_writelane_b32 v40, s30, 18
+; GCN-NEXT: v_writelane_b32 v40, s31, 19
; GCN-NEXT: s_mov_b32 s50, s15
; GCN-NEXT: s_mov_b32 s51, s14
; GCN-NEXT: s_mov_b32 s52, s13
@@ -709,26 +709,26 @@ define void @test_indirect_call_vgpr_ptr_in_branch(ptr %fptr, i1 %cond) {
; GCN-NEXT: s_mov_b64 exec, s[64:65]
; GCN-NEXT: .LBB5_4: ; %bb2
; GCN-NEXT: s_or_b64 exec, exec, s[54:55]
-; GCN-NEXT: v_readlane_b32 s67, v40, 19
-; GCN-NEXT: v_readlane_b32 s66, v40, 18
-; GCN-NEXT: v_readlane_b32 s65, v40, 17
-; GCN-NEXT: v_readlane_b32 s64, v40, 16
-; GCN-NEXT: v_readlane_b32 s55, v40, 15
-; GCN-NEXT: v_readlane_b32 s54, v40, 14
-; GCN-NEXT: v_readlane_b32 s53, v40, 13
-; GCN-NEXT: v_readlane_b32 s52, v40, 12
-; GCN-NEXT: v_readlane_b32 s51, v40, 11
-; GCN-NEXT: v_readlane_b32 s50, v40, 10
-; GCN-NEXT: v_readlane_b32 s49, v40, 9
-; GCN-NEXT: v_readlane_b32 s48, v40, 8
-; GCN-NEXT: v_readlane_b32 s39, v40, 7
-; GCN-NEXT: v_readlane_b32 s38, v40, 6
-; GCN-NEXT: v_readlane_b32 s37, v40, 5
-; GCN-NEXT: v_readlane_b32 s36, v40, 4
-; GCN-NEXT: v_readlane_b32 s35, v40, 3
-; GCN-NEXT: v_readlane_b32 s34, v40, 2
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
-; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s30, v40, 18
+; GCN-NEXT: v_readlane_b32 s31, v40, 19
+; GCN-NEXT: v_readlane_b32 s67, v40, 17
+; GCN-NEXT: v_readlane_b32 s66, v40, 16
+; GCN-NEXT: v_readlane_b32 s65, v40, 15
+; GCN-NEXT: v_readlane_b32 s64, v40, 14
+; GCN-NEXT: v_readlane_b32 s55, v40, 13
+; GCN-NEXT: v_readlane_b32 s54, v40, 12
+; GCN-NEXT: v_readlane_b32 s53, v40, 11
+; GCN-NEXT: v_readlane_b32 s52, v40, 10
+; GCN-NEXT: v_readlane_b32 s51, v40, 9
+; GCN-NEXT: v_readlane_b32 s50, v40, 8
+; GCN-NEXT: v_readlane_b32 s49, v40, 7
+; GCN-NEXT: v_readlane_b32 s48, v40, 6
+; GCN-NEXT: v_readlane_b32 s39, v40, 5
+; GCN-NEXT: v_readlane_b32 s38, v40, 4
+; GCN-NEXT: v_readlane_b32 s37, v40, 3
+; GCN-NEXT: v_readlane_b32 s36, v40, 2
+; GCN-NEXT: v_readlane_b32 s35, v40, 1
+; GCN-NEXT: v_readlane_b32 s34, v40, 0
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 20
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -748,26 +748,26 @@ define void @test_indirect_call_vgpr_ptr_in_branch(ptr %fptr, i1 %cond) {
; GISEL-NEXT: s_mov_b64 exec, s[18:19]
; GISEL-NEXT: v_writelane_b32 v40, s16, 20
; GISEL-NEXT: s_addk_i32 s32, 0x400
-; GISEL-NEXT: v_writelane_b32 v40, s30, 0
-; GISEL-NEXT: v_writelane_b32 v40, s31, 1
-; GISEL-NEXT: v_writelane_b32 v40, s34, 2
-; GISEL-NEXT: v_writelane_b32 v40, s35, 3
-; GISEL-NEXT: v_writelane_b32 v40, s36, 4
-; GISEL-NEXT: v_writelane_b32 v40, s37, 5
-; GISEL-NEXT: v_writelane_b32 v40, s38, 6
-; GISEL-NEXT: v_writelane_b32 v40, s39, 7
-; GISEL-NEXT: v_writelane_b32 v40, s48, 8
-; GISEL-NEXT: v_writelane_b32 v40, s49, 9
-; GISEL-NEXT: v_writelane_b32 v40, s50, 10
-; GISEL-NEXT: v_writelane_b32 v40, s51, 11
-; GISEL-NEXT: v_writelane_b32 v40, s52, 12
-; GISEL-NEXT: v_writelane_b32 v40, s53, 13
-; GISEL-NEXT: v_writelane_b32 v40, s54, 14
-; GISEL-NEXT: v_writelane_b32 v40, s55, 15
-; GISEL-NEXT: v_writelane_b32 v40, s64, 16
-; GISEL-NEXT: v_writelane_b32 v40, s65, 17
-; GISEL-NEXT: v_writelane_b32 v40, s66, 18
-; GISEL-NEXT: v_writelane_b32 v40, s67, 19
+; GISEL-NEXT: v_writelane_b32 v40, s34, 0
+; GISEL-NEXT: v_writelane_b32 v40, s35, 1
+; GISEL-NEXT: v_writelane_b32 v40, s36, 2
+; GISEL-NEXT: v_writelane_b32 v40, s37, 3
+; GISEL-NEXT: v_writelane_b32 v40, s38, 4
+; GISEL-NEXT: v_writelane_b32 v40, s39, 5
+; GISEL-NEXT: v_writelane_b32 v40, s48, 6
+; GISEL-NEXT: v_writelane_b32 v40, s49, 7
+; GISEL-NEXT: v_writelane_b32 v40, s50, 8
+; GISEL-NEXT: v_writelane_b32 v40, s51, 9
+; GISEL-NEXT: v_writelane_b32 v40, s52, 10
+; GISEL-NEXT: v_writelane_b32 v40, s53, 11
+; GISEL-NEXT: v_writelane_b32 v40, s54, 12
+; GISEL-NEXT: v_writelane_b32 v40, s55, 13
+; GISEL-NEXT: v_writelane_b32 v40, s64, 14
+; GISEL-NEXT: v_writelane_b32 v40, s65, 15
+; GISEL-NEXT: v_writelane_b32 v40, s66, 16
+; GISEL-NEXT: v_writelane_b32 v40, s67, 17
+; GISEL-NEXT: v_writelane_b32 v40, s30, 18
+; GISEL-NEXT: v_writelane_b32 v40, s31, 19
; GISEL-NEXT: s_mov_b32 s50, s15
; GISEL-NEXT: s_mov_b32 s51, s14
; GISEL-NEXT: s_mov_b32 s52, s13
@@ -804,26 +804,26 @@ define void @test_indirect_call_vgpr_ptr_in_branch(ptr %fptr, i1 %cond) {
; GISEL-NEXT: s_mov_b64 exec, s[64:65]
; GISEL-NEXT: .LBB5_4: ; %bb2
; GISEL-NEXT: s_or_b64 exec, exec, s[54:55]
-; GISEL-NEXT: v_readlane_b32 s67, v40, 19
-; GISEL-NEXT: v_readlane_b32 s66, v40, 18
-; GISEL-NEXT: v_readlane_b32 s65, v40, 17
-; GISEL-NEXT: v_readlane_b32 s64, v40, 16
-; GISEL-NEXT: v_readlane_b32 s55, v40, 15
-; GISEL-NEXT: v_readlane_b32 s54, v40, 14
-; GISEL-NEXT: v_readlane_b32 s53, v40, 13
-; GISEL-NEXT: v_readlane_b32 s52, v40, 12
-; GISEL-NEXT: v_readlane_b32 s51, v40, 11
-; GISEL-NEXT: v_readlane_b32 s50, v40, 10
-; GISEL-NEXT: v_readlane_b32 s49, v40, 9
-; GISEL-NEXT: v_readlane_b32 s48, v40, 8
-; GISEL-NEXT: v_readlane_b32 s39, v40, 7
-; GISEL-NEXT: v_readlane_b32 s38, v40, 6
-; GISEL-NEXT: v_readlane_b32 s37, v40, 5
-; GISEL-NEXT: v_readlane_b32 s36, v40, 4
-; GISEL-NEXT: v_readlane_b32 s35, v40, 3
-; GISEL-NEXT: v_readlane_b32 s34, v40, 2
-; GISEL-NEXT: v_readlane_b32 s31, v40, 1
-; GISEL-NEXT: v_readlane_b32 s30, v40, 0
+; GISEL-NEXT: v_readlane_b32 s30, v40, 18
+; GISEL-NEXT: v_readlane_b32 s31, v40, 19
+; GISEL-NEXT: v_readlane_b32 s67, v40, 17
+; GISEL-NEXT: v_readlane_b32 s66, v40, 16
+; GISEL-NEXT: v_readlane_b32 s65, v40, 15
+; GISEL-NEXT: v_readlane_b32 s64, v40, 14
+; GISEL-NEXT: v_readlane_b32 s55, v40, 13
+; GISEL-NEXT: v_readlane_b32 s54, v40, 12
+; GISEL-NEXT: v_readlane_b32 s53, v40, 11
+; GISEL-NEXT: v_readlane_b32 s52, v40, 10
+; GISEL-NEXT: v_readlane_b32 s51, v40, 9
+; GISEL-NEXT: v_readlane_b32 s50, v40, 8
+; GISEL-NEXT: v_readlane_b32 s49, v40, 7
+; GISEL-NEXT: v_readlane_b32 s48, v40, 6
+; GISEL-NEXT: v_readlane_b32 s39, v40, 5
+; GISEL-NEXT: v_readlane_b32 s38, v40, 4
+; GISEL-NEXT: v_readlane_b32 s37, v40, 3
+; GISEL-NEXT: v_readlane_b32 s36, v40, 2
+; GISEL-NEXT: v_readlane_b32 s35, v40, 1
+; GISEL-NEXT: v_readlane_b32 s34, v40, 0
; GISEL-NEXT: s_mov_b32 s32, s33
; GISEL-NEXT: v_readlane_b32 s4, v40, 20
; GISEL-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -853,22 +853,22 @@ define void @test_indirect_call_vgpr_ptr_inreg_arg(ptr %fptr) {
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[6:7]
; GCN-NEXT: s_addk_i32 s32, 0x400
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
-; GCN-NEXT: v_writelane_b32 v40, s34, 2
-; GCN-NEXT: v_writelane_b32 v40, s35, 3
-; GCN-NEXT: v_writelane_b32 v40, s36, 4
-; GCN-NEXT: v_writelane_b32 v40, s37, 5
-; GCN-NEXT: v_writelane_b32 v40, s38, 6
-; GCN-NEXT: v_writelane_b32 v40, s39, 7
-; GCN-NEXT: v_writelane_b32 v40, s48, 8
-; GCN-NEXT: v_writelane_b32 v40, s49, 9
-; GCN-NEXT: v_writelane_b32 v40, s50, 10
-; GCN-NEXT: v_writelane_b32 v40, s51, 11
-; GCN-NEXT: v_writelane_b32 v40, s52, 12
-; GCN-NEXT: v_writelane_b32 v40, s53, 13
-; GCN-NEXT: v_writelane_b32 v40, s54, 14
-; GCN-NEXT: v_writelane_b32 v40, s55, 15
+; GCN-NEXT: v_writelane_b32 v40, s34, 0
+; GCN-NEXT: v_writelane_b32 v40, s35, 1
+; GCN-NEXT: v_writelane_b32 v40, s36, 2
+; GCN-NEXT: v_writelane_b32 v40, s37, 3
+; GCN-NEXT: v_writelane_b32 v40, s38, 4
+; GCN-NEXT: v_writelane_b32 v40, s39, 5
+; GCN-NEXT: v_writelane_b32 v40, s48, 6
+; GCN-NEXT: v_writelane_b32 v40, s49, 7
+; GCN-NEXT: v_writelane_b32 v40, s50, 8
+; GCN-NEXT: v_writelane_b32 v40, s51, 9
+; GCN-NEXT: v_writelane_b32 v40, s52, 10
+; GCN-NEXT: v_writelane_b32 v40, s53, 11
+; GCN-NEXT: v_writelane_b32 v40, s54, 12
+; GCN-NEXT: v_writelane_b32 v40, s55, 13
+; GCN-NEXT: v_writelane_b32 v40, s30, 14
+; GCN-NEXT: v_writelane_b32 v40, s31, 15
; GCN-NEXT: s_mov_b64 s[6:7], exec
; GCN-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_readfirstlane_b32 s8, v0
@@ -882,22 +882,22 @@ define void @test_indirect_call_vgpr_ptr_inreg_arg(ptr %fptr) {
; GCN-NEXT: s_cbranch_execnz .LBB6_1
; GCN-NEXT: ; %bb.2:
; GCN-NEXT: s_mov_b64 exec, s[6:7]
-; GCN-NEXT: v_readlane_b32 s55, v40, 15
-; GCN-NEXT: v_readlane_b32 s54, v40, 14
-; GCN-NEXT: v_readlane_b32 s53, v40, 13
-; GCN-NEXT: v_readlane_b32 s52, v40, 12
-; GCN-NEXT: v_readlane_b32 s51, v40, 11
-; GCN-NEXT: v_readlane_b32 s50, v40, 10
-; GCN-NEXT: v_readlane_b32 s49, v40, 9
-; GCN-NEXT: v_readlane_b32 s48, v40, 8
-; GCN-NEXT: v_readlane_b32 s39, v40, 7
-; GCN-NEXT: v_readlane_b32 s38, v40, 6
-; GCN-NEXT: v_readlane_b32 s37, v40, 5
-; GCN-NEXT: v_readlane_b32 s36, v40, 4
-; GCN-NEXT: v_readlane_b32 s35, v40, 3
-; GCN-NEXT: v_readlane_b32 s34, v40, 2
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
-; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s30, v40, 14
+; GCN-NEXT: v_readlane_b32 s31, v40, 15
+; GCN-NEXT: v_readlane_b32 s55, v40, 13
+; GCN-NEXT: v_readlane_b32 s54, v40, 12
+; GCN-NEXT: v_readlane_b32 s53, v40, 11
+; GCN-NEXT: v_readlane_b32 s52, v40, 10
+; GCN-NEXT: v_readlane_b32 s51, v40, 9
+; GCN-NEXT: v_readlane_b32 s50, v40, 8
+; GCN-NEXT: v_readlane_b32 s49, v40, 7
+; GCN-NEXT: v_readlane_b32 s48, v40, 6
+; GCN-NEXT: v_readlane_b32 s39, v40, 5
+; GCN-NEXT: v_readlane_b32 s38, v40, 4
+; GCN-NEXT: v_readlane_b32 s37, v40, 3
+; GCN-NEXT: v_readlane_b32 s36, v40, 2
+; GCN-NEXT: v_readlane_b32 s35, v40, 1
+; GCN-NEXT: v_readlane_b32 s34, v40, 0
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -915,22 +915,22 @@ define void @test_indirect_call_vgpr_ptr_inreg_arg(ptr %fptr) {
; GISEL-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GISEL-NEXT: s_mov_b64 exec, s[6:7]
; GISEL-NEXT: s_addk_i32 s32, 0x400
-; GISEL-NEXT: v_writelane_b32 v40, s30, 0
-; GISEL-NEXT: v_writelane_b32 v40, s31, 1
-; GISEL-NEXT: v_writelane_b32 v40, s34, 2
-; GISEL-NEXT: v_writelane_b32 v40, s35, 3
-; GISEL-NEXT: v_writelane_b32 v40, s36, 4
-; GISEL-NEXT: v_writelane_b32 v40, s37, 5
-; GISEL-NEXT: v_writelane_b32 v40, s38, 6
-; GISEL-NEXT: v_writelane_b32 v40, s39, 7
-; GISEL-NEXT: v_writelane_b32 v40, s48, 8
-; GISEL-NEXT: v_writelane_b32 v40, s49, 9
-; GISEL-NEXT: v_writelane_b32 v40, s50, 10
-; GISEL-NEXT: v_writelane_b32 v40, s51, 11
-; GISEL-NEXT: v_writelane_b32 v40, s52, 12
-; GISEL-NEXT: v_writelane_b32 v40, s53, 13
-; GISEL-NEXT: v_writelane_b32 v40, s54, 14
-; GISEL-NEXT: v_writelane_b32 v40, s55, 15
+; GISEL-NEXT: v_writelane_b32 v40, s34, 0
+; GISEL-NEXT: v_writelane_b32 v40, s35, 1
+; GISEL-NEXT: v_writelane_b32 v40, s36, 2
+; GISEL-NEXT: v_writelane_b32 v40, s37, 3
+; GISEL-NEXT: v_writelane_b32 v40, s38, 4
+; GISEL-NEXT: v_writelane_b32 v40, s39, 5
+; GISEL-NEXT: v_writelane_b32 v40, s48, 6
+; GISEL-NEXT: v_writelane_b32 v40, s49, 7
+; GISEL-NEXT: v_writelane_b32 v40, s50, 8
+; GISEL-NEXT: v_writelane_b32 v40, s51, 9
+; GISEL-NEXT: v_writelane_b32 v40, s52, 10
+; GISEL-NEXT: v_writelane_b32 v40, s53, 11
+; GISEL-NEXT: v_writelane_b32 v40, s54, 12
+; GISEL-NEXT: v_writelane_b32 v40, s55, 13
+; GISEL-NEXT: v_writelane_b32 v40, s30, 14
+; GISEL-NEXT: v_writelane_b32 v40, s31, 15
; GISEL-NEXT: s_mov_b64 s[6:7], exec
; GISEL-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1
; GISEL-NEXT: v_readfirstlane_b32 s8, v0
@@ -944,22 +944,22 @@ define void @test_indirect_call_vgpr_ptr_inreg_arg(ptr %fptr) {
; GISEL-NEXT: s_cbranch_execnz .LBB6_1
; GISEL-NEXT: ; %bb.2:
; GISEL-NEXT: s_mov_b64 exec, s[6:7]
-; GISEL-NEXT: v_readlane_b32 s55, v40, 15
-; GISEL-NEXT: v_readlane_b32 s54, v40, 14
-; GISEL-NEXT: v_readlane_b32 s53, v40, 13
-; GISEL-NEXT: v_readlane_b32 s52, v40, 12
-; GISEL-NEXT: v_readlane_b32 s51, v40, 11
-; GISEL-NEXT: v_readlane_b32 s50, v40, 10
-; GISEL-NEXT: v_readlane_b32 s49, v40, 9
-; GISEL-NEXT: v_readlane_b32 s48, v40, 8
-; GISEL-NEXT: v_readlane_b32 s39, v40, 7
-; GISEL-NEXT: v_readlane_b32 s38, v40, 6
-; GISEL-NEXT: v_readlane_b32 s37, v40, 5
-; GISEL-NEXT: v_readlane_b32 s36, v40, 4
-; GISEL-NEXT: v_readlane_b32 s35, v40, 3
-; GISEL-NEXT: v_readlane_b32 s34, v40, 2
-; GISEL-NEXT: v_readlane_b32 s31, v40, 1
-; GISEL-NEXT: v_readlane_b32 s30, v40, 0
+; GISEL-NEXT: v_readlane_b32 s30, v40, 14
+; GISEL-NEXT: v_readlane_b32 s31, v40, 15
+; GISEL-NEXT: v_readlane_b32 s55, v40, 13
+; GISEL-NEXT: v_readlane_b32 s54, v40, 12
+; GISEL-NEXT: v_readlane_b32 s53, v40, 11
+; GISEL-NEXT: v_readlane_b32 s52, v40, 10
+; GISEL-NEXT: v_readlane_b32 s51, v40, 9
+; GISEL-NEXT: v_readlane_b32 s50, v40, 8
+; GISEL-NEXT: v_readlane_b32 s49, v40, 7
+; GISEL-NEXT: v_readlane_b32 s48, v40, 6
+; GISEL-NEXT: v_readlane_b32 s39, v40, 5
+; GISEL-NEXT: v_readlane_b32 s38, v40, 4
+; GISEL-NEXT: v_readlane_b32 s37, v40, 3
+; GISEL-NEXT: v_readlane_b32 s36, v40, 2
+; GISEL-NEXT: v_readlane_b32 s35, v40, 1
+; GISEL-NEXT: v_readlane_b32 s34, v40, 0
; GISEL-NEXT: s_mov_b32 s32, s33
; GISEL-NEXT: s_or_saveexec_b64 s[6:7], -1
; GISEL-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -982,22 +982,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_reuse(i32 %i, ptr %fptr) {
; GCN-NEXT: s_mov_b64 exec, s[4:5]
; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GCN-NEXT: v_writelane_b32 v41, s30, 0
-; GCN-NEXT: v_writelane_b32 v41, s31, 1
-; GCN-NEXT: v_writelane_b32 v41, s34, 2
-; GCN-NEXT: v_writelane_b32 v41, s35, 3
-; GCN-NEXT: v_writelane_b32 v41, s36, 4
-; GCN-NEXT: v_writelane_b32 v41, s37, 5
-; GCN-NEXT: v_writelane_b32 v41, s38, 6
-; GCN-NEXT: v_writelane_b32 v41, s39, 7
-; GCN-NEXT: v_writelane_b32 v41, s48, 8
-; GCN-NEXT: v_writelane_b32 v41, s49, 9
-; GCN-NEXT: v_writelane_b32 v41, s50, 10
-; GCN-NEXT: v_writelane_b32 v41, s51, 11
-; GCN-NEXT: v_writelane_b32 v41, s52, 12
-; GCN-NEXT: v_writelane_b32 v41, s53, 13
-; GCN-NEXT: v_writelane_b32 v41, s54, 14
-; GCN-NEXT: v_writelane_b32 v41, s55, 15
+; GCN-NEXT: v_writelane_b32 v41, s34, 0
+; GCN-NEXT: v_writelane_b32 v41, s35, 1
+; GCN-NEXT: v_writelane_b32 v41, s36, 2
+; GCN-NEXT: v_writelane_b32 v41, s37, 3
+; GCN-NEXT: v_writelane_b32 v41, s38, 4
+; GCN-NEXT: v_writelane_b32 v41, s39, 5
+; GCN-NEXT: v_writelane_b32 v41, s48, 6
+; GCN-NEXT: v_writelane_b32 v41, s49, 7
+; GCN-NEXT: v_writelane_b32 v41, s50, 8
+; GCN-NEXT: v_writelane_b32 v41, s51, 9
+; GCN-NEXT: v_writelane_b32 v41, s52, 10
+; GCN-NEXT: v_writelane_b32 v41, s53, 11
+; GCN-NEXT: v_writelane_b32 v41, s54, 12
+; GCN-NEXT: v_writelane_b32 v41, s55, 13
+; GCN-NEXT: v_writelane_b32 v41, s30, 14
+; GCN-NEXT: v_writelane_b32 v41, s31, 15
; GCN-NEXT: v_mov_b32_e32 v40, v0
; GCN-NEXT: s_mov_b64 s[4:5], exec
; GCN-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
@@ -1013,22 +1013,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_reuse(i32 %i, ptr %fptr) {
; GCN-NEXT: ; %bb.2:
; GCN-NEXT: s_mov_b64 exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, v40
-; GCN-NEXT: v_readlane_b32 s55, v41, 15
-; GCN-NEXT: v_readlane_b32 s54, v41, 14
-; GCN-NEXT: v_readlane_b32 s53, v41, 13
-; GCN-NEXT: v_readlane_b32 s52, v41, 12
-; GCN-NEXT: v_readlane_b32 s51, v41, 11
-; GCN-NEXT: v_readlane_b32 s50, v41, 10
-; GCN-NEXT: v_readlane_b32 s49, v41, 9
-; GCN-NEXT: v_readlane_b32 s48, v41, 8
-; GCN-NEXT: v_readlane_b32 s39, v41, 7
-; GCN-NEXT: v_readlane_b32 s38, v41, 6
-; GCN-NEXT: v_readlane_b32 s37, v41, 5
-; GCN-NEXT: v_readlane_b32 s36, v41, 4
-; GCN-NEXT: v_readlane_b32 s35, v41, 3
-; GCN-NEXT: v_readlane_b32 s34, v41, 2
-; GCN-NEXT: v_readlane_b32 s31, v41, 1
-; GCN-NEXT: v_readlane_b32 s30, v41, 0
+; GCN-NEXT: v_readlane_b32 s30, v41, 14
+; GCN-NEXT: v_readlane_b32 s31, v41, 15
+; GCN-NEXT: v_readlane_b32 s55, v41, 13
+; GCN-NEXT: v_readlane_b32 s54, v41, 12
+; GCN-NEXT: v_readlane_b32 s53, v41, 11
+; GCN-NEXT: v_readlane_b32 s52, v41, 10
+; GCN-NEXT: v_readlane_b32 s51, v41, 9
+; GCN-NEXT: v_readlane_b32 s50, v41, 8
+; GCN-NEXT: v_readlane_b32 s49, v41, 7
+; GCN-NEXT: v_readlane_b32 s48, v41, 6
+; GCN-NEXT: v_readlane_b32 s39, v41, 5
+; GCN-NEXT: v_readlane_b32 s38, v41, 4
+; GCN-NEXT: v_readlane_b32 s37, v41, 3
+; GCN-NEXT: v_readlane_b32 s36, v41, 2
+; GCN-NEXT: v_readlane_b32 s35, v41, 1
+; GCN-NEXT: v_readlane_b32 s34, v41, 0
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: s_or_saveexec_b64 s[4:5], -1
@@ -1048,22 +1048,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_reuse(i32 %i, ptr %fptr) {
; GISEL-NEXT: s_mov_b64 exec, s[4:5]
; GISEL-NEXT: s_addk_i32 s32, 0x400
; GISEL-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GISEL-NEXT: v_writelane_b32 v41, s30, 0
-; GISEL-NEXT: v_writelane_b32 v41, s31, 1
-; GISEL-NEXT: v_writelane_b32 v41, s34, 2
-; GISEL-NEXT: v_writelane_b32 v41, s35, 3
-; GISEL-NEXT: v_writelane_b32 v41, s36, 4
-; GISEL-NEXT: v_writelane_b32 v41, s37, 5
-; GISEL-NEXT: v_writelane_b32 v41, s38, 6
-; GISEL-NEXT: v_writelane_b32 v41, s39, 7
-; GISEL-NEXT: v_writelane_b32 v41, s48, 8
-; GISEL-NEXT: v_writelane_b32 v41, s49, 9
-; GISEL-NEXT: v_writelane_b32 v41, s50, 10
-; GISEL-NEXT: v_writelane_b32 v41, s51, 11
-; GISEL-NEXT: v_writelane_b32 v41, s52, 12
-; GISEL-NEXT: v_writelane_b32 v41, s53, 13
-; GISEL-NEXT: v_writelane_b32 v41, s54, 14
-; GISEL-NEXT: v_writelane_b32 v41, s55, 15
+; GISEL-NEXT: v_writelane_b32 v41, s34, 0
+; GISEL-NEXT: v_writelane_b32 v41, s35, 1
+; GISEL-NEXT: v_writelane_b32 v41, s36, 2
+; GISEL-NEXT: v_writelane_b32 v41, s37, 3
+; GISEL-NEXT: v_writelane_b32 v41, s38, 4
+; GISEL-NEXT: v_writelane_b32 v41, s39, 5
+; GISEL-NEXT: v_writelane_b32 v41, s48, 6
+; GISEL-NEXT: v_writelane_b32 v41, s49, 7
+; GISEL-NEXT: v_writelane_b32 v41, s50, 8
+; GISEL-NEXT: v_writelane_b32 v41, s51, 9
+; GISEL-NEXT: v_writelane_b32 v41, s52, 10
+; GISEL-NEXT: v_writelane_b32 v41, s53, 11
+; GISEL-NEXT: v_writelane_b32 v41, s54, 12
+; GISEL-NEXT: v_writelane_b32 v41, s55, 13
+; GISEL-NEXT: v_writelane_b32 v41, s30, 14
+; GISEL-NEXT: v_writelane_b32 v41, s31, 15
; GISEL-NEXT: v_mov_b32_e32 v40, v0
; GISEL-NEXT: s_mov_b64 s[4:5], exec
; GISEL-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
@@ -1079,22 +1079,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_reuse(i32 %i, ptr %fptr) {
; GISEL-NEXT: ; %bb.2:
; GISEL-NEXT: s_mov_b64 exec, s[4:5]
; GISEL-NEXT: v_mov_b32_e32 v0, v40
-; GISEL-NEXT: v_readlane_b32 s55, v41, 15
-; GISEL-NEXT: v_readlane_b32 s54, v41, 14
-; GISEL-NEXT: v_readlane_b32 s53, v41, 13
-; GISEL-NEXT: v_readlane_b32 s52, v41, 12
-; GISEL-NEXT: v_readlane_b32 s51, v41, 11
-; GISEL-NEXT: v_readlane_b32 s50, v41, 10
-; GISEL-NEXT: v_readlane_b32 s49, v41, 9
-; GISEL-NEXT: v_readlane_b32 s48, v41, 8
-; GISEL-NEXT: v_readlane_b32 s39, v41, 7
-; GISEL-NEXT: v_readlane_b32 s38, v41, 6
-; GISEL-NEXT: v_readlane_b32 s37, v41, 5
-; GISEL-NEXT: v_readlane_b32 s36, v41, 4
-; GISEL-NEXT: v_readlane_b32 s35, v41, 3
-; GISEL-NEXT: v_readlane_b32 s34, v41, 2
-; GISEL-NEXT: v_readlane_b32 s31, v41, 1
-; GISEL-NEXT: v_readlane_b32 s30, v41, 0
+; GISEL-NEXT: v_readlane_b32 s30, v41, 14
+; GISEL-NEXT: v_readlane_b32 s31, v41, 15
+; GISEL-NEXT: v_readlane_b32 s55, v41, 13
+; GISEL-NEXT: v_readlane_b32 s54, v41, 12
+; GISEL-NEXT: v_readlane_b32 s53, v41, 11
+; GISEL-NEXT: v_readlane_b32 s52, v41, 10
+; GISEL-NEXT: v_readlane_b32 s51, v41, 9
+; GISEL-NEXT: v_readlane_b32 s50, v41, 8
+; GISEL-NEXT: v_readlane_b32 s49, v41, 7
+; GISEL-NEXT: v_readlane_b32 s48, v41, 6
+; GISEL-NEXT: v_readlane_b32 s39, v41, 5
+; GISEL-NEXT: v_readlane_b32 s38, v41, 4
+; GISEL-NEXT: v_readlane_b32 s37, v41, 3
+; GISEL-NEXT: v_readlane_b32 s36, v41, 2
+; GISEL-NEXT: v_readlane_b32 s35, v41, 1
+; GISEL-NEXT: v_readlane_b32 s34, v41, 0
; GISEL-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GISEL-NEXT: s_mov_b32 s32, s33
; GISEL-NEXT: s_or_saveexec_b64 s[4:5], -1
@@ -1121,22 +1121,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_return(i32 %i, ptr %fptr) {
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[4:5]
; GCN-NEXT: s_addk_i32 s32, 0x400
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
-; GCN-NEXT: v_writelane_b32 v40, s34, 2
-; GCN-NEXT: v_writelane_b32 v40, s35, 3
-; GCN-NEXT: v_writelane_b32 v40, s36, 4
-; GCN-NEXT: v_writelane_b32 v40, s37, 5
-; GCN-NEXT: v_writelane_b32 v40, s38, 6
-; GCN-NEXT: v_writelane_b32 v40, s39, 7
-; GCN-NEXT: v_writelane_b32 v40, s48, 8
-; GCN-NEXT: v_writelane_b32 v40, s49, 9
-; GCN-NEXT: v_writelane_b32 v40, s50, 10
-; GCN-NEXT: v_writelane_b32 v40, s51, 11
-; GCN-NEXT: v_writelane_b32 v40, s52, 12
-; GCN-NEXT: v_writelane_b32 v40, s53, 13
-; GCN-NEXT: v_writelane_b32 v40, s54, 14
-; GCN-NEXT: v_writelane_b32 v40, s55, 15
+; GCN-NEXT: v_writelane_b32 v40, s34, 0
+; GCN-NEXT: v_writelane_b32 v40, s35, 1
+; GCN-NEXT: v_writelane_b32 v40, s36, 2
+; GCN-NEXT: v_writelane_b32 v40, s37, 3
+; GCN-NEXT: v_writelane_b32 v40, s38, 4
+; GCN-NEXT: v_writelane_b32 v40, s39, 5
+; GCN-NEXT: v_writelane_b32 v40, s48, 6
+; GCN-NEXT: v_writelane_b32 v40, s49, 7
+; GCN-NEXT: v_writelane_b32 v40, s50, 8
+; GCN-NEXT: v_writelane_b32 v40, s51, 9
+; GCN-NEXT: v_writelane_b32 v40, s52, 10
+; GCN-NEXT: v_writelane_b32 v40, s53, 11
+; GCN-NEXT: v_writelane_b32 v40, s54, 12
+; GCN-NEXT: v_writelane_b32 v40, s55, 13
+; GCN-NEXT: v_writelane_b32 v40, s30, 14
+; GCN-NEXT: v_writelane_b32 v40, s31, 15
; GCN-NEXT: s_mov_b64 s[4:5], exec
; GCN-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_readfirstlane_b32 s8, v1
@@ -1152,22 +1152,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_return(i32 %i, ptr %fptr) {
; GCN-NEXT: ; %bb.2:
; GCN-NEXT: s_mov_b64 exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, v3
-; GCN-NEXT: v_readlane_b32 s55, v40, 15
-; GCN-NEXT: v_readlane_b32 s54, v40, 14
-; GCN-NEXT: v_readlane_b32 s53, v40, 13
-; GCN-NEXT: v_readlane_b32 s52, v40, 12
-; GCN-NEXT: v_readlane_b32 s51, v40, 11
-; GCN-NEXT: v_readlane_b32 s50, v40, 10
-; GCN-NEXT: v_readlane_b32 s49, v40, 9
-; GCN-NEXT: v_readlane_b32 s48, v40, 8
-; GCN-NEXT: v_readlane_b32 s39, v40, 7
-; GCN-NEXT: v_readlane_b32 s38, v40, 6
-; GCN-NEXT: v_readlane_b32 s37, v40, 5
-; GCN-NEXT: v_readlane_b32 s36, v40, 4
-; GCN-NEXT: v_readlane_b32 s35, v40, 3
-; GCN-NEXT: v_readlane_b32 s34, v40, 2
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
-; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s30, v40, 14
+; GCN-NEXT: v_readlane_b32 s31, v40, 15
+; GCN-NEXT: v_readlane_b32 s55, v40, 13
+; GCN-NEXT: v_readlane_b32 s54, v40, 12
+; GCN-NEXT: v_readlane_b32 s53, v40, 11
+; GCN-NEXT: v_readlane_b32 s52, v40, 10
+; GCN-NEXT: v_readlane_b32 s51, v40, 9
+; GCN-NEXT: v_readlane_b32 s50, v40, 8
+; GCN-NEXT: v_readlane_b32 s49, v40, 7
+; GCN-NEXT: v_readlane_b32 s48, v40, 6
+; GCN-NEXT: v_readlane_b32 s39, v40, 5
+; GCN-NEXT: v_readlane_b32 s38, v40, 4
+; GCN-NEXT: v_readlane_b32 s37, v40, 3
+; GCN-NEXT: v_readlane_b32 s36, v40, 2
+; GCN-NEXT: v_readlane_b32 s35, v40, 1
+; GCN-NEXT: v_readlane_b32 s34, v40, 0
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: s_or_saveexec_b64 s[4:5], -1
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -1185,22 +1185,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_return(i32 %i, ptr %fptr) {
; GISEL-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GISEL-NEXT: s_mov_b64 exec, s[4:5]
; GISEL-NEXT: s_addk_i32 s32, 0x400
-; GISEL-NEXT: v_writelane_b32 v40, s30, 0
-; GISEL-NEXT: v_writelane_b32 v40, s31, 1
-; GISEL-NEXT: v_writelane_b32 v40, s34, 2
-; GISEL-NEXT: v_writelane_b32 v40, s35, 3
-; GISEL-NEXT: v_writelane_b32 v40, s36, 4
-; GISEL-NEXT: v_writelane_b32 v40, s37, 5
-; GISEL-NEXT: v_writelane_b32 v40, s38, 6
-; GISEL-NEXT: v_writelane_b32 v40, s39, 7
-; GISEL-NEXT: v_writelane_b32 v40, s48, 8
-; GISEL-NEXT: v_writelane_b32 v40, s49, 9
-; GISEL-NEXT: v_writelane_b32 v40, s50, 10
-; GISEL-NEXT: v_writelane_b32 v40, s51, 11
-; GISEL-NEXT: v_writelane_b32 v40, s52, 12
-; GISEL-NEXT: v_writelane_b32 v40, s53, 13
-; GISEL-NEXT: v_writelane_b32 v40, s54, 14
-; GISEL-NEXT: v_writelane_b32 v40, s55, 15
+; GISEL-NEXT: v_writelane_b32 v40, s34, 0
+; GISEL-NEXT: v_writelane_b32 v40, s35, 1
+; GISEL-NEXT: v_writelane_b32 v40, s36, 2
+; GISEL-NEXT: v_writelane_b32 v40, s37, 3
+; GISEL-NEXT: v_writelane_b32 v40, s38, 4
+; GISEL-NEXT: v_writelane_b32 v40, s39, 5
+; GISEL-NEXT: v_writelane_b32 v40, s48, 6
+; GISEL-NEXT: v_writelane_b32 v40, s49, 7
+; GISEL-NEXT: v_writelane_b32 v40, s50, 8
+; GISEL-NEXT: v_writelane_b32 v40, s51, 9
+; GISEL-NEXT: v_writelane_b32 v40, s52, 10
+; GISEL-NEXT: v_writelane_b32 v40, s53, 11
+; GISEL-NEXT: v_writelane_b32 v40, s54, 12
+; GISEL-NEXT: v_writelane_b32 v40, s55, 13
+; GISEL-NEXT: v_writelane_b32 v40, s30, 14
+; GISEL-NEXT: v_writelane_b32 v40, s31, 15
; GISEL-NEXT: s_mov_b64 s[4:5], exec
; GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
; GISEL-NEXT: v_readfirstlane_b32 s8, v1
@@ -1216,22 +1216,22 @@ define i32 @test_indirect_call_vgpr_ptr_arg_and_return(i32 %i, ptr %fptr) {
; GISEL-NEXT: ; %bb.2:
; GISEL-NEXT: s_mov_b64 exec, s[4:5]
; GISEL-NEXT: v_mov_b32_e32 v0, v2
-; GISEL-NEXT: v_readlane_b32 s55, v40, 15
-; GISEL-NEXT: v_readlane_b32 s54, v40, 14
-; GISEL-NEXT: v_readlane_b32 s53, v40, 13
-; GISEL-NEXT: v_readlane_b32 s52, v40, 12
-; GISEL-NEXT: v_readlane_b32 s51, v40, 11
-; GISEL-NEXT: v_readlane_b32 s50, v40, 10
-; GISEL-NEXT: v_readlane_b32 s49, v40, 9
-; GISEL-NEXT: v_readlane_b32 s48, v40, 8
-; GISEL-NEXT: v_readlane_b32 s39, v40, 7
-; GISEL-NEXT: v_readlane_b32 s38, v40, 6
-; GISEL-NEXT: v_readlane_b32 s37, v40, 5
-; GISEL-NEXT: v_readlane_b32 s36, v40, 4
-; GISEL-NEXT: v_readlane_b32 s35, v40, 3
-; GISEL-NEXT: v_readlane_b32 s34, v40, 2
-; GISEL-NEXT: v_readlane_b32 s31, v40, 1
-; GISEL-NEXT: v_readlane_b32 s30, v40, 0
+; GISEL-NEXT: v_readlane_b32 s30, v40, 14
+; GISEL-NEXT: v_readlane_b32 s31, v40, 15
+; GISEL-NEXT: v_readlane_b32 s55, v40, 13
+; GISEL-NEXT: v_readlane_b32 s54, v40, 12
+; GISEL-NEXT: v_readlane_b32 s53, v40, 11
+; GISEL-NEXT: v_readlane_b32 s52, v40, 10
+; GISEL-NEXT: v_readlane_b32 s51, v40, 9
+; GISEL-NEXT: v_readlane_b32 s50, v40, 8
+; GISEL-NEXT: v_readlane_b32 s49, v40, 7
+; GISEL-NEXT: v_readlane_b32 s48, v40, 6
+; GISEL-NEXT: v_readlane_b32 s39, v40, 5
+; GISEL-NEXT: v_readlane_b32 s38, v40, 4
+; GISEL-NEXT: v_readlane_b32 s37, v40, 3
+; GISEL-NEXT: v_readlane_b32 s36, v40, 2
+; GISEL-NEXT: v_readlane_b32 s35, v40, 1
+; GISEL-NEXT: v_readlane_b32 s34, v40, 0
; GISEL-NEXT: s_mov_b32 s32, s33
; GISEL-NEXT: s_or_saveexec_b64 s[4:5], -1
; GISEL-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -1254,22 +1254,22 @@ define void @test_indirect_tail_call_vgpr_ptr(ptr %fptr) {
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[4:5]
; GCN-NEXT: s_addk_i32 s32, 0x400
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
-; GCN-NEXT: v_writelane_b32 v40, s34, 2
-; GCN-NEXT: v_writelane_b32 v40, s35, 3
-; GCN-NEXT: v_writelane_b32 v40, s36, 4
-; GCN-NEXT: v_writelane_b32 v40, s37, 5
-; GCN-NEXT: v_writelane_b32 v40, s38, 6
-; GCN-NEXT: v_writelane_b32 v40, s39, 7
-; GCN-NEXT: v_writelane_b32 v40, s48, 8
-; GCN-NEXT: v_writelane_b32 v40, s49, 9
-; GCN-NEXT: v_writelane_b32 v40, s50, 10
-; GCN-NEXT: v_writelane_b32 v40, s51, 11
-; GCN-NEXT: v_writelane_b32 v40, s52, 12
-; GCN-NEXT: v_writelane_b32 v40, s53, 13
-; GCN-NEXT: v_writelane_b32 v40, s54, 14
-; GCN-NEXT: v_writelane_b32 v40, s55, 15
+; GCN-NEXT: v_writelane_b32 v40, s34, 0
+; GCN-NEXT: v_writelane_b32 v40, s35, 1
+; GCN-NEXT: v_writelane_b32 v40, s36, 2
+; GCN-NEXT: v_writelane_b32 v40, s37, 3
+; GCN-NEXT: v_writelane_b32 v40, s38, 4
+; GCN-NEXT: v_writelane_b32 v40, s39, 5
+; GCN-NEXT: v_writelane_b32 v40, s48, 6
+; GCN-NEXT: v_writelane_b32 v40, s49, 7
+; GCN-NEXT: v_writelane_b32 v40, s50, 8
+; GCN-NEXT: v_writelane_b32 v40, s51, 9
+; GCN-NEXT: v_writelane_b32 v40, s52, 10
+; GCN-NEXT: v_writelane_b32 v40, s53, 11
+; GCN-NEXT: v_writelane_b32 v40, s54, 12
+; GCN-NEXT: v_writelane_b32 v40, s55, 13
+; GCN-NEXT: v_writelane_b32 v40, s30, 14
+; GCN-NEXT: v_writelane_b32 v40, s31, 15
; GCN-NEXT: s_mov_b64 s[4:5], exec
; GCN-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: v_readfirstlane_b32 s6, v0
@@ -1282,22 +1282,22 @@ define void @test_indirect_tail_call_vgpr_ptr(ptr %fptr) {
; GCN-NEXT: s_cbranch_execnz .LBB9_1
; GCN-NEXT: ; %bb.2:
; GCN-NEXT: s_mov_b64 exec, s[4:5]
-; GCN-NEXT: v_readlane_b32 s55, v40, 15
-; GCN-NEXT: v_readlane_b32 s54, v40, 14
-; GCN-NEXT: v_readlane_b32 s53, v40, 13
-; GCN-NEXT: v_readlane_b32 s52, v40, 12
-; GCN-NEXT: v_readlane_b32 s51, v40, 11
-; GCN-NEXT: v_readlane_b32 s50, v40, 10
-; GCN-NEXT: v_readlane_b32 s49, v40, 9
-; GCN-NEXT: v_readlane_b32 s48, v40, 8
-; GCN-NEXT: v_readlane_b32 s39, v40, 7
-; GCN-NEXT: v_readlane_b32 s38, v40, 6
-; GCN-NEXT: v_readlane_b32 s37, v40, 5
-; GCN-NEXT: v_readlane_b32 s36, v40, 4
-; GCN-NEXT: v_readlane_b32 s35, v40, 3
-; GCN-NEXT: v_readlane_b32 s34, v40, 2
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
-; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s30, v40, 14
+; GCN-NEXT: v_readlane_b32 s31, v40, 15
+; GCN-NEXT: v_readlane_b32 s55, v40, 13
+; GCN-NEXT: v_readlane_b32 s54, v40, 12
+; GCN-NEXT: v_readlane_b32 s53, v40, 11
+; GCN-NEXT: v_readlane_b32 s52, v40, 10
+; GCN-NEXT: v_readlane_b32 s51, v40, 9
+; GCN-NEXT: v_readlane_b32 s50, v40, 8
+; GCN-NEXT: v_readlane_b32 s49, v40, 7
+; GCN-NEXT: v_readlane_b32 s48, v40, 6
+; GCN-NEXT: v_readlane_b32 s39, v40, 5
+; GCN-NEXT: v_readlane_b32 s38, v40, 4
+; GCN-NEXT: v_readlane_b32 s37, v40, 3
+; GCN-NEXT: v_readlane_b32 s36, v40, 2
+; GCN-NEXT: v_readlane_b32 s35, v40, 1
+; GCN-NEXT: v_readlane_b32 s34, v40, 0
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: s_or_saveexec_b64 s[4:5], -1
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -1315,22 +1315,22 @@ define void @test_indirect_tail_call_vgpr_ptr(ptr %fptr) {
; GISEL-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GISEL-NEXT: s_mov_b64 exec, s[4:5]
; GISEL-NEXT: s_addk_i32 s32, 0x400
-; GISEL-NEXT: v_writelane_b32 v40, s30, 0
-; GISEL-NEXT: v_writelane_b32 v40, s31, 1
-; GISEL-NEXT: v_writelane_b32 v40, s34, 2
-; GISEL-NEXT: v_writelane_b32 v40, s35, 3
-; GISEL-NEXT: v_writelane_b32 v40, s36, 4
-; GISEL-NEXT: v_writelane_b32 v40, s37, 5
-; GISEL-NEXT: v_writelane_b32 v40, s38, 6
-; GISEL-NEXT: v_writelane_b32 v40, s39, 7
-; GISEL-NEXT: v_writelane_b32 v40, s48, 8
-; GISEL-NEXT: v_writelane_b32 v40, s49, 9
-; GISEL-NEXT: v_writelane_b32 v40, s50, 10
-; GISEL-NEXT: v_writelane_b32 v40, s51, 11
-; GISEL-NEXT: v_writelane_b32 v40, s52, 12
-; GISEL-NEXT: v_writelane_b32 v40, s53, 13
-; GISEL-NEXT: v_writelane_b32 v40, s54, 14
-; GISEL-NEXT: v_writelane_b32 v40, s55, 15
+; GISEL-NEXT: v_writelane_b32 v40, s34, 0
+; GISEL-NEXT: v_writelane_b32 v40, s35, 1
+; GISEL-NEXT: v_writelane_b32 v40, s36, 2
+; GISEL-NEXT: v_writelane_b32 v40, s37, 3
+; GISEL-NEXT: v_writelane_b32 v40, s38, 4
+; GISEL-NEXT: v_writelane_b32 v40, s39, 5
+; GISEL-NEXT: v_writelane_b32 v40, s48, 6
+; GISEL-NEXT: v_writelane_b32 v40, s49, 7
+; GISEL-NEXT: v_writelane_b32 v40, s50, 8
+; GISEL-NEXT: v_writelane_b32 v40, s51, 9
+; GISEL-NEXT: v_writelane_b32 v40, s52, 10
+; GISEL-NEXT: v_writelane_b32 v40, s53, 11
+; GISEL-NEXT: v_writelane_b32 v40, s54, 12
+; GISEL-NEXT: v_writelane_b32 v40, s55, 13
+; GISEL-NEXT: v_writelane_b32 v40, s30, 14
+; GISEL-NEXT: v_writelane_b32 v40, s31, 15
; GISEL-NEXT: s_mov_b64 s[4:5], exec
; GISEL-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
; GISEL-NEXT: v_readfirstlane_b32 s6, v0
@@ -1343,22 +1343,22 @@ define void @test_indirect_tail_call_vgpr_ptr(ptr %fptr) {
; GISEL-NEXT: s_cbranch_execnz .LBB9_1
; GISEL-NEXT: ; %bb.2:
; GISEL-NEXT: s_mov_b64 exec, s[4:5]
-; GISEL-NEXT: v_readlane_b32 s55, v40, 15
-; GISEL-NEXT: v_readlane_b32 s54, v40, 14
-; GISEL-NEXT: v_readlane_b32 s53, v40, 13
-; GISEL-NEXT: v_readlane_b32 s52, v40, 12
-; GISEL-NEXT: v_readlane_b32 s51, v40, 11
-; GISEL-NEXT: v_readlane_b32 s50, v40, 10
-; GISEL-NEXT: v_readlane_b32 s49, v40, 9
-; GISEL-NEXT: v_readlane_b32 s48, v40, 8
-; GISEL-NEXT: v_readlane_b32 s39, v40, 7
-; GISEL-NEXT: v_readlane_b32 s38, v40, 6
-; GISEL-NEXT: v_readlane_b32 s37, v40, 5
-; GISEL-NEXT: v_readlane_b32 s36, v40, 4
-; GISEL-NEXT: v_readlane_b32 s35, v40, 3
-; GISEL-NEXT: v_readlane_b32 s34, v40, 2
-; GISEL-NEXT: v_readlane_b32 s31, v40, 1
-; GISEL-NEXT: v_readlane_b32 s30, v40, 0
+; GISEL-NEXT: v_readlane_b32 s30, v40, 14
+; GISEL-NEXT: v_readlane_b32 s31, v40, 15
+; GISEL-NEXT: v_readlane_b32 s55, v40, 13
+; GISEL-NEXT: v_readlane_b32 s54, v40, 12
+; GISEL-NEXT: v_readlane_b32 s53, v40, 11
+; GISEL-NEXT: v_readlane_b32 s52, v40, 10
+; GISEL-NEXT: v_readlane_b32 s51, v40, 9
+; GISEL-NEXT: v_readlane_b32 s50, v40, 8
+; GISEL-NEXT: v_readlane_b32 s49, v40, 7
+; GISEL-NEXT: v_readlane_b32 s48, v40, 6
+; GISEL-NEXT: v_readlane_b32 s39, v40, 5
+; GISEL-NEXT: v_readlane_b32 s38, v40, 4
+; GISEL-NEXT: v_readlane_b32 s37, v40, 3
+; GISEL-NEXT: v_readlane_b32 s36, v40, 2
+; GISEL-NEXT: v_readlane_b32 s35, v40, 1
+; GISEL-NEXT: v_readlane_b32 s34, v40, 0
; GISEL-NEXT: s_mov_b32 s32, s33
; GISEL-NEXT: s_or_saveexec_b64 s[4:5], -1
; GISEL-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
index c3f391786f878..fcc43ffd0140e 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
@@ -35,8 +35,8 @@ define void @f0() {
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s31, v4, 1
; GFX11-NEXT: v_readlane_b32 s30, v4, 0
+; GFX11-NEXT: v_readlane_b32 s31, v4, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v4, off, s33 ; 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
index df784a6e00cfc..19869e85ec9d9 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
@@ -7,13 +7,13 @@ define fastcc i32 @foo() #0 {
; CHECK-LABEL: name: foo
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: successors: %bb.1(0x80000000)
- ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr30, $sgpr31, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
+ ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: S_WAITCNT 0
; CHECK-NEXT: $sgpr16 = S_MOV_B32 $sgpr33
; CHECK-NEXT: $sgpr33 = S_MOV_B32 $sgpr32
; CHECK-NEXT: $sgpr17 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
- ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
+ ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)
; CHECK-NEXT: $exec_lo = S_MOV_B32 killed $sgpr17
; CHECK-NEXT: $sgpr32 = frame-setup S_ADDK_I32 $sgpr32, 512, implicit-def dead $scc
; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr16, 2, undef $vgpr40
@@ -26,8 +26,8 @@ define fastcc i32 @foo() #0 {
; CHECK-NEXT: BUFFER_GL1_INV implicit $exec
; CHECK-NEXT: BUFFER_GL0_INV implicit $exec
; CHECK-NEXT: renamable $sgpr16_sgpr17 = S_LOAD_DWORDX2_IMM killed renamable $sgpr16_sgpr17, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
- ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr30, 0, $vgpr40
- ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr31, 1, $vgpr40
+ ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr30, 0, $vgpr40, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
+ ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr31, 1, $vgpr40, implicit $sgpr30_sgpr31
; CHECK-NEXT: S_WAITCNT 49279
; CHECK-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr16_sgpr17, @bar, csr_amdgpu, implicit killed $sgpr4_sgpr5, implicit killed $sgpr6_sgpr7, implicit killed $sgpr8_sgpr9, implicit killed $sgpr10_sgpr11, implicit killed $sgpr12, implicit killed $sgpr13, implicit killed $sgpr14, implicit killed $sgpr15, implicit killed $vgpr31, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $vcc_lo = S_MOV_B32 $exec_lo
@@ -39,12 +39,12 @@ define fastcc i32 @foo() #0 {
; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.DummyReturnBlock:
+ ; CHECK-NEXT: $sgpr30 = V_READLANE_B32 $vgpr40, 0, implicit-def $sgpr30_sgpr31
; CHECK-NEXT: $sgpr31 = V_READLANE_B32 $vgpr40, 1
- ; CHECK-NEXT: $sgpr30 = V_READLANE_B32 $vgpr40, 0
; CHECK-NEXT: $sgpr32 = S_MOV_B32 $sgpr33
; CHECK-NEXT: $sgpr4 = V_READLANE_B32 $vgpr40, 2
; CHECK-NEXT: $sgpr5 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
- ; CHECK-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5)
+ ; CHECK-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5)
; CHECK-NEXT: $exec_lo = S_MOV_B32 killed $sgpr5
; CHECK-NEXT: $sgpr33 = S_MOV_B32 killed $sgpr4
; CHECK-NEXT: S_WAITCNT 16240
diff --git a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
index 17581bcb61e99..8c2c16ccdc2a0 100644
--- a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
@@ -37,26 +37,26 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX7-NEXT: s_add_i32 s6, s32, 0x101100
; GFX7-NEXT: buffer_store_dword v23, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[4:5]
-; GFX7-NEXT: v_writelane_b32 v23, s30, 0
-; GFX7-NEXT: v_writelane_b32 v23, s31, 1
-; GFX7-NEXT: v_writelane_b32 v23, s33, 2
-; GFX7-NEXT: v_writelane_b32 v23, s34, 3
-; GFX7-NEXT: v_writelane_b32 v23, s35, 4
-; GFX7-NEXT: v_writelane_b32 v23, s36, 5
-; GFX7-NEXT: v_writelane_b32 v23, s37, 6
-; GFX7-NEXT: v_writelane_b32 v23, s38, 7
-; GFX7-NEXT: v_writelane_b32 v23, s39, 8
-; GFX7-NEXT: v_writelane_b32 v23, s48, 9
-; GFX7-NEXT: v_writelane_b32 v23, s49, 10
-; GFX7-NEXT: v_writelane_b32 v23, s50, 11
-; GFX7-NEXT: v_writelane_b32 v23, s51, 12
-; GFX7-NEXT: v_writelane_b32 v23, s52, 13
-; GFX7-NEXT: v_writelane_b32 v23, s53, 14
+; GFX7-NEXT: v_writelane_b32 v23, s33, 0
+; GFX7-NEXT: v_writelane_b32 v23, s34, 1
+; GFX7-NEXT: v_writelane_b32 v23, s35, 2
+; GFX7-NEXT: v_writelane_b32 v23, s36, 3
+; GFX7-NEXT: v_writelane_b32 v23, s37, 4
+; GFX7-NEXT: v_writelane_b32 v23, s38, 5
+; GFX7-NEXT: v_writelane_b32 v23, s39, 6
+; GFX7-NEXT: v_writelane_b32 v23, s48, 7
+; GFX7-NEXT: v_writelane_b32 v23, s49, 8
+; GFX7-NEXT: v_writelane_b32 v23, s50, 9
+; GFX7-NEXT: v_writelane_b32 v23, s51, 10
+; GFX7-NEXT: v_writelane_b32 v23, s52, 11
+; GFX7-NEXT: v_writelane_b32 v23, s53, 12
+; GFX7-NEXT: v_writelane_b32 v23, s54, 13
+; GFX7-NEXT: v_writelane_b32 v23, s55, 14
; GFX7-NEXT: v_lshr_b32_e64 v0, s32, 6
-; GFX7-NEXT: v_writelane_b32 v23, s54, 15
+; GFX7-NEXT: v_writelane_b32 v23, s30, 15
; GFX7-NEXT: v_add_i32_e32 v0, vcc, 64, v0
; GFX7-NEXT: s_and_b64 s[4:5], 0, exec
-; GFX7-NEXT: v_writelane_b32 v23, s55, 16
+; GFX7-NEXT: v_writelane_b32 v23, s31, 16
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use alloca0 v0
; GFX7-NEXT: ;;#ASMEND
@@ -73,23 +73,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc
; GFX7-NEXT: ;;#ASMEND
-; GFX7-NEXT: v_readlane_b32 s55, v23, 16
-; GFX7-NEXT: v_readlane_b32 s54, v23, 15
-; GFX7-NEXT: v_readlane_b32 s53, v23, 14
-; GFX7-NEXT: v_readlane_b32 s52, v23, 13
-; GFX7-NEXT: v_readlane_b32 s51, v23, 12
-; GFX7-NEXT: v_readlane_b32 s50, v23, 11
-; GFX7-NEXT: v_readlane_b32 s49, v23, 10
-; GFX7-NEXT: v_readlane_b32 s48, v23, 9
-; GFX7-NEXT: v_readlane_b32 s39, v23, 8
-; GFX7-NEXT: v_readlane_b32 s38, v23, 7
-; GFX7-NEXT: v_readlane_b32 s37, v23, 6
-; GFX7-NEXT: v_readlane_b32 s36, v23, 5
-; GFX7-NEXT: v_readlane_b32 s35, v23, 4
-; GFX7-NEXT: v_readlane_b32 s34, v23, 3
-; GFX7-NEXT: v_readlane_b32 s33, v23, 2
-; GFX7-NEXT: v_readlane_b32 s31, v23, 1
-; GFX7-NEXT: v_readlane_b32 s30, v23, 0
+; GFX7-NEXT: v_readlane_b32 s30, v23, 15
+; GFX7-NEXT: v_readlane_b32 s31, v23, 16
+; GFX7-NEXT: v_readlane_b32 s55, v23, 14
+; GFX7-NEXT: v_readlane_b32 s54, v23, 13
+; GFX7-NEXT: v_readlane_b32 s53, v23, 12
+; GFX7-NEXT: v_readlane_b32 s52, v23, 11
+; GFX7-NEXT: v_readlane_b32 s51, v23, 10
+; GFX7-NEXT: v_readlane_b32 s50, v23, 9
+; GFX7-NEXT: v_readlane_b32 s49, v23, 8
+; GFX7-NEXT: v_readlane_b32 s48, v23, 7
+; GFX7-NEXT: v_readlane_b32 s39, v23, 6
+; GFX7-NEXT: v_readlane_b32 s38, v23, 5
+; GFX7-NEXT: v_readlane_b32 s37, v23, 4
+; GFX7-NEXT: v_readlane_b32 s36, v23, 3
+; GFX7-NEXT: v_readlane_b32 s35, v23, 2
+; GFX7-NEXT: v_readlane_b32 s34, v23, 1
+; GFX7-NEXT: v_readlane_b32 s33, v23, 0
; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX7-NEXT: s_add_i32 s6, s32, 0x101100
; GFX7-NEXT: buffer_load_dword v23, off, s[0:3], s6 ; 4-byte Folded Reload
@@ -104,26 +104,26 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX8-NEXT: s_add_i32 s6, s32, 0x101100
; GFX8-NEXT: buffer_store_dword v23, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
-; GFX8-NEXT: v_writelane_b32 v23, s30, 0
-; GFX8-NEXT: v_writelane_b32 v23, s31, 1
-; GFX8-NEXT: v_writelane_b32 v23, s33, 2
-; GFX8-NEXT: v_writelane_b32 v23, s34, 3
-; GFX8-NEXT: v_writelane_b32 v23, s35, 4
-; GFX8-NEXT: v_writelane_b32 v23, s36, 5
-; GFX8-NEXT: v_writelane_b32 v23, s37, 6
-; GFX8-NEXT: v_writelane_b32 v23, s38, 7
-; GFX8-NEXT: v_writelane_b32 v23, s39, 8
-; GFX8-NEXT: v_writelane_b32 v23, s48, 9
-; GFX8-NEXT: v_writelane_b32 v23, s49, 10
-; GFX8-NEXT: v_writelane_b32 v23, s50, 11
-; GFX8-NEXT: v_writelane_b32 v23, s51, 12
-; GFX8-NEXT: v_writelane_b32 v23, s52, 13
-; GFX8-NEXT: v_writelane_b32 v23, s53, 14
+; GFX8-NEXT: v_writelane_b32 v23, s33, 0
+; GFX8-NEXT: v_writelane_b32 v23, s34, 1
+; GFX8-NEXT: v_writelane_b32 v23, s35, 2
+; GFX8-NEXT: v_writelane_b32 v23, s36, 3
+; GFX8-NEXT: v_writelane_b32 v23, s37, 4
+; GFX8-NEXT: v_writelane_b32 v23, s38, 5
+; GFX8-NEXT: v_writelane_b32 v23, s39, 6
+; GFX8-NEXT: v_writelane_b32 v23, s48, 7
+; GFX8-NEXT: v_writelane_b32 v23, s49, 8
+; GFX8-NEXT: v_writelane_b32 v23, s50, 9
+; GFX8-NEXT: v_writelane_b32 v23, s51, 10
+; GFX8-NEXT: v_writelane_b32 v23, s52, 11
+; GFX8-NEXT: v_writelane_b32 v23, s53, 12
+; GFX8-NEXT: v_writelane_b32 v23, s54, 13
+; GFX8-NEXT: v_writelane_b32 v23, s55, 14
; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32
-; GFX8-NEXT: v_writelane_b32 v23, s54, 15
+; GFX8-NEXT: v_writelane_b32 v23, s30, 15
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 64, v0
; GFX8-NEXT: s_and_b64 s[4:5], 0, exec
-; GFX8-NEXT: v_writelane_b32 v23, s55, 16
+; GFX8-NEXT: v_writelane_b32 v23, s31, 16
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use alloca0 v0
; GFX8-NEXT: ;;#ASMEND
@@ -141,23 +141,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc
; GFX8-NEXT: ;;#ASMEND
-; GFX8-NEXT: v_readlane_b32 s55, v23, 16
-; GFX8-NEXT: v_readlane_b32 s54, v23, 15
-; GFX8-NEXT: v_readlane_b32 s53, v23, 14
-; GFX8-NEXT: v_readlane_b32 s52, v23, 13
-; GFX8-NEXT: v_readlane_b32 s51, v23, 12
-; GFX8-NEXT: v_readlane_b32 s50, v23, 11
-; GFX8-NEXT: v_readlane_b32 s49, v23, 10
-; GFX8-NEXT: v_readlane_b32 s48, v23, 9
-; GFX8-NEXT: v_readlane_b32 s39, v23, 8
-; GFX8-NEXT: v_readlane_b32 s38, v23, 7
-; GFX8-NEXT: v_readlane_b32 s37, v23, 6
-; GFX8-NEXT: v_readlane_b32 s36, v23, 5
-; GFX8-NEXT: v_readlane_b32 s35, v23, 4
-; GFX8-NEXT: v_readlane_b32 s34, v23, 3
-; GFX8-NEXT: v_readlane_b32 s33, v23, 2
-; GFX8-NEXT: v_readlane_b32 s31, v23, 1
-; GFX8-NEXT: v_readlane_b32 s30, v23, 0
+; GFX8-NEXT: v_readlane_b32 s30, v23, 15
+; GFX8-NEXT: v_readlane_b32 s31, v23, 16
+; GFX8-NEXT: v_readlane_b32 s55, v23, 14
+; GFX8-NEXT: v_readlane_b32 s54, v23, 13
+; GFX8-NEXT: v_readlane_b32 s53, v23, 12
+; GFX8-NEXT: v_readlane_b32 s52, v23, 11
+; GFX8-NEXT: v_readlane_b32 s51, v23, 10
+; GFX8-NEXT: v_readlane_b32 s50, v23, 9
+; GFX8-NEXT: v_readlane_b32 s49, v23, 8
+; GFX8-NEXT: v_readlane_b32 s48, v23, 7
+; GFX8-NEXT: v_readlane_b32 s39, v23, 6
+; GFX8-NEXT: v_readlane_b32 s38, v23, 5
+; GFX8-NEXT: v_readlane_b32 s37, v23, 4
+; GFX8-NEXT: v_readlane_b32 s36, v23, 3
+; GFX8-NEXT: v_readlane_b32 s35, v23, 2
+; GFX8-NEXT: v_readlane_b32 s34, v23, 1
+; GFX8-NEXT: v_readlane_b32 s33, v23, 0
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: s_add_i32 s6, s32, 0x101100
; GFX8-NEXT: buffer_load_dword v23, off, s[0:3], s6 ; 4-byte Folded Reload
@@ -172,26 +172,26 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX900-NEXT: s_add_i32 s6, s32, 0x101100
; GFX900-NEXT: buffer_store_dword v23, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
-; GFX900-NEXT: v_writelane_b32 v23, s30, 0
-; GFX900-NEXT: v_writelane_b32 v23, s31, 1
-; GFX900-NEXT: v_writelane_b32 v23, s33, 2
-; GFX900-NEXT: v_writelane_b32 v23, s34, 3
-; GFX900-NEXT: v_writelane_b32 v23, s35, 4
-; GFX900-NEXT: v_writelane_b32 v23, s36, 5
-; GFX900-NEXT: v_writelane_b32 v23, s37, 6
-; GFX900-NEXT: v_writelane_b32 v23, s38, 7
-; GFX900-NEXT: v_writelane_b32 v23, s39, 8
-; GFX900-NEXT: v_writelane_b32 v23, s48, 9
-; GFX900-NEXT: v_writelane_b32 v23, s49, 10
-; GFX900-NEXT: v_writelane_b32 v23, s50, 11
-; GFX900-NEXT: v_writelane_b32 v23, s51, 12
-; GFX900-NEXT: v_writelane_b32 v23, s52, 13
-; GFX900-NEXT: v_writelane_b32 v23, s53, 14
+; GFX900-NEXT: v_writelane_b32 v23, s33, 0
+; GFX900-NEXT: v_writelane_b32 v23, s34, 1
+; GFX900-NEXT: v_writelane_b32 v23, s35, 2
+; GFX900-NEXT: v_writelane_b32 v23, s36, 3
+; GFX900-NEXT: v_writelane_b32 v23, s37, 4
+; GFX900-NEXT: v_writelane_b32 v23, s38, 5
+; GFX900-NEXT: v_writelane_b32 v23, s39, 6
+; GFX900-NEXT: v_writelane_b32 v23, s48, 7
+; GFX900-NEXT: v_writelane_b32 v23, s49, 8
+; GFX900-NEXT: v_writelane_b32 v23, s50, 9
+; GFX900-NEXT: v_writelane_b32 v23, s51, 10
+; GFX900-NEXT: v_writelane_b32 v23, s52, 11
+; GFX900-NEXT: v_writelane_b32 v23, s53, 12
+; GFX900-NEXT: v_writelane_b32 v23, s54, 13
+; GFX900-NEXT: v_writelane_b32 v23, s55, 14
; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32
-; GFX900-NEXT: v_writelane_b32 v23, s54, 15
+; GFX900-NEXT: v_writelane_b32 v23, s30, 15
; GFX900-NEXT: v_add_u32_e32 v0, 64, v0
; GFX900-NEXT: s_and_b64 s[4:5], 0, exec
-; GFX900-NEXT: v_writelane_b32 v23, s55, 16
+; GFX900-NEXT: v_writelane_b32 v23, s31, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use alloca0 v0
; GFX900-NEXT: ;;#ASMEND
@@ -208,23 +208,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_readlane_b32 s55, v23, 16
-; GFX900-NEXT: v_readlane_b32 s54, v23, 15
-; GFX900-NEXT: v_readlane_b32 s53, v23, 14
-; GFX900-NEXT: v_readlane_b32 s52, v23, 13
-; GFX900-NEXT: v_readlane_b32 s51, v23, 12
-; GFX900-NEXT: v_readlane_b32 s50, v23, 11
-; GFX900-NEXT: v_readlane_b32 s49, v23, 10
-; GFX900-NEXT: v_readlane_b32 s48, v23, 9
-; GFX900-NEXT: v_readlane_b32 s39, v23, 8
-; GFX900-NEXT: v_readlane_b32 s38, v23, 7
-; GFX900-NEXT: v_readlane_b32 s37, v23, 6
-; GFX900-NEXT: v_readlane_b32 s36, v23, 5
-; GFX900-NEXT: v_readlane_b32 s35, v23, 4
-; GFX900-NEXT: v_readlane_b32 s34, v23, 3
-; GFX900-NEXT: v_readlane_b32 s33, v23, 2
-; GFX900-NEXT: v_readlane_b32 s31, v23, 1
-; GFX900-NEXT: v_readlane_b32 s30, v23, 0
+; GFX900-NEXT: v_readlane_b32 s30, v23, 15
+; GFX900-NEXT: v_readlane_b32 s31, v23, 16
+; GFX900-NEXT: v_readlane_b32 s55, v23, 14
+; GFX900-NEXT: v_readlane_b32 s54, v23, 13
+; GFX900-NEXT: v_readlane_b32 s53, v23, 12
+; GFX900-NEXT: v_readlane_b32 s52, v23, 11
+; GFX900-NEXT: v_readlane_b32 s51, v23, 10
+; GFX900-NEXT: v_readlane_b32 s50, v23, 9
+; GFX900-NEXT: v_readlane_b32 s49, v23, 8
+; GFX900-NEXT: v_readlane_b32 s48, v23, 7
+; GFX900-NEXT: v_readlane_b32 s39, v23, 6
+; GFX900-NEXT: v_readlane_b32 s38, v23, 5
+; GFX900-NEXT: v_readlane_b32 s37, v23, 4
+; GFX900-NEXT: v_readlane_b32 s36, v23, 3
+; GFX900-NEXT: v_readlane_b32 s35, v23, 2
+; GFX900-NEXT: v_readlane_b32 s34, v23, 1
+; GFX900-NEXT: v_readlane_b32 s33, v23, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: s_add_i32 s6, s32, 0x101100
; GFX900-NEXT: buffer_load_dword v23, off, s[0:3], s6 ; 4-byte Folded Reload
@@ -239,26 +239,26 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX942-NEXT: s_add_i32 s2, s32, 0x4044
; GFX942-NEXT: scratch_store_dword off, v23, s2 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
-; GFX942-NEXT: v_writelane_b32 v23, s30, 0
-; GFX942-NEXT: v_writelane_b32 v23, s31, 1
-; GFX942-NEXT: v_writelane_b32 v23, s33, 2
-; GFX942-NEXT: v_writelane_b32 v23, s34, 3
-; GFX942-NEXT: v_writelane_b32 v23, s35, 4
-; GFX942-NEXT: v_writelane_b32 v23, s36, 5
-; GFX942-NEXT: v_writelane_b32 v23, s37, 6
-; GFX942-NEXT: v_writelane_b32 v23, s38, 7
-; GFX942-NEXT: v_writelane_b32 v23, s39, 8
-; GFX942-NEXT: v_writelane_b32 v23, s48, 9
-; GFX942-NEXT: v_writelane_b32 v23, s49, 10
-; GFX942-NEXT: v_writelane_b32 v23, s50, 11
-; GFX942-NEXT: v_writelane_b32 v23, s51, 12
-; GFX942-NEXT: v_writelane_b32 v23, s52, 13
-; GFX942-NEXT: v_writelane_b32 v23, s53, 14
+; GFX942-NEXT: v_writelane_b32 v23, s33, 0
+; GFX942-NEXT: v_writelane_b32 v23, s34, 1
+; GFX942-NEXT: v_writelane_b32 v23, s35, 2
+; GFX942-NEXT: v_writelane_b32 v23, s36, 3
+; GFX942-NEXT: v_writelane_b32 v23, s37, 4
+; GFX942-NEXT: v_writelane_b32 v23, s38, 5
+; GFX942-NEXT: v_writelane_b32 v23, s39, 6
+; GFX942-NEXT: v_writelane_b32 v23, s48, 7
+; GFX942-NEXT: v_writelane_b32 v23, s49, 8
+; GFX942-NEXT: v_writelane_b32 v23, s50, 9
+; GFX942-NEXT: v_writelane_b32 v23, s51, 10
+; GFX942-NEXT: v_writelane_b32 v23, s52, 11
+; GFX942-NEXT: v_writelane_b32 v23, s53, 12
+; GFX942-NEXT: v_writelane_b32 v23, s54, 13
+; GFX942-NEXT: v_writelane_b32 v23, s55, 14
; GFX942-NEXT: s_add_i32 s0, s32, 64
-; GFX942-NEXT: v_writelane_b32 v23, s54, 15
+; GFX942-NEXT: v_writelane_b32 v23, s30, 15
; GFX942-NEXT: v_mov_b32_e32 v0, s0
; GFX942-NEXT: s_and_b64 s[60:61], 0, exec
-; GFX942-NEXT: v_writelane_b32 v23, s55, 16
+; GFX942-NEXT: v_writelane_b32 v23, s31, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use alloca0 v0
; GFX942-NEXT: ;;#ASMEND
@@ -273,23 +273,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_readlane_b32 s55, v23, 16
-; GFX942-NEXT: v_readlane_b32 s54, v23, 15
-; GFX942-NEXT: v_readlane_b32 s53, v23, 14
-; GFX942-NEXT: v_readlane_b32 s52, v23, 13
-; GFX942-NEXT: v_readlane_b32 s51, v23, 12
-; GFX942-NEXT: v_readlane_b32 s50, v23, 11
-; GFX942-NEXT: v_readlane_b32 s49, v23, 10
-; GFX942-NEXT: v_readlane_b32 s48, v23, 9
-; GFX942-NEXT: v_readlane_b32 s39, v23, 8
-; GFX942-NEXT: v_readlane_b32 s38, v23, 7
-; GFX942-NEXT: v_readlane_b32 s37, v23, 6
-; GFX942-NEXT: v_readlane_b32 s36, v23, 5
-; GFX942-NEXT: v_readlane_b32 s35, v23, 4
-; GFX942-NEXT: v_readlane_b32 s34, v23, 3
-; GFX942-NEXT: v_readlane_b32 s33, v23, 2
-; GFX942-NEXT: v_readlane_b32 s31, v23, 1
-; GFX942-NEXT: v_readlane_b32 s30, v23, 0
+; GFX942-NEXT: v_readlane_b32 s30, v23, 15
+; GFX942-NEXT: v_readlane_b32 s31, v23, 16
+; GFX942-NEXT: v_readlane_b32 s55, v23, 14
+; GFX942-NEXT: v_readlane_b32 s54, v23, 13
+; GFX942-NEXT: v_readlane_b32 s53, v23, 12
+; GFX942-NEXT: v_readlane_b32 s52, v23, 11
+; GFX942-NEXT: v_readlane_b32 s51, v23, 10
+; GFX942-NEXT: v_readlane_b32 s50, v23, 9
+; GFX942-NEXT: v_readlane_b32 s49, v23, 8
+; GFX942-NEXT: v_readlane_b32 s48, v23, 7
+; GFX942-NEXT: v_readlane_b32 s39, v23, 6
+; GFX942-NEXT: v_readlane_b32 s38, v23, 5
+; GFX942-NEXT: v_readlane_b32 s37, v23, 4
+; GFX942-NEXT: v_readlane_b32 s36, v23, 3
+; GFX942-NEXT: v_readlane_b32 s35, v23, 2
+; GFX942-NEXT: v_readlane_b32 s34, v23, 1
+; GFX942-NEXT: v_readlane_b32 s33, v23, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: s_add_i32 s2, s32, 0x4044
; GFX942-NEXT: scratch_load_dword v23, off, s2 ; 4-byte Folded Reload
@@ -305,29 +305,29 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX10_1-NEXT: buffer_store_dword v23, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_1-NEXT: v_writelane_b32 v23, s30, 0
+; GFX10_1-NEXT: v_writelane_b32 v23, s33, 0
; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo
-; GFX10_1-NEXT: v_writelane_b32 v23, s31, 1
+; GFX10_1-NEXT: v_writelane_b32 v23, s34, 1
; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; use alloca0 v0
; GFX10_1-NEXT: ;;#ASMEND
-; GFX10_1-NEXT: v_writelane_b32 v23, s33, 2
-; GFX10_1-NEXT: v_writelane_b32 v23, s34, 3
-; GFX10_1-NEXT: v_writelane_b32 v23, s35, 4
-; GFX10_1-NEXT: v_writelane_b32 v23, s36, 5
-; GFX10_1-NEXT: v_writelane_b32 v23, s37, 6
-; GFX10_1-NEXT: v_writelane_b32 v23, s38, 7
-; GFX10_1-NEXT: v_writelane_b32 v23, s39, 8
-; GFX10_1-NEXT: v_writelane_b32 v23, s48, 9
-; GFX10_1-NEXT: v_writelane_b32 v23, s49, 10
-; GFX10_1-NEXT: v_writelane_b32 v23, s50, 11
-; GFX10_1-NEXT: v_writelane_b32 v23, s51, 12
-; GFX10_1-NEXT: v_writelane_b32 v23, s52, 13
-; GFX10_1-NEXT: v_writelane_b32 v23, s53, 14
-; GFX10_1-NEXT: v_writelane_b32 v23, s54, 15
-; GFX10_1-NEXT: v_writelane_b32 v23, s55, 16
+; GFX10_1-NEXT: v_writelane_b32 v23, s35, 2
+; GFX10_1-NEXT: v_writelane_b32 v23, s36, 3
+; GFX10_1-NEXT: v_writelane_b32 v23, s37, 4
+; GFX10_1-NEXT: v_writelane_b32 v23, s38, 5
+; GFX10_1-NEXT: v_writelane_b32 v23, s39, 6
+; GFX10_1-NEXT: v_writelane_b32 v23, s48, 7
+; GFX10_1-NEXT: v_writelane_b32 v23, s49, 8
+; GFX10_1-NEXT: v_writelane_b32 v23, s50, 9
+; GFX10_1-NEXT: v_writelane_b32 v23, s51, 10
+; GFX10_1-NEXT: v_writelane_b32 v23, s52, 11
+; GFX10_1-NEXT: v_writelane_b32 v23, s53, 12
+; GFX10_1-NEXT: v_writelane_b32 v23, s54, 13
+; GFX10_1-NEXT: v_writelane_b32 v23, s55, 14
+; GFX10_1-NEXT: v_writelane_b32 v23, s30, 15
+; GFX10_1-NEXT: v_writelane_b32 v23, s31, 16
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc
; GFX10_1-NEXT: ;;#ASMEND
@@ -338,23 +338,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc
; GFX10_1-NEXT: ;;#ASMEND
-; GFX10_1-NEXT: v_readlane_b32 s55, v23, 16
-; GFX10_1-NEXT: v_readlane_b32 s54, v23, 15
-; GFX10_1-NEXT: v_readlane_b32 s53, v23, 14
-; GFX10_1-NEXT: v_readlane_b32 s52, v23, 13
-; GFX10_1-NEXT: v_readlane_b32 s51, v23, 12
-; GFX10_1-NEXT: v_readlane_b32 s50, v23, 11
-; GFX10_1-NEXT: v_readlane_b32 s49, v23, 10
-; GFX10_1-NEXT: v_readlane_b32 s48, v23, 9
-; GFX10_1-NEXT: v_readlane_b32 s39, v23, 8
-; GFX10_1-NEXT: v_readlane_b32 s38, v23, 7
-; GFX10_1-NEXT: v_readlane_b32 s37, v23, 6
-; GFX10_1-NEXT: v_readlane_b32 s36, v23, 5
-; GFX10_1-NEXT: v_readlane_b32 s35, v23, 4
-; GFX10_1-NEXT: v_readlane_b32 s34, v23, 3
-; GFX10_1-NEXT: v_readlane_b32 s33, v23, 2
-; GFX10_1-NEXT: v_readlane_b32 s31, v23, 1
-; GFX10_1-NEXT: v_readlane_b32 s30, v23, 0
+; GFX10_1-NEXT: v_readlane_b32 s30, v23, 15
+; GFX10_1-NEXT: v_readlane_b32 s31, v23, 16
+; GFX10_1-NEXT: v_readlane_b32 s55, v23, 14
+; GFX10_1-NEXT: v_readlane_b32 s54, v23, 13
+; GFX10_1-NEXT: v_readlane_b32 s53, v23, 12
+; GFX10_1-NEXT: v_readlane_b32 s52, v23, 11
+; GFX10_1-NEXT: v_readlane_b32 s51, v23, 10
+; GFX10_1-NEXT: v_readlane_b32 s50, v23, 9
+; GFX10_1-NEXT: v_readlane_b32 s49, v23, 8
+; GFX10_1-NEXT: v_readlane_b32 s48, v23, 7
+; GFX10_1-NEXT: v_readlane_b32 s39, v23, 6
+; GFX10_1-NEXT: v_readlane_b32 s38, v23, 5
+; GFX10_1-NEXT: v_readlane_b32 s37, v23, 4
+; GFX10_1-NEXT: v_readlane_b32 s36, v23, 3
+; GFX10_1-NEXT: v_readlane_b32 s35, v23, 2
+; GFX10_1-NEXT: v_readlane_b32 s34, v23, 1
+; GFX10_1-NEXT: v_readlane_b32 s33, v23, 0
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80880
; GFX10_1-NEXT: buffer_load_dword v23, off, s[0:3], s5 ; 4-byte Folded Reload
@@ -370,29 +370,29 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX10_3-NEXT: s_add_i32 s5, s32, 0x80880
; GFX10_3-NEXT: buffer_store_dword v23, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_3-NEXT: v_writelane_b32 v23, s30, 0
+; GFX10_3-NEXT: v_writelane_b32 v23, s33, 0
; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s32
; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo
-; GFX10_3-NEXT: v_writelane_b32 v23, s31, 1
+; GFX10_3-NEXT: v_writelane_b32 v23, s34, 1
; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; use alloca0 v0
; GFX10_3-NEXT: ;;#ASMEND
-; GFX10_3-NEXT: v_writelane_b32 v23, s33, 2
-; GFX10_3-NEXT: v_writelane_b32 v23, s34, 3
-; GFX10_3-NEXT: v_writelane_b32 v23, s35, 4
-; GFX10_3-NEXT: v_writelane_b32 v23, s36, 5
-; GFX10_3-NEXT: v_writelane_b32 v23, s37, 6
-; GFX10_3-NEXT: v_writelane_b32 v23, s38, 7
-; GFX10_3-NEXT: v_writelane_b32 v23, s39, 8
-; GFX10_3-NEXT: v_writelane_b32 v23, s48, 9
-; GFX10_3-NEXT: v_writelane_b32 v23, s49, 10
-; GFX10_3-NEXT: v_writelane_b32 v23, s50, 11
-; GFX10_3-NEXT: v_writelane_b32 v23, s51, 12
-; GFX10_3-NEXT: v_writelane_b32 v23, s52, 13
-; GFX10_3-NEXT: v_writelane_b32 v23, s53, 14
-; GFX10_3-NEXT: v_writelane_b32 v23, s54, 15
-; GFX10_3-NEXT: v_writelane_b32 v23, s55, 16
+; GFX10_3-NEXT: v_writelane_b32 v23, s35, 2
+; GFX10_3-NEXT: v_writelane_b32 v23, s36, 3
+; GFX10_3-NEXT: v_writelane_b32 v23, s37, 4
+; GFX10_3-NEXT: v_writelane_b32 v23, s38, 5
+; GFX10_3-NEXT: v_writelane_b32 v23, s39, 6
+; GFX10_3-NEXT: v_writelane_b32 v23, s48, 7
+; GFX10_3-NEXT: v_writelane_b32 v23, s49, 8
+; GFX10_3-NEXT: v_writelane_b32 v23, s50, 9
+; GFX10_3-NEXT: v_writelane_b32 v23, s51, 10
+; GFX10_3-NEXT: v_writelane_b32 v23, s52, 11
+; GFX10_3-NEXT: v_writelane_b32 v23, s53, 12
+; GFX10_3-NEXT: v_writelane_b32 v23, s54, 13
+; GFX10_3-NEXT: v_writelane_b32 v23, s55, 14
+; GFX10_3-NEXT: v_writelane_b32 v23, s30, 15
+; GFX10_3-NEXT: v_writelane_b32 v23, s31, 16
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc
; GFX10_3-NEXT: ;;#ASMEND
@@ -403,23 +403,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc
; GFX10_3-NEXT: ;;#ASMEND
-; GFX10_3-NEXT: v_readlane_b32 s55, v23, 16
-; GFX10_3-NEXT: v_readlane_b32 s54, v23, 15
-; GFX10_3-NEXT: v_readlane_b32 s53, v23, 14
-; GFX10_3-NEXT: v_readlane_b32 s52, v23, 13
-; GFX10_3-NEXT: v_readlane_b32 s51, v23, 12
-; GFX10_3-NEXT: v_readlane_b32 s50, v23, 11
-; GFX10_3-NEXT: v_readlane_b32 s49, v23, 10
-; GFX10_3-NEXT: v_readlane_b32 s48, v23, 9
-; GFX10_3-NEXT: v_readlane_b32 s39, v23, 8
-; GFX10_3-NEXT: v_readlane_b32 s38, v23, 7
-; GFX10_3-NEXT: v_readlane_b32 s37, v23, 6
-; GFX10_3-NEXT: v_readlane_b32 s36, v23, 5
-; GFX10_3-NEXT: v_readlane_b32 s35, v23, 4
-; GFX10_3-NEXT: v_readlane_b32 s34, v23, 3
-; GFX10_3-NEXT: v_readlane_b32 s33, v23, 2
-; GFX10_3-NEXT: v_readlane_b32 s31, v23, 1
-; GFX10_3-NEXT: v_readlane_b32 s30, v23, 0
+; GFX10_3-NEXT: v_readlane_b32 s30, v23, 15
+; GFX10_3-NEXT: v_readlane_b32 s31, v23, 16
+; GFX10_3-NEXT: v_readlane_b32 s55, v23, 14
+; GFX10_3-NEXT: v_readlane_b32 s54, v23, 13
+; GFX10_3-NEXT: v_readlane_b32 s53, v23, 12
+; GFX10_3-NEXT: v_readlane_b32 s52, v23, 11
+; GFX10_3-NEXT: v_readlane_b32 s51, v23, 10
+; GFX10_3-NEXT: v_readlane_b32 s50, v23, 9
+; GFX10_3-NEXT: v_readlane_b32 s49, v23, 8
+; GFX10_3-NEXT: v_readlane_b32 s48, v23, 7
+; GFX10_3-NEXT: v_readlane_b32 s39, v23, 6
+; GFX10_3-NEXT: v_readlane_b32 s38, v23, 5
+; GFX10_3-NEXT: v_readlane_b32 s37, v23, 4
+; GFX10_3-NEXT: v_readlane_b32 s36, v23, 3
+; GFX10_3-NEXT: v_readlane_b32 s35, v23, 2
+; GFX10_3-NEXT: v_readlane_b32 s34, v23, 1
+; GFX10_3-NEXT: v_readlane_b32 s33, v23, 0
; GFX10_3-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_3-NEXT: s_add_i32 s5, s32, 0x80880
; GFX10_3-NEXT: buffer_load_dword v23, off, s[0:3], s5 ; 4-byte Folded Reload
@@ -434,30 +434,30 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX11-NEXT: s_add_i32 s1, s32, 0x4044
; GFX11-NEXT: scratch_store_b32 off, v23, s1 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-NEXT: v_writelane_b32 v23, s30, 0
+; GFX11-NEXT: v_writelane_b32 v23, s33, 0
; GFX11-NEXT: s_add_i32 s0, s32, 64
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
-; GFX11-NEXT: v_writelane_b32 v23, s31, 1
+; GFX11-NEXT: v_writelane_b32 v23, s34, 1
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use alloca0 v0
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: v_writelane_b32 v23, s33, 2
-; GFX11-NEXT: v_writelane_b32 v23, s34, 3
-; GFX11-NEXT: v_writelane_b32 v23, s35, 4
-; GFX11-NEXT: v_writelane_b32 v23, s36, 5
-; GFX11-NEXT: v_writelane_b32 v23, s37, 6
-; GFX11-NEXT: v_writelane_b32 v23, s38, 7
-; GFX11-NEXT: v_writelane_b32 v23, s39, 8
-; GFX11-NEXT: v_writelane_b32 v23, s48, 9
-; GFX11-NEXT: v_writelane_b32 v23, s49, 10
-; GFX11-NEXT: v_writelane_b32 v23, s50, 11
-; GFX11-NEXT: v_writelane_b32 v23, s51, 12
-; GFX11-NEXT: v_writelane_b32 v23, s52, 13
-; GFX11-NEXT: v_writelane_b32 v23, s53, 14
-; GFX11-NEXT: v_writelane_b32 v23, s54, 15
-; GFX11-NEXT: v_writelane_b32 v23, s55, 16
+; GFX11-NEXT: v_writelane_b32 v23, s35, 2
+; GFX11-NEXT: v_writelane_b32 v23, s36, 3
+; GFX11-NEXT: v_writelane_b32 v23, s37, 4
+; GFX11-NEXT: v_writelane_b32 v23, s38, 5
+; GFX11-NEXT: v_writelane_b32 v23, s39, 6
+; GFX11-NEXT: v_writelane_b32 v23, s48, 7
+; GFX11-NEXT: v_writelane_b32 v23, s49, 8
+; GFX11-NEXT: v_writelane_b32 v23, s50, 9
+; GFX11-NEXT: v_writelane_b32 v23, s51, 10
+; GFX11-NEXT: v_writelane_b32 v23, s52, 11
+; GFX11-NEXT: v_writelane_b32 v23, s53, 12
+; GFX11-NEXT: v_writelane_b32 v23, s54, 13
+; GFX11-NEXT: v_writelane_b32 v23, s55, 14
+; GFX11-NEXT: v_writelane_b32 v23, s30, 15
+; GFX11-NEXT: v_writelane_b32 v23, s31, 16
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc
; GFX11-NEXT: ;;#ASMEND
@@ -470,23 +470,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: v_readlane_b32 s55, v23, 16
-; GFX11-NEXT: v_readlane_b32 s54, v23, 15
-; GFX11-NEXT: v_readlane_b32 s53, v23, 14
-; GFX11-NEXT: v_readlane_b32 s52, v23, 13
-; GFX11-NEXT: v_readlane_b32 s51, v23, 12
-; GFX11-NEXT: v_readlane_b32 s50, v23, 11
-; GFX11-NEXT: v_readlane_b32 s49, v23, 10
-; GFX11-NEXT: v_readlane_b32 s48, v23, 9
-; GFX11-NEXT: v_readlane_b32 s39, v23, 8
-; GFX11-NEXT: v_readlane_b32 s38, v23, 7
-; GFX11-NEXT: v_readlane_b32 s37, v23, 6
-; GFX11-NEXT: v_readlane_b32 s36, v23, 5
-; GFX11-NEXT: v_readlane_b32 s35, v23, 4
-; GFX11-NEXT: v_readlane_b32 s34, v23, 3
-; GFX11-NEXT: v_readlane_b32 s33, v23, 2
-; GFX11-NEXT: v_readlane_b32 s31, v23, 1
-; GFX11-NEXT: v_readlane_b32 s30, v23, 0
+; GFX11-NEXT: v_readlane_b32 s30, v23, 15
+; GFX11-NEXT: v_readlane_b32 s31, v23, 16
+; GFX11-NEXT: v_readlane_b32 s55, v23, 14
+; GFX11-NEXT: v_readlane_b32 s54, v23, 13
+; GFX11-NEXT: v_readlane_b32 s53, v23, 12
+; GFX11-NEXT: v_readlane_b32 s52, v23, 11
+; GFX11-NEXT: v_readlane_b32 s51, v23, 10
+; GFX11-NEXT: v_readlane_b32 s50, v23, 9
+; GFX11-NEXT: v_readlane_b32 s49, v23, 8
+; GFX11-NEXT: v_readlane_b32 s48, v23, 7
+; GFX11-NEXT: v_readlane_b32 s39, v23, 6
+; GFX11-NEXT: v_readlane_b32 s38, v23, 5
+; GFX11-NEXT: v_readlane_b32 s37, v23, 4
+; GFX11-NEXT: v_readlane_b32 s36, v23, 3
+; GFX11-NEXT: v_readlane_b32 s35, v23, 2
+; GFX11-NEXT: v_readlane_b32 s34, v23, 1
+; GFX11-NEXT: v_readlane_b32 s33, v23, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: s_add_i32 s1, s32, 0x4044
; GFX11-NEXT: scratch_load_b32 v23, off, s1 ; 4-byte Folded Reload
@@ -505,28 +505,28 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX12-NEXT: scratch_store_b32 off, v23, s32 offset:16388 ; 4-byte Folded Spill
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s0
-; GFX12-NEXT: v_writelane_b32 v23, s30, 0
+; GFX12-NEXT: v_writelane_b32 v23, s33, 0
; GFX12-NEXT: v_mov_b32_e32 v0, s32
; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use alloca0 v0
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: v_writelane_b32 v23, s31, 1
-; GFX12-NEXT: v_writelane_b32 v23, s33, 2
-; GFX12-NEXT: v_writelane_b32 v23, s34, 3
-; GFX12-NEXT: v_writelane_b32 v23, s35, 4
-; GFX12-NEXT: v_writelane_b32 v23, s36, 5
-; GFX12-NEXT: v_writelane_b32 v23, s37, 6
-; GFX12-NEXT: v_writelane_b32 v23, s38, 7
-; GFX12-NEXT: v_writelane_b32 v23, s39, 8
-; GFX12-NEXT: v_writelane_b32 v23, s48, 9
-; GFX12-NEXT: v_writelane_b32 v23, s49, 10
-; GFX12-NEXT: v_writelane_b32 v23, s50, 11
-; GFX12-NEXT: v_writelane_b32 v23, s51, 12
-; GFX12-NEXT: v_writelane_b32 v23, s52, 13
-; GFX12-NEXT: v_writelane_b32 v23, s53, 14
-; GFX12-NEXT: v_writelane_b32 v23, s54, 15
-; GFX12-NEXT: v_writelane_b32 v23, s55, 16
+; GFX12-NEXT: v_writelane_b32 v23, s34, 1
+; GFX12-NEXT: v_writelane_b32 v23, s35, 2
+; GFX12-NEXT: v_writelane_b32 v23, s36, 3
+; GFX12-NEXT: v_writelane_b32 v23, s37, 4
+; GFX12-NEXT: v_writelane_b32 v23, s38, 5
+; GFX12-NEXT: v_writelane_b32 v23, s39, 6
+; GFX12-NEXT: v_writelane_b32 v23, s48, 7
+; GFX12-NEXT: v_writelane_b32 v23, s49, 8
+; GFX12-NEXT: v_writelane_b32 v23, s50, 9
+; GFX12-NEXT: v_writelane_b32 v23, s51, 10
+; GFX12-NEXT: v_writelane_b32 v23, s52, 11
+; GFX12-NEXT: v_writelane_b32 v23, s53, 12
+; GFX12-NEXT: v_writelane_b32 v23, s54, 13
+; GFX12-NEXT: v_writelane_b32 v23, s55, 14
+; GFX12-NEXT: v_writelane_b32 v23, s30, 15
+; GFX12-NEXT: v_writelane_b32 v23, s31, 16
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc
; GFX12-NEXT: ;;#ASMEND
@@ -540,23 +540,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: v_readlane_b32 s55, v23, 16
-; GFX12-NEXT: v_readlane_b32 s54, v23, 15
-; GFX12-NEXT: v_readlane_b32 s53, v23, 14
-; GFX12-NEXT: v_readlane_b32 s52, v23, 13
-; GFX12-NEXT: v_readlane_b32 s51, v23, 12
-; GFX12-NEXT: v_readlane_b32 s50, v23, 11
-; GFX12-NEXT: v_readlane_b32 s49, v23, 10
-; GFX12-NEXT: v_readlane_b32 s48, v23, 9
-; GFX12-NEXT: v_readlane_b32 s39, v23, 8
-; GFX12-NEXT: v_readlane_b32 s38, v23, 7
-; GFX12-NEXT: v_readlane_b32 s37, v23, 6
-; GFX12-NEXT: v_readlane_b32 s36, v23, 5
-; GFX12-NEXT: v_readlane_b32 s35, v23, 4
-; GFX12-NEXT: v_readlane_b32 s34, v23, 3
-; GFX12-NEXT: v_readlane_b32 s33, v23, 2
-; GFX12-NEXT: v_readlane_b32 s31, v23, 1
-; GFX12-NEXT: v_readlane_b32 s30, v23, 0
+; GFX12-NEXT: v_readlane_b32 s30, v23, 15
+; GFX12-NEXT: v_readlane_b32 s31, v23, 16
+; GFX12-NEXT: v_readlane_b32 s55, v23, 14
+; GFX12-NEXT: v_readlane_b32 s54, v23, 13
+; GFX12-NEXT: v_readlane_b32 s53, v23, 12
+; GFX12-NEXT: v_readlane_b32 s52, v23, 11
+; GFX12-NEXT: v_readlane_b32 s51, v23, 10
+; GFX12-NEXT: v_readlane_b32 s50, v23, 9
+; GFX12-NEXT: v_readlane_b32 s49, v23, 8
+; GFX12-NEXT: v_readlane_b32 s48, v23, 7
+; GFX12-NEXT: v_readlane_b32 s39, v23, 6
+; GFX12-NEXT: v_readlane_b32 s38, v23, 5
+; GFX12-NEXT: v_readlane_b32 s37, v23, 4
+; GFX12-NEXT: v_readlane_b32 s36, v23, 3
+; GFX12-NEXT: v_readlane_b32 s35, v23, 2
+; GFX12-NEXT: v_readlane_b32 s34, v23, 1
+; GFX12-NEXT: v_readlane_b32 s33, v23, 0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v23, off, s32 offset:16388 ; 4-byte Folded Reload
; GFX12-NEXT: s_wait_alu 0xfffe
@@ -613,24 +613,24 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX7-NEXT: s_add_i32 s6, s32, 0x100400
; GFX7-NEXT: buffer_store_dword v21, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[4:5]
-; GFX7-NEXT: v_writelane_b32 v21, s30, 0
-; GFX7-NEXT: v_writelane_b32 v21, s31, 1
-; GFX7-NEXT: v_writelane_b32 v21, s33, 2
-; GFX7-NEXT: v_writelane_b32 v21, s34, 3
-; GFX7-NEXT: v_writelane_b32 v21, s35, 4
-; GFX7-NEXT: v_writelane_b32 v21, s36, 5
-; GFX7-NEXT: v_writelane_b32 v21, s37, 6
-; GFX7-NEXT: v_writelane_b32 v21, s38, 7
-; GFX7-NEXT: v_writelane_b32 v21, s39, 8
-; GFX7-NEXT: v_writelane_b32 v21, s48, 9
-; GFX7-NEXT: v_writelane_b32 v21, s49, 10
-; GFX7-NEXT: v_writelane_b32 v21, s50, 11
-; GFX7-NEXT: v_writelane_b32 v21, s51, 12
-; GFX7-NEXT: v_writelane_b32 v21, s52, 13
-; GFX7-NEXT: v_writelane_b32 v21, s53, 14
-; GFX7-NEXT: v_writelane_b32 v21, s54, 15
+; GFX7-NEXT: v_writelane_b32 v21, s33, 0
+; GFX7-NEXT: v_writelane_b32 v21, s34, 1
+; GFX7-NEXT: v_writelane_b32 v21, s35, 2
+; GFX7-NEXT: v_writelane_b32 v21, s36, 3
+; GFX7-NEXT: v_writelane_b32 v21, s37, 4
+; GFX7-NEXT: v_writelane_b32 v21, s38, 5
+; GFX7-NEXT: v_writelane_b32 v21, s39, 6
+; GFX7-NEXT: v_writelane_b32 v21, s48, 7
+; GFX7-NEXT: v_writelane_b32 v21, s49, 8
+; GFX7-NEXT: v_writelane_b32 v21, s50, 9
+; GFX7-NEXT: v_writelane_b32 v21, s51, 10
+; GFX7-NEXT: v_writelane_b32 v21, s52, 11
+; GFX7-NEXT: v_writelane_b32 v21, s53, 12
+; GFX7-NEXT: v_writelane_b32 v21, s54, 13
+; GFX7-NEXT: v_writelane_b32 v21, s55, 14
+; GFX7-NEXT: v_writelane_b32 v21, s30, 15
; GFX7-NEXT: s_and_b64 s[4:5], 0, exec
-; GFX7-NEXT: v_writelane_b32 v21, s55, 16
+; GFX7-NEXT: v_writelane_b32 v21, s31, 16
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
; GFX7-NEXT: ;;#ASMEND
@@ -640,23 +640,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc
; GFX7-NEXT: ;;#ASMEND
-; GFX7-NEXT: v_readlane_b32 s55, v21, 16
-; GFX7-NEXT: v_readlane_b32 s54, v21, 15
-; GFX7-NEXT: v_readlane_b32 s53, v21, 14
-; GFX7-NEXT: v_readlane_b32 s52, v21, 13
-; GFX7-NEXT: v_readlane_b32 s51, v21, 12
-; GFX7-NEXT: v_readlane_b32 s50, v21, 11
-; GFX7-NEXT: v_readlane_b32 s49, v21, 10
-; GFX7-NEXT: v_readlane_b32 s48, v21, 9
-; GFX7-NEXT: v_readlane_b32 s39, v21, 8
-; GFX7-NEXT: v_readlane_b32 s38, v21, 7
-; GFX7-NEXT: v_readlane_b32 s37, v21, 6
-; GFX7-NEXT: v_readlane_b32 s36, v21, 5
-; GFX7-NEXT: v_readlane_b32 s35, v21, 4
-; GFX7-NEXT: v_readlane_b32 s34, v21, 3
-; GFX7-NEXT: v_readlane_b32 s33, v21, 2
-; GFX7-NEXT: v_readlane_b32 s31, v21, 1
-; GFX7-NEXT: v_readlane_b32 s30, v21, 0
+; GFX7-NEXT: v_readlane_b32 s30, v21, 15
+; GFX7-NEXT: v_readlane_b32 s31, v21, 16
+; GFX7-NEXT: v_readlane_b32 s55, v21, 14
+; GFX7-NEXT: v_readlane_b32 s54, v21, 13
+; GFX7-NEXT: v_readlane_b32 s53, v21, 12
+; GFX7-NEXT: v_readlane_b32 s52, v21, 11
+; GFX7-NEXT: v_readlane_b32 s51, v21, 10
+; GFX7-NEXT: v_readlane_b32 s50, v21, 9
+; GFX7-NEXT: v_readlane_b32 s49, v21, 8
+; GFX7-NEXT: v_readlane_b32 s48, v21, 7
+; GFX7-NEXT: v_readlane_b32 s39, v21, 6
+; GFX7-NEXT: v_readlane_b32 s38, v21, 5
+; GFX7-NEXT: v_readlane_b32 s37, v21, 4
+; GFX7-NEXT: v_readlane_b32 s36, v21, 3
+; GFX7-NEXT: v_readlane_b32 s35, v21, 2
+; GFX7-NEXT: v_readlane_b32 s34, v21, 1
+; GFX7-NEXT: v_readlane_b32 s33, v21, 0
; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX7-NEXT: s_add_i32 s6, s32, 0x100400
; GFX7-NEXT: buffer_load_dword v21, off, s[0:3], s6 ; 4-byte Folded Reload
@@ -671,24 +671,24 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX8-NEXT: s_add_i32 s6, s32, 0x100400
; GFX8-NEXT: buffer_store_dword v21, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
-; GFX8-NEXT: v_writelane_b32 v21, s30, 0
-; GFX8-NEXT: v_writelane_b32 v21, s31, 1
-; GFX8-NEXT: v_writelane_b32 v21, s33, 2
-; GFX8-NEXT: v_writelane_b32 v21, s34, 3
-; GFX8-NEXT: v_writelane_b32 v21, s35, 4
-; GFX8-NEXT: v_writelane_b32 v21, s36, 5
-; GFX8-NEXT: v_writelane_b32 v21, s37, 6
-; GFX8-NEXT: v_writelane_b32 v21, s38, 7
-; GFX8-NEXT: v_writelane_b32 v21, s39, 8
-; GFX8-NEXT: v_writelane_b32 v21, s48, 9
-; GFX8-NEXT: v_writelane_b32 v21, s49, 10
-; GFX8-NEXT: v_writelane_b32 v21, s50, 11
-; GFX8-NEXT: v_writelane_b32 v21, s51, 12
-; GFX8-NEXT: v_writelane_b32 v21, s52, 13
-; GFX8-NEXT: v_writelane_b32 v21, s53, 14
-; GFX8-NEXT: v_writelane_b32 v21, s54, 15
+; GFX8-NEXT: v_writelane_b32 v21, s33, 0
+; GFX8-NEXT: v_writelane_b32 v21, s34, 1
+; GFX8-NEXT: v_writelane_b32 v21, s35, 2
+; GFX8-NEXT: v_writelane_b32 v21, s36, 3
+; GFX8-NEXT: v_writelane_b32 v21, s37, 4
+; GFX8-NEXT: v_writelane_b32 v21, s38, 5
+; GFX8-NEXT: v_writelane_b32 v21, s39, 6
+; GFX8-NEXT: v_writelane_b32 v21, s48, 7
+; GFX8-NEXT: v_writelane_b32 v21, s49, 8
+; GFX8-NEXT: v_writelane_b32 v21, s50, 9
+; GFX8-NEXT: v_writelane_b32 v21, s51, 10
+; GFX8-NEXT: v_writelane_b32 v21, s52, 11
+; GFX8-NEXT: v_writelane_b32 v21, s53, 12
+; GFX8-NEXT: v_writelane_b32 v21, s54, 13
+; GFX8-NEXT: v_writelane_b32 v21, s55, 14
+; GFX8-NEXT: v_writelane_b32 v21, s30, 15
; GFX8-NEXT: s_and_b64 s[4:5], 0, exec
-; GFX8-NEXT: v_writelane_b32 v21, s55, 16
+; GFX8-NEXT: v_writelane_b32 v21, s31, 16
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
; GFX8-NEXT: ;;#ASMEND
@@ -699,23 +699,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc
; GFX8-NEXT: ;;#ASMEND
-; GFX8-NEXT: v_readlane_b32 s55, v21, 16
-; GFX8-NEXT: v_readlane_b32 s54, v21, 15
-; GFX8-NEXT: v_readlane_b32 s53, v21, 14
-; GFX8-NEXT: v_readlane_b32 s52, v21, 13
-; GFX8-NEXT: v_readlane_b32 s51, v21, 12
-; GFX8-NEXT: v_readlane_b32 s50, v21, 11
-; GFX8-NEXT: v_readlane_b32 s49, v21, 10
-; GFX8-NEXT: v_readlane_b32 s48, v21, 9
-; GFX8-NEXT: v_readlane_b32 s39, v21, 8
-; GFX8-NEXT: v_readlane_b32 s38, v21, 7
-; GFX8-NEXT: v_readlane_b32 s37, v21, 6
-; GFX8-NEXT: v_readlane_b32 s36, v21, 5
-; GFX8-NEXT: v_readlane_b32 s35, v21, 4
-; GFX8-NEXT: v_readlane_b32 s34, v21, 3
-; GFX8-NEXT: v_readlane_b32 s33, v21, 2
-; GFX8-NEXT: v_readlane_b32 s31, v21, 1
-; GFX8-NEXT: v_readlane_b32 s30, v21, 0
+; GFX8-NEXT: v_readlane_b32 s30, v21, 15
+; GFX8-NEXT: v_readlane_b32 s31, v21, 16
+; GFX8-NEXT: v_readlane_b32 s55, v21, 14
+; GFX8-NEXT: v_readlane_b32 s54, v21, 13
+; GFX8-NEXT: v_readlane_b32 s53, v21, 12
+; GFX8-NEXT: v_readlane_b32 s52, v21, 11
+; GFX8-NEXT: v_readlane_b32 s51, v21, 10
+; GFX8-NEXT: v_readlane_b32 s50, v21, 9
+; GFX8-NEXT: v_readlane_b32 s49, v21, 8
+; GFX8-NEXT: v_readlane_b32 s48, v21, 7
+; GFX8-NEXT: v_readlane_b32 s39, v21, 6
+; GFX8-NEXT: v_readlane_b32 s38, v21, 5
+; GFX8-NEXT: v_readlane_b32 s37, v21, 4
+; GFX8-NEXT: v_readlane_b32 s36, v21, 3
+; GFX8-NEXT: v_readlane_b32 s35, v21, 2
+; GFX8-NEXT: v_readlane_b32 s34, v21, 1
+; GFX8-NEXT: v_readlane_b32 s33, v21, 0
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: s_add_i32 s6, s32, 0x100400
; GFX8-NEXT: buffer_load_dword v21, off, s[0:3], s6 ; 4-byte Folded Reload
@@ -730,24 +730,24 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX900-NEXT: s_add_i32 s6, s32, 0x100400
; GFX900-NEXT: buffer_store_dword v21, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
-; GFX900-NEXT: v_writelane_b32 v21, s30, 0
-; GFX900-NEXT: v_writelane_b32 v21, s31, 1
-; GFX900-NEXT: v_writelane_b32 v21, s33, 2
-; GFX900-NEXT: v_writelane_b32 v21, s34, 3
-; GFX900-NEXT: v_writelane_b32 v21, s35, 4
-; GFX900-NEXT: v_writelane_b32 v21, s36, 5
-; GFX900-NEXT: v_writelane_b32 v21, s37, 6
-; GFX900-NEXT: v_writelane_b32 v21, s38, 7
-; GFX900-NEXT: v_writelane_b32 v21, s39, 8
-; GFX900-NEXT: v_writelane_b32 v21, s48, 9
-; GFX900-NEXT: v_writelane_b32 v21, s49, 10
-; GFX900-NEXT: v_writelane_b32 v21, s50, 11
-; GFX900-NEXT: v_writelane_b32 v21, s51, 12
-; GFX900-NEXT: v_writelane_b32 v21, s52, 13
-; GFX900-NEXT: v_writelane_b32 v21, s53, 14
-; GFX900-NEXT: v_writelane_b32 v21, s54, 15
+; GFX900-NEXT: v_writelane_b32 v21, s33, 0
+; GFX900-NEXT: v_writelane_b32 v21, s34, 1
+; GFX900-NEXT: v_writelane_b32 v21, s35, 2
+; GFX900-NEXT: v_writelane_b32 v21, s36, 3
+; GFX900-NEXT: v_writelane_b32 v21, s37, 4
+; GFX900-NEXT: v_writelane_b32 v21, s38, 5
+; GFX900-NEXT: v_writelane_b32 v21, s39, 6
+; GFX900-NEXT: v_writelane_b32 v21, s48, 7
+; GFX900-NEXT: v_writelane_b32 v21, s49, 8
+; GFX900-NEXT: v_writelane_b32 v21, s50, 9
+; GFX900-NEXT: v_writelane_b32 v21, s51, 10
+; GFX900-NEXT: v_writelane_b32 v21, s52, 11
+; GFX900-NEXT: v_writelane_b32 v21, s53, 12
+; GFX900-NEXT: v_writelane_b32 v21, s54, 13
+; GFX900-NEXT: v_writelane_b32 v21, s55, 14
+; GFX900-NEXT: v_writelane_b32 v21, s30, 15
; GFX900-NEXT: s_and_b64 s[4:5], 0, exec
-; GFX900-NEXT: v_writelane_b32 v21, s55, 16
+; GFX900-NEXT: v_writelane_b32 v21, s31, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
; GFX900-NEXT: ;;#ASMEND
@@ -758,23 +758,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_readlane_b32 s55, v21, 16
-; GFX900-NEXT: v_readlane_b32 s54, v21, 15
-; GFX900-NEXT: v_readlane_b32 s53, v21, 14
-; GFX900-NEXT: v_readlane_b32 s52, v21, 13
-; GFX900-NEXT: v_readlane_b32 s51, v21, 12
-; GFX900-NEXT: v_readlane_b32 s50, v21, 11
-; GFX900-NEXT: v_readlane_b32 s49, v21, 10
-; GFX900-NEXT: v_readlane_b32 s48, v21, 9
-; GFX900-NEXT: v_readlane_b32 s39, v21, 8
-; GFX900-NEXT: v_readlane_b32 s38, v21, 7
-; GFX900-NEXT: v_readlane_b32 s37, v21, 6
-; GFX900-NEXT: v_readlane_b32 s36, v21, 5
-; GFX900-NEXT: v_readlane_b32 s35, v21, 4
-; GFX900-NEXT: v_readlane_b32 s34, v21, 3
-; GFX900-NEXT: v_readlane_b32 s33, v21, 2
-; GFX900-NEXT: v_readlane_b32 s31, v21, 1
-; GFX900-NEXT: v_readlane_b32 s30, v21, 0
+; GFX900-NEXT: v_readlane_b32 s30, v21, 15
+; GFX900-NEXT: v_readlane_b32 s31, v21, 16
+; GFX900-NEXT: v_readlane_b32 s55, v21, 14
+; GFX900-NEXT: v_readlane_b32 s54, v21, 13
+; GFX900-NEXT: v_readlane_b32 s53, v21, 12
+; GFX900-NEXT: v_readlane_b32 s52, v21, 11
+; GFX900-NEXT: v_readlane_b32 s51, v21, 10
+; GFX900-NEXT: v_readlane_b32 s50, v21, 9
+; GFX900-NEXT: v_readlane_b32 s49, v21, 8
+; GFX900-NEXT: v_readlane_b32 s48, v21, 7
+; GFX900-NEXT: v_readlane_b32 s39, v21, 6
+; GFX900-NEXT: v_readlane_b32 s38, v21, 5
+; GFX900-NEXT: v_readlane_b32 s37, v21, 4
+; GFX900-NEXT: v_readlane_b32 s36, v21, 3
+; GFX900-NEXT: v_readlane_b32 s35, v21, 2
+; GFX900-NEXT: v_readlane_b32 s34, v21, 1
+; GFX900-NEXT: v_readlane_b32 s33, v21, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: s_add_i32 s6, s32, 0x100400
; GFX900-NEXT: buffer_load_dword v21, off, s[0:3], s6 ; 4-byte Folded Reload
@@ -789,24 +789,25 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX942-NEXT: s_add_i32 s2, s32, 0x4010
; GFX942-NEXT: scratch_store_dword off, v21, s2 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
-; GFX942-NEXT: v_writelane_b32 v21, s30, 0
-; GFX942-NEXT: v_writelane_b32 v21, s31, 1
-; GFX942-NEXT: v_writelane_b32 v21, s33, 2
-; GFX942-NEXT: v_writelane_b32 v21, s34, 3
-; GFX942-NEXT: v_writelane_b32 v21, s35, 4
-; GFX942-NEXT: v_writelane_b32 v21, s36, 5
-; GFX942-NEXT: v_writelane_b32 v21, s37, 6
-; GFX942-NEXT: v_writelane_b32 v21, s38, 7
-; GFX942-NEXT: v_writelane_b32 v21, s39, 8
-; GFX942-NEXT: v_writelane_b32 v21, s48, 9
-; GFX942-NEXT: v_writelane_b32 v21, s49, 10
-; GFX942-NEXT: v_writelane_b32 v21, s50, 11
-; GFX942-NEXT: v_writelane_b32 v21, s51, 12
-; GFX942-NEXT: v_writelane_b32 v21, s52, 13
-; GFX942-NEXT: v_writelane_b32 v21, s53, 14
-; GFX942-NEXT: v_writelane_b32 v21, s54, 15
+; GFX942-NEXT: v_writelane_b32 v21, s33, 0
+; GFX942-NEXT: v_writelane_b32 v21, s34, 1
+; GFX942-NEXT: v_writelane_b32 v21, s35, 2
+; GFX942-NEXT: v_writelane_b32 v21, s36, 3
+; GFX942-NEXT: v_writelane_b32 v21, s37, 4
+; GFX942-NEXT: v_writelane_b32 v21, s38, 5
+; GFX942-NEXT: v_writelane_b32 v21, s39, 6
+; GFX942-NEXT: v_writelane_b32 v21, s48, 7
+; GFX942-NEXT: v_writelane_b32 v21, s49, 8
+; GFX942-NEXT: v_writelane_b32 v21, s50, 9
+; GFX942-NEXT: v_writelane_b32 v21, s51, 10
+; GFX942-NEXT: v_writelane_b32 v21, s52, 11
+; GFX942-NEXT: v_writelane_b32 v21, s53, 12
+; GFX942-NEXT: v_writelane_b32 v21, s54, 13
+; GFX942-NEXT: v_writelane_b32 v21, s55, 14
+; GFX942-NEXT: v_writelane_b32 v21, s30, 15
; GFX942-NEXT: s_and_b64 s[60:61], 0, exec
-; GFX942-NEXT: v_writelane_b32 v21, s55, 16
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_writelane_b32 v21, s31, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
; GFX942-NEXT: ;;#ASMEND
@@ -818,23 +819,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_readlane_b32 s55, v21, 16
-; GFX942-NEXT: v_readlane_b32 s54, v21, 15
-; GFX942-NEXT: v_readlane_b32 s53, v21, 14
-; GFX942-NEXT: v_readlane_b32 s52, v21, 13
-; GFX942-NEXT: v_readlane_b32 s51, v21, 12
-; GFX942-NEXT: v_readlane_b32 s50, v21, 11
-; GFX942-NEXT: v_readlane_b32 s49, v21, 10
-; GFX942-NEXT: v_readlane_b32 s48, v21, 9
-; GFX942-NEXT: v_readlane_b32 s39, v21, 8
-; GFX942-NEXT: v_readlane_b32 s38, v21, 7
-; GFX942-NEXT: v_readlane_b32 s37, v21, 6
-; GFX942-NEXT: v_readlane_b32 s36, v21, 5
-; GFX942-NEXT: v_readlane_b32 s35, v21, 4
-; GFX942-NEXT: v_readlane_b32 s34, v21, 3
-; GFX942-NEXT: v_readlane_b32 s33, v21, 2
-; GFX942-NEXT: v_readlane_b32 s31, v21, 1
-; GFX942-NEXT: v_readlane_b32 s30, v21, 0
+; GFX942-NEXT: v_readlane_b32 s30, v21, 15
+; GFX942-NEXT: v_readlane_b32 s31, v21, 16
+; GFX942-NEXT: v_readlane_b32 s55, v21, 14
+; GFX942-NEXT: v_readlane_b32 s54, v21, 13
+; GFX942-NEXT: v_readlane_b32 s53, v21, 12
+; GFX942-NEXT: v_readlane_b32 s52, v21, 11
+; GFX942-NEXT: v_readlane_b32 s51, v21, 10
+; GFX942-NEXT: v_readlane_b32 s50, v21, 9
+; GFX942-NEXT: v_readlane_b32 s49, v21, 8
+; GFX942-NEXT: v_readlane_b32 s48, v21, 7
+; GFX942-NEXT: v_readlane_b32 s39, v21, 6
+; GFX942-NEXT: v_readlane_b32 s38, v21, 5
+; GFX942-NEXT: v_readlane_b32 s37, v21, 4
+; GFX942-NEXT: v_readlane_b32 s36, v21, 3
+; GFX942-NEXT: v_readlane_b32 s35, v21, 2
+; GFX942-NEXT: v_readlane_b32 s34, v21, 1
+; GFX942-NEXT: v_readlane_b32 s33, v21, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: s_add_i32 s2, s32, 0x4010
; GFX942-NEXT: scratch_load_dword v21, off, s2 ; 4-byte Folded Reload
@@ -850,24 +851,24 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX10_1-NEXT: buffer_store_dword v21, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_1-NEXT: v_writelane_b32 v21, s30, 0
+; GFX10_1-NEXT: v_writelane_b32 v21, s33, 0
; GFX10_1-NEXT: s_and_b32 s59, 0, exec_lo
-; GFX10_1-NEXT: v_writelane_b32 v21, s31, 1
-; GFX10_1-NEXT: v_writelane_b32 v21, s33, 2
-; GFX10_1-NEXT: v_writelane_b32 v21, s34, 3
-; GFX10_1-NEXT: v_writelane_b32 v21, s35, 4
-; GFX10_1-NEXT: v_writelane_b32 v21, s36, 5
-; GFX10_1-NEXT: v_writelane_b32 v21, s37, 6
-; GFX10_1-NEXT: v_writelane_b32 v21, s38, 7
-; GFX10_1-NEXT: v_writelane_b32 v21, s39, 8
-; GFX10_1-NEXT: v_writelane_b32 v21, s48, 9
-; GFX10_1-NEXT: v_writelane_b32 v21, s49, 10
-; GFX10_1-NEXT: v_writelane_b32 v21, s50, 11
-; GFX10_1-NEXT: v_writelane_b32 v21, s51, 12
-; GFX10_1-NEXT: v_writelane_b32 v21, s52, 13
-; GFX10_1-NEXT: v_writelane_b32 v21, s53, 14
-; GFX10_1-NEXT: v_writelane_b32 v21, s54, 15
-; GFX10_1-NEXT: v_writelane_b32 v21, s55, 16
+; GFX10_1-NEXT: v_writelane_b32 v21, s34, 1
+; GFX10_1-NEXT: v_writelane_b32 v21, s35, 2
+; GFX10_1-NEXT: v_writelane_b32 v21, s36, 3
+; GFX10_1-NEXT: v_writelane_b32 v21, s37, 4
+; GFX10_1-NEXT: v_writelane_b32 v21, s38, 5
+; GFX10_1-NEXT: v_writelane_b32 v21, s39, 6
+; GFX10_1-NEXT: v_writelane_b32 v21, s48, 7
+; GFX10_1-NEXT: v_writelane_b32 v21, s49, 8
+; GFX10_1-NEXT: v_writelane_b32 v21, s50, 9
+; GFX10_1-NEXT: v_writelane_b32 v21, s51, 10
+; GFX10_1-NEXT: v_writelane_b32 v21, s52, 11
+; GFX10_1-NEXT: v_writelane_b32 v21, s53, 12
+; GFX10_1-NEXT: v_writelane_b32 v21, s54, 13
+; GFX10_1-NEXT: v_writelane_b32 v21, s55, 14
+; GFX10_1-NEXT: v_writelane_b32 v21, s30, 15
+; GFX10_1-NEXT: v_writelane_b32 v21, s31, 16
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
; GFX10_1-NEXT: ;;#ASMEND
@@ -878,23 +879,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc
; GFX10_1-NEXT: ;;#ASMEND
-; GFX10_1-NEXT: v_readlane_b32 s55, v21, 16
-; GFX10_1-NEXT: v_readlane_b32 s54, v21, 15
-; GFX10_1-NEXT: v_readlane_b32 s53, v21, 14
-; GFX10_1-NEXT: v_readlane_b32 s52, v21, 13
-; GFX10_1-NEXT: v_readlane_b32 s51, v21, 12
-; GFX10_1-NEXT: v_readlane_b32 s50, v21, 11
-; GFX10_1-NEXT: v_readlane_b32 s49, v21, 10
-; GFX10_1-NEXT: v_readlane_b32 s48, v21, 9
-; GFX10_1-NEXT: v_readlane_b32 s39, v21, 8
-; GFX10_1-NEXT: v_readlane_b32 s38, v21, 7
-; GFX10_1-NEXT: v_readlane_b32 s37, v21, 6
-; GFX10_1-NEXT: v_readlane_b32 s36, v21, 5
-; GFX10_1-NEXT: v_readlane_b32 s35, v21, 4
-; GFX10_1-NEXT: v_readlane_b32 s34, v21, 3
-; GFX10_1-NEXT: v_readlane_b32 s33, v21, 2
-; GFX10_1-NEXT: v_readlane_b32 s31, v21, 1
-; GFX10_1-NEXT: v_readlane_b32 s30, v21, 0
+; GFX10_1-NEXT: v_readlane_b32 s30, v21, 15
+; GFX10_1-NEXT: v_readlane_b32 s31, v21, 16
+; GFX10_1-NEXT: v_readlane_b32 s55, v21, 14
+; GFX10_1-NEXT: v_readlane_b32 s54, v21, 13
+; GFX10_1-NEXT: v_readlane_b32 s53, v21, 12
+; GFX10_1-NEXT: v_readlane_b32 s52, v21, 11
+; GFX10_1-NEXT: v_readlane_b32 s51, v21, 10
+; GFX10_1-NEXT: v_readlane_b32 s50, v21, 9
+; GFX10_1-NEXT: v_readlane_b32 s49, v21, 8
+; GFX10_1-NEXT: v_readlane_b32 s48, v21, 7
+; GFX10_1-NEXT: v_readlane_b32 s39, v21, 6
+; GFX10_1-NEXT: v_readlane_b32 s38, v21, 5
+; GFX10_1-NEXT: v_readlane_b32 s37, v21, 4
+; GFX10_1-NEXT: v_readlane_b32 s36, v21, 3
+; GFX10_1-NEXT: v_readlane_b32 s35, v21, 2
+; GFX10_1-NEXT: v_readlane_b32 s34, v21, 1
+; GFX10_1-NEXT: v_readlane_b32 s33, v21, 0
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x80200
; GFX10_1-NEXT: buffer_load_dword v21, off, s[0:3], s5 ; 4-byte Folded Reload
@@ -910,24 +911,24 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX10_3-NEXT: s_add_i32 s5, s32, 0x80200
; GFX10_3-NEXT: buffer_store_dword v21, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_3-NEXT: v_writelane_b32 v21, s30, 0
+; GFX10_3-NEXT: v_writelane_b32 v21, s33, 0
; GFX10_3-NEXT: s_and_b32 s59, 0, exec_lo
-; GFX10_3-NEXT: v_writelane_b32 v21, s31, 1
-; GFX10_3-NEXT: v_writelane_b32 v21, s33, 2
-; GFX10_3-NEXT: v_writelane_b32 v21, s34, 3
-; GFX10_3-NEXT: v_writelane_b32 v21, s35, 4
-; GFX10_3-NEXT: v_writelane_b32 v21, s36, 5
-; GFX10_3-NEXT: v_writelane_b32 v21, s37, 6
-; GFX10_3-NEXT: v_writelane_b32 v21, s38, 7
-; GFX10_3-NEXT: v_writelane_b32 v21, s39, 8
-; GFX10_3-NEXT: v_writelane_b32 v21, s48, 9
-; GFX10_3-NEXT: v_writelane_b32 v21, s49, 10
-; GFX10_3-NEXT: v_writelane_b32 v21, s50, 11
-; GFX10_3-NEXT: v_writelane_b32 v21, s51, 12
-; GFX10_3-NEXT: v_writelane_b32 v21, s52, 13
-; GFX10_3-NEXT: v_writelane_b32 v21, s53, 14
-; GFX10_3-NEXT: v_writelane_b32 v21, s54, 15
-; GFX10_3-NEXT: v_writelane_b32 v21, s55, 16
+; GFX10_3-NEXT: v_writelane_b32 v21, s34, 1
+; GFX10_3-NEXT: v_writelane_b32 v21, s35, 2
+; GFX10_3-NEXT: v_writelane_b32 v21, s36, 3
+; GFX10_3-NEXT: v_writelane_b32 v21, s37, 4
+; GFX10_3-NEXT: v_writelane_b32 v21, s38, 5
+; GFX10_3-NEXT: v_writelane_b32 v21, s39, 6
+; GFX10_3-NEXT: v_writelane_b32 v21, s48, 7
+; GFX10_3-NEXT: v_writelane_b32 v21, s49, 8
+; GFX10_3-NEXT: v_writelane_b32 v21, s50, 9
+; GFX10_3-NEXT: v_writelane_b32 v21, s51, 10
+; GFX10_3-NEXT: v_writelane_b32 v21, s52, 11
+; GFX10_3-NEXT: v_writelane_b32 v21, s53, 12
+; GFX10_3-NEXT: v_writelane_b32 v21, s54, 13
+; GFX10_3-NEXT: v_writelane_b32 v21, s55, 14
+; GFX10_3-NEXT: v_writelane_b32 v21, s30, 15
+; GFX10_3-NEXT: v_writelane_b32 v21, s31, 16
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
; GFX10_3-NEXT: ;;#ASMEND
@@ -938,23 +939,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc
; GFX10_3-NEXT: ;;#ASMEND
-; GFX10_3-NEXT: v_readlane_b32 s55, v21, 16
-; GFX10_3-NEXT: v_readlane_b32 s54, v21, 15
-; GFX10_3-NEXT: v_readlane_b32 s53, v21, 14
-; GFX10_3-NEXT: v_readlane_b32 s52, v21, 13
-; GFX10_3-NEXT: v_readlane_b32 s51, v21, 12
-; GFX10_3-NEXT: v_readlane_b32 s50, v21, 11
-; GFX10_3-NEXT: v_readlane_b32 s49, v21, 10
-; GFX10_3-NEXT: v_readlane_b32 s48, v21, 9
-; GFX10_3-NEXT: v_readlane_b32 s39, v21, 8
-; GFX10_3-NEXT: v_readlane_b32 s38, v21, 7
-; GFX10_3-NEXT: v_readlane_b32 s37, v21, 6
-; GFX10_3-NEXT: v_readlane_b32 s36, v21, 5
-; GFX10_3-NEXT: v_readlane_b32 s35, v21, 4
-; GFX10_3-NEXT: v_readlane_b32 s34, v21, 3
-; GFX10_3-NEXT: v_readlane_b32 s33, v21, 2
-; GFX10_3-NEXT: v_readlane_b32 s31, v21, 1
-; GFX10_3-NEXT: v_readlane_b32 s30, v21, 0
+; GFX10_3-NEXT: v_readlane_b32 s30, v21, 15
+; GFX10_3-NEXT: v_readlane_b32 s31, v21, 16
+; GFX10_3-NEXT: v_readlane_b32 s55, v21, 14
+; GFX10_3-NEXT: v_readlane_b32 s54, v21, 13
+; GFX10_3-NEXT: v_readlane_b32 s53, v21, 12
+; GFX10_3-NEXT: v_readlane_b32 s52, v21, 11
+; GFX10_3-NEXT: v_readlane_b32 s51, v21, 10
+; GFX10_3-NEXT: v_readlane_b32 s50, v21, 9
+; GFX10_3-NEXT: v_readlane_b32 s49, v21, 8
+; GFX10_3-NEXT: v_readlane_b32 s48, v21, 7
+; GFX10_3-NEXT: v_readlane_b32 s39, v21, 6
+; GFX10_3-NEXT: v_readlane_b32 s38, v21, 5
+; GFX10_3-NEXT: v_readlane_b32 s37, v21, 4
+; GFX10_3-NEXT: v_readlane_b32 s36, v21, 3
+; GFX10_3-NEXT: v_readlane_b32 s35, v21, 2
+; GFX10_3-NEXT: v_readlane_b32 s34, v21, 1
+; GFX10_3-NEXT: v_readlane_b32 s33, v21, 0
; GFX10_3-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_3-NEXT: s_add_i32 s5, s32, 0x80200
; GFX10_3-NEXT: buffer_load_dword v21, off, s[0:3], s5 ; 4-byte Folded Reload
@@ -969,24 +970,24 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX11-NEXT: s_add_i32 s1, s32, 0x4010
; GFX11-NEXT: scratch_store_b32 off, v21, s1 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-NEXT: v_writelane_b32 v21, s30, 0
+; GFX11-NEXT: v_writelane_b32 v21, s33, 0
; GFX11-NEXT: s_and_b32 s59, 0, exec_lo
-; GFX11-NEXT: v_writelane_b32 v21, s31, 1
-; GFX11-NEXT: v_writelane_b32 v21, s33, 2
-; GFX11-NEXT: v_writelane_b32 v21, s34, 3
-; GFX11-NEXT: v_writelane_b32 v21, s35, 4
-; GFX11-NEXT: v_writelane_b32 v21, s36, 5
-; GFX11-NEXT: v_writelane_b32 v21, s37, 6
-; GFX11-NEXT: v_writelane_b32 v21, s38, 7
-; GFX11-NEXT: v_writelane_b32 v21, s39, 8
-; GFX11-NEXT: v_writelane_b32 v21, s48, 9
-; GFX11-NEXT: v_writelane_b32 v21, s49, 10
-; GFX11-NEXT: v_writelane_b32 v21, s50, 11
-; GFX11-NEXT: v_writelane_b32 v21, s51, 12
-; GFX11-NEXT: v_writelane_b32 v21, s52, 13
-; GFX11-NEXT: v_writelane_b32 v21, s53, 14
-; GFX11-NEXT: v_writelane_b32 v21, s54, 15
-; GFX11-NEXT: v_writelane_b32 v21, s55, 16
+; GFX11-NEXT: v_writelane_b32 v21, s34, 1
+; GFX11-NEXT: v_writelane_b32 v21, s35, 2
+; GFX11-NEXT: v_writelane_b32 v21, s36, 3
+; GFX11-NEXT: v_writelane_b32 v21, s37, 4
+; GFX11-NEXT: v_writelane_b32 v21, s38, 5
+; GFX11-NEXT: v_writelane_b32 v21, s39, 6
+; GFX11-NEXT: v_writelane_b32 v21, s48, 7
+; GFX11-NEXT: v_writelane_b32 v21, s49, 8
+; GFX11-NEXT: v_writelane_b32 v21, s50, 9
+; GFX11-NEXT: v_writelane_b32 v21, s51, 10
+; GFX11-NEXT: v_writelane_b32 v21, s52, 11
+; GFX11-NEXT: v_writelane_b32 v21, s53, 12
+; GFX11-NEXT: v_writelane_b32 v21, s54, 13
+; GFX11-NEXT: v_writelane_b32 v21, s55, 14
+; GFX11-NEXT: v_writelane_b32 v21, s30, 15
+; GFX11-NEXT: v_writelane_b32 v21, s31, 16
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
; GFX11-NEXT: ;;#ASMEND
@@ -999,23 +1000,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: v_readlane_b32 s55, v21, 16
-; GFX11-NEXT: v_readlane_b32 s54, v21, 15
-; GFX11-NEXT: v_readlane_b32 s53, v21, 14
-; GFX11-NEXT: v_readlane_b32 s52, v21, 13
-; GFX11-NEXT: v_readlane_b32 s51, v21, 12
-; GFX11-NEXT: v_readlane_b32 s50, v21, 11
-; GFX11-NEXT: v_readlane_b32 s49, v21, 10
-; GFX11-NEXT: v_readlane_b32 s48, v21, 9
-; GFX11-NEXT: v_readlane_b32 s39, v21, 8
-; GFX11-NEXT: v_readlane_b32 s38, v21, 7
-; GFX11-NEXT: v_readlane_b32 s37, v21, 6
-; GFX11-NEXT: v_readlane_b32 s36, v21, 5
-; GFX11-NEXT: v_readlane_b32 s35, v21, 4
-; GFX11-NEXT: v_readlane_b32 s34, v21, 3
-; GFX11-NEXT: v_readlane_b32 s33, v21, 2
-; GFX11-NEXT: v_readlane_b32 s31, v21, 1
-; GFX11-NEXT: v_readlane_b32 s30, v21, 0
+; GFX11-NEXT: v_readlane_b32 s30, v21, 15
+; GFX11-NEXT: v_readlane_b32 s31, v21, 16
+; GFX11-NEXT: v_readlane_b32 s55, v21, 14
+; GFX11-NEXT: v_readlane_b32 s54, v21, 13
+; GFX11-NEXT: v_readlane_b32 s53, v21, 12
+; GFX11-NEXT: v_readlane_b32 s52, v21, 11
+; GFX11-NEXT: v_readlane_b32 s51, v21, 10
+; GFX11-NEXT: v_readlane_b32 s50, v21, 9
+; GFX11-NEXT: v_readlane_b32 s49, v21, 8
+; GFX11-NEXT: v_readlane_b32 s48, v21, 7
+; GFX11-NEXT: v_readlane_b32 s39, v21, 6
+; GFX11-NEXT: v_readlane_b32 s38, v21, 5
+; GFX11-NEXT: v_readlane_b32 s37, v21, 4
+; GFX11-NEXT: v_readlane_b32 s36, v21, 3
+; GFX11-NEXT: v_readlane_b32 s35, v21, 2
+; GFX11-NEXT: v_readlane_b32 s34, v21, 1
+; GFX11-NEXT: v_readlane_b32 s33, v21, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: s_add_i32 s1, s32, 0x4010
; GFX11-NEXT: scratch_load_b32 v21, off, s1 ; 4-byte Folded Reload
@@ -1034,24 +1035,24 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX12-NEXT: scratch_store_b32 off, v21, s32 offset:16384 ; 4-byte Folded Spill
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s0
-; GFX12-NEXT: v_writelane_b32 v21, s30, 0
+; GFX12-NEXT: v_writelane_b32 v21, s33, 0
; GFX12-NEXT: s_and_b32 s59, 0, exec_lo
-; GFX12-NEXT: v_writelane_b32 v21, s31, 1
-; GFX12-NEXT: v_writelane_b32 v21, s33, 2
-; GFX12-NEXT: v_writelane_b32 v21, s34, 3
-; GFX12-NEXT: v_writelane_b32 v21, s35, 4
-; GFX12-NEXT: v_writelane_b32 v21, s36, 5
-; GFX12-NEXT: v_writelane_b32 v21, s37, 6
-; GFX12-NEXT: v_writelane_b32 v21, s38, 7
-; GFX12-NEXT: v_writelane_b32 v21, s39, 8
-; GFX12-NEXT: v_writelane_b32 v21, s48, 9
-; GFX12-NEXT: v_writelane_b32 v21, s49, 10
-; GFX12-NEXT: v_writelane_b32 v21, s50, 11
-; GFX12-NEXT: v_writelane_b32 v21, s51, 12
-; GFX12-NEXT: v_writelane_b32 v21, s52, 13
-; GFX12-NEXT: v_writelane_b32 v21, s53, 14
-; GFX12-NEXT: v_writelane_b32 v21, s54, 15
-; GFX12-NEXT: v_writelane_b32 v21, s55, 16
+; GFX12-NEXT: v_writelane_b32 v21, s34, 1
+; GFX12-NEXT: v_writelane_b32 v21, s35, 2
+; GFX12-NEXT: v_writelane_b32 v21, s36, 3
+; GFX12-NEXT: v_writelane_b32 v21, s37, 4
+; GFX12-NEXT: v_writelane_b32 v21, s38, 5
+; GFX12-NEXT: v_writelane_b32 v21, s39, 6
+; GFX12-NEXT: v_writelane_b32 v21, s48, 7
+; GFX12-NEXT: v_writelane_b32 v21, s49, 8
+; GFX12-NEXT: v_writelane_b32 v21, s50, 9
+; GFX12-NEXT: v_writelane_b32 v21, s51, 10
+; GFX12-NEXT: v_writelane_b32 v21, s52, 11
+; GFX12-NEXT: v_writelane_b32 v21, s53, 12
+; GFX12-NEXT: v_writelane_b32 v21, s54, 13
+; GFX12-NEXT: v_writelane_b32 v21, s55, 14
+; GFX12-NEXT: v_writelane_b32 v21, s30, 15
+; GFX12-NEXT: v_writelane_b32 v21, s31, 16
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
; GFX12-NEXT: ;;#ASMEND
@@ -1061,23 +1062,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX12-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc
; GFX12-NEXT: ;;#ASMEND
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_readlane_b32 s55, v21, 16
-; GFX12-NEXT: v_readlane_b32 s54, v21, 15
-; GFX12-NEXT: v_readlane_b32 s53, v21, 14
-; GFX12-NEXT: v_readlane_b32 s52, v21, 13
-; GFX12-NEXT: v_readlane_b32 s51, v21, 12
-; GFX12-NEXT: v_readlane_b32 s50, v21, 11
-; GFX12-NEXT: v_readlane_b32 s49, v21, 10
-; GFX12-NEXT: v_readlane_b32 s48, v21, 9
-; GFX12-NEXT: v_readlane_b32 s39, v21, 8
-; GFX12-NEXT: v_readlane_b32 s38, v21, 7
-; GFX12-NEXT: v_readlane_b32 s37, v21, 6
-; GFX12-NEXT: v_readlane_b32 s36, v21, 5
-; GFX12-NEXT: v_readlane_b32 s35, v21, 4
-; GFX12-NEXT: v_readlane_b32 s34, v21, 3
-; GFX12-NEXT: v_readlane_b32 s33, v21, 2
-; GFX12-NEXT: v_readlane_b32 s31, v21, 1
-; GFX12-NEXT: v_readlane_b32 s30, v21, 0
+; GFX12-NEXT: v_readlane_b32 s30, v21, 15
+; GFX12-NEXT: v_readlane_b32 s31, v21, 16
+; GFX12-NEXT: v_readlane_b32 s55, v21, 14
+; GFX12-NEXT: v_readlane_b32 s54, v21, 13
+; GFX12-NEXT: v_readlane_b32 s53, v21, 12
+; GFX12-NEXT: v_readlane_b32 s52, v21, 11
+; GFX12-NEXT: v_readlane_b32 s51, v21, 10
+; GFX12-NEXT: v_readlane_b32 s50, v21, 9
+; GFX12-NEXT: v_readlane_b32 s49, v21, 8
+; GFX12-NEXT: v_readlane_b32 s48, v21, 7
+; GFX12-NEXT: v_readlane_b32 s39, v21, 6
+; GFX12-NEXT: v_readlane_b32 s38, v21, 5
+; GFX12-NEXT: v_readlane_b32 s37, v21, 4
+; GFX12-NEXT: v_readlane_b32 s36, v21, 3
+; GFX12-NEXT: v_readlane_b32 s35, v21, 2
+; GFX12-NEXT: v_readlane_b32 s34, v21, 1
+; GFX12-NEXT: v_readlane_b32 s33, v21, 0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v21, off, s32 offset:16384 ; 4-byte Folded Reload
; GFX12-NEXT: s_wait_alu 0xfffe
@@ -1135,30 +1136,30 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX7-NEXT: s_mov_b64 exec, s[4:5]
; GFX7-NEXT: v_writelane_b32 v23, s28, 17
; GFX7-NEXT: v_writelane_b32 v23, s29, 18
-; GFX7-NEXT: v_writelane_b32 v23, s30, 0
-; GFX7-NEXT: v_writelane_b32 v23, s31, 1
-; GFX7-NEXT: v_writelane_b32 v23, s33, 2
-; GFX7-NEXT: v_writelane_b32 v23, s34, 3
-; GFX7-NEXT: v_writelane_b32 v23, s35, 4
-; GFX7-NEXT: v_writelane_b32 v23, s36, 5
-; GFX7-NEXT: v_writelane_b32 v23, s37, 6
-; GFX7-NEXT: v_writelane_b32 v23, s38, 7
-; GFX7-NEXT: v_writelane_b32 v23, s39, 8
-; GFX7-NEXT: v_writelane_b32 v23, s48, 9
-; GFX7-NEXT: v_writelane_b32 v23, s49, 10
-; GFX7-NEXT: v_writelane_b32 v23, s50, 11
-; GFX7-NEXT: v_writelane_b32 v23, s51, 12
-; GFX7-NEXT: v_writelane_b32 v23, s52, 13
+; GFX7-NEXT: v_writelane_b32 v23, s33, 0
+; GFX7-NEXT: v_writelane_b32 v23, s34, 1
+; GFX7-NEXT: v_writelane_b32 v23, s35, 2
+; GFX7-NEXT: v_writelane_b32 v23, s36, 3
+; GFX7-NEXT: v_writelane_b32 v23, s37, 4
+; GFX7-NEXT: v_writelane_b32 v23, s38, 5
+; GFX7-NEXT: v_writelane_b32 v23, s39, 6
+; GFX7-NEXT: v_writelane_b32 v23, s48, 7
+; GFX7-NEXT: v_writelane_b32 v23, s49, 8
+; GFX7-NEXT: v_writelane_b32 v23, s50, 9
+; GFX7-NEXT: v_writelane_b32 v23, s51, 10
+; GFX7-NEXT: v_writelane_b32 v23, s52, 11
+; GFX7-NEXT: v_writelane_b32 v23, s53, 12
+; GFX7-NEXT: v_writelane_b32 v23, s54, 13
; GFX7-NEXT: s_lshr_b32 s5, s32, 6
-; GFX7-NEXT: v_writelane_b32 v23, s53, 14
+; GFX7-NEXT: v_writelane_b32 v23, s55, 14
; GFX7-NEXT: v_lshr_b32_e64 v0, s32, 6
; GFX7-NEXT: s_add_i32 s4, s5, 0x4240
; GFX7-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
-; GFX7-NEXT: v_writelane_b32 v23, s54, 15
+; GFX7-NEXT: v_writelane_b32 v23, s30, 15
; GFX7-NEXT: v_add_i32_e32 v0, vcc, 64, v0
; GFX7-NEXT: v_writelane_b32 v22, s4, 0
; GFX7-NEXT: s_and_b64 s[4:5], 0, exec
-; GFX7-NEXT: v_writelane_b32 v23, s55, 16
+; GFX7-NEXT: v_writelane_b32 v23, s31, 16
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use alloca0 v0
; GFX7-NEXT: ;;#ASMEND
@@ -1169,23 +1170,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc
; GFX7-NEXT: ;;#ASMEND
-; GFX7-NEXT: v_readlane_b32 s55, v23, 16
-; GFX7-NEXT: v_readlane_b32 s54, v23, 15
-; GFX7-NEXT: v_readlane_b32 s53, v23, 14
-; GFX7-NEXT: v_readlane_b32 s52, v23, 13
-; GFX7-NEXT: v_readlane_b32 s51, v23, 12
-; GFX7-NEXT: v_readlane_b32 s50, v23, 11
-; GFX7-NEXT: v_readlane_b32 s49, v23, 10
-; GFX7-NEXT: v_readlane_b32 s48, v23, 9
-; GFX7-NEXT: v_readlane_b32 s39, v23, 8
-; GFX7-NEXT: v_readlane_b32 s38, v23, 7
-; GFX7-NEXT: v_readlane_b32 s37, v23, 6
-; GFX7-NEXT: v_readlane_b32 s36, v23, 5
-; GFX7-NEXT: v_readlane_b32 s35, v23, 4
-; GFX7-NEXT: v_readlane_b32 s34, v23, 3
-; GFX7-NEXT: v_readlane_b32 s33, v23, 2
-; GFX7-NEXT: v_readlane_b32 s31, v23, 1
-; GFX7-NEXT: v_readlane_b32 s30, v23, 0
+; GFX7-NEXT: v_readlane_b32 s30, v23, 15
+; GFX7-NEXT: v_readlane_b32 s31, v23, 16
+; GFX7-NEXT: v_readlane_b32 s55, v23, 14
+; GFX7-NEXT: v_readlane_b32 s54, v23, 13
+; GFX7-NEXT: v_readlane_b32 s53, v23, 12
+; GFX7-NEXT: v_readlane_b32 s52, v23, 11
+; GFX7-NEXT: v_readlane_b32 s51, v23, 10
+; GFX7-NEXT: v_readlane_b32 s50, v23, 9
+; GFX7-NEXT: v_readlane_b32 s49, v23, 8
+; GFX7-NEXT: v_readlane_b32 s48, v23, 7
+; GFX7-NEXT: v_readlane_b32 s39, v23, 6
+; GFX7-NEXT: v_readlane_b32 s38, v23, 5
+; GFX7-NEXT: v_readlane_b32 s37, v23, 4
+; GFX7-NEXT: v_readlane_b32 s36, v23, 3
+; GFX7-NEXT: v_readlane_b32 s35, v23, 2
+; GFX7-NEXT: v_readlane_b32 s34, v23, 1
+; GFX7-NEXT: v_readlane_b32 s33, v23, 0
; GFX7-NEXT: v_readlane_b32 s28, v23, 17
; GFX7-NEXT: v_readlane_b32 s29, v23, 18
; GFX7-NEXT: s_xor_saveexec_b64 s[4:5], -1
@@ -1206,30 +1207,30 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX8-NEXT: s_add_i32 s6, s32, 0x201100
; GFX8-NEXT: buffer_store_dword v22, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
-; GFX8-NEXT: v_writelane_b32 v23, s30, 0
-; GFX8-NEXT: v_writelane_b32 v23, s31, 1
-; GFX8-NEXT: v_writelane_b32 v23, s33, 2
-; GFX8-NEXT: v_writelane_b32 v23, s34, 3
-; GFX8-NEXT: v_writelane_b32 v23, s35, 4
-; GFX8-NEXT: v_writelane_b32 v23, s36, 5
-; GFX8-NEXT: v_writelane_b32 v23, s37, 6
-; GFX8-NEXT: v_writelane_b32 v23, s38, 7
-; GFX8-NEXT: v_writelane_b32 v23, s39, 8
-; GFX8-NEXT: v_writelane_b32 v23, s48, 9
-; GFX8-NEXT: v_writelane_b32 v23, s49, 10
-; GFX8-NEXT: v_writelane_b32 v23, s50, 11
-; GFX8-NEXT: v_writelane_b32 v23, s51, 12
-; GFX8-NEXT: v_writelane_b32 v23, s52, 13
+; GFX8-NEXT: v_writelane_b32 v23, s33, 0
+; GFX8-NEXT: v_writelane_b32 v23, s34, 1
+; GFX8-NEXT: v_writelane_b32 v23, s35, 2
+; GFX8-NEXT: v_writelane_b32 v23, s36, 3
+; GFX8-NEXT: v_writelane_b32 v23, s37, 4
+; GFX8-NEXT: v_writelane_b32 v23, s38, 5
+; GFX8-NEXT: v_writelane_b32 v23, s39, 6
+; GFX8-NEXT: v_writelane_b32 v23, s48, 7
+; GFX8-NEXT: v_writelane_b32 v23, s49, 8
+; GFX8-NEXT: v_writelane_b32 v23, s50, 9
+; GFX8-NEXT: v_writelane_b32 v23, s51, 10
+; GFX8-NEXT: v_writelane_b32 v23, s52, 11
+; GFX8-NEXT: v_writelane_b32 v23, s53, 12
+; GFX8-NEXT: v_writelane_b32 v23, s54, 13
; GFX8-NEXT: s_lshr_b32 s5, s32, 6
-; GFX8-NEXT: v_writelane_b32 v23, s53, 14
+; GFX8-NEXT: v_writelane_b32 v23, s55, 14
; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32
; GFX8-NEXT: s_add_i32 s4, s5, 0x4240
; GFX8-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
-; GFX8-NEXT: v_writelane_b32 v23, s54, 15
+; GFX8-NEXT: v_writelane_b32 v23, s30, 15
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 64, v0
; GFX8-NEXT: v_writelane_b32 v22, s4, 0
; GFX8-NEXT: s_and_b64 s[4:5], 0, exec
-; GFX8-NEXT: v_writelane_b32 v23, s55, 16
+; GFX8-NEXT: v_writelane_b32 v23, s31, 16
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use alloca0 v0
; GFX8-NEXT: ;;#ASMEND
@@ -1241,23 +1242,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc
; GFX8-NEXT: ;;#ASMEND
-; GFX8-NEXT: v_readlane_b32 s55, v23, 16
-; GFX8-NEXT: v_readlane_b32 s54, v23, 15
-; GFX8-NEXT: v_readlane_b32 s53, v23, 14
-; GFX8-NEXT: v_readlane_b32 s52, v23, 13
-; GFX8-NEXT: v_readlane_b32 s51, v23, 12
-; GFX8-NEXT: v_readlane_b32 s50, v23, 11
-; GFX8-NEXT: v_readlane_b32 s49, v23, 10
-; GFX8-NEXT: v_readlane_b32 s48, v23, 9
-; GFX8-NEXT: v_readlane_b32 s39, v23, 8
-; GFX8-NEXT: v_readlane_b32 s38, v23, 7
-; GFX8-NEXT: v_readlane_b32 s37, v23, 6
-; GFX8-NEXT: v_readlane_b32 s36, v23, 5
-; GFX8-NEXT: v_readlane_b32 s35, v23, 4
-; GFX8-NEXT: v_readlane_b32 s34, v23, 3
-; GFX8-NEXT: v_readlane_b32 s33, v23, 2
-; GFX8-NEXT: v_readlane_b32 s31, v23, 1
-; GFX8-NEXT: v_readlane_b32 s30, v23, 0
+; GFX8-NEXT: v_readlane_b32 s30, v23, 15
+; GFX8-NEXT: v_readlane_b32 s31, v23, 16
+; GFX8-NEXT: v_readlane_b32 s55, v23, 14
+; GFX8-NEXT: v_readlane_b32 s54, v23, 13
+; GFX8-NEXT: v_readlane_b32 s53, v23, 12
+; GFX8-NEXT: v_readlane_b32 s52, v23, 11
+; GFX8-NEXT: v_readlane_b32 s51, v23, 10
+; GFX8-NEXT: v_readlane_b32 s50, v23, 9
+; GFX8-NEXT: v_readlane_b32 s49, v23, 8
+; GFX8-NEXT: v_readlane_b32 s48, v23, 7
+; GFX8-NEXT: v_readlane_b32 s39, v23, 6
+; GFX8-NEXT: v_readlane_b32 s38, v23, 5
+; GFX8-NEXT: v_readlane_b32 s37, v23, 4
+; GFX8-NEXT: v_readlane_b32 s36, v23, 3
+; GFX8-NEXT: v_readlane_b32 s35, v23, 2
+; GFX8-NEXT: v_readlane_b32 s34, v23, 1
+; GFX8-NEXT: v_readlane_b32 s33, v23, 0
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: s_add_i32 s6, s32, 0x201000
; GFX8-NEXT: buffer_load_dword v23, off, s[0:3], s6 ; 4-byte Folded Reload
@@ -1276,30 +1277,30 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX900-NEXT: s_add_i32 s6, s32, 0x201100
; GFX900-NEXT: buffer_store_dword v22, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
-; GFX900-NEXT: v_writelane_b32 v23, s30, 0
-; GFX900-NEXT: v_writelane_b32 v23, s31, 1
-; GFX900-NEXT: v_writelane_b32 v23, s33, 2
-; GFX900-NEXT: v_writelane_b32 v23, s34, 3
-; GFX900-NEXT: v_writelane_b32 v23, s35, 4
-; GFX900-NEXT: v_writelane_b32 v23, s36, 5
-; GFX900-NEXT: v_writelane_b32 v23, s37, 6
-; GFX900-NEXT: v_writelane_b32 v23, s38, 7
-; GFX900-NEXT: v_writelane_b32 v23, s39, 8
-; GFX900-NEXT: v_writelane_b32 v23, s48, 9
-; GFX900-NEXT: v_writelane_b32 v23, s49, 10
-; GFX900-NEXT: v_writelane_b32 v23, s50, 11
-; GFX900-NEXT: v_writelane_b32 v23, s51, 12
-; GFX900-NEXT: v_writelane_b32 v23, s52, 13
+; GFX900-NEXT: v_writelane_b32 v23, s33, 0
+; GFX900-NEXT: v_writelane_b32 v23, s34, 1
+; GFX900-NEXT: v_writelane_b32 v23, s35, 2
+; GFX900-NEXT: v_writelane_b32 v23, s36, 3
+; GFX900-NEXT: v_writelane_b32 v23, s37, 4
+; GFX900-NEXT: v_writelane_b32 v23, s38, 5
+; GFX900-NEXT: v_writelane_b32 v23, s39, 6
+; GFX900-NEXT: v_writelane_b32 v23, s48, 7
+; GFX900-NEXT: v_writelane_b32 v23, s49, 8
+; GFX900-NEXT: v_writelane_b32 v23, s50, 9
+; GFX900-NEXT: v_writelane_b32 v23, s51, 10
+; GFX900-NEXT: v_writelane_b32 v23, s52, 11
+; GFX900-NEXT: v_writelane_b32 v23, s53, 12
+; GFX900-NEXT: v_writelane_b32 v23, s54, 13
; GFX900-NEXT: s_lshr_b32 s5, s32, 6
-; GFX900-NEXT: v_writelane_b32 v23, s53, 14
+; GFX900-NEXT: v_writelane_b32 v23, s55, 14
; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32
; GFX900-NEXT: s_add_i32 s4, s5, 0x4240
; GFX900-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
-; GFX900-NEXT: v_writelane_b32 v23, s54, 15
+; GFX900-NEXT: v_writelane_b32 v23, s30, 15
; GFX900-NEXT: v_add_u32_e32 v0, 64, v0
; GFX900-NEXT: v_writelane_b32 v22, s4, 0
; GFX900-NEXT: s_and_b64 s[4:5], 0, exec
-; GFX900-NEXT: v_writelane_b32 v23, s55, 16
+; GFX900-NEXT: v_writelane_b32 v23, s31, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use alloca0 v0
; GFX900-NEXT: ;;#ASMEND
@@ -1311,23 +1312,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_readlane_b32 s55, v23, 16
-; GFX900-NEXT: v_readlane_b32 s54, v23, 15
-; GFX900-NEXT: v_readlane_b32 s53, v23, 14
-; GFX900-NEXT: v_readlane_b32 s52, v23, 13
-; GFX900-NEXT: v_readlane_b32 s51, v23, 12
-; GFX900-NEXT: v_readlane_b32 s50, v23, 11
-; GFX900-NEXT: v_readlane_b32 s49, v23, 10
-; GFX900-NEXT: v_readlane_b32 s48, v23, 9
-; GFX900-NEXT: v_readlane_b32 s39, v23, 8
-; GFX900-NEXT: v_readlane_b32 s38, v23, 7
-; GFX900-NEXT: v_readlane_b32 s37, v23, 6
-; GFX900-NEXT: v_readlane_b32 s36, v23, 5
-; GFX900-NEXT: v_readlane_b32 s35, v23, 4
-; GFX900-NEXT: v_readlane_b32 s34, v23, 3
-; GFX900-NEXT: v_readlane_b32 s33, v23, 2
-; GFX900-NEXT: v_readlane_b32 s31, v23, 1
-; GFX900-NEXT: v_readlane_b32 s30, v23, 0
+; GFX900-NEXT: v_readlane_b32 s30, v23, 15
+; GFX900-NEXT: v_readlane_b32 s31, v23, 16
+; GFX900-NEXT: v_readlane_b32 s55, v23, 14
+; GFX900-NEXT: v_readlane_b32 s54, v23, 13
+; GFX900-NEXT: v_readlane_b32 s53, v23, 12
+; GFX900-NEXT: v_readlane_b32 s52, v23, 11
+; GFX900-NEXT: v_readlane_b32 s51, v23, 10
+; GFX900-NEXT: v_readlane_b32 s50, v23, 9
+; GFX900-NEXT: v_readlane_b32 s49, v23, 8
+; GFX900-NEXT: v_readlane_b32 s48, v23, 7
+; GFX900-NEXT: v_readlane_b32 s39, v23, 6
+; GFX900-NEXT: v_readlane_b32 s38, v23, 5
+; GFX900-NEXT: v_readlane_b32 s37, v23, 4
+; GFX900-NEXT: v_readlane_b32 s36, v23, 3
+; GFX900-NEXT: v_readlane_b32 s35, v23, 2
+; GFX900-NEXT: v_readlane_b32 s34, v23, 1
+; GFX900-NEXT: v_readlane_b32 s33, v23, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: s_add_i32 s6, s32, 0x201000
; GFX900-NEXT: buffer_load_dword v23, off, s[0:3], s6 ; 4-byte Folded Reload
@@ -1344,28 +1345,29 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX942-NEXT: s_add_i32 s2, s32, 0x8040
; GFX942-NEXT: scratch_store_dword off, v22, s2 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
-; GFX942-NEXT: v_writelane_b32 v22, s30, 0
-; GFX942-NEXT: v_writelane_b32 v22, s31, 1
-; GFX942-NEXT: v_writelane_b32 v22, s33, 2
-; GFX942-NEXT: v_writelane_b32 v22, s34, 3
-; GFX942-NEXT: v_writelane_b32 v22, s35, 4
-; GFX942-NEXT: v_writelane_b32 v22, s36, 5
-; GFX942-NEXT: v_writelane_b32 v22, s37, 6
-; GFX942-NEXT: v_writelane_b32 v22, s38, 7
-; GFX942-NEXT: v_writelane_b32 v22, s39, 8
-; GFX942-NEXT: v_writelane_b32 v22, s48, 9
-; GFX942-NEXT: v_writelane_b32 v22, s49, 10
-; GFX942-NEXT: v_writelane_b32 v22, s50, 11
-; GFX942-NEXT: v_writelane_b32 v22, s51, 12
-; GFX942-NEXT: v_writelane_b32 v22, s52, 13
-; GFX942-NEXT: v_writelane_b32 v22, s53, 14
+; GFX942-NEXT: v_writelane_b32 v22, s33, 0
+; GFX942-NEXT: v_writelane_b32 v22, s34, 1
+; GFX942-NEXT: v_writelane_b32 v22, s35, 2
+; GFX942-NEXT: v_writelane_b32 v22, s36, 3
+; GFX942-NEXT: v_writelane_b32 v22, s37, 4
+; GFX942-NEXT: v_writelane_b32 v22, s38, 5
+; GFX942-NEXT: v_writelane_b32 v22, s39, 6
+; GFX942-NEXT: v_writelane_b32 v22, s48, 7
+; GFX942-NEXT: v_writelane_b32 v22, s49, 8
+; GFX942-NEXT: v_writelane_b32 v22, s50, 9
+; GFX942-NEXT: v_writelane_b32 v22, s51, 10
+; GFX942-NEXT: v_writelane_b32 v22, s52, 11
+; GFX942-NEXT: v_writelane_b32 v22, s53, 12
+; GFX942-NEXT: v_writelane_b32 v22, s54, 13
+; GFX942-NEXT: v_writelane_b32 v22, s55, 14
; GFX942-NEXT: s_add_i32 s0, s32, 64
-; GFX942-NEXT: v_writelane_b32 v22, s54, 15
+; GFX942-NEXT: v_writelane_b32 v22, s30, 15
; GFX942-NEXT: v_mov_b32_e32 v0, s0
-; GFX942-NEXT: v_writelane_b32 v22, s55, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use alloca0 v0
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: v_writelane_b32 v22, s31, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX942-NEXT: ;;#ASMEND
@@ -1376,23 +1378,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: v_readlane_b32 s55, v22, 16
-; GFX942-NEXT: v_readlane_b32 s54, v22, 15
-; GFX942-NEXT: v_readlane_b32 s53, v22, 14
-; GFX942-NEXT: v_readlane_b32 s52, v22, 13
-; GFX942-NEXT: v_readlane_b32 s51, v22, 12
-; GFX942-NEXT: v_readlane_b32 s50, v22, 11
-; GFX942-NEXT: v_readlane_b32 s49, v22, 10
-; GFX942-NEXT: v_readlane_b32 s48, v22, 9
-; GFX942-NEXT: v_readlane_b32 s39, v22, 8
-; GFX942-NEXT: v_readlane_b32 s38, v22, 7
-; GFX942-NEXT: v_readlane_b32 s37, v22, 6
-; GFX942-NEXT: v_readlane_b32 s36, v22, 5
-; GFX942-NEXT: v_readlane_b32 s35, v22, 4
-; GFX942-NEXT: v_readlane_b32 s34, v22, 3
-; GFX942-NEXT: v_readlane_b32 s33, v22, 2
-; GFX942-NEXT: v_readlane_b32 s31, v22, 1
-; GFX942-NEXT: v_readlane_b32 s30, v22, 0
+; GFX942-NEXT: v_readlane_b32 s30, v22, 15
+; GFX942-NEXT: v_readlane_b32 s31, v22, 16
+; GFX942-NEXT: v_readlane_b32 s55, v22, 14
+; GFX942-NEXT: v_readlane_b32 s54, v22, 13
+; GFX942-NEXT: v_readlane_b32 s53, v22, 12
+; GFX942-NEXT: v_readlane_b32 s52, v22, 11
+; GFX942-NEXT: v_readlane_b32 s51, v22, 10
+; GFX942-NEXT: v_readlane_b32 s50, v22, 9
+; GFX942-NEXT: v_readlane_b32 s49, v22, 8
+; GFX942-NEXT: v_readlane_b32 s48, v22, 7
+; GFX942-NEXT: v_readlane_b32 s39, v22, 6
+; GFX942-NEXT: v_readlane_b32 s38, v22, 5
+; GFX942-NEXT: v_readlane_b32 s37, v22, 4
+; GFX942-NEXT: v_readlane_b32 s36, v22, 3
+; GFX942-NEXT: v_readlane_b32 s35, v22, 2
+; GFX942-NEXT: v_readlane_b32 s34, v22, 1
+; GFX942-NEXT: v_readlane_b32 s33, v22, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: s_add_i32 s2, s32, 0x8040
; GFX942-NEXT: scratch_load_dword v22, off, s2 ; 4-byte Folded Reload
@@ -1408,31 +1410,31 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX10_1-NEXT: buffer_store_dword v22, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_1-NEXT: v_writelane_b32 v22, s30, 0
+; GFX10_1-NEXT: v_writelane_b32 v22, s33, 0
; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
; GFX10_1-NEXT: s_lshr_b32 s4, s32, 5
; GFX10_1-NEXT: s_add_i32 s58, s4, 0x4240
-; GFX10_1-NEXT: v_writelane_b32 v22, s31, 1
+; GFX10_1-NEXT: v_writelane_b32 v22, s34, 1
; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0
; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; use alloca0 v0
; GFX10_1-NEXT: ;;#ASMEND
-; GFX10_1-NEXT: v_writelane_b32 v22, s33, 2
-; GFX10_1-NEXT: v_writelane_b32 v22, s34, 3
-; GFX10_1-NEXT: v_writelane_b32 v22, s35, 4
-; GFX10_1-NEXT: v_writelane_b32 v22, s36, 5
-; GFX10_1-NEXT: v_writelane_b32 v22, s37, 6
-; GFX10_1-NEXT: v_writelane_b32 v22, s38, 7
-; GFX10_1-NEXT: v_writelane_b32 v22, s39, 8
-; GFX10_1-NEXT: v_writelane_b32 v22, s48, 9
-; GFX10_1-NEXT: v_writelane_b32 v22, s49, 10
-; GFX10_1-NEXT: v_writelane_b32 v22, s50, 11
-; GFX10_1-NEXT: v_writelane_b32 v22, s51, 12
-; GFX10_1-NEXT: v_writelane_b32 v22, s52, 13
-; GFX10_1-NEXT: v_writelane_b32 v22, s53, 14
-; GFX10_1-NEXT: v_writelane_b32 v22, s54, 15
-; GFX10_1-NEXT: v_writelane_b32 v22, s55, 16
+; GFX10_1-NEXT: v_writelane_b32 v22, s35, 2
+; GFX10_1-NEXT: v_writelane_b32 v22, s36, 3
+; GFX10_1-NEXT: v_writelane_b32 v22, s37, 4
+; GFX10_1-NEXT: v_writelane_b32 v22, s38, 5
+; GFX10_1-NEXT: v_writelane_b32 v22, s39, 6
+; GFX10_1-NEXT: v_writelane_b32 v22, s48, 7
+; GFX10_1-NEXT: v_writelane_b32 v22, s49, 8
+; GFX10_1-NEXT: v_writelane_b32 v22, s50, 9
+; GFX10_1-NEXT: v_writelane_b32 v22, s51, 10
+; GFX10_1-NEXT: v_writelane_b32 v22, s52, 11
+; GFX10_1-NEXT: v_writelane_b32 v22, s53, 12
+; GFX10_1-NEXT: v_writelane_b32 v22, s54, 13
+; GFX10_1-NEXT: v_writelane_b32 v22, s55, 14
+; GFX10_1-NEXT: v_writelane_b32 v22, s30, 15
+; GFX10_1-NEXT: v_writelane_b32 v22, s31, 16
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX10_1-NEXT: ;;#ASMEND
@@ -1441,23 +1443,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc
; GFX10_1-NEXT: ;;#ASMEND
-; GFX10_1-NEXT: v_readlane_b32 s55, v22, 16
-; GFX10_1-NEXT: v_readlane_b32 s54, v22, 15
-; GFX10_1-NEXT: v_readlane_b32 s53, v22, 14
-; GFX10_1-NEXT: v_readlane_b32 s52, v22, 13
-; GFX10_1-NEXT: v_readlane_b32 s51, v22, 12
-; GFX10_1-NEXT: v_readlane_b32 s50, v22, 11
-; GFX10_1-NEXT: v_readlane_b32 s49, v22, 10
-; GFX10_1-NEXT: v_readlane_b32 s48, v22, 9
-; GFX10_1-NEXT: v_readlane_b32 s39, v22, 8
-; GFX10_1-NEXT: v_readlane_b32 s38, v22, 7
-; GFX10_1-NEXT: v_readlane_b32 s37, v22, 6
-; GFX10_1-NEXT: v_readlane_b32 s36, v22, 5
-; GFX10_1-NEXT: v_readlane_b32 s35, v22, 4
-; GFX10_1-NEXT: v_readlane_b32 s34, v22, 3
-; GFX10_1-NEXT: v_readlane_b32 s33, v22, 2
-; GFX10_1-NEXT: v_readlane_b32 s31, v22, 1
-; GFX10_1-NEXT: v_readlane_b32 s30, v22, 0
+; GFX10_1-NEXT: v_readlane_b32 s30, v22, 15
+; GFX10_1-NEXT: v_readlane_b32 s31, v22, 16
+; GFX10_1-NEXT: v_readlane_b32 s55, v22, 14
+; GFX10_1-NEXT: v_readlane_b32 s54, v22, 13
+; GFX10_1-NEXT: v_readlane_b32 s53, v22, 12
+; GFX10_1-NEXT: v_readlane_b32 s52, v22, 11
+; GFX10_1-NEXT: v_readlane_b32 s51, v22, 10
+; GFX10_1-NEXT: v_readlane_b32 s50, v22, 9
+; GFX10_1-NEXT: v_readlane_b32 s49, v22, 8
+; GFX10_1-NEXT: v_readlane_b32 s48, v22, 7
+; GFX10_1-NEXT: v_readlane_b32 s39, v22, 6
+; GFX10_1-NEXT: v_readlane_b32 s38, v22, 5
+; GFX10_1-NEXT: v_readlane_b32 s37, v22, 4
+; GFX10_1-NEXT: v_readlane_b32 s36, v22, 3
+; GFX10_1-NEXT: v_readlane_b32 s35, v22, 2
+; GFX10_1-NEXT: v_readlane_b32 s34, v22, 1
+; GFX10_1-NEXT: v_readlane_b32 s33, v22, 0
; GFX10_1-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_1-NEXT: s_add_i32 s5, s32, 0x100800
; GFX10_1-NEXT: buffer_load_dword v22, off, s[0:3], s5 ; 4-byte Folded Reload
@@ -1473,31 +1475,31 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX10_3-NEXT: s_add_i32 s5, s32, 0x100800
; GFX10_3-NEXT: buffer_store_dword v22, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_3-NEXT: v_writelane_b32 v22, s30, 0
+; GFX10_3-NEXT: v_writelane_b32 v22, s33, 0
; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s32
; GFX10_3-NEXT: s_lshr_b32 s4, s32, 5
; GFX10_3-NEXT: s_add_i32 s58, s4, 0x4240
-; GFX10_3-NEXT: v_writelane_b32 v22, s31, 1
+; GFX10_3-NEXT: v_writelane_b32 v22, s34, 1
; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0
; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; use alloca0 v0
; GFX10_3-NEXT: ;;#ASMEND
-; GFX10_3-NEXT: v_writelane_b32 v22, s33, 2
-; GFX10_3-NEXT: v_writelane_b32 v22, s34, 3
-; GFX10_3-NEXT: v_writelane_b32 v22, s35, 4
-; GFX10_3-NEXT: v_writelane_b32 v22, s36, 5
-; GFX10_3-NEXT: v_writelane_b32 v22, s37, 6
-; GFX10_3-NEXT: v_writelane_b32 v22, s38, 7
-; GFX10_3-NEXT: v_writelane_b32 v22, s39, 8
-; GFX10_3-NEXT: v_writelane_b32 v22, s48, 9
-; GFX10_3-NEXT: v_writelane_b32 v22, s49, 10
-; GFX10_3-NEXT: v_writelane_b32 v22, s50, 11
-; GFX10_3-NEXT: v_writelane_b32 v22, s51, 12
-; GFX10_3-NEXT: v_writelane_b32 v22, s52, 13
-; GFX10_3-NEXT: v_writelane_b32 v22, s53, 14
-; GFX10_3-NEXT: v_writelane_b32 v22, s54, 15
-; GFX10_3-NEXT: v_writelane_b32 v22, s55, 16
+; GFX10_3-NEXT: v_writelane_b32 v22, s35, 2
+; GFX10_3-NEXT: v_writelane_b32 v22, s36, 3
+; GFX10_3-NEXT: v_writelane_b32 v22, s37, 4
+; GFX10_3-NEXT: v_writelane_b32 v22, s38, 5
+; GFX10_3-NEXT: v_writelane_b32 v22, s39, 6
+; GFX10_3-NEXT: v_writelane_b32 v22, s48, 7
+; GFX10_3-NEXT: v_writelane_b32 v22, s49, 8
+; GFX10_3-NEXT: v_writelane_b32 v22, s50, 9
+; GFX10_3-NEXT: v_writelane_b32 v22, s51, 10
+; GFX10_3-NEXT: v_writelane_b32 v22, s52, 11
+; GFX10_3-NEXT: v_writelane_b32 v22, s53, 12
+; GFX10_3-NEXT: v_writelane_b32 v22, s54, 13
+; GFX10_3-NEXT: v_writelane_b32 v22, s55, 14
+; GFX10_3-NEXT: v_writelane_b32 v22, s30, 15
+; GFX10_3-NEXT: v_writelane_b32 v22, s31, 16
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX10_3-NEXT: ;;#ASMEND
@@ -1506,23 +1508,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc
; GFX10_3-NEXT: ;;#ASMEND
-; GFX10_3-NEXT: v_readlane_b32 s55, v22, 16
-; GFX10_3-NEXT: v_readlane_b32 s54, v22, 15
-; GFX10_3-NEXT: v_readlane_b32 s53, v22, 14
-; GFX10_3-NEXT: v_readlane_b32 s52, v22, 13
-; GFX10_3-NEXT: v_readlane_b32 s51, v22, 12
-; GFX10_3-NEXT: v_readlane_b32 s50, v22, 11
-; GFX10_3-NEXT: v_readlane_b32 s49, v22, 10
-; GFX10_3-NEXT: v_readlane_b32 s48, v22, 9
-; GFX10_3-NEXT: v_readlane_b32 s39, v22, 8
-; GFX10_3-NEXT: v_readlane_b32 s38, v22, 7
-; GFX10_3-NEXT: v_readlane_b32 s37, v22, 6
-; GFX10_3-NEXT: v_readlane_b32 s36, v22, 5
-; GFX10_3-NEXT: v_readlane_b32 s35, v22, 4
-; GFX10_3-NEXT: v_readlane_b32 s34, v22, 3
-; GFX10_3-NEXT: v_readlane_b32 s33, v22, 2
-; GFX10_3-NEXT: v_readlane_b32 s31, v22, 1
-; GFX10_3-NEXT: v_readlane_b32 s30, v22, 0
+; GFX10_3-NEXT: v_readlane_b32 s30, v22, 15
+; GFX10_3-NEXT: v_readlane_b32 s31, v22, 16
+; GFX10_3-NEXT: v_readlane_b32 s55, v22, 14
+; GFX10_3-NEXT: v_readlane_b32 s54, v22, 13
+; GFX10_3-NEXT: v_readlane_b32 s53, v22, 12
+; GFX10_3-NEXT: v_readlane_b32 s52, v22, 11
+; GFX10_3-NEXT: v_readlane_b32 s51, v22, 10
+; GFX10_3-NEXT: v_readlane_b32 s50, v22, 9
+; GFX10_3-NEXT: v_readlane_b32 s49, v22, 8
+; GFX10_3-NEXT: v_readlane_b32 s48, v22, 7
+; GFX10_3-NEXT: v_readlane_b32 s39, v22, 6
+; GFX10_3-NEXT: v_readlane_b32 s38, v22, 5
+; GFX10_3-NEXT: v_readlane_b32 s37, v22, 4
+; GFX10_3-NEXT: v_readlane_b32 s36, v22, 3
+; GFX10_3-NEXT: v_readlane_b32 s35, v22, 2
+; GFX10_3-NEXT: v_readlane_b32 s34, v22, 1
+; GFX10_3-NEXT: v_readlane_b32 s33, v22, 0
; GFX10_3-NEXT: s_xor_saveexec_b32 s4, -1
; GFX10_3-NEXT: s_add_i32 s5, s32, 0x100800
; GFX10_3-NEXT: buffer_load_dword v22, off, s[0:3], s5 ; 4-byte Folded Reload
@@ -1537,30 +1539,30 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX11-NEXT: s_add_i32 s1, s32, 0x8040
; GFX11-NEXT: scratch_store_b32 off, v22, s1 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-NEXT: v_writelane_b32 v22, s30, 0
+; GFX11-NEXT: v_writelane_b32 v22, s33, 0
; GFX11-NEXT: s_add_i32 s0, s32, 64
; GFX11-NEXT: s_add_i32 s58, s32, 0x4240
; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
-; GFX11-NEXT: v_writelane_b32 v22, s31, 1
+; GFX11-NEXT: v_writelane_b32 v22, s34, 1
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use alloca0 v0
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: v_writelane_b32 v22, s33, 2
-; GFX11-NEXT: v_writelane_b32 v22, s34, 3
-; GFX11-NEXT: v_writelane_b32 v22, s35, 4
-; GFX11-NEXT: v_writelane_b32 v22, s36, 5
-; GFX11-NEXT: v_writelane_b32 v22, s37, 6
-; GFX11-NEXT: v_writelane_b32 v22, s38, 7
-; GFX11-NEXT: v_writelane_b32 v22, s39, 8
-; GFX11-NEXT: v_writelane_b32 v22, s48, 9
-; GFX11-NEXT: v_writelane_b32 v22, s49, 10
-; GFX11-NEXT: v_writelane_b32 v22, s50, 11
-; GFX11-NEXT: v_writelane_b32 v22, s51, 12
-; GFX11-NEXT: v_writelane_b32 v22, s52, 13
-; GFX11-NEXT: v_writelane_b32 v22, s53, 14
-; GFX11-NEXT: v_writelane_b32 v22, s54, 15
-; GFX11-NEXT: v_writelane_b32 v22, s55, 16
+; GFX11-NEXT: v_writelane_b32 v22, s35, 2
+; GFX11-NEXT: v_writelane_b32 v22, s36, 3
+; GFX11-NEXT: v_writelane_b32 v22, s37, 4
+; GFX11-NEXT: v_writelane_b32 v22, s38, 5
+; GFX11-NEXT: v_writelane_b32 v22, s39, 6
+; GFX11-NEXT: v_writelane_b32 v22, s48, 7
+; GFX11-NEXT: v_writelane_b32 v22, s49, 8
+; GFX11-NEXT: v_writelane_b32 v22, s50, 9
+; GFX11-NEXT: v_writelane_b32 v22, s51, 10
+; GFX11-NEXT: v_writelane_b32 v22, s52, 11
+; GFX11-NEXT: v_writelane_b32 v22, s53, 12
+; GFX11-NEXT: v_writelane_b32 v22, s54, 13
+; GFX11-NEXT: v_writelane_b32 v22, s55, 14
+; GFX11-NEXT: v_writelane_b32 v22, s30, 15
+; GFX11-NEXT: v_writelane_b32 v22, s31, 16
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX11-NEXT: ;;#ASMEND
@@ -1570,23 +1572,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX11-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readlane_b32 s55, v22, 16
-; GFX11-NEXT: v_readlane_b32 s54, v22, 15
-; GFX11-NEXT: v_readlane_b32 s53, v22, 14
-; GFX11-NEXT: v_readlane_b32 s52, v22, 13
-; GFX11-NEXT: v_readlane_b32 s51, v22, 12
-; GFX11-NEXT: v_readlane_b32 s50, v22, 11
-; GFX11-NEXT: v_readlane_b32 s49, v22, 10
-; GFX11-NEXT: v_readlane_b32 s48, v22, 9
-; GFX11-NEXT: v_readlane_b32 s39, v22, 8
-; GFX11-NEXT: v_readlane_b32 s38, v22, 7
-; GFX11-NEXT: v_readlane_b32 s37, v22, 6
-; GFX11-NEXT: v_readlane_b32 s36, v22, 5
-; GFX11-NEXT: v_readlane_b32 s35, v22, 4
-; GFX11-NEXT: v_readlane_b32 s34, v22, 3
-; GFX11-NEXT: v_readlane_b32 s33, v22, 2
-; GFX11-NEXT: v_readlane_b32 s31, v22, 1
-; GFX11-NEXT: v_readlane_b32 s30, v22, 0
+; GFX11-NEXT: v_readlane_b32 s30, v22, 15
+; GFX11-NEXT: v_readlane_b32 s31, v22, 16
+; GFX11-NEXT: v_readlane_b32 s55, v22, 14
+; GFX11-NEXT: v_readlane_b32 s54, v22, 13
+; GFX11-NEXT: v_readlane_b32 s53, v22, 12
+; GFX11-NEXT: v_readlane_b32 s52, v22, 11
+; GFX11-NEXT: v_readlane_b32 s51, v22, 10
+; GFX11-NEXT: v_readlane_b32 s50, v22, 9
+; GFX11-NEXT: v_readlane_b32 s49, v22, 8
+; GFX11-NEXT: v_readlane_b32 s48, v22, 7
+; GFX11-NEXT: v_readlane_b32 s39, v22, 6
+; GFX11-NEXT: v_readlane_b32 s38, v22, 5
+; GFX11-NEXT: v_readlane_b32 s37, v22, 4
+; GFX11-NEXT: v_readlane_b32 s36, v22, 3
+; GFX11-NEXT: v_readlane_b32 s35, v22, 2
+; GFX11-NEXT: v_readlane_b32 s34, v22, 1
+; GFX11-NEXT: v_readlane_b32 s33, v22, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: s_add_i32 s1, s32, 0x8040
; GFX11-NEXT: scratch_load_b32 v22, off, s1 ; 4-byte Folded Reload
@@ -1605,29 +1607,29 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX12-NEXT: scratch_store_b32 off, v22, s32 offset:32768 ; 4-byte Folded Spill
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s0
-; GFX12-NEXT: v_writelane_b32 v22, s30, 0
+; GFX12-NEXT: v_writelane_b32 v22, s33, 0
; GFX12-NEXT: s_add_co_i32 s58, s32, 0x4200
; GFX12-NEXT: v_mov_b32_e32 v0, s32
; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use alloca0 v0
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: v_writelane_b32 v22, s31, 1
-; GFX12-NEXT: v_writelane_b32 v22, s33, 2
-; GFX12-NEXT: v_writelane_b32 v22, s34, 3
-; GFX12-NEXT: v_writelane_b32 v22, s35, 4
-; GFX12-NEXT: v_writelane_b32 v22, s36, 5
-; GFX12-NEXT: v_writelane_b32 v22, s37, 6
-; GFX12-NEXT: v_writelane_b32 v22, s38, 7
-; GFX12-NEXT: v_writelane_b32 v22, s39, 8
-; GFX12-NEXT: v_writelane_b32 v22, s48, 9
-; GFX12-NEXT: v_writelane_b32 v22, s49, 10
-; GFX12-NEXT: v_writelane_b32 v22, s50, 11
-; GFX12-NEXT: v_writelane_b32 v22, s51, 12
-; GFX12-NEXT: v_writelane_b32 v22, s52, 13
-; GFX12-NEXT: v_writelane_b32 v22, s53, 14
-; GFX12-NEXT: v_writelane_b32 v22, s54, 15
-; GFX12-NEXT: v_writelane_b32 v22, s55, 16
+; GFX12-NEXT: v_writelane_b32 v22, s34, 1
+; GFX12-NEXT: v_writelane_b32 v22, s35, 2
+; GFX12-NEXT: v_writelane_b32 v22, s36, 3
+; GFX12-NEXT: v_writelane_b32 v22, s37, 4
+; GFX12-NEXT: v_writelane_b32 v22, s38, 5
+; GFX12-NEXT: v_writelane_b32 v22, s39, 6
+; GFX12-NEXT: v_writelane_b32 v22, s48, 7
+; GFX12-NEXT: v_writelane_b32 v22, s49, 8
+; GFX12-NEXT: v_writelane_b32 v22, s50, 9
+; GFX12-NEXT: v_writelane_b32 v22, s51, 10
+; GFX12-NEXT: v_writelane_b32 v22, s52, 11
+; GFX12-NEXT: v_writelane_b32 v22, s53, 12
+; GFX12-NEXT: v_writelane_b32 v22, s54, 13
+; GFX12-NEXT: v_writelane_b32 v22, s55, 14
+; GFX12-NEXT: v_writelane_b32 v22, s30, 15
+; GFX12-NEXT: v_writelane_b32 v22, s31, 16
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX12-NEXT: ;;#ASMEND
@@ -1637,23 +1639,23 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: v_readlane_b32 s55, v22, 16
-; GFX12-NEXT: v_readlane_b32 s54, v22, 15
-; GFX12-NEXT: v_readlane_b32 s53, v22, 14
-; GFX12-NEXT: v_readlane_b32 s52, v22, 13
-; GFX12-NEXT: v_readlane_b32 s51, v22, 12
-; GFX12-NEXT: v_readlane_b32 s50, v22, 11
-; GFX12-NEXT: v_readlane_b32 s49, v22, 10
-; GFX12-NEXT: v_readlane_b32 s48, v22, 9
-; GFX12-NEXT: v_readlane_b32 s39, v22, 8
-; GFX12-NEXT: v_readlane_b32 s38, v22, 7
-; GFX12-NEXT: v_readlane_b32 s37, v22, 6
-; GFX12-NEXT: v_readlane_b32 s36, v22, 5
-; GFX12-NEXT: v_readlane_b32 s35, v22, 4
-; GFX12-NEXT: v_readlane_b32 s34, v22, 3
-; GFX12-NEXT: v_readlane_b32 s33, v22, 2
-; GFX12-NEXT: v_readlane_b32 s31, v22, 1
-; GFX12-NEXT: v_readlane_b32 s30, v22, 0
+; GFX12-NEXT: v_readlane_b32 s30, v22, 15
+; GFX12-NEXT: v_readlane_b32 s31, v22, 16
+; GFX12-NEXT: v_readlane_b32 s55, v22, 14
+; GFX12-NEXT: v_readlane_b32 s54, v22, 13
+; GFX12-NEXT: v_readlane_b32 s53, v22, 12
+; GFX12-NEXT: v_readlane_b32 s52, v22, 11
+; GFX12-NEXT: v_readlane_b32 s51, v22, 10
+; GFX12-NEXT: v_readlane_b32 s50, v22, 9
+; GFX12-NEXT: v_readlane_b32 s49, v22, 8
+; GFX12-NEXT: v_readlane_b32 s48, v22, 7
+; GFX12-NEXT: v_readlane_b32 s39, v22, 6
+; GFX12-NEXT: v_readlane_b32 s38, v22, 5
+; GFX12-NEXT: v_readlane_b32 s37, v22, 4
+; GFX12-NEXT: v_readlane_b32 s36, v22, 3
+; GFX12-NEXT: v_readlane_b32 s35, v22, 2
+; GFX12-NEXT: v_readlane_b32 s34, v22, 1
+; GFX12-NEXT: v_readlane_b32 s33, v22, 0
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v22, off, s32 offset:32768 ; 4-byte Folded Reload
; GFX12-NEXT: s_wait_alu 0xfffe
diff --git a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
index 33cd598aae9b5..7b87cb014ecbf 100644
--- a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
+++ b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
@@ -194,22 +194,22 @@ define void @slsr1_1(i32 %b.arg, i32 %s.arg) #0 {
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[6:7]
; GFX9-NEXT: v_writelane_b32 v43, s4, 5
-; GFX9-NEXT: v_writelane_b32 v43, s30, 0
-; GFX9-NEXT: v_writelane_b32 v43, s31, 1
; GFX9-NEXT: s_addk_i32 s32, 0x800
-; GFX9-NEXT: v_writelane_b32 v43, s34, 2
-; GFX9-NEXT: v_writelane_b32 v43, s36, 3
+; GFX9-NEXT: v_writelane_b32 v43, s34, 0
+; GFX9-NEXT: v_writelane_b32 v43, s36, 1
; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, foo at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, foo at gotpcrel32@hi+12
-; GFX9-NEXT: v_writelane_b32 v43, s37, 4
+; GFX9-NEXT: v_writelane_b32 v43, s37, 2
; GFX9-NEXT: s_load_dwordx2 s[36:37], s[4:5], 0x0
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, v1
; GFX9-NEXT: v_mov_b32_e32 v41, v0
+; GFX9-NEXT: v_writelane_b32 v43, s30, 3
; GFX9-NEXT: v_mul_u32_u24_e32 v0, v41, v40
+; GFX9-NEXT: v_writelane_b32 v43, s31, 4
; GFX9-NEXT: s_mov_b32 s34, s15
; GFX9-NEXT: v_and_b32_e32 v42, 0xffffff, v40
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
@@ -224,11 +224,11 @@ define void @slsr1_1(i32 %b.arg, i32 %s.arg) #0 {
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s37, v43, 4
-; GFX9-NEXT: v_readlane_b32 s36, v43, 3
-; GFX9-NEXT: v_readlane_b32 s34, v43, 2
-; GFX9-NEXT: v_readlane_b32 s31, v43, 1
-; GFX9-NEXT: v_readlane_b32 s30, v43, 0
+; GFX9-NEXT: v_readlane_b32 s30, v43, 3
+; GFX9-NEXT: v_readlane_b32 s31, v43, 4
+; GFX9-NEXT: v_readlane_b32 s37, v43, 2
+; GFX9-NEXT: v_readlane_b32 s36, v43, 1
+; GFX9-NEXT: v_readlane_b32 s34, v43, 0
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v43, 5
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll b/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
index 65446a036c91b..878302e4865bb 100644
--- a/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
+++ b/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
@@ -47,8 +47,8 @@ define internal fastcc void @csr_vgpr_spill_fp_callee() #0 {
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; clobber csr v40
; CHECK-NEXT: ;;#ASMEND
-; CHECK-NEXT: v_readlane_b32 s31, v1, 1
; CHECK-NEXT: v_readlane_b32 s30, v1, 0
+; CHECK-NEXT: v_readlane_b32 s31, v1, 1
; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
@@ -190,8 +190,8 @@ define hidden i32 @caller_save_vgpr_spill_fp_tail_call() #0 {
; CHECK-NEXT: s_mov_b64 s[0:1], s[20:21]
; CHECK-NEXT: s_mov_b64 s[2:3], s[22:23]
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; CHECK-NEXT: v_readlane_b32 s31, v1, 1
; CHECK-NEXT: v_readlane_b32 s30, v1, 0
+; CHECK-NEXT: v_readlane_b32 s31, v1, 1
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -224,8 +224,8 @@ define hidden i32 @caller_save_vgpr_spill_fp() #0 {
; CHECK-NEXT: s_mov_b64 s[0:1], s[20:21]
; CHECK-NEXT: s_mov_b64 s[2:3], s[22:23]
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; CHECK-NEXT: v_readlane_b32 s31, v2, 1
; CHECK-NEXT: v_readlane_b32 s30, v2, 0
+; CHECK-NEXT: v_readlane_b32 s31, v2, 1
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/AMDGPU/nested-calls.ll b/llvm/test/CodeGen/AMDGPU/nested-calls.ll
index ccaf0ac5377e4..8394b325bee6d 100644
--- a/llvm/test/CodeGen/AMDGPU/nested-calls.ll
+++ b/llvm/test/CodeGen/AMDGPU/nested-calls.ll
@@ -29,8 +29,8 @@ define void @test_func_call_external_void_func_i32_imm() #0 {
; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -68,8 +68,8 @@ define void @test_func_call_external_void_func_i32_imm_stack_use() #0 {
; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll b/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
index 6b6c60ebe2a9e..133cc166c3311 100644
--- a/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
+++ b/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
@@ -247,8 +247,8 @@ define hidden void @_ZL3barv() #0 !dbg !1644 {
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: .loc 0 32 1 ; lane-info.cpp:32:1
-; CHECK-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-NEXT: v_readlane_b32 s30, v40, 0
+; CHECK-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: v_readlane_b32 s4, v40, 2
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll b/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
index 21f33efbfbdfe..1576e951ec422 100644
--- a/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
+++ b/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
@@ -338,8 +338,8 @@ define void @preserve_wwm_copy_dstreg(ptr %parg0, ptr %parg1, ptr %parg2) #0 {
; GFX906-NEXT: buffer_load_dword v31, off, s[0:3], s33 offset:136 ; 4-byte Folded Reload
; GFX906-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:140 ; 4-byte Folded Reload
; GFX906-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:144 ; 4-byte Folded Reload
-; GFX906-NEXT: v_readlane_b32 s31, v41, 1
; GFX906-NEXT: v_readlane_b32 s30, v41, 0
+; GFX906-NEXT: v_readlane_b32 s31, v41, 1
; GFX906-NEXT: s_mov_b32 s32, s33
; GFX906-NEXT: v_readlane_b32 s4, v41, 4
; GFX906-NEXT: v_readlane_b32 s34, v41, 2
@@ -388,21 +388,14 @@ define void @preserve_wwm_copy_dstreg(ptr %parg0, ptr %parg1, ptr %parg2) #0 {
; GFX908-NEXT: s_addk_i32 s32, 0x2c00
; GFX908-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX908-NEXT: s_mov_b64 s[16:17], exec
-; GFX908-NEXT: s_mov_b64 exec, 1
+; GFX908-NEXT: s_mov_b64 exec, 3
; GFX908-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:168
; GFX908-NEXT: v_writelane_b32 v2, s30, 0
+; GFX908-NEXT: v_writelane_b32 v2, s31, 1
; GFX908-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX908-NEXT: buffer_load_dword v2, off, s[0:3], s33 offset:168
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: s_mov_b64 exec, s[16:17]
-; GFX908-NEXT: s_mov_b64 s[16:17], exec
-; GFX908-NEXT: s_mov_b64 exec, 1
-; GFX908-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:168
-; GFX908-NEXT: v_writelane_b32 v2, s31, 0
-; GFX908-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GFX908-NEXT: buffer_load_dword v2, off, s[0:3], s33 offset:168
-; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: s_mov_b64 exec, s[16:17]
; GFX908-NEXT: s_mov_b32 s21, s15
; GFX908-NEXT: ; implicit-def: $vgpr39 : SGPR spill to VGPR lane
; GFX908-NEXT: s_mov_b32 s22, s14
@@ -735,20 +728,12 @@ define void @preserve_wwm_copy_dstreg(ptr %parg0, ptr %parg1, ptr %parg2) #0 {
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: flat_store_dwordx4 v[0:1], v[2:5]
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: s_mov_b64 exec, 1
-; GFX908-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:168
-; GFX908-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: v_readlane_b32 s31, v0, 0
-; GFX908-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:168
-; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: s_mov_b64 exec, s[4:5]
-; GFX908-NEXT: s_mov_b64 s[4:5], exec
-; GFX908-NEXT: s_mov_b64 exec, 1
+; GFX908-NEXT: s_mov_b64 exec, 3
; GFX908-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:168
; GFX908-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_readlane_b32 s30, v0, 0
+; GFX908-NEXT: v_readlane_b32 s31, v0, 1
; GFX908-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:168
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: s_mov_b64 exec, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll b/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
index dba10f19eb500..ef5681798fb19 100644
--- a/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
+++ b/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
@@ -20,9 +20,9 @@ define void @test_remat_s_getpc_b64() {
; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_readlane_b32 s30, v2, 0
; GFX9-NEXT: global_store_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: v_readlane_b32 s31, v2, 1
-; GFX9-NEXT: v_readlane_b32 s30, v2, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -45,8 +45,8 @@ define void @test_remat_s_getpc_b64() {
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: v_readlane_b32 s31, v2, 1
; GFX11-NEXT: v_readlane_b32 s30, v2, 0
+; GFX11-NEXT: v_readlane_b32 s31, v2, 1
; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v2, off, s32 ; 4-byte Folded Reload
@@ -79,8 +79,8 @@ define void @test_remat_s_getpc_b64() {
; GFX12-NEXT: s_sext_i32_i16 s1, s1
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT: v_readlane_b32 s31, v2, 1
; GFX12-NEXT: v_readlane_b32 s30, v2, 0
+; GFX12-NEXT: v_readlane_b32 s31, v2, 1
; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
; GFX12-NEXT: scratch_load_b32 v2, off, s32 ; 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
index 925984b15367d..4a2829947f9a0 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
@@ -28,16 +28,16 @@ body: |
; GCN-LABEL: name: test_main
; GCN: bb.0:
; GCN-NEXT: successors: %bb.1(0x80000000)
- ; GCN-NEXT: liveins: $vcc_hi, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $sgpr102, $sgpr103, $vgpr0
+ ; GCN-NEXT: liveins: $vcc_hi, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $sgpr102, $sgpr103, $vgpr0, $sgpr30_sgpr31
; GCN-NEXT: {{ $}}
; GCN-NEXT: $vcc_hi = frame-setup COPY $sgpr33
; GCN-NEXT: $sgpr33 = frame-setup COPY $sgpr32
; GCN-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
- ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5)
- ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5)
- ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5)
- ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr33, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5)
- ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr5, $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5)
+ ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5)
+ ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5)
+ ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5)
+ ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr33, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5)
+ ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr5, $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5)
; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0
; GCN-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 24, implicit-def dead $scc
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, $vgpr2
@@ -66,48 +66,48 @@ body: |
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr27, 23, $vgpr2
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr28, 24, $vgpr2
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr29, 25, $vgpr2
- ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr30, 26, $vgpr2
- ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr31, 27, $vgpr2
- ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr64, 28, $vgpr2
- ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr65, 29, $vgpr2
- ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr66, 30, $vgpr2
- ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr67, 31, $vgpr2
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr68, 0, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr69, 1, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr70, 2, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr71, 3, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr72, 4, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr73, 5, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr74, 6, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr75, 7, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr76, 8, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr77, 9, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr78, 10, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr79, 11, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr80, 12, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr81, 13, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr82, 14, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr83, 15, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr84, 16, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr85, 17, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr86, 18, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr87, 19, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr88, 20, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr89, 21, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr90, 22, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr91, 23, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr92, 24, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr93, 25, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr94, 26, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr95, 27, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr96, 28, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr97, 29, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr98, 30, $vgpr3
- ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr99, 31, $vgpr3
- ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr100, 0, $vgpr4
- ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr101, 1, $vgpr4
- ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr102, 2, $vgpr4
- ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr103, 3, $vgpr4
+ ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr64, 26, $vgpr2
+ ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr65, 27, $vgpr2
+ ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr66, 28, $vgpr2
+ ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr67, 29, $vgpr2
+ ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr68, 30, $vgpr2
+ ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr69, 31, $vgpr2
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr70, 0, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr71, 1, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr72, 2, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr73, 3, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr74, 4, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr75, 5, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr76, 6, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr77, 7, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr78, 8, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr79, 9, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr80, 10, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr81, 11, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr82, 12, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr83, 13, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr84, 14, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr85, 15, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr86, 16, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr87, 17, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr88, 18, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr89, 19, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr90, 20, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr91, 21, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr92, 22, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr93, 23, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr94, 24, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr95, 25, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr96, 26, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr97, 27, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr98, 28, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr99, 29, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr100, 30, $vgpr3
+ ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr101, 31, $vgpr3
+ ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr102, 0, $vgpr4
+ ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr103, 1, $vgpr4
+ ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr30, 2, $vgpr4, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
+ ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr31, 3, $vgpr4, implicit $sgpr30_sgpr31
; GCN-NEXT: $sgpr22 = IMPLICIT_DEF
; GCN-NEXT: $vgpr5 = IMPLICIT_DEF
; GCN-NEXT: $vgpr5 = SI_SPILL_S32_TO_VGPR $sgpr22, 0, killed $vgpr5
@@ -130,48 +130,48 @@ body: |
; GCN-NEXT: bb.3:
; GCN-NEXT: liveins: $vcc_hi
; GCN-NEXT: {{ $}}
- ; GCN-NEXT: $sgpr103 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 3
- ; GCN-NEXT: $sgpr102 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 2
- ; GCN-NEXT: $sgpr101 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 1
- ; GCN-NEXT: $sgpr100 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 0
- ; GCN-NEXT: $sgpr99 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 31
- ; GCN-NEXT: $sgpr98 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 30
- ; GCN-NEXT: $sgpr97 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 29
- ; GCN-NEXT: $sgpr96 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 28
- ; GCN-NEXT: $sgpr95 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 27
- ; GCN-NEXT: $sgpr94 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 26
- ; GCN-NEXT: $sgpr93 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 25
- ; GCN-NEXT: $sgpr92 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 24
- ; GCN-NEXT: $sgpr91 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 23
- ; GCN-NEXT: $sgpr90 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 22
- ; GCN-NEXT: $sgpr89 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 21
- ; GCN-NEXT: $sgpr88 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 20
- ; GCN-NEXT: $sgpr87 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 19
- ; GCN-NEXT: $sgpr86 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 18
- ; GCN-NEXT: $sgpr85 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 17
- ; GCN-NEXT: $sgpr84 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 16
- ; GCN-NEXT: $sgpr83 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 15
- ; GCN-NEXT: $sgpr82 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 14
- ; GCN-NEXT: $sgpr81 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 13
- ; GCN-NEXT: $sgpr80 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 12
- ; GCN-NEXT: $sgpr79 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 11
- ; GCN-NEXT: $sgpr78 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 10
- ; GCN-NEXT: $sgpr77 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 9
- ; GCN-NEXT: $sgpr76 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 8
- ; GCN-NEXT: $sgpr75 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 7
- ; GCN-NEXT: $sgpr74 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 6
- ; GCN-NEXT: $sgpr73 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 5
- ; GCN-NEXT: $sgpr72 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 4
- ; GCN-NEXT: $sgpr71 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 3
- ; GCN-NEXT: $sgpr70 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 2
- ; GCN-NEXT: $sgpr69 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 1
- ; GCN-NEXT: $sgpr68 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 0
- ; GCN-NEXT: $sgpr67 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 31
- ; GCN-NEXT: $sgpr66 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 30
- ; GCN-NEXT: $sgpr65 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 29
- ; GCN-NEXT: $sgpr64 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 28
- ; GCN-NEXT: $sgpr31 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 27
- ; GCN-NEXT: $sgpr30 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 26
+ ; GCN-NEXT: $sgpr30 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 2, implicit-def $sgpr30_sgpr31
+ ; GCN-NEXT: $sgpr31 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 3
+ ; GCN-NEXT: $sgpr103 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 1
+ ; GCN-NEXT: $sgpr102 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 0
+ ; GCN-NEXT: $sgpr101 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 31
+ ; GCN-NEXT: $sgpr100 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 30
+ ; GCN-NEXT: $sgpr99 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 29
+ ; GCN-NEXT: $sgpr98 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 28
+ ; GCN-NEXT: $sgpr97 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 27
+ ; GCN-NEXT: $sgpr96 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 26
+ ; GCN-NEXT: $sgpr95 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 25
+ ; GCN-NEXT: $sgpr94 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 24
+ ; GCN-NEXT: $sgpr93 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 23
+ ; GCN-NEXT: $sgpr92 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 22
+ ; GCN-NEXT: $sgpr91 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 21
+ ; GCN-NEXT: $sgpr90 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 20
+ ; GCN-NEXT: $sgpr89 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 19
+ ; GCN-NEXT: $sgpr88 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 18
+ ; GCN-NEXT: $sgpr87 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 17
+ ; GCN-NEXT: $sgpr86 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 16
+ ; GCN-NEXT: $sgpr85 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 15
+ ; GCN-NEXT: $sgpr84 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 14
+ ; GCN-NEXT: $sgpr83 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 13
+ ; GCN-NEXT: $sgpr82 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 12
+ ; GCN-NEXT: $sgpr81 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 11
+ ; GCN-NEXT: $sgpr80 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 10
+ ; GCN-NEXT: $sgpr79 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 9
+ ; GCN-NEXT: $sgpr78 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 8
+ ; GCN-NEXT: $sgpr77 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 7
+ ; GCN-NEXT: $sgpr76 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 6
+ ; GCN-NEXT: $sgpr75 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 5
+ ; GCN-NEXT: $sgpr74 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 4
+ ; GCN-NEXT: $sgpr73 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 3
+ ; GCN-NEXT: $sgpr72 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 2
+ ; GCN-NEXT: $sgpr71 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 1
+ ; GCN-NEXT: $sgpr70 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 0
+ ; GCN-NEXT: $sgpr69 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 31
+ ; GCN-NEXT: $sgpr68 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 30
+ ; GCN-NEXT: $sgpr67 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 29
+ ; GCN-NEXT: $sgpr66 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 28
+ ; GCN-NEXT: $sgpr65 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 27
+ ; GCN-NEXT: $sgpr64 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 26
; GCN-NEXT: $sgpr29 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 25
; GCN-NEXT: $sgpr28 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 24
; GCN-NEXT: $sgpr27 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 23
@@ -200,11 +200,11 @@ body: |
; GCN-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 0
; GCN-NEXT: $sgpr32 = frame-destroy COPY $sgpr33
; GCN-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
- ; GCN-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.69, addrspace 5)
- ; GCN-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.70, addrspace 5)
- ; GCN-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.71, addrspace 5)
- ; GCN-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.72, addrspace 5)
- ; GCN-NEXT: $vgpr5 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.73, addrspace 5)
+ ; GCN-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.68, addrspace 5)
+ ; GCN-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.69, addrspace 5)
+ ; GCN-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.70, addrspace 5)
+ ; GCN-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.71, addrspace 5)
+ ; GCN-NEXT: $vgpr5 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.72, addrspace 5)
; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0
; GCN-NEXT: $sgpr33 = frame-destroy COPY $vcc_hi
; GCN-NEXT: S_ENDPGM 0
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll b/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
index 702953c56a5cb..cb54b0ba629c3 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
@@ -152,8 +152,8 @@ define void @spill_sgpr_with_no_lower_vgpr_available() #0 {
; GCN-NEXT: s_mov_b64 s[2:3], s[22:23]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GCN-NEXT: v_readlane_b32 s31, v255, 1
; GCN-NEXT: v_readlane_b32 s30, v255, 0
+; GCN-NEXT: v_readlane_b32 s31, v255, 1
; GCN-NEXT: buffer_load_dword v254, off, s[0:3], s33 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v253, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v252, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
@@ -445,8 +445,8 @@ define void @spill_to_lowest_available_vgpr() #0 {
; GCN-NEXT: s_mov_b64 s[2:3], s[22:23]
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GCN-NEXT: v_readlane_b32 s31, v254, 1
; GCN-NEXT: v_readlane_b32 s30, v254, 0
+; GCN-NEXT: v_readlane_b32 s31, v254, 1
; GCN-NEXT: buffer_load_dword v253, off, s[0:3], s33 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v252, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v251, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
@@ -1632,21 +1632,14 @@ define void @spill_sgpr_no_free_vgpr_ipra() #0 {
; GCN-NEXT: buffer_store_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v255, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 s[16:17], exec
-; GCN-NEXT: s_mov_b64 exec, 1
+; GCN-NEXT: s_mov_b64 exec, 3
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:456
; GCN-NEXT: v_writelane_b32 v0, s30, 0
+; GCN-NEXT: v_writelane_b32 v0, s31, 1
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:448 ; 4-byte Folded Spill
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:456
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_mov_b64 exec, s[16:17]
-; GCN-NEXT: s_mov_b64 s[16:17], exec
-; GCN-NEXT: s_mov_b64 exec, 1
-; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:456
-; GCN-NEXT: v_writelane_b32 v0, s31, 0
-; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:452 ; 4-byte Folded Spill
-; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:456
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_mov_b64 exec, s[16:17]
; GCN-NEXT: s_getpc_b64 s[16:17]
; GCN-NEXT: s_add_u32 s16, s16, child_function_ipra at rel32@lo+4
; GCN-NEXT: s_addc_u32 s17, s17, child_function_ipra at rel32@hi+12
@@ -1656,20 +1649,12 @@ define void @spill_sgpr_no_free_vgpr_ipra() #0 {
; GCN-NEXT: s_mov_b64 s[2:3], s[22:23]
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: s_mov_b64 s[4:5], exec
-; GCN-NEXT: s_mov_b64 exec, 1
-; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:456
-; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:452 ; 4-byte Folded Reload
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readlane_b32 s31, v0, 0
-; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:456
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_mov_b64 exec, s[4:5]
-; GCN-NEXT: s_mov_b64 s[4:5], exec
-; GCN-NEXT: s_mov_b64 exec, 1
+; GCN-NEXT: s_mov_b64 exec, 3
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:456
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:448 ; 4-byte Folded Reload
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_readlane_b32 s30, v0, 0
+; GCN-NEXT: v_readlane_b32 s31, v0, 1
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:456
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_mov_b64 exec, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
index 7ee7c83e0122d..2317a30d7c017 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
@@ -14698,13 +14698,13 @@ define void @s_shuffle_v2i64_v8i64__15_2() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s30
; GFX900-NEXT: s_mov_b32 s9, s31
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -14727,13 +14727,13 @@ define void @s_shuffle_v2i64_v8i64__15_2() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s30
; GFX90A-NEXT: s_mov_b32 s9, s31
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -14838,13 +14838,13 @@ define void @s_shuffle_v2i64_v8i64__15_4() {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s8, s30
; GFX900-NEXT: s_mov_b32 s9, s31
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b32 s10, s12
; GFX900-NEXT: s_mov_b32 s11, s13
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -14867,13 +14867,13 @@ define void @s_shuffle_v2i64_v8i64__15_4() {
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: s_mov_b32 s8, s30
; GFX90A-NEXT: s_mov_b32 s9, s31
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b32 s10, s12
; GFX90A-NEXT: s_mov_b32 s11, s13
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -14890,19 +14890,19 @@ define void @s_shuffle_v2i64_v8i64__15_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:19]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_mov_b32 s10, s12
+; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s30
; GFX942-NEXT: s_mov_b32 s9, s31
-; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -14933,12 +14933,12 @@ define void @s_shuffle_v2i64_v8i64__15_5() {
; GFX900-NEXT: s_mov_b32 s12, s30
; GFX900-NEXT: s_mov_b32 s13, s31
; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -14962,12 +14962,12 @@ define void @s_shuffle_v2i64_v8i64__15_5() {
; GFX90A-NEXT: s_mov_b32 s12, s30
; GFX90A-NEXT: s_mov_b32 s13, s31
; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -15087,22 +15087,22 @@ define void @s_shuffle_v2i64_v8i64__15_6() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_mov_b32 s10, s12
+; GFX942-NEXT: s_mov_b32 s11, s13
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s30
; GFX942-NEXT: s_mov_b32 s9, s31
-; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -15208,6 +15208,7 @@ define void @s_shuffle_v2i64_v8i64__15_7() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
@@ -15215,12 +15216,12 @@ define void @s_shuffle_v2i64_v8i64__15_7() {
; GFX942-NEXT: s_mov_b32 s12, s30
; GFX942-NEXT: s_mov_b32 s13, s31
; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -16255,20 +16256,21 @@ define void @s_shuffle_v2i64_v8i64__12_0() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[16:31]
+; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
+; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s10, s16
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s11, s17
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -16978,20 +16980,21 @@ define void @s_shuffle_v2i64_v8i64__12_1() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[16:31]
+; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
+; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s10, s18
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s11, s19
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -17569,6 +17572,7 @@ define void @s_shuffle_v2i64_v8i64__9_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b32 s8, s18
; GFX900-NEXT: s_mov_b32 s9, s19
; GFX900-NEXT: s_mov_b32 s10, s12
@@ -17577,7 +17581,6 @@ define void @s_shuffle_v2i64_v8i64__9_2() {
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -17598,6 +17601,7 @@ define void @s_shuffle_v2i64_v8i64__9_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b32 s8, s18
; GFX90A-NEXT: s_mov_b32 s9, s19
; GFX90A-NEXT: s_mov_b32 s10, s12
@@ -17606,7 +17610,6 @@ define void @s_shuffle_v2i64_v8i64__9_2() {
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -17653,13 +17656,13 @@ define void @s_shuffle_v2i64_v8i64__10_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b32 s10, s20
; GFX900-NEXT: s_mov_b32 s11, s21
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -17680,13 +17683,13 @@ define void @s_shuffle_v2i64_v8i64__10_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b32 s10, s20
; GFX90A-NEXT: s_mov_b32 s11, s21
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -17700,6 +17703,7 @@ define void @s_shuffle_v2i64_v8i64__10_2() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
@@ -17708,13 +17712,13 @@ define void @s_shuffle_v2i64_v8i64__10_2() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:19]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s10, s20
; GFX942-NEXT: s_mov_b32 s11, s21
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -17742,6 +17746,7 @@ define void @s_shuffle_v2i64_v8i64__11_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b32 s8, s22
; GFX900-NEXT: s_mov_b32 s9, s23
; GFX900-NEXT: s_mov_b32 s10, s12
@@ -17750,7 +17755,6 @@ define void @s_shuffle_v2i64_v8i64__11_2() {
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -17771,6 +17775,7 @@ define void @s_shuffle_v2i64_v8i64__11_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b32 s8, s22
; GFX90A-NEXT: s_mov_b32 s9, s23
; GFX90A-NEXT: s_mov_b32 s10, s12
@@ -17779,7 +17784,6 @@ define void @s_shuffle_v2i64_v8i64__11_2() {
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -17886,6 +17890,7 @@ define void @s_shuffle_v2i64_v8i64__13_2() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b32 s8, s26
; GFX900-NEXT: s_mov_b32 s9, s27
; GFX900-NEXT: s_mov_b32 s10, s12
@@ -17894,7 +17899,6 @@ define void @s_shuffle_v2i64_v8i64__13_2() {
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -17915,6 +17919,7 @@ define void @s_shuffle_v2i64_v8i64__13_2() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b32 s8, s26
; GFX90A-NEXT: s_mov_b32 s9, s27
; GFX90A-NEXT: s_mov_b32 s10, s12
@@ -17923,7 +17928,6 @@ define void @s_shuffle_v2i64_v8i64__13_2() {
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -18403,13 +18407,13 @@ define void @s_shuffle_v2i64_v8i64__10_3() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b32 s10, s22
; GFX900-NEXT: s_mov_b32 s11, s23
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -18430,13 +18434,13 @@ define void @s_shuffle_v2i64_v8i64__10_3() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b32 s10, s22
; GFX90A-NEXT: s_mov_b32 s11, s23
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -18450,6 +18454,7 @@ define void @s_shuffle_v2i64_v8i64__10_3() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
@@ -18458,13 +18463,13 @@ define void @s_shuffle_v2i64_v8i64__10_3() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:19]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s10, s22
; GFX942-NEXT: s_mov_b32 s11, s23
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -19038,6 +19043,7 @@ define void @s_shuffle_v2i64_v8i64__9_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b32 s8, s18
; GFX900-NEXT: s_mov_b32 s9, s19
; GFX900-NEXT: s_mov_b32 s10, s12
@@ -19046,7 +19052,6 @@ define void @s_shuffle_v2i64_v8i64__9_4() {
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -19067,6 +19072,7 @@ define void @s_shuffle_v2i64_v8i64__9_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b32 s8, s18
; GFX90A-NEXT: s_mov_b32 s9, s19
; GFX90A-NEXT: s_mov_b32 s10, s12
@@ -19075,7 +19081,6 @@ define void @s_shuffle_v2i64_v8i64__9_4() {
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -19092,19 +19097,19 @@ define void @s_shuffle_v2i64_v8i64__9_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:19]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_mov_b32 s10, s12
+; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s18
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s19
-; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -19188,6 +19193,7 @@ define void @s_shuffle_v2i64_v8i64__11_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b32 s8, s22
; GFX900-NEXT: s_mov_b32 s9, s23
; GFX900-NEXT: s_mov_b32 s10, s12
@@ -19196,7 +19202,6 @@ define void @s_shuffle_v2i64_v8i64__11_4() {
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -19217,6 +19222,7 @@ define void @s_shuffle_v2i64_v8i64__11_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b32 s8, s22
; GFX90A-NEXT: s_mov_b32 s9, s23
; GFX90A-NEXT: s_mov_b32 s10, s12
@@ -19225,7 +19231,6 @@ define void @s_shuffle_v2i64_v8i64__11_4() {
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -19242,19 +19247,19 @@ define void @s_shuffle_v2i64_v8i64__11_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:19]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_mov_b32 s10, s12
+; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s22
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s23
-; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -19285,12 +19290,12 @@ define void @s_shuffle_v2i64_v8i64__12_4() {
; GFX900-NEXT: s_mov_b32 s26, s12
; GFX900-NEXT: s_mov_b32 s27, s13
; GFX900-NEXT: s_mov_b64 s[8:9], s[24:25]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b64 s[10:11], s[26:27]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -19314,12 +19319,12 @@ define void @s_shuffle_v2i64_v8i64__12_4() {
; GFX90A-NEXT: s_mov_b32 s26, s12
; GFX90A-NEXT: s_mov_b32 s27, s13
; GFX90A-NEXT: s_mov_b64 s[8:9], s[24:25]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b64 s[10:11], s[26:27]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -19364,6 +19369,7 @@ define void @s_shuffle_v2i64_v8i64__13_4() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b32 s8, s26
; GFX900-NEXT: s_mov_b32 s9, s27
; GFX900-NEXT: s_mov_b32 s10, s12
@@ -19372,7 +19378,6 @@ define void @s_shuffle_v2i64_v8i64__13_4() {
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -19393,6 +19398,7 @@ define void @s_shuffle_v2i64_v8i64__13_4() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b32 s8, s26
; GFX90A-NEXT: s_mov_b32 s9, s27
; GFX90A-NEXT: s_mov_b32 s10, s12
@@ -19401,7 +19407,6 @@ define void @s_shuffle_v2i64_v8i64__13_4() {
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -19418,19 +19423,19 @@ define void @s_shuffle_v2i64_v8i64__13_4() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:19]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_mov_b32 s10, s12
+; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s26
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s27
-; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -19462,11 +19467,11 @@ define void @s_shuffle_v2i64_v8i64__14_4() {
; GFX900-NEXT: s_mov_b32 s31, s13
; GFX900-NEXT: s_mov_b64 s[8:9], s[28:29]
; GFX900-NEXT: s_mov_b64 s[10:11], s[30:31]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -19491,11 +19496,11 @@ define void @s_shuffle_v2i64_v8i64__14_4() {
; GFX90A-NEXT: s_mov_b32 s31, s13
; GFX90A-NEXT: s_mov_b64 s[8:9], s[28:29]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[30:31]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -19962,12 +19967,12 @@ define void @s_shuffle_v2i64_v8i64__9_5() {
; GFX900-NEXT: s_mov_b32 s12, s18
; GFX900-NEXT: s_mov_b32 s13, s19
; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -19991,12 +19996,12 @@ define void @s_shuffle_v2i64_v8i64__9_5() {
; GFX90A-NEXT: s_mov_b32 s12, s18
; GFX90A-NEXT: s_mov_b32 s13, s19
; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -20100,12 +20105,12 @@ define void @s_shuffle_v2i64_v8i64__11_5() {
; GFX900-NEXT: s_mov_b32 s12, s22
; GFX900-NEXT: s_mov_b32 s13, s23
; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -20129,12 +20134,12 @@ define void @s_shuffle_v2i64_v8i64__11_5() {
; GFX90A-NEXT: s_mov_b32 s12, s22
; GFX90A-NEXT: s_mov_b32 s13, s23
; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -20182,12 +20187,12 @@ define void @s_shuffle_v2i64_v8i64__12_5() {
; GFX900-NEXT: s_mov_b32 s26, s14
; GFX900-NEXT: s_mov_b32 s27, s15
; GFX900-NEXT: s_mov_b64 s[8:9], s[24:25]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b64 s[10:11], s[26:27]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -20211,12 +20216,12 @@ define void @s_shuffle_v2i64_v8i64__12_5() {
; GFX90A-NEXT: s_mov_b32 s26, s14
; GFX90A-NEXT: s_mov_b32 s27, s15
; GFX90A-NEXT: s_mov_b64 s[8:9], s[24:25]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b64 s[10:11], s[26:27]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -20264,12 +20269,12 @@ define void @s_shuffle_v2i64_v8i64__13_5() {
; GFX900-NEXT: s_mov_b32 s12, s26
; GFX900-NEXT: s_mov_b32 s13, s27
; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -20293,12 +20298,12 @@ define void @s_shuffle_v2i64_v8i64__13_5() {
; GFX90A-NEXT: s_mov_b32 s12, s26
; GFX90A-NEXT: s_mov_b32 s13, s27
; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -20347,11 +20352,11 @@ define void @s_shuffle_v2i64_v8i64__14_5() {
; GFX900-NEXT: s_mov_b32 s31, s15
; GFX900-NEXT: s_mov_b64 s[8:9], s[28:29]
; GFX900-NEXT: s_mov_b64 s[10:11], s[30:31]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -20376,11 +20381,11 @@ define void @s_shuffle_v2i64_v8i64__14_5() {
; GFX90A-NEXT: s_mov_b32 s31, s15
; GFX90A-NEXT: s_mov_b64 s[8:9], s[28:29]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[30:31]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -20934,22 +20939,22 @@ define void @s_shuffle_v2i64_v8i64__9_6() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_mov_b32 s10, s12
+; GFX942-NEXT: s_mov_b32 s11, s13
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s18
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s19
-; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -21108,22 +21113,22 @@ define void @s_shuffle_v2i64_v8i64__11_6() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_mov_b32 s10, s12
+; GFX942-NEXT: s_mov_b32 s11, s13
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s22
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s23
-; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -21332,22 +21337,22 @@ define void @s_shuffle_v2i64_v8i64__13_6() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_mov_b32 s10, s12
+; GFX942-NEXT: s_mov_b32 s11, s13
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s26
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s27
-; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -21450,10 +21455,11 @@ define void @s_shuffle_v2i64_v8i64__14_6() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
@@ -21461,11 +21467,11 @@ define void @s_shuffle_v2i64_v8i64__14_6() {
; GFX942-NEXT: s_mov_b32 s31, s13
; GFX942-NEXT: s_mov_b64 s[8:9], s[28:29]
; GFX942-NEXT: s_mov_b64 s[10:11], s[30:31]
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -21997,6 +22003,7 @@ define void @s_shuffle_v2i64_v8i64__9_7() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
@@ -22004,12 +22011,12 @@ define void @s_shuffle_v2i64_v8i64__9_7() {
; GFX942-NEXT: s_mov_b32 s12, s18
; GFX942-NEXT: s_mov_b32 s13, s19
; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -22171,6 +22178,7 @@ define void @s_shuffle_v2i64_v8i64__11_7() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
@@ -22178,12 +22186,12 @@ define void @s_shuffle_v2i64_v8i64__11_7() {
; GFX942-NEXT: s_mov_b32 s12, s22
; GFX942-NEXT: s_mov_b32 s13, s23
; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -22395,6 +22403,7 @@ define void @s_shuffle_v2i64_v8i64__13_7() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
@@ -22402,12 +22411,12 @@ define void @s_shuffle_v2i64_v8i64__13_7() {
; GFX942-NEXT: s_mov_b32 s12, s26
; GFX942-NEXT: s_mov_b32 s13, s27
; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -22510,10 +22519,11 @@ define void @s_shuffle_v2i64_v8i64__14_7() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
@@ -22521,11 +22531,11 @@ define void @s_shuffle_v2i64_v8i64__14_7() {
; GFX942-NEXT: s_mov_b32 s31, s15
; GFX942-NEXT: s_mov_b64 s[8:9], s[28:29]
; GFX942-NEXT: s_mov_b64 s[10:11], s[30:31]
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -23522,12 +23532,12 @@ define void @s_shuffle_v2i64_v8i64__4_9() {
; GFX900-NEXT: s_mov_b32 s14, s18
; GFX900-NEXT: s_mov_b32 s15, s19
; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -23551,12 +23561,12 @@ define void @s_shuffle_v2i64_v8i64__4_9() {
; GFX90A-NEXT: s_mov_b32 s14, s18
; GFX90A-NEXT: s_mov_b32 s15, s19
; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -23601,13 +23611,13 @@ define void @s_shuffle_v2i64_v8i64__5_9() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:23]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b32 s8, s26
; GFX900-NEXT: s_mov_b32 s9, s27
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -23628,13 +23638,13 @@ define void @s_shuffle_v2i64_v8i64__5_9() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:23]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b32 s8, s26
; GFX90A-NEXT: s_mov_b32 s9, s27
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -23648,6 +23658,7 @@ define void @s_shuffle_v2i64_v8i64__5_9() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
@@ -23656,13 +23667,13 @@ define void @s_shuffle_v2i64_v8i64__5_9() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[8:23]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s8, s26
; GFX942-NEXT: s_mov_b32 s9, s27
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -23768,6 +23779,7 @@ define void @s_shuffle_v2i64_v8i64__6_9() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
@@ -23775,12 +23787,12 @@ define void @s_shuffle_v2i64_v8i64__6_9() {
; GFX942-NEXT: s_mov_b32 s14, s18
; GFX942-NEXT: s_mov_b32 s15, s19
; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -24372,12 +24384,12 @@ define void @s_shuffle_v2i64_v8i64__4_10() {
; GFX900-NEXT: s_mov_b32 s14, s20
; GFX900-NEXT: s_mov_b32 s15, s21
; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -24401,12 +24413,12 @@ define void @s_shuffle_v2i64_v8i64__4_10() {
; GFX90A-NEXT: s_mov_b32 s14, s20
; GFX90A-NEXT: s_mov_b32 s15, s21
; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -24451,6 +24463,7 @@ define void @s_shuffle_v2i64_v8i64__5_10() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b32 s8, s14
; GFX900-NEXT: s_mov_b32 s9, s15
; GFX900-NEXT: s_mov_b32 s10, s20
@@ -24459,7 +24472,6 @@ define void @s_shuffle_v2i64_v8i64__5_10() {
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -24480,6 +24492,7 @@ define void @s_shuffle_v2i64_v8i64__5_10() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b32 s8, s14
; GFX90A-NEXT: s_mov_b32 s9, s15
; GFX90A-NEXT: s_mov_b32 s10, s20
@@ -24488,7 +24501,6 @@ define void @s_shuffle_v2i64_v8i64__5_10() {
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -24612,6 +24624,7 @@ define void @s_shuffle_v2i64_v8i64__6_10() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
@@ -24619,12 +24632,12 @@ define void @s_shuffle_v2i64_v8i64__6_10() {
; GFX942-NEXT: s_mov_b32 s14, s20
; GFX942-NEXT: s_mov_b32 s15, s21
; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -24727,22 +24740,22 @@ define void @s_shuffle_v2i64_v8i64__7_10() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_mov_b32 s8, s14
+; GFX942-NEXT: s_mov_b32 s9, s15
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s8, s14
-; GFX942-NEXT: s_mov_b32 s9, s15
; GFX942-NEXT: s_mov_b32 s10, s20
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s11, s21
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -25323,13 +25336,13 @@ define void @s_shuffle_v2i64_v8i64__3_11() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b32 s8, s22
; GFX900-NEXT: s_mov_b32 s9, s23
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -25350,13 +25363,13 @@ define void @s_shuffle_v2i64_v8i64__3_11() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b32 s8, s22
; GFX90A-NEXT: s_mov_b32 s9, s23
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -25370,6 +25383,7 @@ define void @s_shuffle_v2i64_v8i64__3_11() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
@@ -25378,13 +25392,13 @@ define void @s_shuffle_v2i64_v8i64__3_11() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:19]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s8, s22
; GFX942-NEXT: s_mov_b32 s9, s23
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -25415,12 +25429,12 @@ define void @s_shuffle_v2i64_v8i64__4_11() {
; GFX900-NEXT: s_mov_b32 s14, s22
; GFX900-NEXT: s_mov_b32 s15, s23
; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -25444,12 +25458,12 @@ define void @s_shuffle_v2i64_v8i64__4_11() {
; GFX90A-NEXT: s_mov_b32 s14, s22
; GFX90A-NEXT: s_mov_b32 s15, s23
; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -25628,6 +25642,7 @@ define void @s_shuffle_v2i64_v8i64__6_11() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
@@ -25635,12 +25650,12 @@ define void @s_shuffle_v2i64_v8i64__6_11() {
; GFX942-NEXT: s_mov_b32 s14, s22
; GFX942-NEXT: s_mov_b32 s15, s23
; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -26232,12 +26247,12 @@ define void @s_shuffle_v2i64_v8i64__4_12() {
; GFX900-NEXT: s_mov_b32 s14, s24
; GFX900-NEXT: s_mov_b32 s15, s25
; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -26261,12 +26276,12 @@ define void @s_shuffle_v2i64_v8i64__4_12() {
; GFX90A-NEXT: s_mov_b32 s14, s24
; GFX90A-NEXT: s_mov_b32 s15, s25
; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -26311,6 +26326,7 @@ define void @s_shuffle_v2i64_v8i64__5_12() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b32 s8, s14
; GFX900-NEXT: s_mov_b32 s9, s15
; GFX900-NEXT: s_mov_b32 s10, s24
@@ -26319,7 +26335,6 @@ define void @s_shuffle_v2i64_v8i64__5_12() {
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -26340,6 +26355,7 @@ define void @s_shuffle_v2i64_v8i64__5_12() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b32 s8, s14
; GFX90A-NEXT: s_mov_b32 s9, s15
; GFX90A-NEXT: s_mov_b32 s10, s24
@@ -26348,7 +26364,6 @@ define void @s_shuffle_v2i64_v8i64__5_12() {
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -26472,6 +26487,7 @@ define void @s_shuffle_v2i64_v8i64__6_12() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
@@ -26479,12 +26495,12 @@ define void @s_shuffle_v2i64_v8i64__6_12() {
; GFX942-NEXT: s_mov_b32 s14, s24
; GFX942-NEXT: s_mov_b32 s15, s25
; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -26587,22 +26603,22 @@ define void @s_shuffle_v2i64_v8i64__7_12() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_mov_b32 s8, s14
+; GFX942-NEXT: s_mov_b32 s9, s15
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s8, s14
-; GFX942-NEXT: s_mov_b32 s9, s15
; GFX942-NEXT: s_mov_b32 s10, s24
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s11, s25
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -26968,20 +26984,21 @@ define void @s_shuffle_v2i64_v8i64__1_13() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[16:31]
+; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
+; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s18
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s19
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -27128,12 +27145,12 @@ define void @s_shuffle_v2i64_v8i64__4_13() {
; GFX900-NEXT: s_mov_b32 s14, s26
; GFX900-NEXT: s_mov_b32 s15, s27
; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -27157,12 +27174,12 @@ define void @s_shuffle_v2i64_v8i64__4_13() {
; GFX90A-NEXT: s_mov_b32 s14, s26
; GFX90A-NEXT: s_mov_b32 s15, s27
; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -27210,12 +27227,12 @@ define void @s_shuffle_v2i64_v8i64__5_13() {
; GFX900-NEXT: s_mov_b32 s24, s14
; GFX900-NEXT: s_mov_b32 s25, s15
; GFX900-NEXT: s_mov_b64 s[8:9], s[24:25]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b64 s[10:11], s[26:27]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -27239,12 +27256,12 @@ define void @s_shuffle_v2i64_v8i64__5_13() {
; GFX90A-NEXT: s_mov_b32 s24, s14
; GFX90A-NEXT: s_mov_b32 s25, s15
; GFX90A-NEXT: s_mov_b64 s[8:9], s[24:25]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b64 s[10:11], s[26:27]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -27367,6 +27384,7 @@ define void @s_shuffle_v2i64_v8i64__6_13() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
@@ -27374,12 +27392,12 @@ define void @s_shuffle_v2i64_v8i64__6_13() {
; GFX942-NEXT: s_mov_b32 s14, s26
; GFX942-NEXT: s_mov_b32 s15, s27
; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -28085,12 +28103,12 @@ define void @s_shuffle_v2i64_v8i64__4_14() {
; GFX900-NEXT: s_mov_b32 s14, s28
; GFX900-NEXT: s_mov_b32 s15, s29
; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -28114,12 +28132,12 @@ define void @s_shuffle_v2i64_v8i64__4_14() {
; GFX90A-NEXT: s_mov_b32 s14, s28
; GFX90A-NEXT: s_mov_b32 s15, s29
; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -28164,6 +28182,7 @@ define void @s_shuffle_v2i64_v8i64__5_14() {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b32 s8, s14
; GFX900-NEXT: s_mov_b32 s9, s15
; GFX900-NEXT: s_mov_b32 s10, s28
@@ -28172,7 +28191,6 @@ define void @s_shuffle_v2i64_v8i64__5_14() {
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -28193,6 +28211,7 @@ define void @s_shuffle_v2i64_v8i64__5_14() {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b32 s8, s14
; GFX90A-NEXT: s_mov_b32 s9, s15
; GFX90A-NEXT: s_mov_b32 s10, s28
@@ -28201,7 +28220,6 @@ define void @s_shuffle_v2i64_v8i64__5_14() {
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -28325,6 +28343,7 @@ define void @s_shuffle_v2i64_v8i64__6_14() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
@@ -28332,12 +28351,12 @@ define void @s_shuffle_v2i64_v8i64__6_14() {
; GFX942-NEXT: s_mov_b32 s14, s28
; GFX942-NEXT: s_mov_b32 s15, s29
; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -28440,22 +28459,22 @@ define void @s_shuffle_v2i64_v8i64__7_14() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_mov_b32 s8, s14
+; GFX942-NEXT: s_mov_b32 s9, s15
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s8, s14
-; GFX942-NEXT: s_mov_b32 s9, s15
; GFX942-NEXT: s_mov_b32 s10, s28
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s11, s29
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -29066,12 +29085,12 @@ define void @s_shuffle_v2i64_v8i64__4_15() {
; GFX900-NEXT: s_mov_b32 s14, s30
; GFX900-NEXT: s_mov_b32 s15, s31
; GFX900-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -29095,12 +29114,12 @@ define void @s_shuffle_v2i64_v8i64__4_15() {
; GFX90A-NEXT: s_mov_b32 s14, s30
; GFX90A-NEXT: s_mov_b32 s15, s31
; GFX90A-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -29149,11 +29168,11 @@ define void @s_shuffle_v2i64_v8i64__5_15() {
; GFX900-NEXT: s_mov_b32 s29, s15
; GFX900-NEXT: s_mov_b64 s[8:9], s[28:29]
; GFX900-NEXT: s_mov_b64 s[10:11], s[30:31]
+; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use s[8:11]
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_readlane_b32 s31, v0, 1
-; GFX900-NEXT: v_readlane_b32 s30, v0, 0
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
@@ -29178,11 +29197,11 @@ define void @s_shuffle_v2i64_v8i64__5_15() {
; GFX90A-NEXT: s_mov_b32 s29, s15
; GFX90A-NEXT: s_mov_b64 s[8:9], s[28:29]
; GFX90A-NEXT: s_mov_b64 s[10:11], s[30:31]
+; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s[8:11]
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v0, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v0, 0
; GFX90A-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX90A-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
@@ -29307,6 +29326,7 @@ define void @s_shuffle_v2i64_v8i64__6_15() {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
@@ -29314,12 +29334,12 @@ define void @s_shuffle_v2i64_v8i64__6_15() {
; GFX942-NEXT: s_mov_b32 s14, s30
; GFX942-NEXT: s_mov_b32 s15, s31
; GFX942-NEXT: s_mov_b64 s[8:9], s[12:13]
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b64 s[10:11], s[14:15]
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
@@ -29422,22 +29442,23 @@ define void @s_shuffle_v2i64_v8i64__7_15() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[16:31]
+; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
+; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s28, s14
; GFX942-NEXT: s_mov_b32 s29, s15
; GFX942-NEXT: s_mov_b64 s[8:9], s[28:29]
; GFX942-NEXT: s_mov_b64 s[10:11], s[30:31]
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: v_readlane_b32 s31, v0, 1
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-NEXT: scratch_load_dword v0, off, s32 ; 4-byte Folded Reload
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
index 1ffef8e60d90d..ea67593d72761 100644
--- a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
@@ -24,10 +24,10 @@ machineFunctionInfo:
body: |
bb.0:
; SGPR_SPILLED-LABEL: name: stack-slot-share-equal-sized-spills
- ; SGPR_SPILLED: liveins: $sgpr30, $sgpr31, $vgpr62
+ ; SGPR_SPILLED: liveins: $vgpr62, $sgpr30_sgpr31
; SGPR_SPILLED-NEXT: {{ $}}
- ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr30, 0, $vgpr62
- ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 1, $vgpr62
+ ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR $sgpr30, 0, $vgpr62, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
+ ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 1, $vgpr62, implicit killed $sgpr30_sgpr31
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr32, 0, [[DEF]]
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr0, 1, [[DEF]], implicit-def $sgpr0_sgpr1, implicit $sgpr0_sgpr1
@@ -89,10 +89,10 @@ machineFunctionInfo:
body: |
bb.0:
; SGPR_SPILLED-LABEL: name: stack-slot-share-unequal-sized-spills-with-large-spill-first
- ; SGPR_SPILLED: liveins: $sgpr30, $sgpr31, $vgpr62
+ ; SGPR_SPILLED: liveins: $vgpr62, $sgpr30_sgpr31
; SGPR_SPILLED-NEXT: {{ $}}
- ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr30, 0, $vgpr62
- ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 1, $vgpr62
+ ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR $sgpr30, 0, $vgpr62, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
+ ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 1, $vgpr62, implicit killed $sgpr30_sgpr31
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr32, 0, [[DEF]]
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr2, 1, [[DEF]], implicit-def $sgpr2_sgpr3, implicit $sgpr2_sgpr3
@@ -152,10 +152,10 @@ machineFunctionInfo:
body: |
bb.0:
; SGPR_SPILLED-LABEL: name: stack-slot-share-unequal-sized-spills-with-small-spill-first
- ; SGPR_SPILLED: liveins: $sgpr30, $sgpr31, $vgpr62
+ ; SGPR_SPILLED: liveins: $vgpr62, $sgpr30_sgpr31
; SGPR_SPILLED-NEXT: {{ $}}
- ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr30, 0, $vgpr62
- ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 1, $vgpr62
+ ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR $sgpr30, 0, $vgpr62, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
+ ; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 1, $vgpr62, implicit killed $sgpr30_sgpr31
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr32, 0, [[DEF]]
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr0, 1, [[DEF]]
diff --git a/llvm/test/CodeGen/AMDGPU/sibling-call.ll b/llvm/test/CodeGen/AMDGPU/sibling-call.ll
index 00214ef36e1f0..d4b53e9d338f8 100644
--- a/llvm/test/CodeGen/AMDGPU/sibling-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/sibling-call.ll
@@ -242,8 +242,8 @@ define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, pt
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -425,8 +425,8 @@ define fastcc i32 @no_sibling_call_callee_more_stack_space(i32 %a, i32 %b) #1 {
; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -469,11 +469,11 @@ define fastcc i32 @sibling_call_i32_fastcc_i32_i32_other_call(i32 %a, i32 %b, i3
; GCN-NEXT: v_mov_b32_e32 v1, v40
; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
+; GCN-NEXT: v_readlane_b32 s30, v42, 0
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, sibling_call_i32_fastcc_i32_i32 at rel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, sibling_call_i32_fastcc_i32_i32 at rel32@hi+12
; GCN-NEXT: v_readlane_b32 s31, v42, 1
-; GCN-NEXT: v_readlane_b32 s30, v42, 0
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s6, v42, 2
; GCN-NEXT: s_or_saveexec_b64 s[8:9], -1
@@ -603,23 +603,23 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; FIJI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; FIJI-NEXT: s_mov_b64 exec, s[18:19]
; FIJI-NEXT: v_writelane_b32 v40, s16, 18
-; FIJI-NEXT: v_writelane_b32 v40, s30, 0
-; FIJI-NEXT: v_writelane_b32 v40, s31, 1
-; FIJI-NEXT: v_writelane_b32 v40, s34, 2
-; FIJI-NEXT: v_writelane_b32 v40, s35, 3
-; FIJI-NEXT: v_writelane_b32 v40, s36, 4
-; FIJI-NEXT: v_writelane_b32 v40, s37, 5
-; FIJI-NEXT: v_writelane_b32 v40, s38, 6
-; FIJI-NEXT: v_writelane_b32 v40, s39, 7
-; FIJI-NEXT: v_writelane_b32 v40, s48, 8
-; FIJI-NEXT: v_writelane_b32 v40, s49, 9
-; FIJI-NEXT: v_writelane_b32 v40, s50, 10
-; FIJI-NEXT: v_writelane_b32 v40, s51, 11
-; FIJI-NEXT: v_writelane_b32 v40, s52, 12
-; FIJI-NEXT: v_writelane_b32 v40, s53, 13
-; FIJI-NEXT: v_writelane_b32 v40, s54, 14
-; FIJI-NEXT: v_writelane_b32 v40, s55, 15
-; FIJI-NEXT: v_writelane_b32 v40, s64, 16
+; FIJI-NEXT: v_writelane_b32 v40, s34, 0
+; FIJI-NEXT: v_writelane_b32 v40, s35, 1
+; FIJI-NEXT: v_writelane_b32 v40, s36, 2
+; FIJI-NEXT: v_writelane_b32 v40, s37, 3
+; FIJI-NEXT: v_writelane_b32 v40, s38, 4
+; FIJI-NEXT: v_writelane_b32 v40, s39, 5
+; FIJI-NEXT: v_writelane_b32 v40, s48, 6
+; FIJI-NEXT: v_writelane_b32 v40, s49, 7
+; FIJI-NEXT: v_writelane_b32 v40, s50, 8
+; FIJI-NEXT: v_writelane_b32 v40, s51, 9
+; FIJI-NEXT: v_writelane_b32 v40, s52, 10
+; FIJI-NEXT: v_writelane_b32 v40, s53, 11
+; FIJI-NEXT: v_writelane_b32 v40, s54, 12
+; FIJI-NEXT: v_writelane_b32 v40, s55, 13
+; FIJI-NEXT: v_writelane_b32 v40, s64, 14
+; FIJI-NEXT: v_writelane_b32 v40, s65, 15
+; FIJI-NEXT: v_writelane_b32 v40, s30, 16
; FIJI-NEXT: s_mov_b32 s50, s15
; FIJI-NEXT: s_mov_b32 s51, s14
; FIJI-NEXT: s_mov_b32 s52, s13
@@ -631,7 +631,7 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; FIJI-NEXT: v_add_u32_e32 v3, vcc, v3, v4
; FIJI-NEXT: s_mov_b64 s[54:55], exec
; FIJI-NEXT: s_addk_i32 s32, 0x400
-; FIJI-NEXT: v_writelane_b32 v40, s65, 17
+; FIJI-NEXT: v_writelane_b32 v40, s31, 17
; FIJI-NEXT: .LBB18_1: ; =>This Inner Loop Header: Depth=1
; FIJI-NEXT: v_readfirstlane_b32 s16, v0
; FIJI-NEXT: v_readfirstlane_b32 s17, v1
@@ -657,25 +657,25 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; FIJI-NEXT: s_cbranch_execnz .LBB18_1
; FIJI-NEXT: ; %bb.2:
; FIJI-NEXT: s_mov_b64 exec, s[54:55]
+; FIJI-NEXT: v_readlane_b32 s30, v40, 16
; FIJI-NEXT: v_mov_b32_e32 v0, v4
-; FIJI-NEXT: v_readlane_b32 s65, v40, 17
-; FIJI-NEXT: v_readlane_b32 s64, v40, 16
-; FIJI-NEXT: v_readlane_b32 s55, v40, 15
-; FIJI-NEXT: v_readlane_b32 s54, v40, 14
-; FIJI-NEXT: v_readlane_b32 s53, v40, 13
-; FIJI-NEXT: v_readlane_b32 s52, v40, 12
-; FIJI-NEXT: v_readlane_b32 s51, v40, 11
-; FIJI-NEXT: v_readlane_b32 s50, v40, 10
-; FIJI-NEXT: v_readlane_b32 s49, v40, 9
-; FIJI-NEXT: v_readlane_b32 s48, v40, 8
-; FIJI-NEXT: v_readlane_b32 s39, v40, 7
-; FIJI-NEXT: v_readlane_b32 s38, v40, 6
-; FIJI-NEXT: v_readlane_b32 s37, v40, 5
-; FIJI-NEXT: v_readlane_b32 s36, v40, 4
-; FIJI-NEXT: v_readlane_b32 s35, v40, 3
-; FIJI-NEXT: v_readlane_b32 s34, v40, 2
-; FIJI-NEXT: v_readlane_b32 s31, v40, 1
-; FIJI-NEXT: v_readlane_b32 s30, v40, 0
+; FIJI-NEXT: v_readlane_b32 s31, v40, 17
+; FIJI-NEXT: v_readlane_b32 s65, v40, 15
+; FIJI-NEXT: v_readlane_b32 s64, v40, 14
+; FIJI-NEXT: v_readlane_b32 s55, v40, 13
+; FIJI-NEXT: v_readlane_b32 s54, v40, 12
+; FIJI-NEXT: v_readlane_b32 s53, v40, 11
+; FIJI-NEXT: v_readlane_b32 s52, v40, 10
+; FIJI-NEXT: v_readlane_b32 s51, v40, 9
+; FIJI-NEXT: v_readlane_b32 s50, v40, 8
+; FIJI-NEXT: v_readlane_b32 s49, v40, 7
+; FIJI-NEXT: v_readlane_b32 s48, v40, 6
+; FIJI-NEXT: v_readlane_b32 s39, v40, 5
+; FIJI-NEXT: v_readlane_b32 s38, v40, 4
+; FIJI-NEXT: v_readlane_b32 s37, v40, 3
+; FIJI-NEXT: v_readlane_b32 s36, v40, 2
+; FIJI-NEXT: v_readlane_b32 s35, v40, 1
+; FIJI-NEXT: v_readlane_b32 s34, v40, 0
; FIJI-NEXT: s_mov_b32 s32, s33
; FIJI-NEXT: v_readlane_b32 s4, v40, 18
; FIJI-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -694,23 +694,23 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; HAWAII-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; HAWAII-NEXT: s_mov_b64 exec, s[18:19]
; HAWAII-NEXT: v_writelane_b32 v40, s16, 18
-; HAWAII-NEXT: v_writelane_b32 v40, s30, 0
-; HAWAII-NEXT: v_writelane_b32 v40, s31, 1
-; HAWAII-NEXT: v_writelane_b32 v40, s34, 2
-; HAWAII-NEXT: v_writelane_b32 v40, s35, 3
-; HAWAII-NEXT: v_writelane_b32 v40, s36, 4
-; HAWAII-NEXT: v_writelane_b32 v40, s37, 5
-; HAWAII-NEXT: v_writelane_b32 v40, s38, 6
-; HAWAII-NEXT: v_writelane_b32 v40, s39, 7
-; HAWAII-NEXT: v_writelane_b32 v40, s48, 8
-; HAWAII-NEXT: v_writelane_b32 v40, s49, 9
-; HAWAII-NEXT: v_writelane_b32 v40, s50, 10
-; HAWAII-NEXT: v_writelane_b32 v40, s51, 11
-; HAWAII-NEXT: v_writelane_b32 v40, s52, 12
-; HAWAII-NEXT: v_writelane_b32 v40, s53, 13
-; HAWAII-NEXT: v_writelane_b32 v40, s54, 14
-; HAWAII-NEXT: v_writelane_b32 v40, s55, 15
-; HAWAII-NEXT: v_writelane_b32 v40, s64, 16
+; HAWAII-NEXT: v_writelane_b32 v40, s34, 0
+; HAWAII-NEXT: v_writelane_b32 v40, s35, 1
+; HAWAII-NEXT: v_writelane_b32 v40, s36, 2
+; HAWAII-NEXT: v_writelane_b32 v40, s37, 3
+; HAWAII-NEXT: v_writelane_b32 v40, s38, 4
+; HAWAII-NEXT: v_writelane_b32 v40, s39, 5
+; HAWAII-NEXT: v_writelane_b32 v40, s48, 6
+; HAWAII-NEXT: v_writelane_b32 v40, s49, 7
+; HAWAII-NEXT: v_writelane_b32 v40, s50, 8
+; HAWAII-NEXT: v_writelane_b32 v40, s51, 9
+; HAWAII-NEXT: v_writelane_b32 v40, s52, 10
+; HAWAII-NEXT: v_writelane_b32 v40, s53, 11
+; HAWAII-NEXT: v_writelane_b32 v40, s54, 12
+; HAWAII-NEXT: v_writelane_b32 v40, s55, 13
+; HAWAII-NEXT: v_writelane_b32 v40, s64, 14
+; HAWAII-NEXT: v_writelane_b32 v40, s65, 15
+; HAWAII-NEXT: v_writelane_b32 v40, s30, 16
; HAWAII-NEXT: s_mov_b32 s50, s15
; HAWAII-NEXT: s_mov_b32 s51, s14
; HAWAII-NEXT: s_mov_b32 s52, s13
@@ -722,7 +722,7 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; HAWAII-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; HAWAII-NEXT: s_mov_b64 s[54:55], exec
; HAWAII-NEXT: s_addk_i32 s32, 0x400
-; HAWAII-NEXT: v_writelane_b32 v40, s65, 17
+; HAWAII-NEXT: v_writelane_b32 v40, s31, 17
; HAWAII-NEXT: .LBB18_1: ; =>This Inner Loop Header: Depth=1
; HAWAII-NEXT: v_readfirstlane_b32 s16, v0
; HAWAII-NEXT: v_readfirstlane_b32 s17, v1
@@ -748,25 +748,25 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; HAWAII-NEXT: s_cbranch_execnz .LBB18_1
; HAWAII-NEXT: ; %bb.2:
; HAWAII-NEXT: s_mov_b64 exec, s[54:55]
+; HAWAII-NEXT: v_readlane_b32 s30, v40, 16
; HAWAII-NEXT: v_mov_b32_e32 v0, v4
-; HAWAII-NEXT: v_readlane_b32 s65, v40, 17
-; HAWAII-NEXT: v_readlane_b32 s64, v40, 16
-; HAWAII-NEXT: v_readlane_b32 s55, v40, 15
-; HAWAII-NEXT: v_readlane_b32 s54, v40, 14
-; HAWAII-NEXT: v_readlane_b32 s53, v40, 13
-; HAWAII-NEXT: v_readlane_b32 s52, v40, 12
-; HAWAII-NEXT: v_readlane_b32 s51, v40, 11
-; HAWAII-NEXT: v_readlane_b32 s50, v40, 10
-; HAWAII-NEXT: v_readlane_b32 s49, v40, 9
-; HAWAII-NEXT: v_readlane_b32 s48, v40, 8
-; HAWAII-NEXT: v_readlane_b32 s39, v40, 7
-; HAWAII-NEXT: v_readlane_b32 s38, v40, 6
-; HAWAII-NEXT: v_readlane_b32 s37, v40, 5
-; HAWAII-NEXT: v_readlane_b32 s36, v40, 4
-; HAWAII-NEXT: v_readlane_b32 s35, v40, 3
-; HAWAII-NEXT: v_readlane_b32 s34, v40, 2
-; HAWAII-NEXT: v_readlane_b32 s31, v40, 1
-; HAWAII-NEXT: v_readlane_b32 s30, v40, 0
+; HAWAII-NEXT: v_readlane_b32 s31, v40, 17
+; HAWAII-NEXT: v_readlane_b32 s65, v40, 15
+; HAWAII-NEXT: v_readlane_b32 s64, v40, 14
+; HAWAII-NEXT: v_readlane_b32 s55, v40, 13
+; HAWAII-NEXT: v_readlane_b32 s54, v40, 12
+; HAWAII-NEXT: v_readlane_b32 s53, v40, 11
+; HAWAII-NEXT: v_readlane_b32 s52, v40, 10
+; HAWAII-NEXT: v_readlane_b32 s51, v40, 9
+; HAWAII-NEXT: v_readlane_b32 s50, v40, 8
+; HAWAII-NEXT: v_readlane_b32 s49, v40, 7
+; HAWAII-NEXT: v_readlane_b32 s48, v40, 6
+; HAWAII-NEXT: v_readlane_b32 s39, v40, 5
+; HAWAII-NEXT: v_readlane_b32 s38, v40, 4
+; HAWAII-NEXT: v_readlane_b32 s37, v40, 3
+; HAWAII-NEXT: v_readlane_b32 s36, v40, 2
+; HAWAII-NEXT: v_readlane_b32 s35, v40, 1
+; HAWAII-NEXT: v_readlane_b32 s34, v40, 0
; HAWAII-NEXT: s_mov_b32 s32, s33
; HAWAII-NEXT: v_readlane_b32 s4, v40, 18
; HAWAII-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -785,23 +785,23 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-NEXT: v_writelane_b32 v40, s16, 18
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: v_writelane_b32 v40, s35, 3
-; GFX9-NEXT: v_writelane_b32 v40, s36, 4
-; GFX9-NEXT: v_writelane_b32 v40, s37, 5
-; GFX9-NEXT: v_writelane_b32 v40, s38, 6
-; GFX9-NEXT: v_writelane_b32 v40, s39, 7
-; GFX9-NEXT: v_writelane_b32 v40, s48, 8
-; GFX9-NEXT: v_writelane_b32 v40, s49, 9
-; GFX9-NEXT: v_writelane_b32 v40, s50, 10
-; GFX9-NEXT: v_writelane_b32 v40, s51, 11
-; GFX9-NEXT: v_writelane_b32 v40, s52, 12
-; GFX9-NEXT: v_writelane_b32 v40, s53, 13
-; GFX9-NEXT: v_writelane_b32 v40, s54, 14
-; GFX9-NEXT: v_writelane_b32 v40, s55, 15
-; GFX9-NEXT: v_writelane_b32 v40, s64, 16
+; GFX9-NEXT: v_writelane_b32 v40, s34, 0
+; GFX9-NEXT: v_writelane_b32 v40, s35, 1
+; GFX9-NEXT: v_writelane_b32 v40, s36, 2
+; GFX9-NEXT: v_writelane_b32 v40, s37, 3
+; GFX9-NEXT: v_writelane_b32 v40, s38, 4
+; GFX9-NEXT: v_writelane_b32 v40, s39, 5
+; GFX9-NEXT: v_writelane_b32 v40, s48, 6
+; GFX9-NEXT: v_writelane_b32 v40, s49, 7
+; GFX9-NEXT: v_writelane_b32 v40, s50, 8
+; GFX9-NEXT: v_writelane_b32 v40, s51, 9
+; GFX9-NEXT: v_writelane_b32 v40, s52, 10
+; GFX9-NEXT: v_writelane_b32 v40, s53, 11
+; GFX9-NEXT: v_writelane_b32 v40, s54, 12
+; GFX9-NEXT: v_writelane_b32 v40, s55, 13
+; GFX9-NEXT: v_writelane_b32 v40, s64, 14
+; GFX9-NEXT: v_writelane_b32 v40, s65, 15
+; GFX9-NEXT: v_writelane_b32 v40, s30, 16
; GFX9-NEXT: s_mov_b32 s50, s15
; GFX9-NEXT: s_mov_b32 s51, s14
; GFX9-NEXT: s_mov_b32 s52, s13
@@ -813,7 +813,7 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
; GFX9-NEXT: s_mov_b64 s[54:55], exec
; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s65, 17
+; GFX9-NEXT: v_writelane_b32 v40, s31, 17
; GFX9-NEXT: .LBB18_1: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_readfirstlane_b32 s16, v0
; GFX9-NEXT: v_readfirstlane_b32 s17, v1
@@ -839,25 +839,25 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; GFX9-NEXT: s_cbranch_execnz .LBB18_1
; GFX9-NEXT: ; %bb.2:
; GFX9-NEXT: s_mov_b64 exec, s[54:55]
+; GFX9-NEXT: v_readlane_b32 s30, v40, 16
; GFX9-NEXT: v_mov_b32_e32 v0, v4
-; GFX9-NEXT: v_readlane_b32 s65, v40, 17
-; GFX9-NEXT: v_readlane_b32 s64, v40, 16
-; GFX9-NEXT: v_readlane_b32 s55, v40, 15
-; GFX9-NEXT: v_readlane_b32 s54, v40, 14
-; GFX9-NEXT: v_readlane_b32 s53, v40, 13
-; GFX9-NEXT: v_readlane_b32 s52, v40, 12
-; GFX9-NEXT: v_readlane_b32 s51, v40, 11
-; GFX9-NEXT: v_readlane_b32 s50, v40, 10
-; GFX9-NEXT: v_readlane_b32 s49, v40, 9
-; GFX9-NEXT: v_readlane_b32 s48, v40, 8
-; GFX9-NEXT: v_readlane_b32 s39, v40, 7
-; GFX9-NEXT: v_readlane_b32 s38, v40, 6
-; GFX9-NEXT: v_readlane_b32 s37, v40, 5
-; GFX9-NEXT: v_readlane_b32 s36, v40, 4
-; GFX9-NEXT: v_readlane_b32 s35, v40, 3
-; GFX9-NEXT: v_readlane_b32 s34, v40, 2
-; GFX9-NEXT: v_readlane_b32 s31, v40, 1
-; GFX9-NEXT: v_readlane_b32 s30, v40, 0
+; GFX9-NEXT: v_readlane_b32 s31, v40, 17
+; GFX9-NEXT: v_readlane_b32 s65, v40, 15
+; GFX9-NEXT: v_readlane_b32 s64, v40, 14
+; GFX9-NEXT: v_readlane_b32 s55, v40, 13
+; GFX9-NEXT: v_readlane_b32 s54, v40, 12
+; GFX9-NEXT: v_readlane_b32 s53, v40, 11
+; GFX9-NEXT: v_readlane_b32 s52, v40, 10
+; GFX9-NEXT: v_readlane_b32 s51, v40, 9
+; GFX9-NEXT: v_readlane_b32 s50, v40, 8
+; GFX9-NEXT: v_readlane_b32 s49, v40, 7
+; GFX9-NEXT: v_readlane_b32 s48, v40, 6
+; GFX9-NEXT: v_readlane_b32 s39, v40, 5
+; GFX9-NEXT: v_readlane_b32 s38, v40, 4
+; GFX9-NEXT: v_readlane_b32 s37, v40, 3
+; GFX9-NEXT: v_readlane_b32 s36, v40, 2
+; GFX9-NEXT: v_readlane_b32 s35, v40, 1
+; GFX9-NEXT: v_readlane_b32 s34, v40, 0
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v40, 18
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/stack-realign.ll b/llvm/test/CodeGen/AMDGPU/stack-realign.ll
index 52d9a30ffb8ba..1c9ee01807a5f 100644
--- a/llvm/test/CodeGen/AMDGPU/stack-realign.ll
+++ b/llvm/test/CodeGen/AMDGPU/stack-realign.ll
@@ -311,8 +311,8 @@ define void @func_call_align1024_bp_gets_vgpr_spill(<32 x i32> %a, i32 %b) #0 {
; GCN-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 1
; GCN-NEXT: s_mov_b32 s32, s34
; GCN-NEXT: v_readlane_b32 s4, v40, 2
; GCN-NEXT: v_readlane_b32 s34, v40, 3
diff --git a/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll b/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
index d2394bab82c77..06f1c08d1f04e 100644
--- a/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
+++ b/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
@@ -1283,11 +1283,11 @@ define void @func_stacksave_stackrestore_call_with_stack_objects() {
; WAVE32-OPT-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4
; WAVE32-OPT-NEXT: s_swappc_b64 s[30:31], s[16:17]
; WAVE32-OPT-NEXT: s_mov_b32 s32, s18
+; WAVE32-OPT-NEXT: v_readlane_b32 s30, v32, 0
; WAVE32-OPT-NEXT: ;;#ASMSTART
; WAVE32-OPT-NEXT: ; use s19
; WAVE32-OPT-NEXT: ;;#ASMEND
; WAVE32-OPT-NEXT: v_readlane_b32 s31, v32, 1
-; WAVE32-OPT-NEXT: v_readlane_b32 s30, v32, 0
; WAVE32-OPT-NEXT: s_mov_b32 s32, s33
; WAVE32-OPT-NEXT: s_xor_saveexec_b32 s4, -1
; WAVE32-OPT-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload
@@ -1318,11 +1318,11 @@ define void @func_stacksave_stackrestore_call_with_stack_objects() {
; WAVE64-OPT-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4
; WAVE64-OPT-NEXT: s_swappc_b64 s[30:31], s[16:17]
; WAVE64-OPT-NEXT: s_mov_b32 s32, s18
+; WAVE64-OPT-NEXT: v_readlane_b32 s30, v32, 0
; WAVE64-OPT-NEXT: ;;#ASMSTART
; WAVE64-OPT-NEXT: ; use s19
; WAVE64-OPT-NEXT: ;;#ASMEND
; WAVE64-OPT-NEXT: v_readlane_b32 s31, v32, 1
-; WAVE64-OPT-NEXT: v_readlane_b32 s30, v32, 0
; WAVE64-OPT-NEXT: s_mov_b32 s32, s33
; WAVE64-OPT-NEXT: s_xor_saveexec_b64 s[4:5], -1
; WAVE64-OPT-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload
@@ -1431,8 +1431,8 @@ define void @func_stacksave_stackrestore_call_with_stack_objects() {
; WAVE32-O0-NEXT: ; use s5
; WAVE32-O0-NEXT: ;;#ASMEND
; WAVE32-O0-NEXT: s_mov_b32 s32, s4
-; WAVE32-O0-NEXT: v_readlane_b32 s31, v32, 1
; WAVE32-O0-NEXT: v_readlane_b32 s30, v32, 0
+; WAVE32-O0-NEXT: v_readlane_b32 s31, v32, 1
; WAVE32-O0-NEXT: s_mov_b32 s32, s33
; WAVE32-O0-NEXT: s_xor_saveexec_b32 s4, -1
; WAVE32-O0-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload
@@ -1542,8 +1542,8 @@ define void @func_stacksave_stackrestore_call_with_stack_objects() {
; WAVE64-O0-NEXT: ; use s5
; WAVE64-O0-NEXT: ;;#ASMEND
; WAVE64-O0-NEXT: s_mov_b32 s32, s4
-; WAVE64-O0-NEXT: v_readlane_b32 s31, v32, 1
; WAVE64-O0-NEXT: v_readlane_b32 s30, v32, 0
+; WAVE64-O0-NEXT: v_readlane_b32 s31, v32, 1
; WAVE64-O0-NEXT: s_mov_b32 s32, s33
; WAVE64-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
; WAVE64-O0-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload
@@ -1653,8 +1653,8 @@ define void @func_stacksave_stackrestore_call_with_stack_objects() {
; WAVE32-WWM-PREALLOC-NEXT: ; use s5
; WAVE32-WWM-PREALLOC-NEXT: ;;#ASMEND
; WAVE32-WWM-PREALLOC-NEXT: s_mov_b32 s32, s4
-; WAVE32-WWM-PREALLOC-NEXT: v_readlane_b32 s31, v33, 1
; WAVE32-WWM-PREALLOC-NEXT: v_readlane_b32 s30, v33, 0
+; WAVE32-WWM-PREALLOC-NEXT: v_readlane_b32 s31, v33, 1
; WAVE32-WWM-PREALLOC-NEXT: s_mov_b32 s32, s33
; WAVE32-WWM-PREALLOC-NEXT: s_xor_saveexec_b32 s4, -1
; WAVE32-WWM-PREALLOC-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:128 ; 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll b/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
index 5c83491e7289e..4232a09d9fc3a 100644
--- a/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
+++ b/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
@@ -194,8 +194,8 @@ define void @outgoing_f16_arg(ptr %ptr) #0 {
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX7-NEXT: v_readlane_b32 s31, v40, 1
; GFX7-NEXT: v_readlane_b32 s30, v40, 0
+; GFX7-NEXT: v_readlane_b32 s31, v40, 1
; GFX7-NEXT: s_mov_b32 s32, s33
; GFX7-NEXT: v_readlane_b32 s4, v40, 2
; GFX7-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -230,8 +230,8 @@ define void @outgoing_v2f16_arg(ptr %ptr) #0 {
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX7-NEXT: v_readlane_b32 s31, v40, 1
; GFX7-NEXT: v_readlane_b32 s30, v40, 0
+; GFX7-NEXT: v_readlane_b32 s31, v40, 1
; GFX7-NEXT: s_mov_b32 s32, s33
; GFX7-NEXT: v_readlane_b32 s4, v40, 2
; GFX7-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -266,8 +266,8 @@ define void @outgoing_f16_return(ptr %ptr) #0 {
; GFX7-NEXT: v_mov_b32_e32 v40, v0
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_readlane_b32 s31, v42, 1
; GFX7-NEXT: v_readlane_b32 s30, v42, 0
+; GFX7-NEXT: v_readlane_b32 s31, v42, 1
; GFX7-NEXT: s_mov_b32 s32, s33
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
@@ -309,8 +309,8 @@ define void @outgoing_v2f16_return(ptr %ptr) #0 {
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7-NEXT: v_readlane_b32 s31, v42, 1
; GFX7-NEXT: v_readlane_b32 s30, v42, 0
+; GFX7-NEXT: v_readlane_b32 s31, v42, 1
; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -381,8 +381,8 @@ define void @outgoing_v4f16_return(ptr %ptr) #0 {
; GFX7-NEXT: flat_store_dword v[40:41], v4
; GFX7-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX7-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX7-NEXT: v_readlane_b32 s31, v42, 1
; GFX7-NEXT: v_readlane_b32 s30, v42, 0
+; GFX7-NEXT: v_readlane_b32 s31, v42, 1
; GFX7-NEXT: s_mov_b32 s32, s33
; GFX7-NEXT: v_readlane_b32 s4, v42, 2
; GFX7-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -468,8 +468,8 @@ define void @outgoing_v8f16_return(ptr %ptr) #0 {
; GFX7-NEXT: flat_store_dword v[40:41], v8
; GFX7-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX7-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GFX7-NEXT: v_readlane_b32 s31, v42, 1
; GFX7-NEXT: v_readlane_b32 s30, v42, 0
+; GFX7-NEXT: v_readlane_b32 s31, v42, 1
; GFX7-NEXT: s_mov_b32 s32, s33
; GFX7-NEXT: v_readlane_b32 s4, v42, 2
; GFX7-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -518,6 +518,7 @@ define half @call_split_type_used_outside_block_v8f16() #0 {
; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX7-NEXT: v_readlane_b32 s30, v40, 0
; GFX7-NEXT: v_cvt_f32_f16_e32 v7, v7
; GFX7-NEXT: v_cvt_f32_f16_e32 v6, v6
; GFX7-NEXT: v_cvt_f32_f16_e32 v5, v5
@@ -527,7 +528,6 @@ define half @call_split_type_used_outside_block_v8f16() #0 {
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-NEXT: v_readlane_b32 s31, v40, 1
-; GFX7-NEXT: v_readlane_b32 s30, v40, 0
; GFX7-NEXT: s_mov_b32 s32, s33
; GFX7-NEXT: v_readlane_b32 s4, v40, 2
; GFX7-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll b/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
index 5c6fcd4f977e3..13cde61ff16a0 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
+++ b/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
@@ -18,11 +18,12 @@ define void @test_load_zext() #0 {
; CHECK-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; CHECK-NEXT: v_writelane_b32 v40, s30, 0
; CHECK-NEXT: s_mov_b32 s0, DescriptorBuffer at abs32@lo
+; CHECK-NEXT: s_nop 0
; CHECK-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; CHECK-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-NEXT: v_readlane_b32 s30, v40, 0
+; CHECK-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: v_readlane_b32 s0, v40, 2
; CHECK-NEXT: s_or_saveexec_b64 s[2:3], -1
diff --git a/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll b/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll
index d76b2e5f2358d..837b66dadbba5 100644
--- a/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll
+++ b/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll
@@ -26,8 +26,8 @@ define void @tail_call_i32_inreg_divergent(i32 %vgpr) #0 {
; CHECK-NEXT: s_addc_u32 s17, s17, void_func_i32_inreg at rel32@hi+12
; CHECK-NEXT: ; illegal copy v0 to s0
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; CHECK-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-NEXT: v_readlane_b32 s30, v40, 0
+; CHECK-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: v_readlane_b32 s4, v40, 2
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -62,8 +62,8 @@ define void @indirect_tail_call_i32_inreg_divergent(i32 %vgpr) #0 {
; CHECK-NEXT: ; illegal copy v0 to s0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; CHECK-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-NEXT: v_readlane_b32 s30, v40, 0
+; CHECK-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-NEXT: s_mov_b32 s32, s33
; CHECK-NEXT: v_readlane_b32 s4, v40, 2
; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll b/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll
index e78d62561238b..e5215fe1acdef 100644
--- a/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll
+++ b/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll
@@ -646,29 +646,30 @@ define i32 @s_in_multiuse_A(i32 inreg %x, i32 inreg %y, i32 inreg %z, i32 inreg
; GCN-NEXT: s_or_saveexec_b32 s16, -1
; GCN-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b32 exec_lo, s16
-; GCN-NEXT: v_writelane_b32 v40, s2, 4
; GCN-NEXT: s_add_i32 s32, s32, 16
; GCN-NEXT: s_getpc_b64 s[16:17]
; GCN-NEXT: s_add_u32 s16, s16, use32 at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s17, s17, use32 at gotpcrel32@hi+12
-; GCN-NEXT: s_xor_b32 s0, s0, s1
+; GCN-NEXT: v_writelane_b32 v40, s2, 4
; GCN-NEXT: s_load_b64 s[16:17], s[16:17], 0x0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
-; GCN-NEXT: v_writelane_b32 v40, s34, 2
+; GCN-NEXT: s_xor_b32 s0, s0, s1
+; GCN-NEXT: v_writelane_b32 v40, s34, 0
; GCN-NEXT: s_mov_b32 s34, s1
-; GCN-NEXT: v_writelane_b32 v40, s35, 3
+; GCN-NEXT: v_writelane_b32 v40, s35, 1
; GCN-NEXT: s_and_b32 s35, s0, s3
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GCN-NEXT: v_mov_b32_e32 v0, s35
+; GCN-NEXT: v_writelane_b32 v40, s30, 2
+; GCN-NEXT: v_writelane_b32 v40, s31, 3
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: s_xor_b32 s0, s35, s34
-; GCN-NEXT: v_readlane_b32 s35, v40, 3
+; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GCN-NEXT: v_readlane_b32 s30, v40, 2
; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_readlane_b32 s34, v40, 2
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
-; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 3
+; GCN-NEXT: v_readlane_b32 s35, v40, 1
+; GCN-NEXT: v_readlane_b32 s34, v40, 0
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s0, v40, 4
; GCN-NEXT: s_or_saveexec_b32 s1, -1
@@ -702,20 +703,21 @@ define i32 @s_in_multiuse_B(i32 inreg %x, i32 inreg %y, i32 inreg %z, i32 inreg
; GCN-NEXT: s_xor_b32 s0, s0, s1
; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
-; GCN-NEXT: v_writelane_b32 v40, s34, 2
+; GCN-NEXT: v_writelane_b32 v40, s34, 0
; GCN-NEXT: s_mov_b32 s34, s1
-; GCN-NEXT: v_writelane_b32 v40, s35, 3
+; GCN-NEXT: v_writelane_b32 v40, s35, 1
; GCN-NEXT: s_and_b32 s35, s0, s3
+; GCN-NEXT: v_writelane_b32 v40, s30, 2
+; GCN-NEXT: v_writelane_b32 v40, s31, 3
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: s_xor_b32 s0, s35, s34
-; GCN-NEXT: v_readlane_b32 s35, v40, 3
+; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GCN-NEXT: v_readlane_b32 s30, v40, 2
; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_readlane_b32 s34, v40, 2
-; GCN-NEXT: v_readlane_b32 s31, v40, 1
-; GCN-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-NEXT: v_readlane_b32 s31, v40, 3
+; GCN-NEXT: v_readlane_b32 s35, v40, 1
+; GCN-NEXT: v_readlane_b32 s34, v40, 0
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s0, v40, 4
; GCN-NEXT: s_or_saveexec_b32 s1, -1
diff --git a/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll b/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
index 25e8581fb6cdd..639dcdcbf1c2a 100644
--- a/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
+++ b/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
@@ -14,22 +14,22 @@ define hidden void @widget() {
; GCN-NEXT: v_writelane_b32 v41, s16, 16
; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GCN-NEXT: v_writelane_b32 v41, s30, 0
-; GCN-NEXT: v_writelane_b32 v41, s31, 1
-; GCN-NEXT: v_writelane_b32 v41, s34, 2
-; GCN-NEXT: v_writelane_b32 v41, s35, 3
-; GCN-NEXT: v_writelane_b32 v41, s36, 4
-; GCN-NEXT: v_writelane_b32 v41, s37, 5
-; GCN-NEXT: v_writelane_b32 v41, s38, 6
-; GCN-NEXT: v_writelane_b32 v41, s39, 7
-; GCN-NEXT: v_writelane_b32 v41, s48, 8
-; GCN-NEXT: v_writelane_b32 v41, s49, 9
-; GCN-NEXT: v_writelane_b32 v41, s50, 10
-; GCN-NEXT: v_writelane_b32 v41, s51, 11
-; GCN-NEXT: v_writelane_b32 v41, s52, 12
-; GCN-NEXT: v_writelane_b32 v41, s53, 13
-; GCN-NEXT: v_writelane_b32 v41, s54, 14
-; GCN-NEXT: v_writelane_b32 v41, s55, 15
+; GCN-NEXT: v_writelane_b32 v41, s34, 0
+; GCN-NEXT: v_writelane_b32 v41, s35, 1
+; GCN-NEXT: v_writelane_b32 v41, s36, 2
+; GCN-NEXT: v_writelane_b32 v41, s37, 3
+; GCN-NEXT: v_writelane_b32 v41, s38, 4
+; GCN-NEXT: v_writelane_b32 v41, s39, 5
+; GCN-NEXT: v_writelane_b32 v41, s48, 6
+; GCN-NEXT: v_writelane_b32 v41, s49, 7
+; GCN-NEXT: v_writelane_b32 v41, s50, 8
+; GCN-NEXT: v_writelane_b32 v41, s51, 9
+; GCN-NEXT: v_writelane_b32 v41, s52, 10
+; GCN-NEXT: v_writelane_b32 v41, s53, 11
+; GCN-NEXT: v_writelane_b32 v41, s54, 12
+; GCN-NEXT: v_writelane_b32 v41, s55, 13
+; GCN-NEXT: v_writelane_b32 v41, s30, 14
+; GCN-NEXT: v_writelane_b32 v41, s31, 15
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: flat_load_dword v0, v[0:1]
@@ -93,22 +93,22 @@ define hidden void @widget() {
; GCN-NEXT: s_addc_u32 s17, s17, wibble at rel32@hi+12
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: .LBB0_8: ; %UnifiedReturnBlock
-; GCN-NEXT: v_readlane_b32 s55, v41, 15
-; GCN-NEXT: v_readlane_b32 s54, v41, 14
-; GCN-NEXT: v_readlane_b32 s53, v41, 13
-; GCN-NEXT: v_readlane_b32 s52, v41, 12
-; GCN-NEXT: v_readlane_b32 s51, v41, 11
-; GCN-NEXT: v_readlane_b32 s50, v41, 10
-; GCN-NEXT: v_readlane_b32 s49, v41, 9
-; GCN-NEXT: v_readlane_b32 s48, v41, 8
-; GCN-NEXT: v_readlane_b32 s39, v41, 7
-; GCN-NEXT: v_readlane_b32 s38, v41, 6
-; GCN-NEXT: v_readlane_b32 s37, v41, 5
-; GCN-NEXT: v_readlane_b32 s36, v41, 4
-; GCN-NEXT: v_readlane_b32 s35, v41, 3
-; GCN-NEXT: v_readlane_b32 s34, v41, 2
-; GCN-NEXT: v_readlane_b32 s31, v41, 1
-; GCN-NEXT: v_readlane_b32 s30, v41, 0
+; GCN-NEXT: v_readlane_b32 s30, v41, 14
+; GCN-NEXT: v_readlane_b32 s31, v41, 15
+; GCN-NEXT: v_readlane_b32 s55, v41, 13
+; GCN-NEXT: v_readlane_b32 s54, v41, 12
+; GCN-NEXT: v_readlane_b32 s53, v41, 11
+; GCN-NEXT: v_readlane_b32 s52, v41, 10
+; GCN-NEXT: v_readlane_b32 s51, v41, 9
+; GCN-NEXT: v_readlane_b32 s50, v41, 8
+; GCN-NEXT: v_readlane_b32 s49, v41, 7
+; GCN-NEXT: v_readlane_b32 s48, v41, 6
+; GCN-NEXT: v_readlane_b32 s39, v41, 5
+; GCN-NEXT: v_readlane_b32 s38, v41, 4
+; GCN-NEXT: v_readlane_b32 s37, v41, 3
+; GCN-NEXT: v_readlane_b32 s36, v41, 2
+; GCN-NEXT: v_readlane_b32 s35, v41, 1
+; GCN-NEXT: v_readlane_b32 s34, v41, 0
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v41, 16
@@ -266,32 +266,32 @@ define hidden void @blam() {
; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 ; 4-byte Folded Spill
-; GCN-NEXT: v_writelane_b32 v45, s30, 0
-; GCN-NEXT: v_writelane_b32 v45, s31, 1
-; GCN-NEXT: v_writelane_b32 v45, s34, 2
-; GCN-NEXT: v_writelane_b32 v45, s35, 3
-; GCN-NEXT: v_writelane_b32 v45, s36, 4
-; GCN-NEXT: v_writelane_b32 v45, s37, 5
-; GCN-NEXT: v_writelane_b32 v45, s38, 6
-; GCN-NEXT: v_writelane_b32 v45, s39, 7
-; GCN-NEXT: v_writelane_b32 v45, s48, 8
-; GCN-NEXT: v_writelane_b32 v45, s49, 9
-; GCN-NEXT: v_writelane_b32 v45, s50, 10
-; GCN-NEXT: v_writelane_b32 v45, s51, 11
-; GCN-NEXT: v_writelane_b32 v45, s52, 12
-; GCN-NEXT: v_writelane_b32 v45, s53, 13
-; GCN-NEXT: v_writelane_b32 v45, s54, 14
-; GCN-NEXT: v_writelane_b32 v45, s55, 15
-; GCN-NEXT: v_writelane_b32 v45, s64, 16
-; GCN-NEXT: v_writelane_b32 v45, s65, 17
-; GCN-NEXT: v_writelane_b32 v45, s66, 18
-; GCN-NEXT: v_writelane_b32 v45, s67, 19
-; GCN-NEXT: v_writelane_b32 v45, s68, 20
-; GCN-NEXT: v_writelane_b32 v45, s69, 21
-; GCN-NEXT: v_writelane_b32 v45, s70, 22
-; GCN-NEXT: v_writelane_b32 v45, s71, 23
-; GCN-NEXT: v_writelane_b32 v45, s80, 24
-; GCN-NEXT: v_writelane_b32 v45, s81, 25
+; GCN-NEXT: v_writelane_b32 v45, s34, 0
+; GCN-NEXT: v_writelane_b32 v45, s35, 1
+; GCN-NEXT: v_writelane_b32 v45, s36, 2
+; GCN-NEXT: v_writelane_b32 v45, s37, 3
+; GCN-NEXT: v_writelane_b32 v45, s38, 4
+; GCN-NEXT: v_writelane_b32 v45, s39, 5
+; GCN-NEXT: v_writelane_b32 v45, s48, 6
+; GCN-NEXT: v_writelane_b32 v45, s49, 7
+; GCN-NEXT: v_writelane_b32 v45, s50, 8
+; GCN-NEXT: v_writelane_b32 v45, s51, 9
+; GCN-NEXT: v_writelane_b32 v45, s52, 10
+; GCN-NEXT: v_writelane_b32 v45, s53, 11
+; GCN-NEXT: v_writelane_b32 v45, s54, 12
+; GCN-NEXT: v_writelane_b32 v45, s55, 13
+; GCN-NEXT: v_writelane_b32 v45, s64, 14
+; GCN-NEXT: v_writelane_b32 v45, s65, 15
+; GCN-NEXT: v_writelane_b32 v45, s66, 16
+; GCN-NEXT: v_writelane_b32 v45, s67, 17
+; GCN-NEXT: v_writelane_b32 v45, s68, 18
+; GCN-NEXT: v_writelane_b32 v45, s69, 19
+; GCN-NEXT: v_writelane_b32 v45, s70, 20
+; GCN-NEXT: v_writelane_b32 v45, s71, 21
+; GCN-NEXT: v_writelane_b32 v45, s80, 22
+; GCN-NEXT: v_writelane_b32 v45, s81, 23
+; GCN-NEXT: v_writelane_b32 v45, s30, 24
+; GCN-NEXT: v_writelane_b32 v45, s31, 25
; GCN-NEXT: v_mov_b32_e32 v40, v31
; GCN-NEXT: s_mov_b32 s54, s15
; GCN-NEXT: s_mov_b32 s55, s14
@@ -427,32 +427,32 @@ define hidden void @blam() {
; GCN-NEXT: s_branch .LBB1_1
; GCN-NEXT: .LBB1_18: ; %DummyReturnBlock
; GCN-NEXT: s_or_b64 exec, exec, s[66:67]
-; GCN-NEXT: v_readlane_b32 s81, v45, 25
-; GCN-NEXT: v_readlane_b32 s80, v45, 24
-; GCN-NEXT: v_readlane_b32 s71, v45, 23
-; GCN-NEXT: v_readlane_b32 s70, v45, 22
-; GCN-NEXT: v_readlane_b32 s69, v45, 21
-; GCN-NEXT: v_readlane_b32 s68, v45, 20
-; GCN-NEXT: v_readlane_b32 s67, v45, 19
-; GCN-NEXT: v_readlane_b32 s66, v45, 18
-; GCN-NEXT: v_readlane_b32 s65, v45, 17
-; GCN-NEXT: v_readlane_b32 s64, v45, 16
-; GCN-NEXT: v_readlane_b32 s55, v45, 15
-; GCN-NEXT: v_readlane_b32 s54, v45, 14
-; GCN-NEXT: v_readlane_b32 s53, v45, 13
-; GCN-NEXT: v_readlane_b32 s52, v45, 12
-; GCN-NEXT: v_readlane_b32 s51, v45, 11
-; GCN-NEXT: v_readlane_b32 s50, v45, 10
-; GCN-NEXT: v_readlane_b32 s49, v45, 9
-; GCN-NEXT: v_readlane_b32 s48, v45, 8
-; GCN-NEXT: v_readlane_b32 s39, v45, 7
-; GCN-NEXT: v_readlane_b32 s38, v45, 6
-; GCN-NEXT: v_readlane_b32 s37, v45, 5
-; GCN-NEXT: v_readlane_b32 s36, v45, 4
-; GCN-NEXT: v_readlane_b32 s35, v45, 3
-; GCN-NEXT: v_readlane_b32 s34, v45, 2
-; GCN-NEXT: v_readlane_b32 s31, v45, 1
-; GCN-NEXT: v_readlane_b32 s30, v45, 0
+; GCN-NEXT: v_readlane_b32 s30, v45, 24
+; GCN-NEXT: v_readlane_b32 s31, v45, 25
+; GCN-NEXT: v_readlane_b32 s81, v45, 23
+; GCN-NEXT: v_readlane_b32 s80, v45, 22
+; GCN-NEXT: v_readlane_b32 s71, v45, 21
+; GCN-NEXT: v_readlane_b32 s70, v45, 20
+; GCN-NEXT: v_readlane_b32 s69, v45, 19
+; GCN-NEXT: v_readlane_b32 s68, v45, 18
+; GCN-NEXT: v_readlane_b32 s67, v45, 17
+; GCN-NEXT: v_readlane_b32 s66, v45, 16
+; GCN-NEXT: v_readlane_b32 s65, v45, 15
+; GCN-NEXT: v_readlane_b32 s64, v45, 14
+; GCN-NEXT: v_readlane_b32 s55, v45, 13
+; GCN-NEXT: v_readlane_b32 s54, v45, 12
+; GCN-NEXT: v_readlane_b32 s53, v45, 11
+; GCN-NEXT: v_readlane_b32 s52, v45, 10
+; GCN-NEXT: v_readlane_b32 s51, v45, 9
+; GCN-NEXT: v_readlane_b32 s50, v45, 8
+; GCN-NEXT: v_readlane_b32 s49, v45, 7
+; GCN-NEXT: v_readlane_b32 s48, v45, 6
+; GCN-NEXT: v_readlane_b32 s39, v45, 5
+; GCN-NEXT: v_readlane_b32 s38, v45, 4
+; GCN-NEXT: v_readlane_b32 s37, v45, 3
+; GCN-NEXT: v_readlane_b32 s36, v45, 2
+; GCN-NEXT: v_readlane_b32 s35, v45, 1
+; GCN-NEXT: v_readlane_b32 s34, v45, 0
; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s33 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll b/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
index 9ce8859c410fc..c902ac6173935 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
@@ -52,8 +52,8 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s31, v44, 1
; GFX9-NEXT: v_readlane_b32 s30, v44, 0
+; GFX9-NEXT: v_readlane_b32 s31, v44, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v44, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -109,8 +109,8 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:4
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:8
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:12
-; GFX10-NEXT: v_readlane_b32 s31, v44, 1
; GFX10-NEXT: v_readlane_b32 s30, v44, 0
+; GFX10-NEXT: v_readlane_b32 s31, v44, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s4, v44, 2
; GFX10-NEXT: s_or_saveexec_b32 s5, -1
@@ -163,8 +163,8 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX11-NEXT: scratch_load_b32 v42, off, s33 offset:4
; GFX11-NEXT: scratch_load_b32 v41, off, s33 offset:8
; GFX11-NEXT: scratch_load_b32 v40, off, s33 offset:12
-; GFX11-NEXT: v_readlane_b32 s31, v44, 1
; GFX11-NEXT: v_readlane_b32 s30, v44, 0
+; GFX11-NEXT: v_readlane_b32 s31, v44, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v44, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
@@ -236,8 +236,8 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
-; GFX9-NEXT: v_readlane_b32 s31, v45, 1
; GFX9-NEXT: v_readlane_b32 s30, v45, 0
+; GFX9-NEXT: v_readlane_b32 s31, v45, 1
; GFX9-NEXT: s_mov_b32 s32, s33
; GFX9-NEXT: v_readlane_b32 s4, v45, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
@@ -286,8 +286,8 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:8
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:12
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:16
-; GFX10-NEXT: v_readlane_b32 s31, v45, 1
; GFX10-NEXT: v_readlane_b32 s30, v45, 0
+; GFX10-NEXT: v_readlane_b32 s31, v45, 1
; GFX10-NEXT: s_mov_b32 s32, s33
; GFX10-NEXT: v_readlane_b32 s4, v45, 2
; GFX10-NEXT: s_or_saveexec_b32 s5, -1
@@ -335,8 +335,8 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX11-NEXT: scratch_load_b32 v42, off, s33 offset:8
; GFX11-NEXT: scratch_load_b32 v41, off, s33 offset:12
; GFX11-NEXT: scratch_load_b32 v40, off, s33 offset:16
-; GFX11-NEXT: v_readlane_b32 s31, v45, 1
; GFX11-NEXT: v_readlane_b32 s30, v45, 0
+; GFX11-NEXT: v_readlane_b32 s31, v45, 1
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_readlane_b32 s0, v45, 2
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll
index 1805add14e47a..a76f4495f85d5 100644
--- a/llvm/test/CodeGen/AMDGPU/wave32.ll
+++ b/llvm/test/CodeGen/AMDGPU/wave32.ll
@@ -3086,8 +3086,8 @@ define void @callee_no_stack_with_call() #1 {
; GFX1032-NEXT: v_writelane_b32 v40, s31, 1
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX1032-NEXT: v_readlane_b32 s31, v40, 1
; GFX1032-NEXT: v_readlane_b32 s30, v40, 0
+; GFX1032-NEXT: v_readlane_b32 s31, v40, 1
; GFX1032-NEXT: s_mov_b32 s32, s33
; GFX1032-NEXT: v_readlane_b32 s4, v40, 2
; GFX1032-NEXT: s_or_saveexec_b32 s5, -1
@@ -3117,8 +3117,8 @@ define void @callee_no_stack_with_call() #1 {
; GFX1064-NEXT: v_writelane_b32 v40, s31, 1
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX1064-NEXT: v_readlane_b32 s31, v40, 1
; GFX1064-NEXT: v_readlane_b32 s30, v40, 0
+; GFX1064-NEXT: v_readlane_b32 s31, v40, 1
; GFX1064-NEXT: s_mov_b32 s32, s33
; GFX1064-NEXT: v_readlane_b32 s4, v40, 2
; GFX1064-NEXT: s_or_saveexec_b64 s[6:7], -1
diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
index d1d591d19a58b..c44fff4ad82be 100644
--- a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+++ b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
@@ -1593,8 +1593,8 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; DAGISEL-NEXT: s_wait_alu 0xfffe
; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; DAGISEL-NEXT: v_readlane_b32 s31, v40, 2
; DAGISEL-NEXT: v_readlane_b32 s30, v40, 1
+; DAGISEL-NEXT: v_readlane_b32 s31, v40, 2
; DAGISEL-NEXT: v_readlane_b32 s4, v40, 0
; DAGISEL-NEXT: v_readlane_b32 s0, v40, 3
; DAGISEL-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
@@ -1929,8 +1929,8 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; GISEL-NEXT: s_wait_alu 0xfffe
; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-NEXT: v_readlane_b32 s31, v40, 2
; GISEL-NEXT: v_readlane_b32 s30, v40, 1
+; GISEL-NEXT: v_readlane_b32 s31, v40, 2
; GISEL-NEXT: v_readlane_b32 s4, v40, 0
; GISEL-NEXT: v_readlane_b32 s0, v40, 3
; GISEL-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
@@ -2266,8 +2266,8 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; DAGISEL64-NEXT: s_wait_alu 0xfffe
; DAGISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1]
; DAGISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; DAGISEL64-NEXT: v_readlane_b32 s31, v40, 3
; DAGISEL64-NEXT: v_readlane_b32 s30, v40, 2
+; DAGISEL64-NEXT: v_readlane_b32 s31, v40, 3
; DAGISEL64-NEXT: v_readlane_b32 s5, v40, 1
; DAGISEL64-NEXT: v_readlane_b32 s4, v40, 0
; DAGISEL64-NEXT: v_readlane_b32 s0, v40, 4
@@ -2604,8 +2604,8 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; GISEL64-NEXT: s_wait_alu 0xfffe
; GISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL64-NEXT: v_readlane_b32 s31, v40, 3
; GISEL64-NEXT: v_readlane_b32 s30, v40, 2
+; GISEL64-NEXT: v_readlane_b32 s31, v40, 3
; GISEL64-NEXT: v_readlane_b32 s5, v40, 1
; GISEL64-NEXT: v_readlane_b32 s4, v40, 0
; GISEL64-NEXT: v_readlane_b32 s0, v40, 4
@@ -3719,8 +3719,8 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; GFX1250-DAGISEL-NEXT: v_writelane_b32 v40, s31, 2
; GFX1250-DAGISEL-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
; GFX1250-DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-DAGISEL-NEXT: v_readlane_b32 s31, v40, 2
; GFX1250-DAGISEL-NEXT: v_readlane_b32 s30, v40, 1
+; GFX1250-DAGISEL-NEXT: v_readlane_b32 s31, v40, 2
; GFX1250-DAGISEL-NEXT: v_readlane_b32 s4, v40, 0
; GFX1250-DAGISEL-NEXT: v_readlane_b32 s0, v40, 3
; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
@@ -8048,8 +8048,8 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; DAGISEL-NEXT: s_wait_alu 0xfffe
; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; DAGISEL-NEXT: flat_store_b32 v[40:41], v0
-; DAGISEL-NEXT: v_readlane_b32 s31, v42, 2
; DAGISEL-NEXT: v_readlane_b32 s30, v42, 1
+; DAGISEL-NEXT: v_readlane_b32 s31, v42, 2
; DAGISEL-NEXT: v_readlane_b32 s4, v42, 0
; DAGISEL-NEXT: v_readlane_b32 s0, v42, 3
; DAGISEL-NEXT: s_clause 0x2
@@ -8389,8 +8389,8 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; GISEL-NEXT: s_wait_alu 0xfffe
; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GISEL-NEXT: flat_store_b32 v[40:41], v0
-; GISEL-NEXT: v_readlane_b32 s31, v42, 2
; GISEL-NEXT: v_readlane_b32 s30, v42, 1
+; GISEL-NEXT: v_readlane_b32 s31, v42, 2
; GISEL-NEXT: v_readlane_b32 s4, v42, 0
; GISEL-NEXT: v_readlane_b32 s0, v42, 3
; GISEL-NEXT: s_clause 0x2
@@ -8732,8 +8732,8 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; DAGISEL64-NEXT: s_wait_alu 0xfffe
; DAGISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1]
; DAGISEL64-NEXT: flat_store_b32 v[40:41], v0
-; DAGISEL64-NEXT: v_readlane_b32 s31, v42, 3
; DAGISEL64-NEXT: v_readlane_b32 s30, v42, 2
+; DAGISEL64-NEXT: v_readlane_b32 s31, v42, 3
; DAGISEL64-NEXT: v_readlane_b32 s5, v42, 1
; DAGISEL64-NEXT: v_readlane_b32 s4, v42, 0
; DAGISEL64-NEXT: v_readlane_b32 s0, v42, 4
@@ -9076,8 +9076,8 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; GISEL64-NEXT: s_wait_alu 0xfffe
; GISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GISEL64-NEXT: flat_store_b32 v[40:41], v0
-; GISEL64-NEXT: v_readlane_b32 s31, v42, 3
; GISEL64-NEXT: v_readlane_b32 s30, v42, 2
+; GISEL64-NEXT: v_readlane_b32 s31, v42, 3
; GISEL64-NEXT: v_readlane_b32 s5, v42, 1
; GISEL64-NEXT: v_readlane_b32 s4, v42, 0
; GISEL64-NEXT: v_readlane_b32 s0, v42, 4
@@ -10197,8 +10197,8 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; GFX1250-DAGISEL-NEXT: v_writelane_b32 v42, s31, 2
; GFX1250-DAGISEL-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
; GFX1250-DAGISEL-NEXT: flat_store_b32 v[40:41], v0
-; GFX1250-DAGISEL-NEXT: v_readlane_b32 s31, v42, 2
; GFX1250-DAGISEL-NEXT: v_readlane_b32 s30, v42, 1
+; GFX1250-DAGISEL-NEXT: v_readlane_b32 s31, v42, 2
; GFX1250-DAGISEL-NEXT: v_readlane_b32 s4, v42, 0
; GFX1250-DAGISEL-NEXT: v_readlane_b32 s0, v42, 3
; GFX1250-DAGISEL-NEXT: s_clause 0x2
diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll b/llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
index 06c451869e841..3fe54cd045c0f 100644
--- a/llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
+++ b/llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
@@ -41,12 +41,12 @@ define void @vector_reg_liverange_split() #0 {
; GFX90A-NEXT: s_or_saveexec_b64 s[28:29], -1
; GFX90A-NEXT: v_accvgpr_read_b32 v39, a32
; GFX90A-NEXT: s_mov_b64 exec, s[28:29]
+; GFX90A-NEXT: v_readlane_b32 s30, v40, 0
; GFX90A-NEXT: v_readlane_b32 s20, v39, 0
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; use s20
; GFX90A-NEXT: ;;#ASMEND
; GFX90A-NEXT: v_readlane_b32 s31, v40, 1
-; GFX90A-NEXT: v_readlane_b32 s30, v40, 0
; GFX90A-NEXT: s_mov_b32 s32, s33
; GFX90A-NEXT: v_readlane_b32 s4, v40, 4
; GFX90A-NEXT: v_readlane_b32 s28, v40, 2
diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll b/llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
index 9e9fe1809c780..b5c0023bd5c2a 100644
--- a/llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
+++ b/llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
@@ -49,10 +49,10 @@ define void @test() #0 {
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_readlane_b32 s4, v39, 0
; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: v_readlane_b32 s30, v40, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_readlane_b32 s31, v40, 1
-; GCN-NEXT: v_readlane_b32 s30, v40, 0
; GCN-NEXT: s_mov_b32 s32, s33
; GCN-NEXT: v_readlane_b32 s4, v40, 4
; GCN-NEXT: v_readlane_b32 s28, v40, 2
@@ -111,8 +111,8 @@ define void @test() #0 {
; GCN-O0-NEXT: v_mov_b32_e32 v2, s4
; GCN-O0-NEXT: global_store_dword v[0:1], v2, off
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s31, v40, 1
; GCN-O0-NEXT: v_readlane_b32 s30, v40, 0
+; GCN-O0-NEXT: v_readlane_b32 s31, v40, 1
; GCN-O0-NEXT: s_mov_b32 s32, s33
; GCN-O0-NEXT: v_readlane_b32 s4, v40, 4
; GCN-O0-NEXT: v_readlane_b32 s28, v40, 2
diff --git a/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll b/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
index 74e9ab718c3d2..f28ceb4e0d8b7 100644
--- a/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
+++ b/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
@@ -387,8 +387,8 @@ define amdgpu_gfx void @strict_wwm_call(ptr addrspace(8) inreg %tmp14, i32 inreg
; GFX9-O0-NEXT: s_mov_b64 exec, s[40:41]
; GFX9-O0-NEXT: v_mov_b32_e32 v0, v1
; GFX9-O0-NEXT: buffer_store_dword v0, off, s[36:39], s34 offset:4
-; GFX9-O0-NEXT: v_readlane_b32 s31, v3, 1
; GFX9-O0-NEXT: v_readlane_b32 s30, v3, 0
+; GFX9-O0-NEXT: v_readlane_b32 s31, v3, 1
; GFX9-O0-NEXT: s_mov_b32 s32, s33
; GFX9-O0-NEXT: s_xor_saveexec_b64 s[34:35], -1
; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -424,9 +424,9 @@ define amdgpu_gfx void @strict_wwm_call(ptr addrspace(8) inreg %tmp14, i32 inreg
; GFX9-O3-NEXT: v_add_u32_e32 v1, v1, v2
; GFX9-O3-NEXT: s_mov_b64 exec, s[34:35]
; GFX9-O3-NEXT: v_mov_b32_e32 v0, v1
+; GFX9-O3-NEXT: v_readlane_b32 s30, v3, 0
; GFX9-O3-NEXT: buffer_store_dword v0, off, s[4:7], 0 offset:4
; GFX9-O3-NEXT: v_readlane_b32 s31, v3, 1
-; GFX9-O3-NEXT: v_readlane_b32 s30, v3, 0
; GFX9-O3-NEXT: s_mov_b32 s32, s33
; GFX9-O3-NEXT: s_xor_saveexec_b64 s[34:35], -1
; GFX9-O3-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -624,8 +624,8 @@ define amdgpu_gfx void @strict_wwm_call_i64(ptr addrspace(8) inreg %tmp14, i64 i
; GFX9-O0-NEXT: v_mov_b32_e32 v1, v3
; GFX9-O0-NEXT: s_mov_b32 s34, 0
; GFX9-O0-NEXT: buffer_store_dwordx2 v[0:1], off, s[36:39], s34 offset:4
-; GFX9-O0-NEXT: v_readlane_b32 s31, v10, 1
; GFX9-O0-NEXT: v_readlane_b32 s30, v10, 0
+; GFX9-O0-NEXT: v_readlane_b32 s31, v10, 1
; GFX9-O0-NEXT: s_mov_b32 s32, s33
; GFX9-O0-NEXT: s_xor_saveexec_b64 s[34:35], -1
; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -685,9 +685,9 @@ define amdgpu_gfx void @strict_wwm_call_i64(ptr addrspace(8) inreg %tmp14, i64 i
; GFX9-O3-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-O3-NEXT: v_mov_b32_e32 v0, v2
; GFX9-O3-NEXT: v_mov_b32_e32 v1, v3
+; GFX9-O3-NEXT: v_readlane_b32 s30, v8, 0
; GFX9-O3-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 offset:4
; GFX9-O3-NEXT: v_readlane_b32 s31, v8, 1
-; GFX9-O3-NEXT: v_readlane_b32 s30, v8, 0
; GFX9-O3-NEXT: s_mov_b32 s32, s33
; GFX9-O3-NEXT: s_xor_saveexec_b64 s[34:35], -1
; GFX9-O3-NEXT: buffer_load_dword v6, off, s[0:3], s33 ; 4-byte Folded Reload
>From 9624e4ddd2a526f9e6b21cf62862128b1a804acb Mon Sep 17 00:00:00 2001
From: Emma Pilkington <Emma.Pilkington at amd.com>
Date: Wed, 25 Jun 2025 11:06:31 -0400
Subject: [PATCH 2/3] [AMDGPU] Implement CFI for CSR spills
Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.
Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.
Co-authored-by: Scott Linder <scott.linder at amd.com>
Co-authored-by: Venkata Ramanaiah Nalamothu <VenkataRamanaiah.Nalamothu at amd.com>
---
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 99 +-
llvm/lib/Target/AMDGPU/SIFrameLowering.h | 22 +
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 137 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 19 +-
llvm/lib/Target/AMDGPU/SIInstructions.td | 18 +
llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 70 +-
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 223 +-
llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 15 +-
.../CodeGen/AMDGPU/GlobalISel/assert-align.ll | 4 +-
.../GlobalISel/call-outgoing-stack-args.ll | 26 +-
.../CodeGen/AMDGPU/GlobalISel/localizer.ll | 8 +-
.../test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll | 8 +-
.../CodeGen/AMDGPU/a-v-global-atomicrmw.ll | 8 +-
.../abi-attribute-hints-undefined-behavior.ll | 4 +-
.../AMDGPU/accvgpr-spill-scc-clobber.mir | 2688 +++++++++++
.../AMDGPU/agpr-copy-no-free-registers.ll | 7 +-
.../CodeGen/AMDGPU/amdgcn-call-whole-wave.ll | 24 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 4038 +++++++++++++----
.../CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll | 10 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll | 12 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll | 496 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll | 228 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll | 642 ++-
.../CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll | 706 ++-
.../CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll | 840 +++-
.../CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll | 1076 ++++-
.../CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll | 1340 ++++--
.../CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll | 1554 +++++--
.../AMDGPU/amdgpu-cs-chain-preserve-cc.ll | 2 +
.../amdgpu-simplify-libcall-pow-codegen.ll | 98 +-
...tor-flatscratchinit-undefined-behavior2.ll | 26 +-
.../AMDGPU/av_spill_cross_bb_usage.mir | 12 +
llvm/test/CodeGen/AMDGPU/bf16.ll | 320 +-
.../test/CodeGen/AMDGPU/branch-relax-spill.ll | 4 +-
llvm/test/CodeGen/AMDGPU/call-args-inreg.ll | 240 +-
.../CodeGen/AMDGPU/call-argument-types.ll | 128 +-
.../AMDGPU/call-preserved-registers.ll | 28 +-
.../test/CodeGen/AMDGPU/callee-frame-setup.ll | 104 +-
.../callee-special-input-vgprs-packed.ll | 46 +-
.../AMDGPU/callee-special-input-vgprs.ll | 44 +-
.../AMDGPU/cross-block-use-is-not-abi-copy.ll | 16 +-
llvm/test/CodeGen/AMDGPU/debug-frame.ll | 498 +-
.../AMDGPU/dwarf-multi-register-use-crash.ll | 26 +-
.../dynamic-vgpr-reserve-stack-for-cwsr.ll | 14 +-
.../eliminate-frame-index-s-mov-b32.mir | 96 +
.../fix-frame-reg-in-custom-csr-spills.ll | 8 +-
llvm/test/CodeGen/AMDGPU/frame-index.mir | 96 +
...frame-setup-without-sgpr-to-vgpr-spills.ll | 4 +-
.../CodeGen/AMDGPU/function-args-inreg.ll | 30 +-
.../CodeGen/AMDGPU/gfx-call-non-gfx-func.ll | 8 +-
.../AMDGPU/gfx-callable-argument-types.ll | 3687 ++++++++-------
.../gfx-callable-preserved-registers.ll | 181 +-
.../AMDGPU/gfx-callable-return-types.ll | 190 +-
.../identical-subrange-spill-infloop.ll | 2 +-
.../CodeGen/AMDGPU/insert-delay-alu-bug.ll | 5 +-
.../CodeGen/AMDGPU/insert-waitcnts-crash.ll | 7 +-
.../AMDGPU/llvm.amdgcn.readfirstlane.ll | 32 +-
llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll | 12 +-
llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll | 12 +-
.../materialize-frame-index-sgpr.gfx10.ll | 100 +-
.../AMDGPU/materialize-frame-index-sgpr.ll | 169 +-
llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll | 28 +-
.../CodeGen/AMDGPU/memintrinsic-unroll.ll | 6 +-
llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll | 28 +-
.../CodeGen/AMDGPU/mul24-pass-ordering.ll | 12 +-
llvm/test/CodeGen/AMDGPU/nested-calls.ll | 12 +-
.../AMDGPU/no-source-locations-in-prologue.ll | 1 +
.../AMDGPU/pei-amdgpu-cs-chain-preserve.mir | 1 +
.../AMDGPU/pei-vgpr-block-spill-csr.mir | 572 ++-
.../AMDGPU/preserve-wwm-copy-dst-reg.ll | 14 +-
llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll | 11 +-
.../AMDGPU/sgpr-spill-overlap-wwm-reserve.mir | 67 +
.../AMDGPU/shufflevector.v2i64.v8i64.ll | 325 +-
.../si-lower-sgpr-spills-vgpr-lanes-usage.mir | 3 +
.../CodeGen/AMDGPU/si-lower-sgpr-spills.mir | 5 +
llvm/test/CodeGen/AMDGPU/sibling-call.ll | 34 +-
.../spill-partial-csr-sgpr-live-ins.mir | 5 +
.../AMDGPU/spill-sgpr-csr-live-ins.mir | 1 +
.../AMDGPU/spill-sgpr-to-virtual-vgpr.mir | 16 +
llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll | 6 +-
.../spill_more_than_wavesize_csr_sgprs.ll | 2 +-
llvm/test/CodeGen/AMDGPU/stack-realign.ll | 18 +-
.../CodeGen/AMDGPU/stacksave_stackrestore.ll | 12 +-
.../AMDGPU/strictfp_f16_abi_promote.ll | 40 +-
.../CodeGen/AMDGPU/swdev504645-global-fold.ll | 8 +-
.../AMDGPU/tuple-allocation-failure.ll | 6 +-
...unfold-masked-merge-scalar-variablemask.ll | 30 +-
.../unspill-vgpr-after-rewrite-vgpr-mfma.ll | 18 +-
.../CodeGen/AMDGPU/vgpr-tuple-allocation.ll | 79 +-
llvm/test/CodeGen/AMDGPU/wave32.ll | 12 +-
.../AMDGPU/whole-wave-register-copy.ll | 2 +-
.../AMDGPU/whole-wave-register-spill.ll | 2 +-
92 files changed, 16066 insertions(+), 5877 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index 414f33a2ebb09..6b0af497dfa98 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -2234,17 +2234,49 @@ bool SIFrameLowering::allocateScavengingFrameIndexesNearIncomingSP(
return true;
}
+static bool isLiveIntoMBB(MCRegister Reg, MachineBasicBlock &MBB,
+ const TargetRegisterInfo *TRI) {
+ for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R) {
+ if (MBB.isLiveIn(*R)) {
+ return true;
+ }
+ }
+ return false;
+}
+
bool SIFrameLowering::spillCalleeSavedRegisters(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
MachineFunction *MF = MBB.getParent();
const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
- if (!ST.useVGPRBlockOpsForCSR())
- return false;
+ const SIInstrInfo *TII = ST.getInstrInfo();
+ const SIRegisterInfo *SITRI = static_cast<const SIRegisterInfo *>(TRI);
+
+ if (!ST.useVGPRBlockOpsForCSR()) {
+ for (const CalleeSavedInfo &CS : CSI) {
+ // Insert the spill to the stack frame.
+ unsigned Reg = CS.getReg();
+
+ if (CS.isSpilledToReg()) {
+ BuildMI(MBB, MI, DebugLoc(), TII->get(TargetOpcode::COPY),
+ CS.getDstReg())
+ .addReg(Reg, getKillRegState(true));
+ } else {
+ const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(
+ Reg, Reg == SITRI->getReturnAddressReg(*MF) ? MVT::i64 : MVT::i32);
+ // If this value was already livein, we probably have a direct use of
+ // the incoming register value, so don't kill at the spill point. This
+ // happens since we pass some special inputs (workgroup IDs) in the
+ // callee saved range.
+ const bool IsLiveIn = isLiveIntoMBB(Reg, MBB, TRI);
+ TII->storeRegToStackSlotCFI(MBB, MI, Reg, !IsLiveIn, CS.getFrameIdx(),
+ RC, TRI);
+ }
+ }
+ return true;
+ }
MachineFrameInfo &FrameInfo = MF->getFrameInfo();
- SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
- const SIInstrInfo *TII = ST.getInstrInfo();
SIMachineFunctionInfo *FuncInfo = MF->getInfo<SIMachineFunctionInfo>();
const TargetRegisterClass *BlockRegClass =
@@ -2268,10 +2300,10 @@ bool SIFrameLowering::spillCalleeSavedRegisters(
FrameInfo.getObjectAlign(FrameIndex));
BuildMI(MBB, MI, MI->getDebugLoc(),
- TII->get(AMDGPU::SI_BLOCK_SPILL_V1024_SAVE))
+ TII->get(AMDGPU::SI_BLOCK_SPILL_V1024_CFI_SAVE))
.addReg(Reg, getKillRegState(false))
.addFrameIndex(FrameIndex)
- .addReg(MFI->getStackPtrOffsetReg())
+ .addReg(FuncInfo->getStackPtrOffsetReg())
.addImm(0)
.addImm(Mask)
.addMemOperand(MMO);
@@ -2459,6 +2491,22 @@ MachineInstr *SIFrameLowering::buildCFI(MachineBasicBlock &MBB,
.setMIFlag(flag);
}
+MachineInstr *SIFrameLowering::buildCFIForVRegToVRegSpill(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, const Register Reg, const Register RegCopy) const {
+ MachineFunction &MF = *MBB.getParent();
+ const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo();
+ const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+
+ unsigned MaskReg = MCRI.getDwarfRegNum(
+ ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC, false);
+ auto CFIInst = MCCFIInstruction::createLLVMVectorRegisterMask(
+ nullptr, MCRI.getDwarfRegNum(Reg, false),
+ MCRI.getDwarfRegNum(RegCopy, false), VGPRLaneBitSize, MaskReg,
+ ST.getWavefrontSize());
+ return buildCFI(MBB, MBBI, DL, std::move(CFIInst));
+}
+
MachineInstr *SIFrameLowering::buildCFIForSGPRToVGPRSpill(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, const Register SGPR, const Register VGPR,
@@ -2507,6 +2555,34 @@ MachineInstr *SIFrameLowering::buildCFIForSGPRToVGPRSpill(
return buildCFI(MBB, MBBI, DL, std::move(CFIInst));
}
+MachineInstr *SIFrameLowering::buildCFIForSGPRToVMEMSpill(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, unsigned SGPR, int64_t Offset) const {
+ MachineFunction &MF = *MBB.getParent();
+ const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo();
+ return buildCFI(MBB, MBBI, DL,
+ llvm::MCCFIInstruction::createOffset(
+ nullptr, MCRI.getDwarfRegNum(SGPR, false), Offset));
+}
+
+MachineInstr *SIFrameLowering::buildCFIForVGPRToVMEMSpill(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, unsigned VGPR, int64_t Offset) const {
+ const MachineFunction &MF = *MBB.getParent();
+ const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo();
+ const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+
+ int DwarfVGPR = MCRI.getDwarfRegNum(VGPR, false);
+ assert(DwarfVGPR != -1);
+
+ unsigned MaskReg = MCRI.getDwarfRegNum(
+ ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC, false);
+ auto CFIInst = MCCFIInstruction::createLLVMVectorOffset(
+ nullptr, DwarfVGPR, VGPRLaneBitSize, MaskReg, ST.getWavefrontSize(),
+ Offset);
+ return buildCFI(MBB, MBBI, DL, std::move(CFIInst));
+}
+
MachineInstr *SIFrameLowering::buildCFIForRegToSGPRPairSpill(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, const Register Reg, const Register SGPRPair) const {
@@ -2527,3 +2603,14 @@ MachineInstr *SIFrameLowering::buildCFIForRegToSGPRPairSpill(
nullptr, DwarfReg, DwarfSGPR0, SGPRBitSize, DwarfSGPR1, SGPRBitSize);
return buildCFI(MBB, MBBI, DL, std::move(CFIInst));
}
+
+MachineInstr *
+SIFrameLowering::buildCFIForSameValue(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, Register Reg) const {
+ const MachineFunction &MF = *MBB.getParent();
+ const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo();
+ int DwarfReg = MCRI.getDwarfRegNum(Reg, /*isEH=*/false);
+ auto CFIInst = MCCFIInstruction::createSameValue(nullptr, DwarfReg);
+ return buildCFI(MBB, MBBI, DL, std::move(CFIInst));
+}
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.h b/llvm/lib/Target/AMDGPU/SIFrameLowering.h
index 20f608f2dfc24..2b716db0b7a22 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.h
@@ -120,6 +120,13 @@ class SIFrameLowering final : public AMDGPUFrameLowering {
const DebugLoc &DL, const MCCFIInstruction &CFIInst,
MachineInstr::MIFlag flag = MachineInstr::FrameSetup) const;
+ /// Create a CFI index describing a spill of the VGPR/AGPR \p Reg to another
+ /// VGPR/AGPR \p RegCopy and build a MachineInstr around it.
+ MachineInstr *buildCFIForVRegToVRegSpill(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL,
+ const Register Reg,
+ const Register RegCopy) const;
/// Create a CFI index describing a spill of an SGPR to a single lane of
/// a VGPR and build a MachineInstr around it.
MachineInstr *buildCFIForSGPRToVGPRSpill(MachineBasicBlock &MBB,
@@ -134,10 +141,25 @@ class SIFrameLowering final : public AMDGPUFrameLowering {
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, Register SGPR,
ArrayRef<SIRegisterInfo::SpilledReg> VGPRSpills) const;
+ /// Create a CFI index describing a spill of a SGPR to VMEM and
+ /// build a MachineInstr around it.
+ MachineInstr *buildCFIForSGPRToVMEMSpill(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, unsigned SGPR,
+ int64_t Offset) const;
+ /// Create a CFI index describing a spill of a VGPR to VMEM and
+ /// build a MachineInstr around it.
+ MachineInstr *buildCFIForVGPRToVMEMSpill(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, unsigned VGPR,
+ int64_t Offset) const;
MachineInstr *buildCFIForRegToSGPRPairSpill(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, Register Reg,
Register SGPRPair) const;
+ MachineInstr *buildCFIForSameValue(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, Register Reg) const;
// Returns true if the function may need to reserve space on the stack for the
// CWSR trap handler.
bool mayReserveScratchForCWSR(const MachineFunction &MF) const;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 45f591927b86e..b40e55e2654ac 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1530,22 +1530,26 @@ SIInstrInfo::getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize,
return get(getIndirectVGPRWriteMovRelPseudoOpc(VecSize));
}
-static unsigned getSGPRSpillSaveOpcode(unsigned Size) {
+static unsigned getSGPRSpillSaveOpcode(unsigned Size, bool NeedsCFI) {
switch (Size) {
case 4:
- return AMDGPU::SI_SPILL_S32_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_S32_CFI_SAVE : AMDGPU::SI_SPILL_S32_SAVE;
case 8:
- return AMDGPU::SI_SPILL_S64_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_S64_CFI_SAVE : AMDGPU::SI_SPILL_S64_SAVE;
case 12:
- return AMDGPU::SI_SPILL_S96_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_S96_CFI_SAVE : AMDGPU::SI_SPILL_S96_SAVE;
case 16:
- return AMDGPU::SI_SPILL_S128_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_S128_CFI_SAVE
+ : AMDGPU::SI_SPILL_S128_SAVE;
case 20:
- return AMDGPU::SI_SPILL_S160_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_S160_CFI_SAVE
+ : AMDGPU::SI_SPILL_S160_SAVE;
case 24:
- return AMDGPU::SI_SPILL_S192_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_S192_CFI_SAVE
+ : AMDGPU::SI_SPILL_S192_SAVE;
case 28:
- return AMDGPU::SI_SPILL_S224_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_S224_CFI_SAVE
+ : AMDGPU::SI_SPILL_S224_SAVE;
case 32:
return AMDGPU::SI_SPILL_S256_SAVE;
case 36:
@@ -1557,69 +1561,90 @@ static unsigned getSGPRSpillSaveOpcode(unsigned Size) {
case 48:
return AMDGPU::SI_SPILL_S384_SAVE;
case 64:
- return AMDGPU::SI_SPILL_S512_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_S512_CFI_SAVE
+ : AMDGPU::SI_SPILL_S512_SAVE;
case 128:
- return AMDGPU::SI_SPILL_S1024_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_S1024_CFI_SAVE
+ : AMDGPU::SI_SPILL_S1024_SAVE;
default:
llvm_unreachable("unknown register size");
}
}
-static unsigned getVGPRSpillSaveOpcode(unsigned Size) {
+static unsigned getVGPRSpillSaveOpcode(unsigned Size, bool NeedsCFI) {
switch (Size) {
case 2:
return AMDGPU::SI_SPILL_V16_SAVE;
case 4:
- return AMDGPU::SI_SPILL_V32_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_V32_CFI_SAVE : AMDGPU::SI_SPILL_V32_SAVE;
case 8:
- return AMDGPU::SI_SPILL_V64_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_V64_CFI_SAVE : AMDGPU::SI_SPILL_V64_SAVE;
case 12:
- return AMDGPU::SI_SPILL_V96_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_V96_CFI_SAVE : AMDGPU::SI_SPILL_V96_SAVE;
case 16:
- return AMDGPU::SI_SPILL_V128_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_V128_CFI_SAVE
+ : AMDGPU::SI_SPILL_V128_SAVE;
case 20:
- return AMDGPU::SI_SPILL_V160_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_V160_CFI_SAVE
+ : AMDGPU::SI_SPILL_V160_SAVE;
case 24:
- return AMDGPU::SI_SPILL_V192_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_V192_CFI_SAVE
+ : AMDGPU::SI_SPILL_V192_SAVE;
case 28:
- return AMDGPU::SI_SPILL_V224_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_V224_CFI_SAVE
+ : AMDGPU::SI_SPILL_V224_SAVE;
case 32:
- return AMDGPU::SI_SPILL_V256_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_V256_CFI_SAVE
+ : AMDGPU::SI_SPILL_V256_SAVE;
case 36:
- return AMDGPU::SI_SPILL_V288_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_V288_CFI_SAVE
+ : AMDGPU::SI_SPILL_V288_SAVE;
case 40:
- return AMDGPU::SI_SPILL_V320_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_V320_CFI_SAVE
+ : AMDGPU::SI_SPILL_V320_SAVE;
case 44:
- return AMDGPU::SI_SPILL_V352_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_V352_CFI_SAVE
+ : AMDGPU::SI_SPILL_V352_SAVE;
case 48:
- return AMDGPU::SI_SPILL_V384_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_V384_CFI_SAVE
+ : AMDGPU::SI_SPILL_V384_SAVE;
case 64:
- return AMDGPU::SI_SPILL_V512_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_V512_CFI_SAVE
+ : AMDGPU::SI_SPILL_V512_SAVE;
case 128:
- return AMDGPU::SI_SPILL_V1024_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_V1024_CFI_SAVE
+ : AMDGPU::SI_SPILL_V1024_SAVE;
default:
llvm_unreachable("unknown register size");
}
}
-static unsigned getAVSpillSaveOpcode(unsigned Size) {
+static unsigned getAVSpillSaveOpcode(unsigned Size, bool NeedsCFI) {
switch (Size) {
case 4:
- return AMDGPU::SI_SPILL_AV32_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_AV32_CFI_SAVE
+ : AMDGPU::SI_SPILL_AV32_SAVE;
case 8:
- return AMDGPU::SI_SPILL_AV64_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_AV64_CFI_SAVE
+ : AMDGPU::SI_SPILL_AV64_SAVE;
case 12:
- return AMDGPU::SI_SPILL_AV96_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_AV96_CFI_SAVE
+ : AMDGPU::SI_SPILL_AV96_SAVE;
case 16:
- return AMDGPU::SI_SPILL_AV128_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_AV128_CFI_SAVE
+ : AMDGPU::SI_SPILL_AV128_SAVE;
case 20:
- return AMDGPU::SI_SPILL_AV160_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_AV160_CFI_SAVE
+ : AMDGPU::SI_SPILL_AV160_SAVE;
case 24:
- return AMDGPU::SI_SPILL_AV192_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_AV192_CFI_SAVE
+ : AMDGPU::SI_SPILL_AV192_SAVE;
case 28:
- return AMDGPU::SI_SPILL_AV224_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_AV224_CFI_SAVE
+ : AMDGPU::SI_SPILL_AV224_SAVE;
case 32:
- return AMDGPU::SI_SPILL_AV256_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_AV256_CFI_SAVE
+ : AMDGPU::SI_SPILL_AV256_SAVE;
case 36:
return AMDGPU::SI_SPILL_AV288_SAVE;
case 40:
@@ -1629,9 +1654,11 @@ static unsigned getAVSpillSaveOpcode(unsigned Size) {
case 48:
return AMDGPU::SI_SPILL_AV384_SAVE;
case 64:
- return AMDGPU::SI_SPILL_AV512_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_AV512_CFI_SAVE
+ : AMDGPU::SI_SPILL_AV512_SAVE;
case 128:
- return AMDGPU::SI_SPILL_AV1024_SAVE;
+ return NeedsCFI ? AMDGPU::SI_SPILL_AV1024_CFI_SAVE
+ : AMDGPU::SI_SPILL_AV1024_SAVE;
default:
llvm_unreachable("unknown register size");
}
@@ -1651,7 +1678,7 @@ static unsigned getWWMRegSpillSaveOpcode(unsigned Size,
unsigned SIInstrInfo::getVectorRegSpillSaveOpcode(
Register Reg, const TargetRegisterClass *RC, unsigned Size,
- const SIMachineFunctionInfo &MFI) const {
+ const SIMachineFunctionInfo &MFI, bool NeedsCFI) const {
bool IsVectorSuperClass = RI.isVectorSuperClass(RC);
// Choose the right opcode if spilling a WWM register.
@@ -1660,16 +1687,16 @@ unsigned SIInstrInfo::getVectorRegSpillSaveOpcode(
// TODO: Check if AGPRs are available
if (ST.hasMAIInsts())
- return getAVSpillSaveOpcode(Size);
+ return getAVSpillSaveOpcode(Size, NeedsCFI);
- return getVGPRSpillSaveOpcode(Size);
+ return getVGPRSpillSaveOpcode(Size, NeedsCFI);
}
-void SIInstrInfo::storeRegToStackSlot(
+void SIInstrInfo::storeRegToStackSlotImpl(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, Register VReg,
- MachineInstr::MIFlag Flags) const {
+ const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags,
+ bool NeedsCFI) const {
MachineFunction *MF = MBB.getParent();
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
MachineFrameInfo &FrameInfo = MF->getFrameInfo();
@@ -1691,7 +1718,8 @@ void SIInstrInfo::storeRegToStackSlot(
// We are only allowed to create one new instruction when spilling
// registers, so we need to use pseudo instruction for spilling SGPRs.
- const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize));
+ const MCInstrDesc &OpDesc =
+ get(getSGPRSpillSaveOpcode(SpillSize, NeedsCFI));
// The SGPR spill/restore instructions only work on number sgprs, so we need
// to make sure we are using the correct register class.
@@ -1710,8 +1738,8 @@ void SIInstrInfo::storeRegToStackSlot(
return;
}
- unsigned Opcode =
- getVectorRegSpillSaveOpcode(VReg ? VReg : SrcReg, RC, SpillSize, *MFI);
+ unsigned Opcode = getVectorRegSpillSaveOpcode(VReg ? VReg : SrcReg, RC,
+ SpillSize, *MFI, NeedsCFI);
MFI->setHasSpilledVGPRs();
BuildMI(MBB, MI, DL, get(Opcode))
@@ -1722,6 +1750,25 @@ void SIInstrInfo::storeRegToStackSlot(
.addMemOperand(MMO);
}
+void SIInstrInfo::storeRegToStackSlot(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags) const {
+ storeRegToStackSlotImpl(MBB, MI, SrcReg, isKill, FrameIndex, RC, TRI, VReg,
+ Flags, false);
+}
+
+void SIInstrInfo::storeRegToStackSlotCFI(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ Register SrcReg, bool isKill,
+ int FrameIndex,
+ const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI) const {
+ storeRegToStackSlotImpl(MBB, MI, SrcReg, isKill, FrameIndex, RC, TRI,
+ Register(), MachineInstr::NoFlags, true);
+}
+
static unsigned getSGPRSpillRestoreOpcode(unsigned Size) {
switch (Size) {
case 4:
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index dc23a21f959ce..42e5c69773176 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -293,13 +293,29 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
MachineBasicBlock::iterator I, const DebugLoc &DL,
Register SrcReg, int Value) const;
+private:
+ void storeRegToStackSlotImpl(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI, Register SrcReg,
+ bool isKill, int FrameIndex,
+ const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI, Register VReg,
+ MachineInstr::MIFlag Flags, bool NeedsCFI) const;
+
+public:
+ void storeRegToStackSlotCFI(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI, Register SrcReg,
+ bool isKill, int FrameIndex,
+ const TargetRegisterClass *RC,
+ const TargetRegisterInfo *TRI) const;
+
bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg,
int64_t &ImmVal) const override;
unsigned getVectorRegSpillSaveOpcode(Register Reg,
const TargetRegisterClass *RC,
unsigned Size,
- const SIMachineFunctionInfo &MFI) const;
+ const SIMachineFunctionInfo &MFI,
+ bool NeedsCFI) const;
unsigned
getVectorRegSpillRestoreOpcode(Register Reg, const TargetRegisterClass *RC,
unsigned Size,
@@ -703,6 +719,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
static bool isBlockLoadStore(uint16_t Opcode) {
switch (Opcode) {
case AMDGPU::SI_BLOCK_SPILL_V1024_SAVE:
+ case AMDGPU::SI_BLOCK_SPILL_V1024_CFI_SAVE:
case AMDGPU::SI_BLOCK_SPILL_V1024_RESTORE:
case AMDGPU::SCRATCH_STORE_BLOCK_SADDR:
case AMDGPU::SCRATCH_LOAD_BLOCK_SADDR:
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 6f1feb1dc2996..3498f18467466 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -1086,6 +1086,11 @@ multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
let mayLoad = 0;
}
+ def _CFI_SAVE : PseudoInstSI<(outs), (ins sgpr_class:$data, i32imm:$addr)> {
+ let mayStore = 1;
+ let mayLoad = 0;
+ }
+
def _RESTORE : PseudoInstSI <
(outs sgpr_class:$data),
(ins i32imm:$addr)> {
@@ -1159,6 +1164,19 @@ multiclass SI_SPILL_VGPR <SIRegisterClassLike vgpr_class,
let Size = !if(!le(MaxSize, 256), MaxSize, 252);
}
+ def _CFI_SAVE
+ : VPseudoInstSI<(outs),
+ !con((ins vgpr_class:$vdata, i32imm:$vaddr,
+ SReg_32:$soffset, i32imm:$offset),
+ !if(HasMask, (ins SReg_32:$mask), (ins)))> {
+ let mayStore = 1;
+ let mayLoad = 0;
+ // (2 * 4) + (8 * num_subregs) bytes maximum
+ int MaxSize = !add(!shl(!srl(vgpr_class.Size, 5), !add(UsesTmp, 3)), 8);
+ // Size field is unsigned char and cannot fit more.
+ let Size = !if(!le(MaxSize, 256), MaxSize, 252);
+ }
+
def _RESTORE : VPseudoInstSI <
(outs vgpr_class:$vdata),
!con(
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index 057a5e2df8bf7..62386da94d854 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -100,63 +100,25 @@ INITIALIZE_PASS_END(SILowerSGPRSpillsLegacy, DEBUG_TYPE,
char &llvm::SILowerSGPRSpillsLegacyID = SILowerSGPRSpillsLegacy::ID;
-static bool isLiveIntoMBB(MCRegister Reg, MachineBasicBlock &MBB,
- const TargetRegisterInfo *TRI) {
- for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R) {
- if (MBB.isLiveIn(*R)) {
- return true;
- }
- }
- return false;
-}
-
/// Insert spill code for the callee-saved registers used in the function.
-static void insertCSRSaves(MachineBasicBlock &SaveBlock,
+static void insertCSRSaves(const GCNSubtarget &ST, MachineBasicBlock &SaveBlock,
ArrayRef<CalleeSavedInfo> CSI, SlotIndexes *Indexes,
LiveIntervals *LIS) {
- MachineFunction &MF = *SaveBlock.getParent();
- const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
- const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
- const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
- const SIRegisterInfo *RI = ST.getRegisterInfo();
-
+ const TargetFrameLowering *TFI = ST.getFrameLowering();
+ const TargetRegisterInfo *TRI = ST.getRegisterInfo();
MachineBasicBlock::iterator I = SaveBlock.begin();
- if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) {
- for (const CalleeSavedInfo &CS : CSI) {
- // Insert the spill to the stack frame.
- MCRegister Reg = CS.getReg();
-
- MachineInstrSpan MIS(I, &SaveBlock);
- const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(
- Reg, Reg == RI->getReturnAddressReg(MF) ? MVT::i64 : MVT::i32);
-
- // If this value was already livein, we probably have a direct use of the
- // incoming register value, so don't kill at the spill point. This happens
- // since we pass some special inputs (workgroup IDs) in the callee saved
- // range.
- const bool IsLiveIn = isLiveIntoMBB(Reg, SaveBlock, TRI);
- TII.storeRegToStackSlot(SaveBlock, I, Reg, !IsLiveIn, CS.getFrameIdx(),
- RC, TRI, Register());
-
- if (Indexes) {
- assert(std::distance(MIS.begin(), I) == 1);
- MachineInstr &Inst = *std::prev(I);
- Indexes->insertMachineInstrInMaps(Inst);
- }
-
- if (LIS)
- LIS->removeAllRegUnitsForPhysReg(Reg);
- }
- } else {
- // TFI doesn't update Indexes and LIS, so we have to do it separately.
- if (Indexes)
- Indexes->repairIndexesInRange(&SaveBlock, SaveBlock.begin(), I);
-
- if (LIS)
- for (const CalleeSavedInfo &CS : CSI)
- LIS->removeAllRegUnitsForPhysReg(CS.getReg());
- }
+ MachineInstrSpan MIS(I, &SaveBlock);
+ bool Success = TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI);
+ assert(Success && "spillCalleeSavedRegisters should always succeed");
+ (void)Success;
+
+ // TFI doesn't update Indexes and LIS, so we have to do it separately.
+ if (Indexes)
+ Indexes->repairIndexesInRange(&SaveBlock, SaveBlock.begin(), I);
+
+ if (LIS)
+ for (const CalleeSavedInfo &CS : CSI)
+ LIS->removeAllRegUnitsForPhysReg(CS.getReg());
}
/// Insert restore code for the callee-saved registers used in the function.
@@ -305,7 +267,7 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs(
if (!CSI.empty()) {
for (MachineBasicBlock *SaveBlock : SaveBlocks)
- insertCSRSaves(*SaveBlock, CSI, Indexes, LIS);
+ insertCSRSaves(ST, *SaveBlock, CSI, Indexes, LIS);
// Add live ins to save blocks.
assert(SaveBlocks.size() == 1 && "shrink wrapping not fully implemented");
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index a6c1af24e13e9..89fc72595bf66 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1128,6 +1128,7 @@ static unsigned getNumSubRegsForSpillOp(const MachineInstr &MI,
unsigned Op = MI.getOpcode();
switch (Op) {
case AMDGPU::SI_BLOCK_SPILL_V1024_SAVE:
+ case AMDGPU::SI_BLOCK_SPILL_V1024_CFI_SAVE:
case AMDGPU::SI_BLOCK_SPILL_V1024_RESTORE:
// FIXME: This assumes the mask is statically known and not computed at
// runtime. However, some ABIs may want to compute the mask dynamically and
@@ -1135,21 +1136,29 @@ static unsigned getNumSubRegsForSpillOp(const MachineInstr &MI,
return llvm::popcount(
(uint64_t)TII->getNamedOperand(MI, AMDGPU::OpName::mask)->getImm());
case AMDGPU::SI_SPILL_S1024_SAVE:
+ case AMDGPU::SI_SPILL_S1024_CFI_SAVE:
case AMDGPU::SI_SPILL_S1024_RESTORE:
case AMDGPU::SI_SPILL_V1024_SAVE:
+ case AMDGPU::SI_SPILL_V1024_CFI_SAVE:
case AMDGPU::SI_SPILL_V1024_RESTORE:
case AMDGPU::SI_SPILL_A1024_SAVE:
+ case AMDGPU::SI_SPILL_A1024_CFI_SAVE:
case AMDGPU::SI_SPILL_A1024_RESTORE:
case AMDGPU::SI_SPILL_AV1024_SAVE:
+ case AMDGPU::SI_SPILL_AV1024_CFI_SAVE:
case AMDGPU::SI_SPILL_AV1024_RESTORE:
return 32;
case AMDGPU::SI_SPILL_S512_SAVE:
+ case AMDGPU::SI_SPILL_S512_CFI_SAVE:
case AMDGPU::SI_SPILL_S512_RESTORE:
case AMDGPU::SI_SPILL_V512_SAVE:
+ case AMDGPU::SI_SPILL_V512_CFI_SAVE:
case AMDGPU::SI_SPILL_V512_RESTORE:
case AMDGPU::SI_SPILL_A512_SAVE:
+ case AMDGPU::SI_SPILL_A512_CFI_SAVE:
case AMDGPU::SI_SPILL_A512_RESTORE:
case AMDGPU::SI_SPILL_AV512_SAVE:
+ case AMDGPU::SI_SPILL_AV512_CFI_SAVE:
case AMDGPU::SI_SPILL_AV512_RESTORE:
return 16;
case AMDGPU::SI_SPILL_S384_SAVE:
@@ -1189,75 +1198,107 @@ static unsigned getNumSubRegsForSpillOp(const MachineInstr &MI,
case AMDGPU::SI_SPILL_AV288_RESTORE:
return 9;
case AMDGPU::SI_SPILL_S256_SAVE:
+ case AMDGPU::SI_SPILL_S256_CFI_SAVE:
case AMDGPU::SI_SPILL_S256_RESTORE:
case AMDGPU::SI_SPILL_V256_SAVE:
+ case AMDGPU::SI_SPILL_V256_CFI_SAVE:
case AMDGPU::SI_SPILL_V256_RESTORE:
case AMDGPU::SI_SPILL_A256_SAVE:
+ case AMDGPU::SI_SPILL_A256_CFI_SAVE:
case AMDGPU::SI_SPILL_A256_RESTORE:
case AMDGPU::SI_SPILL_AV256_SAVE:
+ case AMDGPU::SI_SPILL_AV256_CFI_SAVE:
case AMDGPU::SI_SPILL_AV256_RESTORE:
return 8;
case AMDGPU::SI_SPILL_S224_SAVE:
+ case AMDGPU::SI_SPILL_S224_CFI_SAVE:
case AMDGPU::SI_SPILL_S224_RESTORE:
case AMDGPU::SI_SPILL_V224_SAVE:
+ case AMDGPU::SI_SPILL_V224_CFI_SAVE:
case AMDGPU::SI_SPILL_V224_RESTORE:
case AMDGPU::SI_SPILL_A224_SAVE:
+ case AMDGPU::SI_SPILL_A224_CFI_SAVE:
case AMDGPU::SI_SPILL_A224_RESTORE:
case AMDGPU::SI_SPILL_AV224_SAVE:
+ case AMDGPU::SI_SPILL_AV224_CFI_SAVE:
case AMDGPU::SI_SPILL_AV224_RESTORE:
return 7;
case AMDGPU::SI_SPILL_S192_SAVE:
+ case AMDGPU::SI_SPILL_S192_CFI_SAVE:
case AMDGPU::SI_SPILL_S192_RESTORE:
case AMDGPU::SI_SPILL_V192_SAVE:
+ case AMDGPU::SI_SPILL_V192_CFI_SAVE:
case AMDGPU::SI_SPILL_V192_RESTORE:
case AMDGPU::SI_SPILL_A192_SAVE:
+ case AMDGPU::SI_SPILL_A192_CFI_SAVE:
case AMDGPU::SI_SPILL_A192_RESTORE:
case AMDGPU::SI_SPILL_AV192_SAVE:
+ case AMDGPU::SI_SPILL_AV192_CFI_SAVE:
case AMDGPU::SI_SPILL_AV192_RESTORE:
return 6;
case AMDGPU::SI_SPILL_S160_SAVE:
+ case AMDGPU::SI_SPILL_S160_CFI_SAVE:
case AMDGPU::SI_SPILL_S160_RESTORE:
case AMDGPU::SI_SPILL_V160_SAVE:
+ case AMDGPU::SI_SPILL_V160_CFI_SAVE:
case AMDGPU::SI_SPILL_V160_RESTORE:
case AMDGPU::SI_SPILL_A160_SAVE:
+ case AMDGPU::SI_SPILL_A160_CFI_SAVE:
case AMDGPU::SI_SPILL_A160_RESTORE:
case AMDGPU::SI_SPILL_AV160_SAVE:
+ case AMDGPU::SI_SPILL_AV160_CFI_SAVE:
case AMDGPU::SI_SPILL_AV160_RESTORE:
return 5;
case AMDGPU::SI_SPILL_S128_SAVE:
+ case AMDGPU::SI_SPILL_S128_CFI_SAVE:
case AMDGPU::SI_SPILL_S128_RESTORE:
case AMDGPU::SI_SPILL_V128_SAVE:
+ case AMDGPU::SI_SPILL_V128_CFI_SAVE:
case AMDGPU::SI_SPILL_V128_RESTORE:
case AMDGPU::SI_SPILL_A128_SAVE:
+ case AMDGPU::SI_SPILL_A128_CFI_SAVE:
case AMDGPU::SI_SPILL_A128_RESTORE:
case AMDGPU::SI_SPILL_AV128_SAVE:
+ case AMDGPU::SI_SPILL_AV128_CFI_SAVE:
case AMDGPU::SI_SPILL_AV128_RESTORE:
return 4;
case AMDGPU::SI_SPILL_S96_SAVE:
+ case AMDGPU::SI_SPILL_S96_CFI_SAVE:
case AMDGPU::SI_SPILL_S96_RESTORE:
case AMDGPU::SI_SPILL_V96_SAVE:
+ case AMDGPU::SI_SPILL_V96_CFI_SAVE:
case AMDGPU::SI_SPILL_V96_RESTORE:
case AMDGPU::SI_SPILL_A96_SAVE:
+ case AMDGPU::SI_SPILL_A96_CFI_SAVE:
case AMDGPU::SI_SPILL_A96_RESTORE:
case AMDGPU::SI_SPILL_AV96_SAVE:
+ case AMDGPU::SI_SPILL_AV96_CFI_SAVE:
case AMDGPU::SI_SPILL_AV96_RESTORE:
return 3;
case AMDGPU::SI_SPILL_S64_SAVE:
+ case AMDGPU::SI_SPILL_S64_CFI_SAVE:
case AMDGPU::SI_SPILL_S64_RESTORE:
case AMDGPU::SI_SPILL_V64_SAVE:
+ case AMDGPU::SI_SPILL_V64_CFI_SAVE:
case AMDGPU::SI_SPILL_V64_RESTORE:
case AMDGPU::SI_SPILL_A64_SAVE:
+ case AMDGPU::SI_SPILL_A64_CFI_SAVE:
case AMDGPU::SI_SPILL_A64_RESTORE:
case AMDGPU::SI_SPILL_AV64_SAVE:
+ case AMDGPU::SI_SPILL_AV64_CFI_SAVE:
case AMDGPU::SI_SPILL_AV64_RESTORE:
return 2;
case AMDGPU::SI_SPILL_S32_SAVE:
+ case AMDGPU::SI_SPILL_S32_CFI_SAVE:
case AMDGPU::SI_SPILL_S32_RESTORE:
case AMDGPU::SI_SPILL_V32_SAVE:
+ case AMDGPU::SI_SPILL_V32_CFI_SAVE:
case AMDGPU::SI_SPILL_V32_RESTORE:
case AMDGPU::SI_SPILL_A32_SAVE:
+ case AMDGPU::SI_SPILL_A32_CFI_SAVE:
case AMDGPU::SI_SPILL_A32_RESTORE:
case AMDGPU::SI_SPILL_AV32_SAVE:
+ case AMDGPU::SI_SPILL_AV32_CFI_SAVE:
case AMDGPU::SI_SPILL_AV32_RESTORE:
case AMDGPU::SI_SPILL_WWM_V32_SAVE:
case AMDGPU::SI_SPILL_WWM_V32_RESTORE:
@@ -1386,14 +1427,14 @@ static int getOffenMUBUFLoad(unsigned Opc) {
}
}
-static MachineInstrBuilder spillVGPRtoAGPR(const GCNSubtarget &ST,
- MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- int Index, unsigned Lane,
- unsigned ValueReg, bool IsKill) {
+static MachineInstrBuilder
+spillVGPRtoAGPR(const GCNSubtarget &ST, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI, int Index, unsigned Lane,
+ unsigned ValueReg, bool IsKill, bool NeedsCFI) {
MachineFunction *MF = MBB.getParent();
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
const SIInstrInfo *TII = ST.getInstrInfo();
+ const SIFrameLowering *TFL = ST.getFrameLowering();
MCPhysReg Reg = MFI->getVGPRToAGPRSpill(Index, Lane);
@@ -1416,6 +1457,8 @@ static MachineInstrBuilder spillVGPRtoAGPR(const GCNSubtarget &ST,
auto CopyMIB = BuildMI(MBB, MI, DL, TII->get(AMDGPU::COPY), Dst)
.addReg(Src, getKillRegState(IsKill));
CopyMIB->setAsmPrinterFlag(MachineInstr::ReloadReuse);
+ if (NeedsCFI)
+ TFL->buildCFIForVRegToVRegSpill(MBB, MI, DL, Src, Dst);
return CopyMIB;
}
unsigned Opc = (IsStore ^ IsVGPR) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64
@@ -1424,6 +1467,8 @@ static MachineInstrBuilder spillVGPRtoAGPR(const GCNSubtarget &ST,
auto MIB = BuildMI(MBB, MI, DL, TII->get(Opc), Dst)
.addReg(Src, getKillRegState(IsKill));
MIB->setAsmPrinterFlag(MachineInstr::ReloadReuse);
+ if (NeedsCFI)
+ TFL->buildCFIForVRegToVRegSpill(MBB, MI, DL, Src, Dst);
return MIB;
}
@@ -1446,7 +1491,8 @@ static bool buildMUBUFOffsetLoadStore(const GCNSubtarget &ST,
return false;
const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata);
- if (spillVGPRtoAGPR(ST, *MBB, MI, Index, 0, Reg->getReg(), false).getInstr())
+ if (spillVGPRtoAGPR(ST, *MBB, MI, Index, 0, Reg->getReg(), false, false)
+ .getInstr())
return true;
MachineInstrBuilder NewMI =
@@ -1511,12 +1557,13 @@ void SIRegisterInfo::buildSpillLoadStore(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL,
unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill,
MCRegister ScratchOffsetReg, int64_t InstOffset, MachineMemOperand *MMO,
- RegScavenger *RS, LiveRegUnits *LiveUnits) const {
+ RegScavenger *RS, LiveRegUnits *LiveUnits, bool NeedsCFI) const {
assert((!RS || !LiveUnits) && "Only RS or LiveUnits can be set but not both");
MachineFunction *MF = MBB.getParent();
const SIInstrInfo *TII = ST.getInstrInfo();
const MachineFrameInfo &MFI = MF->getFrameInfo();
+ const SIFrameLowering *TFL = ST.getFrameLowering();
const SIMachineFunctionInfo *FuncInfo = MF->getInfo<SIMachineFunctionInfo>();
const MCInstrDesc *Desc = &TII->get(LoadStoreOp);
@@ -1548,6 +1595,7 @@ void SIRegisterInfo::buildSpillLoadStore(
int64_t MaxOffset = Offset + Size + RemSize - EltSize;
int64_t ScratchOffsetRegDelta = 0;
+ int64_t AdditionalCFIOffset = 0;
if (IsFlat && EltSize > 4) {
LoadStoreOp = getFlatScratchSpillOpcode(TII, LoadStoreOp, EltSize);
@@ -1660,6 +1708,7 @@ void SIRegisterInfo::buildSpillLoadStore(
Scavenged = true;
}
+ AdditionalCFIOffset = Offset;
// We currently only support spilling VGPRs to EltSize boundaries, meaning
// we can simplify the adjustment of Offset here to just scale with
// WavefrontSize.
@@ -1762,7 +1811,8 @@ void SIRegisterInfo::buildSpillLoadStore(
Register Sub = IsSubReg
? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane)))
: ValueReg;
- auto MIB = spillVGPRtoAGPR(ST, MBB, MI, Index, Lane, Sub, IsKill);
+ auto MIB =
+ spillVGPRtoAGPR(ST, MBB, MI, Index, Lane, Sub, IsKill, NeedsCFI);
if (!MIB.getInstr())
break;
if (NeedSuperRegDef || (IsSubReg && IsStore && Lane == LaneS && IsFirstSubReg)) {
@@ -1884,6 +1934,18 @@ void SIRegisterInfo::buildSpillLoadStore(
ValueReg = FinalValueReg;
}
+ if (IsStore && NeedsCFI) {
+ if (TII->isBlockLoadStore(LoadStoreOp)) {
+ assert(RegOffset == 0 &&
+ "expected whole register block to be treated as single element");
+ buildCFIForBlockCSRStore(MBB, MI, ValueReg, Offset);
+ } else {
+ TFL->buildCFIForVGPRToVMEMSpill(
+ MBB, MI, DebugLoc(), SubReg,
+ (Offset + RegOffset) * ST.getWavefrontSize() + AdditionalCFIOffset);
+ }
+ }
+
if (!IsAGPR && NeedSuperRegDef)
MIB.addReg(ValueReg, RegState::ImplicitDefine);
@@ -1959,6 +2021,31 @@ void SIRegisterInfo::addImplicitUsesForBlockCSRLoad(MachineInstrBuilder &MIB,
MIB.addUse(BaseVGPR + RegOffset, RegState::Implicit);
}
+void SIRegisterInfo::buildCFIForBlockCSRStore(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ Register BlockReg,
+ int64_t Offset) const {
+ const MachineFunction *MF = MBB.getParent();
+ const SIMachineFunctionInfo *FuncInfo = MF->getInfo<SIMachineFunctionInfo>();
+ uint32_t Mask = FuncInfo->getMaskForVGPRBlockOps(BlockReg);
+ Register BaseVGPR = getSubReg(BlockReg, AMDGPU::sub0);
+ for (unsigned RegOffset = 0; RegOffset < 32; ++RegOffset) {
+ Register VGPR = BaseVGPR + RegOffset;
+ if (Mask & (1 << RegOffset)) {
+ assert(isCalleeSavedPhysReg(VGPR, *MF));
+ ST.getFrameLowering()->buildCFIForVGPRToVMEMSpill(
+ MBB, MBBI, DebugLoc(), VGPR,
+ (Offset + RegOffset) * ST.getWavefrontSize());
+ } else if (isCalleeSavedPhysReg(VGPR, *MF)) {
+ // FIXME: This is a workaround for the fact that FrameLowering's
+ // emitPrologueEntryCFI considers the block load to clobber all registers
+ // in the block.
+ ST.getFrameLowering()->buildCFIForSameValue(MBB, MBBI, DebugLoc(),
+ BaseVGPR + RegOffset);
+ }
+ }
+}
+
void SIRegisterInfo::buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index,
int Offset, bool IsLoad,
bool IsKill) const {
@@ -1995,7 +2082,7 @@ void SIRegisterInfo::buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index,
bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index,
RegScavenger *RS, SlotIndexes *Indexes,
LiveIntervals *LIS, bool OnlyToVGPR,
- bool SpillToPhysVGPRLane) const {
+ bool SpillToPhysVGPRLane, bool NeedsCFI) const {
assert(!MI->getOperand(0).isUndef() &&
"undef spill should have been deleted earlier");
@@ -2008,6 +2095,8 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index,
if (OnlyToVGPR && !SpillToVGPR)
return false;
+ const SIFrameLowering *TFL = ST.getFrameLowering();
+
assert(SpillToVGPR || (SB.SuperReg != SB.MFI.getStackPtrOffsetReg() &&
SB.SuperReg != SB.MFI.getFrameOffsetReg()));
@@ -2040,11 +2129,27 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index,
.addReg(SubReg, getKillRegState(UseKill))
.addImm(Spill.Lane)
.addReg(Spill.VGPR);
+
+ MachineInstr *CFI = nullptr;
+ if (NeedsCFI) {
+ if (SB.SuperReg == SB.TRI.getReturnAddressReg(SB.MF)) {
+ if (i == e - 1)
+ CFI = TFL->buildCFIForSGPRToVGPRSpill(*SB.MBB, MI, DebugLoc(),
+ AMDGPU::PC_REG, VGPRSpills);
+ } else {
+ CFI = TFL->buildCFIForSGPRToVGPRSpill(*SB.MBB, MI, DebugLoc(), SubReg,
+ Spill.VGPR, Spill.Lane);
+ }
+ }
+
if (Indexes) {
if (IsFirstSubreg)
Indexes->replaceMachineInstrInMaps(*MI, *MIB);
else
Indexes->insertMachineInstrInMaps(*MIB);
+
+ if (CFI)
+ Indexes->insertMachineInstrInMaps(*CFI);
}
if (IsFirstSubreg && SB.NumSubRegs > 1) {
@@ -2109,6 +2214,18 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index,
// Write out VGPR
SB.readWriteTmpVGPR(Offset, /*IsLoad*/ false);
+
+ // TODO: Implement CFI for SpillToVMEM for all scenarios.
+ MachineInstr *CFI = nullptr;
+ if (NeedsCFI && SB.SuperReg == SB.TRI.getReturnAddressReg(SB.MF)) {
+ int64_t CFIOffset = (Offset * SB.EltSize +
+ SB.MF.getFrameInfo().getObjectOffset(Index)) *
+ ST.getWavefrontSize();
+ CFI = TFL->buildCFIForSGPRToVMEMSpill(*SB.MBB, MI, DebugLoc(),
+ AMDGPU::PC_REG, CFIOffset);
+ }
+ if (Indexes && CFI)
+ Indexes->insertMachineInstrInMaps(*CFI);
}
SB.restore();
@@ -2280,7 +2397,20 @@ bool SIRegisterInfo::spillEmergencySGPR(MachineBasicBlock::iterator MI,
bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex(
MachineBasicBlock::iterator MI, int FI, RegScavenger *RS,
SlotIndexes *Indexes, LiveIntervals *LIS, bool SpillToPhysVGPRLane) const {
+ bool NeedsCFI = false;
switch (MI->getOpcode()) {
+ case AMDGPU::SI_SPILL_S1024_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S512_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S256_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S224_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S192_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S160_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S128_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S96_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S64_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S32_CFI_SAVE:
+ NeedsCFI = true;
+ [[fallthrough]];
case AMDGPU::SI_SPILL_S1024_SAVE:
case AMDGPU::SI_SPILL_S512_SAVE:
case AMDGPU::SI_SPILL_S384_SAVE:
@@ -2295,7 +2425,8 @@ bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex(
case AMDGPU::SI_SPILL_S96_SAVE:
case AMDGPU::SI_SPILL_S64_SAVE:
case AMDGPU::SI_SPILL_S32_SAVE:
- return spillSGPR(MI, FI, RS, Indexes, LIS, true, SpillToPhysVGPRLane);
+ return spillSGPR(MI, FI, RS, Indexes, LIS, true, SpillToPhysVGPRLane,
+ NeedsCFI);
case AMDGPU::SI_SPILL_S1024_RESTORE:
case AMDGPU::SI_SPILL_S512_RESTORE:
case AMDGPU::SI_SPILL_S384_RESTORE:
@@ -2338,8 +2469,23 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
? getBaseRegister()
: getFrameRegister(*MF);
+ bool NeedsCFI = false;
+
switch (MI->getOpcode()) {
// SGPR register spill
+ case AMDGPU::SI_SPILL_S1024_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S512_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S256_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S224_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S192_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S160_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S128_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S96_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S64_CFI_SAVE:
+ case AMDGPU::SI_SPILL_S32_CFI_SAVE: {
+ NeedsCFI = true;
+ [[fallthrough]];
+ }
case AMDGPU::SI_SPILL_S1024_SAVE:
case AMDGPU::SI_SPILL_S512_SAVE:
case AMDGPU::SI_SPILL_S384_SAVE:
@@ -2354,7 +2500,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
case AMDGPU::SI_SPILL_S96_SAVE:
case AMDGPU::SI_SPILL_S64_SAVE:
case AMDGPU::SI_SPILL_S32_SAVE: {
- return spillSGPR(MI, Index, RS);
+ return spillSGPR(MI, Index, RS, nullptr, nullptr, false, false, NeedsCFI);
}
// SGPR register restore
@@ -2376,13 +2522,40 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
}
// VGPR register spill
- case AMDGPU::SI_BLOCK_SPILL_V1024_SAVE: {
- // Put mask into M0.
- BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32),
- AMDGPU::M0)
- .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::mask));
+ case AMDGPU::SI_BLOCK_SPILL_V1024_CFI_SAVE:
+ case AMDGPU::SI_SPILL_V1024_CFI_SAVE:
+ case AMDGPU::SI_SPILL_V512_CFI_SAVE:
+ case AMDGPU::SI_SPILL_V256_CFI_SAVE:
+ case AMDGPU::SI_SPILL_V224_CFI_SAVE:
+ case AMDGPU::SI_SPILL_V192_CFI_SAVE:
+ case AMDGPU::SI_SPILL_V160_CFI_SAVE:
+ case AMDGPU::SI_SPILL_V128_CFI_SAVE:
+ case AMDGPU::SI_SPILL_V96_CFI_SAVE:
+ case AMDGPU::SI_SPILL_V64_CFI_SAVE:
+ case AMDGPU::SI_SPILL_V32_CFI_SAVE:
+ case AMDGPU::SI_SPILL_A1024_CFI_SAVE:
+ case AMDGPU::SI_SPILL_A512_CFI_SAVE:
+ case AMDGPU::SI_SPILL_A256_CFI_SAVE:
+ case AMDGPU::SI_SPILL_A224_CFI_SAVE:
+ case AMDGPU::SI_SPILL_A192_CFI_SAVE:
+ case AMDGPU::SI_SPILL_A160_CFI_SAVE:
+ case AMDGPU::SI_SPILL_A128_CFI_SAVE:
+ case AMDGPU::SI_SPILL_A96_CFI_SAVE:
+ case AMDGPU::SI_SPILL_A64_CFI_SAVE:
+ case AMDGPU::SI_SPILL_A32_CFI_SAVE:
+ case AMDGPU::SI_SPILL_AV1024_CFI_SAVE:
+ case AMDGPU::SI_SPILL_AV512_CFI_SAVE:
+ case AMDGPU::SI_SPILL_AV256_CFI_SAVE:
+ case AMDGPU::SI_SPILL_AV224_CFI_SAVE:
+ case AMDGPU::SI_SPILL_AV192_CFI_SAVE:
+ case AMDGPU::SI_SPILL_AV160_CFI_SAVE:
+ case AMDGPU::SI_SPILL_AV128_CFI_SAVE:
+ case AMDGPU::SI_SPILL_AV96_CFI_SAVE:
+ case AMDGPU::SI_SPILL_AV64_CFI_SAVE:
+ case AMDGPU::SI_SPILL_AV32_CFI_SAVE:
+ NeedsCFI = true;
[[fallthrough]];
- }
+ case AMDGPU::SI_BLOCK_SPILL_V1024_SAVE:
case AMDGPU::SI_SPILL_V1024_SAVE:
case AMDGPU::SI_SPILL_V512_SAVE:
case AMDGPU::SI_SPILL_V384_SAVE:
@@ -2428,6 +2601,16 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
case AMDGPU::SI_SPILL_AV32_SAVE:
case AMDGPU::SI_SPILL_WWM_V32_SAVE:
case AMDGPU::SI_SPILL_WWM_AV32_SAVE: {
+ assert(
+ MI->getOpcode() != AMDGPU::SI_BLOCK_SPILL_V1024_SAVE &&
+ "block spill does not currenty support spilling non-CSR registers");
+
+ if (MI->getOpcode() == AMDGPU::SI_BLOCK_SPILL_V1024_CFI_SAVE)
+ // Put mask into M0.
+ BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32),
+ AMDGPU::M0)
+ .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::mask));
+
const MachineOperand *VData = TII->getNamedOperand(*MI,
AMDGPU::OpName::vdata);
if (VData->isUndef()) {
@@ -2443,7 +2626,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
assert(ST.enableFlatScratch() && "Flat Scratch is not enabled!");
Opc = AMDGPU::SCRATCH_STORE_SHORT_SADDR_t16;
} else {
- Opc = MI->getOpcode() == AMDGPU::SI_BLOCK_SPILL_V1024_SAVE
+ Opc = MI->getOpcode() == AMDGPU::SI_BLOCK_SPILL_V1024_CFI_SAVE
? AMDGPU::SCRATCH_STORE_BLOCK_SADDR
: ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
: AMDGPU::BUFFER_STORE_DWORD_OFFSET;
@@ -2453,12 +2636,12 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
bool IsWWMRegSpill = TII->isWWMRegSpillOpcode(MI->getOpcode());
if (IsWWMRegSpill) {
TII->insertScratchExecCopy(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy(),
- RS->isRegUsed(AMDGPU::SCC));
+ RS->isRegUsed(AMDGPU::SCC));
}
buildSpillLoadStore(
*MBB, MI, DL, Opc, Index, VData->getReg(), VData->isKill(), FrameReg,
TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(),
- *MI->memoperands_begin(), RS);
+ *MI->memoperands_begin(), RS, nullptr, NeedsCFI);
MFI->addToSpilledVGPRs(getNumSubRegsForSpillOp(*MI, TII));
if (IsWWMRegSpill)
TII->restoreExec(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy());
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 7b91ba7bc581f..2dae5f0eb1c69 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -121,6 +121,13 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
void addImplicitUsesForBlockCSRLoad(MachineInstrBuilder &MIB,
Register BlockReg) const;
+ // Iterate over all VGPRs in the given BlockReg and emit CFI for each VGPR
+ // as-needed depending on the (statically known) mask, relative to the given
+ // base Offset.
+ void buildCFIForBlockCSRStore(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ Register BlockReg, int64_t Offset) const;
+
const TargetRegisterClass *
getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &MF) const override;
@@ -176,8 +183,8 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
/// free VGPR lane to spill.
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS,
SlotIndexes *Indexes = nullptr, LiveIntervals *LIS = nullptr,
- bool OnlyToVGPR = false,
- bool SpillToPhysVGPRLane = false) const;
+ bool OnlyToVGPR = false, bool SpillToPhysVGPRLane = false,
+ bool NeedsCFI = false) const;
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS,
SlotIndexes *Indexes = nullptr, LiveIntervals *LIS = nullptr,
@@ -459,8 +466,8 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
unsigned LoadStoreOp, int Index, Register ValueReg,
bool ValueIsKill, MCRegister ScratchOffsetReg,
int64_t InstrOffset, MachineMemOperand *MMO,
- RegScavenger *RS,
- LiveRegUnits *LiveUnits = nullptr) const;
+ RegScavenger *RS, LiveRegUnits *LiveUnits = nullptr,
+ bool NeedsCFI = false) const;
// Return alignment in register file of first register in a register tuple.
unsigned getRegClassAlignmentNumBits(const TargetRegisterClass *RC) const {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
index 023398377de94..2a5c8be7a987a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
@@ -13,14 +13,14 @@ define ptr addrspace(1) @call_assert_align() {
; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
; CHECK-NEXT: v_writelane_b32 v40, s16, 2
-; CHECK-NEXT: s_addk_i32 s32, 0x400
; CHECK-NEXT: v_writelane_b32 v40, s30, 0
+; CHECK-NEXT: s_addk_i32 s32, 0x400
+; CHECK-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-NEXT: s_getpc_b64 s[16:17]
; CHECK-NEXT: s_add_u32 s16, s16, ext at rel32@lo+4
; CHECK-NEXT: s_addc_u32 s17, s17, ext at rel32@hi+12
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_mov_b32_e32 v1, 0
-; CHECK-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT: v_mov_b32_e32 v2, 0
; CHECK-NEXT: v_readlane_b32 s30, v40, 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
index 2c1beb8468576..083bb2ed981e0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
@@ -222,20 +222,20 @@ define void @func_caller_stack() #2 {
; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1
; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[6:7]
+; MUBUF-NEXT: v_writelane_b32 v40, s4, 2
+; MUBUF-NEXT: v_writelane_b32 v40, s30, 0
; MUBUF-NEXT: s_addk_i32 s32, 0x400
+; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
; MUBUF-NEXT: v_mov_b32_e32 v0, 9
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4
; MUBUF-NEXT: v_mov_b32_e32 v0, 10
-; MUBUF-NEXT: v_writelane_b32 v40, s4, 2
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8
; MUBUF-NEXT: v_mov_b32_e32 v0, 11
-; MUBUF-NEXT: v_writelane_b32 v40, s30, 0
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12
; MUBUF-NEXT: v_mov_b32_e32 v0, 12
; MUBUF-NEXT: s_getpc_b64 s[4:5]
; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_v16i32_v16i32_v4i32 at rel32@lo+4
; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_v16i32_v16i32_v4i32 at rel32@hi+12
-; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5]
; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
@@ -257,8 +257,10 @@ define void @func_caller_stack() #2 {
; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1
; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
-; FLATSCR-NEXT: s_add_i32 s32, s32, 16
; FLATSCR-NEXT: v_writelane_b32 v40, s0, 2
+; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0
+; FLATSCR-NEXT: s_add_i32 s32, s32, 16
+; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
; FLATSCR-NEXT: s_add_u32 s0, s32, 4
; FLATSCR-NEXT: v_mov_b32_e32 v0, 9
; FLATSCR-NEXT: scratch_store_dword off, v0, s0
@@ -270,12 +272,10 @@ define void @func_caller_stack() #2 {
; FLATSCR-NEXT: scratch_store_dword off, v0, s0
; FLATSCR-NEXT: s_add_u32 s0, s32, 16
; FLATSCR-NEXT: v_mov_b32_e32 v0, 12
-; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0
; FLATSCR-NEXT: scratch_store_dword off, v0, s0
; FLATSCR-NEXT: s_getpc_b64 s[0:1]
; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_v16i32_v16i32_v4i32 at rel32@lo+4
; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_v16i32_v16i32_v4i32 at rel32@hi+12
-; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1]
; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
@@ -300,15 +300,15 @@ define void @func_caller_byval(ptr addrspace(5) %argptr) #2 {
; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1
; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[6:7]
-; MUBUF-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
-; MUBUF-NEXT: buffer_load_dword v2, v0, s[0:3], 0 offen offset:4
-; MUBUF-NEXT: s_addk_i32 s32, 0x400
; MUBUF-NEXT: v_writelane_b32 v40, s4, 2
; MUBUF-NEXT: v_writelane_b32 v40, s30, 0
+; MUBUF-NEXT: s_addk_i32 s32, 0x400
+; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
+; MUBUF-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
+; MUBUF-NEXT: buffer_load_dword v2, v0, s[0:3], 0 offen offset:4
; MUBUF-NEXT: s_getpc_b64 s[4:5]
; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_byval at rel32@lo+4
; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_byval at rel32@hi+12
-; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
; MUBUF-NEXT: s_waitcnt vmcnt(1)
; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s32
; MUBUF-NEXT: s_waitcnt vmcnt(1)
@@ -382,14 +382,14 @@ define void @func_caller_byval(ptr addrspace(5) %argptr) #2 {
; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1
; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
-; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v0, off
-; FLATSCR-NEXT: s_add_i32 s32, s32, 16
; FLATSCR-NEXT: v_writelane_b32 v40, s0, 2
; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0
+; FLATSCR-NEXT: s_add_i32 s32, s32, 16
+; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
+; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v0, off
; FLATSCR-NEXT: s_getpc_b64 s[0:1]
; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_byval at rel32@lo+4
; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_byval at rel32@hi+12
-; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: scratch_store_dwordx2 off, v[1:2], s32
; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v0, off offset:8
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
index 35591cd602992..f1f1dc896070d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
@@ -235,14 +235,14 @@ define void @sink_null_insert_pt(ptr addrspace(4) %arg0) #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[18:19], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[18:19]
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: global_load_dword v0, v[0:1], off glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_writelane_b32 v40, s16, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: global_load_dword v0, v[0:1], off glc
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_swappc_b64 s[30:31], 0
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
diff --git a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
index 003aa049b2d1b..324d853145924 100644
--- a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
+++ b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
@@ -337,7 +337,6 @@ define void @flat_atomic_xchg_i32_ret_av_av_no_agprs(ptr %ptr) #0 {
; GFX90A-LABEL: flat_atomic_xchg_i32_ret_av_av_no_agprs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse
@@ -354,6 +353,7 @@ define void @flat_atomic_xchg_i32_ret_av_av_no_agprs(ptr %ptr) #0 {
; GFX90A-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:31]
@@ -464,7 +464,6 @@ define void @flat_atomic_xchg_i32_ret_av_av_no_agprs(ptr %ptr) #0 {
; GFX950-LABEL: flat_atomic_xchg_i32_ret_av_av_no_agprs:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse
@@ -481,6 +480,7 @@ define void @flat_atomic_xchg_i32_ret_av_av_no_agprs(ptr %ptr) #0 {
; GFX950-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def v[0:31]
@@ -4006,7 +4006,6 @@ define void @flat_atomic_xor_i32_ret_av_av_no_agprs(ptr %ptr) #0 {
; GFX90A-LABEL: flat_atomic_xor_i32_ret_av_av_no_agprs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse
@@ -4023,6 +4022,7 @@ define void @flat_atomic_xor_i32_ret_av_av_no_agprs(ptr %ptr) #0 {
; GFX90A-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:31]
@@ -4131,7 +4131,6 @@ define void @flat_atomic_xor_i32_ret_av_av_no_agprs(ptr %ptr) #0 {
; GFX950-LABEL: flat_atomic_xor_i32_ret_av_av_no_agprs:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse
@@ -4148,6 +4147,7 @@ define void @flat_atomic_xor_i32_ret_av_av_no_agprs(ptr %ptr) #0 {
; GFX950-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def v[0:31]
diff --git a/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
index 34a4899123749..e67d5b0fad14a 100644
--- a/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
+++ b/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
@@ -337,7 +337,6 @@ define void @global_atomic_xchg_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0
; GFX90A-LABEL: global_atomic_xchg_i32_ret_av_av_no_agprs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse
@@ -354,6 +353,7 @@ define void @global_atomic_xchg_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0
; GFX90A-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:31]
@@ -464,7 +464,6 @@ define void @global_atomic_xchg_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0
; GFX950-LABEL: global_atomic_xchg_i32_ret_av_av_no_agprs:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse
@@ -481,6 +480,7 @@ define void @global_atomic_xchg_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0
; GFX950-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def v[0:31]
@@ -2985,7 +2985,6 @@ define void @global_atomic_xor_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0
; GFX90A-LABEL: global_atomic_xor_i32_ret_av_av_no_agprs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse
@@ -3002,6 +3001,7 @@ define void @global_atomic_xor_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0
; GFX90A-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse
+; GFX90A-NEXT: v_accvgpr_write_b32 a0, v0
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v[0:31]
@@ -3110,7 +3110,6 @@ define void @global_atomic_xor_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0
; GFX950-LABEL: global_atomic_xor_i32_ret_av_av_no_agprs:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a3, v40 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a4, v41 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a5, v42 ; Reload Reuse
@@ -3127,6 +3126,7 @@ define void @global_atomic_xor_i32_ret_av_av_no_agprs(ptr addrspace(1) %ptr) #0
; GFX950-NEXT: v_accvgpr_write_b32 a16, v61 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a17, v62 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a18, v63 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v0
; GFX950-NEXT: v_accvgpr_write_b32 a1, v1
; GFX950-NEXT: ;;#ASMSTART
; GFX950-NEXT: ; def v[0:31]
diff --git a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
index 0e24430e7be20..2d7cfcea04124 100644
--- a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
+++ b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
@@ -23,12 +23,12 @@ define void @parent_func_missing_inputs() #0 {
; FIXEDABI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; FIXEDABI-NEXT: s_mov_b64 exec, s[18:19]
; FIXEDABI-NEXT: v_writelane_b32 v40, s16, 2
-; FIXEDABI-NEXT: s_addk_i32 s32, 0x400
; FIXEDABI-NEXT: v_writelane_b32 v40, s30, 0
+; FIXEDABI-NEXT: s_addk_i32 s32, 0x400
+; FIXEDABI-NEXT: v_writelane_b32 v40, s31, 1
; FIXEDABI-NEXT: s_getpc_b64 s[16:17]
; FIXEDABI-NEXT: s_add_u32 s16, s16, requires_all_inputs at rel32@lo+4
; FIXEDABI-NEXT: s_addc_u32 s17, s17, requires_all_inputs at rel32@hi+12
-; FIXEDABI-NEXT: v_writelane_b32 v40, s31, 1
; FIXEDABI-NEXT: s_swappc_b64 s[30:31], s[16:17]
; FIXEDABI-NEXT: v_readlane_b32 s30, v40, 0
; FIXEDABI-NEXT: v_readlane_b32 s31, v40, 1
diff --git a/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir b/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
index 4ff3f5c13d42a..23cae4b6a6baa 100644
--- a/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+++ b/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
@@ -514,229 +514,453 @@ body: |
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95
; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64
; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64
; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64
; GFX90A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64
; GFX90A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64
; GFX90A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64
; GFX90A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64
; GFX90A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64
; GFX90A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64
; GFX90A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64
; GFX90A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64
; GFX90A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64
; GFX90A-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64
; GFX90A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64
; GFX90A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64
; GFX90A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64
; GFX90A-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64
; GFX90A-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64
; GFX90A-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64
; GFX90A-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64
; GFX90A-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64
; GFX90A-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64
; GFX90A-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64
; GFX90A-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64
; GFX90A-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64
; GFX90A-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64
; GFX90A-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64
; GFX90A-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64
; GFX90A-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64
; GFX90A-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64
; GFX90A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64
; GFX90A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64
; GFX90A-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64
; GFX90A-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64
; GFX90A-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64
; GFX90A-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64
; GFX90A-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64
; GFX90A-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64
; GFX90A-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64
; GFX90A-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64
; GFX90A-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64
; GFX90A-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64
; GFX90A-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64
; GFX90A-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64
; GFX90A-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64
; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64
; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64
; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0
; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5)
; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec
@@ -1473,229 +1697,453 @@ body: |
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95
; GFX90A-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0
; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5)
; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec
@@ -2462,229 +2910,453 @@ body: |
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95
; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64
; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64
; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64
; GFX90A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64
; GFX90A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64
; GFX90A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64
; GFX90A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64
; GFX90A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64
; GFX90A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64
; GFX90A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64
; GFX90A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64
; GFX90A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64
; GFX90A-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64
; GFX90A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64
; GFX90A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64
; GFX90A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64
; GFX90A-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64
; GFX90A-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64
; GFX90A-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64
; GFX90A-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64
; GFX90A-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64
; GFX90A-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64
; GFX90A-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64
; GFX90A-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64
; GFX90A-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64
; GFX90A-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64
; GFX90A-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64
; GFX90A-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64
; GFX90A-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64
; GFX90A-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64
; GFX90A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64
; GFX90A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64
; GFX90A-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64
; GFX90A-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64
; GFX90A-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64
; GFX90A-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64
; GFX90A-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64
; GFX90A-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64
; GFX90A-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64
; GFX90A-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64
; GFX90A-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64
; GFX90A-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64
; GFX90A-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64
; GFX90A-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64
; GFX90A-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64
; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64
; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64
; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0
; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5)
; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec
@@ -3424,229 +4096,453 @@ body: |
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95
; GFX90A-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0
; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5)
; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec
@@ -4415,229 +5311,453 @@ body: |
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95
; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64
; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64
; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64
; GFX90A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64
; GFX90A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64
; GFX90A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64
; GFX90A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64
; GFX90A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64
; GFX90A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64
; GFX90A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64
; GFX90A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64
; GFX90A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64
; GFX90A-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64
; GFX90A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64
; GFX90A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64
; GFX90A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64
; GFX90A-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64
; GFX90A-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64
; GFX90A-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64
; GFX90A-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64
; GFX90A-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64
; GFX90A-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64
; GFX90A-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64
; GFX90A-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64
; GFX90A-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64
; GFX90A-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64
; GFX90A-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64
; GFX90A-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64
; GFX90A-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64
; GFX90A-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64
; GFX90A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64
; GFX90A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64
; GFX90A-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64
; GFX90A-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64
; GFX90A-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64
; GFX90A-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64
; GFX90A-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64
; GFX90A-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64
; GFX90A-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64
; GFX90A-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64
; GFX90A-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64
; GFX90A-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64
; GFX90A-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64
; GFX90A-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64
; GFX90A-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64
; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64
; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64
; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0
; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5)
; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec
@@ -5380,229 +6500,453 @@ body: |
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95
; GFX90A-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0
; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5)
; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec
@@ -6367,229 +7711,453 @@ body: |
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95
; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64
; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64
; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64
; GFX90A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64
; GFX90A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64
; GFX90A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64
; GFX90A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64
; GFX90A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64
; GFX90A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64
; GFX90A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64
; GFX90A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64
; GFX90A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64
; GFX90A-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64
; GFX90A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64
; GFX90A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64
; GFX90A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64
; GFX90A-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64
; GFX90A-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64
; GFX90A-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64
; GFX90A-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64
; GFX90A-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64
; GFX90A-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64
; GFX90A-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64
; GFX90A-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64
; GFX90A-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64
; GFX90A-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64
; GFX90A-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64
; GFX90A-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64
; GFX90A-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64
; GFX90A-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64
; GFX90A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64
; GFX90A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64
; GFX90A-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64
; GFX90A-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64
; GFX90A-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64
; GFX90A-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64
; GFX90A-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64
; GFX90A-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64
; GFX90A-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64
; GFX90A-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64
; GFX90A-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64
; GFX90A-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64
; GFX90A-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64
; GFX90A-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64
; GFX90A-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64
; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64
; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64
; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0
; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5)
; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec
@@ -7326,229 +8894,453 @@ body: |
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95
; GFX90A-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0
; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5)
; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec
@@ -8314,229 +10106,453 @@ body: |
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95
; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64
; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64
; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64
; GFX90A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64
; GFX90A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64
; GFX90A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64
; GFX90A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64
; GFX90A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64
; GFX90A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64
; GFX90A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64
; GFX90A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64
; GFX90A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64
; GFX90A-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64
; GFX90A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64
; GFX90A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64
; GFX90A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64
; GFX90A-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64
; GFX90A-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64
; GFX90A-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64
; GFX90A-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64
; GFX90A-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64
; GFX90A-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64
; GFX90A-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64
; GFX90A-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64
; GFX90A-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64
; GFX90A-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64
; GFX90A-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64
; GFX90A-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64
; GFX90A-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64
; GFX90A-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64
; GFX90A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64
; GFX90A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64
; GFX90A-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64
; GFX90A-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64
; GFX90A-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64
; GFX90A-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64
; GFX90A-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64
; GFX90A-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64
; GFX90A-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64
; GFX90A-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64
; GFX90A-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64
; GFX90A-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64
; GFX90A-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64
; GFX90A-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64
; GFX90A-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64
; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64
; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64
; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0
; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5)
; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec
@@ -9276,229 +11292,453 @@ body: |
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95
; GFX90A-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0
; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5)
; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec
@@ -10265,229 +12505,453 @@ body: |
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95
; GFX90A-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64
; GFX90A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64
; GFX90A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64
; GFX90A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64
; GFX90A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64
; GFX90A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64
; GFX90A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64
; GFX90A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64
; GFX90A-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64
; GFX90A-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64
; GFX90A-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64
; GFX90A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64
; GFX90A-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64
; GFX90A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64
; GFX90A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64
; GFX90A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64
; GFX90A-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64
; GFX90A-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64
; GFX90A-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64
; GFX90A-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64
; GFX90A-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64
; GFX90A-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64
; GFX90A-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64
; GFX90A-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64
; GFX90A-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64
; GFX90A-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64
; GFX90A-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64
; GFX90A-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64
; GFX90A-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64
; GFX90A-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64
; GFX90A-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64
; GFX90A-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64
; GFX90A-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64
; GFX90A-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64
; GFX90A-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64
; GFX90A-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64
; GFX90A-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64
; GFX90A-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64
; GFX90A-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64
; GFX90A-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64
; GFX90A-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64
; GFX90A-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64
; GFX90A-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64
; GFX90A-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64
; GFX90A-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64
; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64
; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64
; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5)
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0
; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5)
; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec
@@ -11230,229 +13694,453 @@ body: |
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95
; GFX90A-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr32, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr32, $vgpr0, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 killed $agpr33, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr33, $vgpr1, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 killed $agpr34, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr34, $vgpr2, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr35, $vgpr3, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 killed $agpr36, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr36, $vgpr4, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 killed $agpr37, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr37, $vgpr5, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 killed $agpr38, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr38, $vgpr6, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 killed $agpr39, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr39, $vgpr7, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr8 = V_ACCVGPR_READ_B32_e64 killed $agpr40, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr40, $vgpr8, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr9 = V_ACCVGPR_READ_B32_e64 killed $agpr41, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr41, $vgpr9, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr10 = V_ACCVGPR_READ_B32_e64 killed $agpr42, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr42, $vgpr10, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 killed $agpr43, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr43, $vgpr11, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 killed $agpr44, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr44, $vgpr12, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 killed $agpr45, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr45, $vgpr13, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 killed $agpr46, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr46, $vgpr14, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 killed $agpr47, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr47, $vgpr15, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr16 = V_ACCVGPR_READ_B32_e64 killed $agpr48, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr48, $vgpr16, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr17 = V_ACCVGPR_READ_B32_e64 killed $agpr49, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr49, $vgpr17, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr18 = V_ACCVGPR_READ_B32_e64 killed $agpr50, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr50, $vgpr18, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr19 = V_ACCVGPR_READ_B32_e64 killed $agpr51, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr51, $vgpr19, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr20 = V_ACCVGPR_READ_B32_e64 killed $agpr52, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr52, $vgpr20, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr21 = V_ACCVGPR_READ_B32_e64 killed $agpr53, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr53, $vgpr21, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr22 = V_ACCVGPR_READ_B32_e64 killed $agpr54, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr54, $vgpr22, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr23 = V_ACCVGPR_READ_B32_e64 killed $agpr55, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr55, $vgpr23, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr24 = V_ACCVGPR_READ_B32_e64 killed $agpr56, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr56, $vgpr24, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr25 = V_ACCVGPR_READ_B32_e64 killed $agpr57, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr57, $vgpr25, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr26 = V_ACCVGPR_READ_B32_e64 killed $agpr58, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr58, $vgpr26, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr27 = V_ACCVGPR_READ_B32_e64 killed $agpr59, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr59, $vgpr27, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr28 = V_ACCVGPR_READ_B32_e64 killed $agpr60, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr60, $vgpr28, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr29 = V_ACCVGPR_READ_B32_e64 killed $agpr61, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr61, $vgpr29, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr30 = V_ACCVGPR_READ_B32_e64 killed $agpr62, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr62, $vgpr30, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr31 = V_ACCVGPR_READ_B32_e64 killed $agpr63, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr63, $vgpr31, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr32 = V_ACCVGPR_READ_B32_e64 killed $agpr64, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr64, $vgpr32, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr33 = V_ACCVGPR_READ_B32_e64 killed $agpr65, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr65, $vgpr33, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr34 = V_ACCVGPR_READ_B32_e64 killed $agpr66, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr66, $vgpr34, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr35 = V_ACCVGPR_READ_B32_e64 killed $agpr67, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr67, $vgpr35, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr36 = V_ACCVGPR_READ_B32_e64 killed $agpr68, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr68, $vgpr36, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr37 = V_ACCVGPR_READ_B32_e64 killed $agpr69, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr69, $vgpr37, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr38 = V_ACCVGPR_READ_B32_e64 killed $agpr70, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr70, $vgpr38, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr39 = V_ACCVGPR_READ_B32_e64 killed $agpr71, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr71, $vgpr39, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr48 = V_ACCVGPR_READ_B32_e64 killed $agpr72, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr72, $vgpr48, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr49 = V_ACCVGPR_READ_B32_e64 killed $agpr73, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr73, $vgpr49, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr50 = V_ACCVGPR_READ_B32_e64 killed $agpr74, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr74, $vgpr50, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr51 = V_ACCVGPR_READ_B32_e64 killed $agpr75, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr75, $vgpr51, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr52 = V_ACCVGPR_READ_B32_e64 killed $agpr76, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr76, $vgpr52, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr77, $vgpr53, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr78, $vgpr54, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $agpr79, $vgpr55, 32, $exec, 64
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr80, 32, $exec, 64, 44800
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr81, 32, $exec, 64, 44544
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr82, 32, $exec, 64, 44288
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr83, 32, $exec, 64, 44032
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr84, 32, $exec, 64, 43776
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr85, 32, $exec, 64, 43520
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr86, 32, $exec, 64, 43264
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr87, 32, $exec, 64, 43008
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr88, 32, $exec, 64, 42752
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr89, 32, $exec, 64, 42496
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr90, 32, $exec, 64, 42240
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr91, 32, $exec, 64, 41984
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr92, 32, $exec, 64, 41728
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr93, 32, $exec, 64, 41472
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr94, 32, $exec, 64, 41216
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr95, 32, $exec, 64, 40960
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr96, 32, $exec, 64, 40704
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr97, 32, $exec, 64, 40448
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr98, 32, $exec, 64, 40192
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr99, 32, $exec, 64, 39936
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr100, 32, $exec, 64, 39680
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr101, 32, $exec, 64, 39424
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr102, 32, $exec, 64, 39168
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr103, 32, $exec, 64, 38912
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr104, 32, $exec, 64, 38656
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr105, 32, $exec, 64, 38400
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr106, 32, $exec, 64, 38144
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr107, 32, $exec, 64, 37888
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr108, 32, $exec, 64, 37632
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr109, 32, $exec, 64, 37376
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr110, 32, $exec, 64, 37120
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr111, 32, $exec, 64, 36864
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr112, 32, $exec, 64, 36608
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr113, 32, $exec, 64, 36352
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr114, 32, $exec, 64, 36096
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr115, 32, $exec, 64, 35840
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr116, 32, $exec, 64, 35584
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr117, 32, $exec, 64, 35328
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr118, 32, $exec, 64, 35072
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr119, 32, $exec, 64, 34816
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr120, 32, $exec, 64, 34560
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr121, 32, $exec, 64, 34304
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr122, 32, $exec, 64, 34048
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr123, 32, $exec, 64, 33792
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr124, 32, $exec, 64, 33536
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr125, 32, $exec, 64, 33280
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr126, 32, $exec, 64, 33024
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr127, 32, $exec, 64, 32768
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr128, 32, $exec, 64, 32512
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr129, 32, $exec, 64, 32256
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr130, 32, $exec, 64, 32000
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr131, 32, $exec, 64, 31744
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr132, 32, $exec, 64, 31488
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr133, 32, $exec, 64, 31232
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr134, 32, $exec, 64, 30976
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr135, 32, $exec, 64, 30720
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr136, 32, $exec, 64, 30464
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr137, 32, $exec, 64, 30208
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr138, 32, $exec, 64, 29952
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr139, 32, $exec, 64, 29696
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr140, 32, $exec, 64, 29440
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr141, 32, $exec, 64, 29184
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr142, 32, $exec, 64, 28928
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr143, 32, $exec, 64, 28672
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr144, 32, $exec, 64, 28416
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr145, 32, $exec, 64, 28160
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr146, 32, $exec, 64, 27904
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr147, 32, $exec, 64, 27648
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr148, 32, $exec, 64, 27392
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr149, 32, $exec, 64, 27136
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr150, 32, $exec, 64, 26880
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr151, 32, $exec, 64, 26624
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr152, 32, $exec, 64, 26368
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr153, 32, $exec, 64, 26112
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr154, 32, $exec, 64, 25856
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr155, 32, $exec, 64, 25600
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr156, 32, $exec, 64, 25344
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr157, 32, $exec, 64, 25088
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr158, 32, $exec, 64, 24832
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr159, 32, $exec, 64, 24576
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr160, 32, $exec, 64, 24320
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr161, 32, $exec, 64, 24064
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr162, 32, $exec, 64, 23808
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr163, 32, $exec, 64, 23552
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr164, 32, $exec, 64, 23296
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr165, 32, $exec, 64, 23040
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr166, 32, $exec, 64, 22784
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr167, 32, $exec, 64, 22528
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr168, 32, $exec, 64, 22272
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr169, 32, $exec, 64, 22016
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr170, 32, $exec, 64, 21760
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr171, 32, $exec, 64, 21504
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr172, 32, $exec, 64, 21248
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr173, 32, $exec, 64, 20992
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr174, 32, $exec, 64, 20736
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr175, 32, $exec, 64, 20480
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr176, 32, $exec, 64, 20224
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr177, 32, $exec, 64, 19968
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr178, 32, $exec, 64, 19712
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr179, 32, $exec, 64, 19456
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr180, 32, $exec, 64, 19200
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr181, 32, $exec, 64, 18944
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr182, 32, $exec, 64, 18688
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr183, 32, $exec, 64, 18432
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr184, 32, $exec, 64, 18176
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr185, 32, $exec, 64, 17920
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr186, 32, $exec, 64, 17664
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr187, 32, $exec, 64, 17408
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr188, 32, $exec, 64, 17152
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr189, 32, $exec, 64, 16896
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr190, 32, $exec, 64, 16640
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr191, 32, $exec, 64, 16384
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr192, 32, $exec, 64, 16128
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr193, 32, $exec, 64, 15872
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr194, 32, $exec, 64, 15616
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr195, 32, $exec, 64, 15360
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr196, 32, $exec, 64, 15104
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr197, 32, $exec, 64, 14848
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr198, 32, $exec, 64, 14592
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr199, 32, $exec, 64, 14336
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr200, 32, $exec, 64, 14080
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr201, 32, $exec, 64, 13824
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr202, 32, $exec, 64, 13568
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr203, 32, $exec, 64, 13312
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr204, 32, $exec, 64, 13056
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr205, 32, $exec, 64, 12800
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr206, 32, $exec, 64, 12544
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr207, 32, $exec, 64, 12288
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr208, 32, $exec, 64, 12032
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr209, 32, $exec, 64, 11776
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr210, 32, $exec, 64, 11520
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr211, 32, $exec, 64, 11264
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr212, 32, $exec, 64, 11008
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr213, 32, $exec, 64, 10752
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr214, 32, $exec, 64, 10496
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr215, 32, $exec, 64, 10240
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr216, 32, $exec, 64, 9984
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr217, 32, $exec, 64, 9728
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr218, 32, $exec, 64, 9472
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr219, 32, $exec, 64, 9216
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr220, 32, $exec, 64, 8960
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr221, 32, $exec, 64, 8704
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr222, 32, $exec, 64, 8448
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr223, 32, $exec, 64, 8192
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr224, 32, $exec, 64, 7936
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr225, 32, $exec, 64, 7680
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr226, 32, $exec, 64, 7424
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr227, 32, $exec, 64, 7168
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr228, 32, $exec, 64, 6912
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr229, 32, $exec, 64, 6656
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr230, 32, $exec, 64, 6400
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr231, 32, $exec, 64, 6144
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr232, 32, $exec, 64, 5888
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr233, 32, $exec, 64, 5632
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr234, 32, $exec, 64, 5376
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr235, 32, $exec, 64, 5120
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr236, 32, $exec, 64, 4864
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr237, 32, $exec, 64, 4608
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr238, 32, $exec, 64, 4352
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr239, 32, $exec, 64, 4096
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr240, 32, $exec, 64, 3840
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr241, 32, $exec, 64, 3584
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr242, 32, $exec, 64, 3328
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr243, 32, $exec, 64, 3072
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr244, 32, $exec, 64, 2816
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr245, 32, $exec, 64, 2560
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr246, 32, $exec, 64, 2304
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr247, 32, $exec, 64, 2048
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr248, 32, $exec, 64, 1792
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr249, 32, $exec, 64, 1536
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr250, 32, $exec, 64, 1280
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr251, 32, $exec, 64, 1024
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr252, 32, $exec, 64, 768
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr253, 32, $exec, 64, 512
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr254, 32, $exec, 64, 256
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5)
+ ; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $agpr255, 32, $exec, 64, 0
; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc
; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5)
; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
index ebbeab94066d6..a21db73cf3714 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
+++ b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
@@ -451,6 +451,7 @@ define void @v32_asm_def_use(float %v0, float %v1) #4 {
; GFX90A-LABEL: v32_asm_def_use:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_accvgpr_read_b32 v35, a32 ; Reload Reuse
; GFX90A-NEXT: v_mov_b32_e32 v34, v0
; GFX90A-NEXT: v_mov_b32_e32 v33, v1
; GFX90A-NEXT: ;;#ASMSTART
@@ -478,8 +479,8 @@ define void @v32_asm_def_use(float %v0, float %v1) #4 {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; copy
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_accvgpr_read_b32 v35, a32 ; Reload Reuse
; GFX90A-NEXT: v_accvgpr_mov_b32 a32, a1
+; GFX90A-NEXT: s_nop 0
; GFX90A-NEXT: v_mfma_f32_16x16x1f32 a[0:15], v34, v33, a[16:31]
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; copy
@@ -1056,6 +1057,7 @@ define void @no_free_vgprs_at_sgpr_to_agpr_copy(float %v0, float %v1) #0 {
; GFX90A-LABEL: no_free_vgprs_at_sgpr_to_agpr_copy:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX90A-NEXT: v_accvgpr_read_b32 v34, a32 ; Reload Reuse
; GFX90A-NEXT: v_mov_b32_e32 v33, v0
; GFX90A-NEXT: v_mov_b32_e32 v32, v1
; GFX90A-NEXT: ;;#ASMSTART
@@ -1077,8 +1079,7 @@ define void @no_free_vgprs_at_sgpr_to_agpr_copy(float %v0, float %v1) #0 {
; GFX90A-NEXT: v_accvgpr_write_b32 a18, s2
; GFX90A-NEXT: v_accvgpr_write_b32 a17, s1
; GFX90A-NEXT: v_accvgpr_write_b32 a16, s0
-; GFX90A-NEXT: v_accvgpr_read_b32 v34, a32 ; Reload Reuse
-; GFX90A-NEXT: s_nop 0
+; GFX90A-NEXT: s_nop 1
; GFX90A-NEXT: v_mfma_f32_16x16x1f32 a[0:15], v33, v32, a[16:31]
; GFX90A-NEXT: s_nop 10
; GFX90A-NEXT: buffer_store_dword a0, off, s[0:3], s32 ; 4-byte Folded Spill
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll b/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
index b6e65c8842904..d20b15408b7c6 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
@@ -19,16 +19,17 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr)
; DAGISEL-NEXT: s_wait_alu 0xfffe
; DAGISEL-NEXT: s_mov_b32 exec_lo, s1
; DAGISEL-NEXT: v_writelane_b32 v42, s0, 2
+; DAGISEL-NEXT: s_add_co_i32 s32, s32, 16
; DAGISEL-NEXT: s_clause 0x1
; DAGISEL-NEXT: scratch_store_b32 off, v40, s33 offset:4
+; DAGISEL-NEXT: ; meta instruction
; DAGISEL-NEXT: scratch_store_b32 off, v41, s33
+; DAGISEL-NEXT: v_writelane_b32 v42, s30, 0
+; DAGISEL-NEXT: v_writelane_b32 v42, s31, 1
; DAGISEL-NEXT: v_dual_mov_b32 v41, v2 :: v_dual_mov_b32 v40, v1
; DAGISEL-NEXT: v_add_nc_u32_e32 v1, 13, v0
-; DAGISEL-NEXT: v_writelane_b32 v42, s30, 0
; DAGISEL-NEXT: s_mov_b32 s1, good_callee at abs32@hi
; DAGISEL-NEXT: s_mov_b32 s0, good_callee at abs32@lo
-; DAGISEL-NEXT: s_add_co_i32 s32, s32, 16
-; DAGISEL-NEXT: v_writelane_b32 v42, s31, 1
; DAGISEL-NEXT: s_wait_alu 0xfffe
; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; DAGISEL-NEXT: global_store_b32 v[40:41], v0, off
@@ -62,16 +63,17 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr)
; GISEL-NEXT: s_wait_alu 0xfffe
; GISEL-NEXT: s_mov_b32 exec_lo, s1
; GISEL-NEXT: v_writelane_b32 v42, s0, 2
+; GISEL-NEXT: s_add_co_i32 s32, s32, 16
; GISEL-NEXT: s_clause 0x1
; GISEL-NEXT: scratch_store_b32 off, v40, s33 offset:4
+; GISEL-NEXT: ; meta instruction
; GISEL-NEXT: scratch_store_b32 off, v41, s33
+; GISEL-NEXT: v_writelane_b32 v42, s30, 0
+; GISEL-NEXT: v_writelane_b32 v42, s31, 1
; GISEL-NEXT: v_dual_mov_b32 v40, v1 :: v_dual_mov_b32 v41, v2
; GISEL-NEXT: v_add_nc_u32_e32 v1, 13, v0
-; GISEL-NEXT: v_writelane_b32 v42, s30, 0
; GISEL-NEXT: s_mov_b32 s0, good_callee at abs32@lo
; GISEL-NEXT: s_mov_b32 s1, good_callee at abs32@hi
-; GISEL-NEXT: s_add_co_i32 s32, s32, 16
-; GISEL-NEXT: v_writelane_b32 v42, s31, 1
; GISEL-NEXT: s_wait_alu 0xfffe
; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GISEL-NEXT: global_store_b32 v[40:41], v0, off
@@ -779,14 +781,13 @@ define amdgpu_gfx void @ret_void(i32 %x) #0 {
; DAGISEL-NEXT: s_wait_alu 0xfffe
; DAGISEL-NEXT: s_mov_b32 exec_lo, s1
; DAGISEL-NEXT: v_writelane_b32 v40, s0, 2
-; DAGISEL-NEXT: s_mov_b32 s1, void_callee at abs32@hi
-; DAGISEL-NEXT: s_mov_b32 s0, void_callee at abs32@lo
; DAGISEL-NEXT: s_add_co_i32 s32, s32, 16
; DAGISEL-NEXT: v_writelane_b32 v40, s30, 0
; DAGISEL-NEXT: v_writelane_b32 v40, s31, 1
+; DAGISEL-NEXT: s_mov_b32 s1, void_callee at abs32@hi
+; DAGISEL-NEXT: s_mov_b32 s0, void_callee at abs32@lo
; DAGISEL-NEXT: s_wait_alu 0xfffe
; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL-NEXT: v_readlane_b32 s30, v40, 0
; DAGISEL-NEXT: v_readlane_b32 s31, v40, 1
; DAGISEL-NEXT: s_mov_b32 s32, s33
@@ -814,14 +815,13 @@ define amdgpu_gfx void @ret_void(i32 %x) #0 {
; GISEL-NEXT: s_wait_alu 0xfffe
; GISEL-NEXT: s_mov_b32 exec_lo, s1
; GISEL-NEXT: v_writelane_b32 v40, s0, 2
-; GISEL-NEXT: s_mov_b32 s0, void_callee at abs32@lo
-; GISEL-NEXT: s_mov_b32 s1, void_callee at abs32@hi
; GISEL-NEXT: s_add_co_i32 s32, s32, 16
; GISEL-NEXT: v_writelane_b32 v40, s30, 0
; GISEL-NEXT: v_writelane_b32 v40, s31, 1
+; GISEL-NEXT: s_mov_b32 s0, void_callee at abs32@lo
+; GISEL-NEXT: s_mov_b32 s1, void_callee at abs32@hi
; GISEL-NEXT: s_wait_alu 0xfffe
; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_readlane_b32 s30, v40, 0
; GISEL-NEXT: v_readlane_b32 s31, v40, 1
; GISEL-NEXT: s_mov_b32 s32, s33
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 1e2a46fcefa36..7ab46020d6efc 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -6757,24 +6757,43 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x13
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:88
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:84
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:80
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:76
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:72
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:68
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:64
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:60
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:56
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:52
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:48
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:44
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:40
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:36
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:32
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:28
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:24
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:20
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:16
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:12
; GFX11-FAKE16-NEXT: s_clause 0x2
; GFX11-FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
@@ -7500,8 +7519,9 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: v_writelane_b32 v20, s97, 31
; SI-NEXT: v_writelane_b32 v20, s98, 32
; SI-NEXT: v_writelane_b32 v20, s99, 33
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_writelane_b32 v20, s30, 34
+; SI-NEXT: v_writelane_b32 v20, s31, 35
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_readfirstlane_b32 s44, v1
; SI-NEXT: v_readfirstlane_b32 s45, v2
; SI-NEXT: v_readfirstlane_b32 s42, v3
@@ -7521,7 +7541,6 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v17
; SI-NEXT: s_and_b64 s[46:47], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v18
-; SI-NEXT: v_writelane_b32 v20, s31, 35
; SI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB13_4
@@ -8660,8 +8679,9 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_writelane_b32 v20, s85, 27
; VI-NEXT: v_writelane_b32 v20, s86, 28
; VI-NEXT: v_writelane_b32 v20, s87, 29
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; VI-NEXT: v_writelane_b32 v20, s30, 30
+; VI-NEXT: v_writelane_b32 v20, s31, 31
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: v_readfirstlane_b32 s45, v2
; VI-NEXT: v_readfirstlane_b32 s42, v3
@@ -8681,7 +8701,6 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s4, v17
; VI-NEXT: s_and_b64 s[46:47], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v18
-; VI-NEXT: v_writelane_b32 v20, s31, 31
; VI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; VI-NEXT: s_cbranch_scc0 .LBB13_4
; VI-NEXT: ; %bb.1: ; %cmp.false
@@ -9713,8 +9732,9 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_writelane_b32 v20, s97, 31
; GFX9-NEXT: v_writelane_b32 v20, s98, 32
; GFX9-NEXT: v_writelane_b32 v20, s99, 33
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; GFX9-NEXT: v_writelane_b32 v20, s30, 34
+; GFX9-NEXT: v_writelane_b32 v20, s31, 35
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; GFX9-NEXT: v_readfirstlane_b32 s44, v1
; GFX9-NEXT: v_readfirstlane_b32 s45, v2
; GFX9-NEXT: v_readfirstlane_b32 s42, v3
@@ -9734,7 +9754,6 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s4, v17
; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v18
-; GFX9-NEXT: v_writelane_b32 v20, s31, 35
; GFX9-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; GFX9-NEXT: s_cbranch_scc0 .LBB13_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
@@ -10673,42 +10692,14 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: scratch_store_b32 off, v19, s32 offset:12
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v16, s34, 0
-; GFX11-NEXT: v_writelane_b32 v17, s98, 0
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
-; GFX11-NEXT: v_readfirstlane_b32 s40, v1
-; GFX11-NEXT: v_readfirstlane_b32 s41, v2
; GFX11-NEXT: v_writelane_b32 v16, s35, 1
-; GFX11-NEXT: v_writelane_b32 v17, s99, 1
-; GFX11-NEXT: v_readfirstlane_b32 s14, v3
-; GFX11-NEXT: v_readfirstlane_b32 s15, v4
-; GFX11-NEXT: v_readfirstlane_b32 s12, v5
; GFX11-NEXT: v_writelane_b32 v16, s36, 2
-; GFX11-NEXT: v_writelane_b32 v17, s100, 2
-; GFX11-NEXT: v_readfirstlane_b32 s13, v6
-; GFX11-NEXT: v_readfirstlane_b32 s10, v7
-; GFX11-NEXT: v_readfirstlane_b32 s11, v8
; GFX11-NEXT: v_writelane_b32 v16, s37, 3
-; GFX11-NEXT: v_writelane_b32 v17, s101, 3
-; GFX11-NEXT: v_readfirstlane_b32 s8, v9
-; GFX11-NEXT: v_readfirstlane_b32 s9, v10
-; GFX11-NEXT: v_readfirstlane_b32 s6, v11
; GFX11-NEXT: v_writelane_b32 v16, s38, 4
-; GFX11-NEXT: v_writelane_b32 v17, s102, 4
-; GFX11-NEXT: v_readfirstlane_b32 s7, v12
-; GFX11-NEXT: v_readfirstlane_b32 s4, v13
-; GFX11-NEXT: v_readfirstlane_b32 s5, v14
; GFX11-NEXT: v_writelane_b32 v16, s39, 5
-; GFX11-NEXT: v_writelane_b32 v17, s103, 5
-; GFX11-NEXT: s_mov_b32 s101, 0
-; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
-; GFX11-NEXT: ; implicit-def: $vgpr19 : SGPR spill to VGPR lane
-; GFX11-NEXT: ; implicit-def: $vgpr18 : SGPR spill to VGPR lane
; GFX11-NEXT: v_writelane_b32 v16, s48, 6
-; GFX11-NEXT: v_writelane_b32 v17, s104, 6
; GFX11-NEXT: v_writelane_b32 v16, s49, 7
-; GFX11-NEXT: v_writelane_b32 v17, s30, 7
; GFX11-NEXT: v_writelane_b32 v16, s50, 8
-; GFX11-NEXT: v_writelane_b32 v17, s31, 8
; GFX11-NEXT: v_writelane_b32 v16, s51, 9
; GFX11-NEXT: v_writelane_b32 v16, s52, 10
; GFX11-NEXT: v_writelane_b32 v16, s53, 11
@@ -10732,6 +10723,34 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: v_writelane_b32 v16, s87, 29
; GFX11-NEXT: v_writelane_b32 v16, s96, 30
; GFX11-NEXT: v_writelane_b32 v16, s97, 31
+; GFX11-NEXT: v_writelane_b32 v17, s98, 0
+; GFX11-NEXT: v_writelane_b32 v17, s99, 1
+; GFX11-NEXT: v_writelane_b32 v17, s100, 2
+; GFX11-NEXT: v_writelane_b32 v17, s101, 3
+; GFX11-NEXT: v_writelane_b32 v17, s102, 4
+; GFX11-NEXT: v_writelane_b32 v17, s103, 5
+; GFX11-NEXT: v_writelane_b32 v17, s104, 6
+; GFX11-NEXT: v_writelane_b32 v17, s30, 7
+; GFX11-NEXT: v_writelane_b32 v17, s31, 8
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
+; GFX11-NEXT: v_readfirstlane_b32 s40, v1
+; GFX11-NEXT: v_readfirstlane_b32 s41, v2
+; GFX11-NEXT: v_readfirstlane_b32 s14, v3
+; GFX11-NEXT: v_readfirstlane_b32 s15, v4
+; GFX11-NEXT: v_readfirstlane_b32 s12, v5
+; GFX11-NEXT: v_readfirstlane_b32 s13, v6
+; GFX11-NEXT: v_readfirstlane_b32 s10, v7
+; GFX11-NEXT: v_readfirstlane_b32 s11, v8
+; GFX11-NEXT: v_readfirstlane_b32 s8, v9
+; GFX11-NEXT: v_readfirstlane_b32 s9, v10
+; GFX11-NEXT: v_readfirstlane_b32 s6, v11
+; GFX11-NEXT: v_readfirstlane_b32 s7, v12
+; GFX11-NEXT: v_readfirstlane_b32 s4, v13
+; GFX11-NEXT: v_readfirstlane_b32 s5, v14
+; GFX11-NEXT: s_mov_b32 s101, 0
+; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
+; GFX11-NEXT: ; implicit-def: $vgpr19 : SGPR spill to VGPR lane
+; GFX11-NEXT: ; implicit-def: $vgpr18 : SGPR spill to VGPR lane
; GFX11-NEXT: s_cbranch_scc0 .LBB13_2
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s43, s25, 8
@@ -16364,56 +16383,105 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:592
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:588
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:584
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:580
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:576
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:572
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:568
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:564
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:560
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:556
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:552
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:548
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:544
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:540
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:536
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:532
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:528
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:524
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:520
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:516
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:512
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:508
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:504
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:500
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:496
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:492
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:488
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:484
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:480
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:476
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:472
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:468
; GFX11-FAKE16-NEXT: s_clause 0x12
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:464
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:460
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:456
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:452
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:448
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:444
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:440
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:436
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:432
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:428
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:424
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:420
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:416
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:412
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:408
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:404
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:400
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:396
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:392
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
@@ -20685,45 +20753,83 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:476
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:472
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:468
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:464
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:460
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:456
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:452
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:448
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:444
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:440
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:436
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:432
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:428
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:424
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:420
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:416
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:412
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:408
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:404
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:400
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:396
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:392
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:388
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:384
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:380
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:376
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:372
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:368
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:364
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:360
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:356
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:352
; GFX11-TRUE16-NEXT: s_clause 0x7
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:348
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:344
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:340
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:336
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:332
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:328
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:324
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:320
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
@@ -21626,45 +21732,83 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:476
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:472
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:468
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:464
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:460
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:456
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:452
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:448
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:444
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:440
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:436
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:432
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:428
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:424
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:420
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:416
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:412
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:408
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:404
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:400
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:396
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:392
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:388
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:384
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:380
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:376
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:372
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:368
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:364
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:360
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:356
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:352
; GFX11-FAKE16-NEXT: s_clause 0x7
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:348
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:344
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:340
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:336
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:332
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:328
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:324
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:320
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
@@ -23522,8 +23666,9 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a
; SI-NEXT: v_writelane_b32 v20, s97, 31
; SI-NEXT: v_writelane_b32 v20, s98, 32
; SI-NEXT: v_writelane_b32 v20, s99, 33
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_writelane_b32 v20, s30, 34
+; SI-NEXT: v_writelane_b32 v20, s31, 35
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_readfirstlane_b32 s70, v1
; SI-NEXT: v_readfirstlane_b32 s71, v2
; SI-NEXT: v_readfirstlane_b32 s80, v3
@@ -23543,7 +23688,6 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a
; SI-NEXT: v_readfirstlane_b32 s8, v17
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v18
-; SI-NEXT: v_writelane_b32 v20, s31, 35
; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB17_2
; SI-NEXT: ; %bb.1: ; %cmp.false
@@ -26131,20 +26275,35 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
@@ -29180,81 +29339,149 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v32i32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:156
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:28
; GFX11-TRUE16-NEXT: s_clause 0x6
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v167, v13 :: v_dual_mov_b32 v176, v12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v177, v11 :: v_dual_mov_b32 v178, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v179, v9 :: v_dual_mov_b32 v180, v8
@@ -30154,83 +30381,153 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v32i32_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:288
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:284
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:280
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:276
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:272
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:268
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:264
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:260
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:256
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:252
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:248
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:244
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:240
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:236
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:232
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:228
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:224
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:220
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:216
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:212
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:208
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:204
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:200
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:196
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:192
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:188
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:184
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:180
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:176
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:172
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:168
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:164
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:160
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:156
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:152
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:148
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:144
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:140
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:136
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:132
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:128
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:124
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:120
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:116
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:112
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:108
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:104
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:100
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:96
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:92
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:88
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v139, s32 offset:84
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v140, s32 offset:80
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v141, s32 offset:76
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v142, s32 offset:72
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v143, s32 offset:68
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v152, s32 offset:64
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v153, s32 offset:60
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v154, s32 offset:56
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v155, s32 offset:52
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v156, s32 offset:48
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v157, s32 offset:44
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v158, s32 offset:40
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v159, s32 offset:36
; GFX11-FAKE16-NEXT: s_clause 0x8
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v168, s32 offset:32
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v169, s32 offset:28
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v170, s32 offset:24
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v171, s32 offset:20
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v172, s32 offset:16
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v173, s32 offset:12
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v174, s32 offset:8
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v175, s32 offset:4
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v184, s32
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v178, v13 :: v_dual_mov_b32 v179, v12
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v180, v11 :: v_dual_mov_b32 v181, v9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v182, v10 :: v_dual_mov_b32 v169, v7
@@ -32001,12 +32298,26 @@ define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_writelane_b32 v63, s34, 0
; SI-NEXT: v_writelane_b32 v63, s35, 1
; SI-NEXT: v_writelane_b32 v63, s30, 2
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_writelane_b32 v63, s31, 3
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_readfirstlane_b32 s47, v1
; SI-NEXT: v_readfirstlane_b32 s46, v2
; SI-NEXT: v_readfirstlane_b32 s45, v3
@@ -32026,21 +32337,6 @@ define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s6, v17
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v18
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB21_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -34731,84 +35027,155 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i
; GFX11-LABEL: bitcast_v64f16_to_v32i32_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40
; GFX11-NEXT: s_clause 0x9
; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v185, s32
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12
; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10
; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8
@@ -35584,8 +35951,9 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: v_writelane_b32 v20, s67, 17
; SI-NEXT: v_writelane_b32 v20, s68, 18
; SI-NEXT: v_writelane_b32 v20, s69, 19
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_writelane_b32 v20, s30, 20
+; SI-NEXT: v_writelane_b32 v20, s31, 21
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_readfirstlane_b32 s44, v1
; SI-NEXT: v_readfirstlane_b32 s45, v2
; SI-NEXT: v_readfirstlane_b32 s42, v3
@@ -35605,7 +35973,6 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v17
; SI-NEXT: s_and_b64 s[46:47], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v18
-; SI-NEXT: v_writelane_b32 v20, s31, 21
; SI-NEXT: s_cbranch_scc0 .LBB25_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s38, s5, 16
@@ -37781,84 +38148,155 @@ define inreg <32 x i32> @bitcast_v64i16_to_v32i32_scalar(<64 x i16> inreg %a, i3
; GFX11-LABEL: bitcast_v64i16_to_v32i32_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40
; GFX11-NEXT: s_clause 0x9
; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v185, s32
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12
; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10
; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8
@@ -43668,24 +44106,43 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x13
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:88
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:84
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:80
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:76
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:72
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:68
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:64
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:60
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:56
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:52
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:48
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:44
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:40
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:36
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:32
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:28
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:24
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:20
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:16
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:12
; GFX11-FAKE16-NEXT: s_clause 0x2
; GFX11-FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
@@ -44359,7 +44816,19 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_writelane_b32 v63, s34, 0
; SI-NEXT: v_writelane_b32 v63, s35, 1
; SI-NEXT: v_writelane_b32 v63, s36, 2
@@ -44395,8 +44864,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; SI-NEXT: v_writelane_b32 v63, s98, 32
; SI-NEXT: v_writelane_b32 v63, s99, 33
; SI-NEXT: v_writelane_b32 v63, s30, 34
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_writelane_b32 v63, s31, 35
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_readfirstlane_b32 s44, v1
; SI-NEXT: v_readfirstlane_b32 s45, v2
; SI-NEXT: v_readfirstlane_b32 s42, v3
@@ -44416,19 +44885,6 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; SI-NEXT: v_readfirstlane_b32 s4, v17
; SI-NEXT: s_and_b64 s[46:47], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v18
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr61 : SGPR spill to VGPR lane
; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB37_3
@@ -46098,6 +46554,20 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_writelane_b32 v63, s34, 0
; VI-NEXT: v_writelane_b32 v63, s35, 1
; VI-NEXT: v_writelane_b32 v63, s36, 2
@@ -46129,8 +46599,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: v_writelane_b32 v63, s86, 28
; VI-NEXT: v_writelane_b32 v63, s87, 29
; VI-NEXT: v_writelane_b32 v63, s30, 30
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; VI-NEXT: v_writelane_b32 v63, s31, 31
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: v_readfirstlane_b32 s45, v2
; VI-NEXT: v_readfirstlane_b32 s42, v3
@@ -46150,20 +46620,6 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: v_readfirstlane_b32 s4, v17
; VI-NEXT: s_and_b64 s[46:47], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v18
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; VI-NEXT: s_cbranch_scc0 .LBB37_3
; VI-NEXT: ; %bb.1: ; %cmp.false
@@ -47369,6 +47825,20 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_writelane_b32 v63, s34, 0
; GFX9-NEXT: v_writelane_b32 v63, s35, 1
; GFX9-NEXT: v_writelane_b32 v63, s36, 2
@@ -47404,8 +47874,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: v_writelane_b32 v63, s98, 32
; GFX9-NEXT: v_writelane_b32 v63, s99, 33
; GFX9-NEXT: v_writelane_b32 v63, s30, 34
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; GFX9-NEXT: v_writelane_b32 v63, s31, 35
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; GFX9-NEXT: v_readfirstlane_b32 s44, v1
; GFX9-NEXT: v_readfirstlane_b32 s45, v2
; GFX9-NEXT: v_readfirstlane_b32 s42, v3
@@ -47425,20 +47895,6 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: v_readfirstlane_b32 s4, v17
; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v18
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; GFX9-NEXT: s_cbranch_scc0 .LBB37_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
@@ -48652,63 +49108,53 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v75, s34, 0
-; GFX11-NEXT: v_writelane_b32 v76, s98, 0
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
-; GFX11-NEXT: v_readfirstlane_b32 s40, v1
-; GFX11-NEXT: v_readfirstlane_b32 s41, v2
-; GFX11-NEXT: v_writelane_b32 v75, s35, 1
-; GFX11-NEXT: v_writelane_b32 v76, s99, 1
-; GFX11-NEXT: v_readfirstlane_b32 s14, v3
-; GFX11-NEXT: v_readfirstlane_b32 s15, v4
-; GFX11-NEXT: v_readfirstlane_b32 s4, v5
-; GFX11-NEXT: v_writelane_b32 v75, s36, 2
-; GFX11-NEXT: v_writelane_b32 v76, s100, 2
-; GFX11-NEXT: v_readfirstlane_b32 s5, v6
-; GFX11-NEXT: v_readfirstlane_b32 s6, v7
-; GFX11-NEXT: v_readfirstlane_b32 s7, v8
-; GFX11-NEXT: v_writelane_b32 v75, s37, 3
-; GFX11-NEXT: v_writelane_b32 v76, s101, 3
-; GFX11-NEXT: v_readfirstlane_b32 s8, v9
-; GFX11-NEXT: v_readfirstlane_b32 s9, v10
-; GFX11-NEXT: v_readfirstlane_b32 s10, v11
-; GFX11-NEXT: v_writelane_b32 v75, s38, 4
-; GFX11-NEXT: v_writelane_b32 v76, s102, 4
-; GFX11-NEXT: v_readfirstlane_b32 s11, v12
-; GFX11-NEXT: v_readfirstlane_b32 s12, v13
-; GFX11-NEXT: v_readfirstlane_b32 s13, v14
-; GFX11-NEXT: v_writelane_b32 v75, s39, 5
-; GFX11-NEXT: v_writelane_b32 v76, s103, 5
-; GFX11-NEXT: s_mov_b32 vcc_hi, 0
-; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
; GFX11-NEXT: s_clause 0x12
; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:72
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:68
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:64
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:60
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:56
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:52
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:48
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:44
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:40
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:36
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:32
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:28
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:24
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:20
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:16
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v74, s32
+; GFX11-NEXT: v_writelane_b32 v75, s34, 0
+; GFX11-NEXT: v_writelane_b32 v75, s35, 1
+; GFX11-NEXT: v_writelane_b32 v75, s36, 2
+; GFX11-NEXT: v_writelane_b32 v75, s37, 3
+; GFX11-NEXT: v_writelane_b32 v75, s38, 4
+; GFX11-NEXT: v_writelane_b32 v75, s39, 5
; GFX11-NEXT: v_writelane_b32 v75, s48, 6
-; GFX11-NEXT: v_writelane_b32 v76, s104, 6
-; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane
-; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane
; GFX11-NEXT: v_writelane_b32 v75, s49, 7
-; GFX11-NEXT: v_writelane_b32 v76, s30, 7
; GFX11-NEXT: v_writelane_b32 v75, s50, 8
-; GFX11-NEXT: v_writelane_b32 v76, s31, 8
; GFX11-NEXT: v_writelane_b32 v75, s51, 9
; GFX11-NEXT: v_writelane_b32 v75, s52, 10
; GFX11-NEXT: v_writelane_b32 v75, s53, 11
@@ -48732,6 +49178,34 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX11-NEXT: v_writelane_b32 v75, s87, 29
; GFX11-NEXT: v_writelane_b32 v75, s96, 30
; GFX11-NEXT: v_writelane_b32 v75, s97, 31
+; GFX11-NEXT: v_writelane_b32 v76, s98, 0
+; GFX11-NEXT: v_writelane_b32 v76, s99, 1
+; GFX11-NEXT: v_writelane_b32 v76, s100, 2
+; GFX11-NEXT: v_writelane_b32 v76, s101, 3
+; GFX11-NEXT: v_writelane_b32 v76, s102, 4
+; GFX11-NEXT: v_writelane_b32 v76, s103, 5
+; GFX11-NEXT: v_writelane_b32 v76, s104, 6
+; GFX11-NEXT: v_writelane_b32 v76, s30, 7
+; GFX11-NEXT: v_writelane_b32 v76, s31, 8
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
+; GFX11-NEXT: v_readfirstlane_b32 s40, v1
+; GFX11-NEXT: v_readfirstlane_b32 s41, v2
+; GFX11-NEXT: v_readfirstlane_b32 s14, v3
+; GFX11-NEXT: v_readfirstlane_b32 s15, v4
+; GFX11-NEXT: v_readfirstlane_b32 s4, v5
+; GFX11-NEXT: v_readfirstlane_b32 s5, v6
+; GFX11-NEXT: v_readfirstlane_b32 s6, v7
+; GFX11-NEXT: v_readfirstlane_b32 s7, v8
+; GFX11-NEXT: v_readfirstlane_b32 s8, v9
+; GFX11-NEXT: v_readfirstlane_b32 s9, v10
+; GFX11-NEXT: v_readfirstlane_b32 s10, v11
+; GFX11-NEXT: v_readfirstlane_b32 s11, v12
+; GFX11-NEXT: v_readfirstlane_b32 s12, v13
+; GFX11-NEXT: v_readfirstlane_b32 s13, v14
+; GFX11-NEXT: s_mov_b32 vcc_hi, 0
+; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
+; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane
+; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane
; GFX11-NEXT: s_cbranch_scc0 .LBB37_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s13, 24
@@ -54428,56 +54902,105 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:592
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:588
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:584
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:580
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:576
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:572
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:568
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:564
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:560
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:556
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:552
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:548
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:544
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:540
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:536
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:532
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:528
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:524
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:520
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:516
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:512
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:508
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:504
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:500
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:496
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:492
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:488
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:484
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:480
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:476
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:472
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:468
; GFX11-FAKE16-NEXT: s_clause 0x12
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:464
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:460
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:456
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:452
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:448
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:444
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:440
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:436
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:432
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:428
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:424
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:420
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:416
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:412
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:408
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:404
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:400
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:396
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:392
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
@@ -58749,45 +59272,83 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:476
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:472
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:468
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:464
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:460
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:456
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:452
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:448
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:444
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:440
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:436
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:432
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:428
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:424
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:420
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:416
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:412
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:408
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:404
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:400
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:396
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:392
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:388
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:384
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:380
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:376
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:372
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:368
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:364
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:360
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:356
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:352
; GFX11-TRUE16-NEXT: s_clause 0x7
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:348
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:344
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:340
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:336
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:332
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:328
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:324
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:320
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
@@ -59690,45 +60251,83 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:476
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:472
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:468
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:464
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:460
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:456
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:452
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:448
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:444
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:440
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:436
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:432
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:428
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:424
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:420
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:416
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:412
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:408
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:404
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:400
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:396
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:392
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:388
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:384
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:380
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:376
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:372
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:368
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:364
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:360
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:356
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:352
; GFX11-FAKE16-NEXT: s_clause 0x7
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:348
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:344
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:340
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:336
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:332
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:328
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:324
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:320
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
@@ -61535,7 +62134,20 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_writelane_b32 v63, s34, 0
; SI-NEXT: v_writelane_b32 v63, s35, 1
; SI-NEXT: v_writelane_b32 v63, s36, 2
@@ -61571,8 +62183,8 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg
; SI-NEXT: v_writelane_b32 v63, s98, 32
; SI-NEXT: v_writelane_b32 v63, s99, 33
; SI-NEXT: v_writelane_b32 v63, s30, 34
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_writelane_b32 v63, s31, 35
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_readfirstlane_b32 s6, v1
; SI-NEXT: v_readfirstlane_b32 s7, v2
; SI-NEXT: v_readfirstlane_b32 s8, v3
@@ -61592,20 +62204,6 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg
; SI-NEXT: v_readfirstlane_b32 s46, v17
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s47, v18
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB41_3
; SI-NEXT: ; %bb.1: ; %cmp.false
@@ -64241,20 +64839,35 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
@@ -67290,81 +67903,149 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v32f32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:156
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:28
; GFX11-TRUE16-NEXT: s_clause 0x6
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v167, v13 :: v_dual_mov_b32 v176, v12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v177, v11 :: v_dual_mov_b32 v178, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v179, v9 :: v_dual_mov_b32 v180, v8
@@ -68264,83 +68945,153 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg
; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v32f32_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:288
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:284
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:280
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:276
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:272
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:268
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:264
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:260
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:256
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:252
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:248
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:244
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:240
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:236
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:232
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:228
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:224
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:220
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:216
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:212
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:208
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:204
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:200
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:196
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:192
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:188
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:184
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:180
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:176
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:172
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:168
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:164
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:160
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:156
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:152
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:148
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:144
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:140
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:136
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:132
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:128
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:124
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:120
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:116
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:112
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:108
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:104
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:100
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:96
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:92
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:88
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v139, s32 offset:84
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v140, s32 offset:80
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v141, s32 offset:76
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v142, s32 offset:72
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v143, s32 offset:68
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v152, s32 offset:64
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v153, s32 offset:60
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v154, s32 offset:56
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v155, s32 offset:52
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v156, s32 offset:48
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v157, s32 offset:44
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v158, s32 offset:40
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v159, s32 offset:36
; GFX11-FAKE16-NEXT: s_clause 0x8
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v168, s32 offset:32
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v169, s32 offset:28
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v170, s32 offset:24
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v171, s32 offset:20
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v172, s32 offset:16
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v173, s32 offset:12
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v174, s32 offset:8
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v175, s32 offset:4
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v184, s32
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v178, v13 :: v_dual_mov_b32 v179, v12
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v180, v11 :: v_dual_mov_b32 v181, v9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v182, v10 :: v_dual_mov_b32 v169, v7
@@ -70092,6 +70843,22 @@ define inreg <64 x half> @bitcast_v32f32_to_v64f16_scalar(<32 x float> inreg %a,
; SI-LABEL: bitcast_v32f32_to_v64f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_readfirstlane_b32 s47, v1
; SI-NEXT: v_readfirstlane_b32 s46, v2
@@ -70112,22 +70879,6 @@ define inreg <64 x half> @bitcast_v32f32_to_v64f16_scalar(<32 x float> inreg %a,
; SI-NEXT: v_readfirstlane_b32 s6, v17
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v18
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB45_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -72812,84 +73563,155 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a,
; GFX11-LABEL: bitcast_v64f16_to_v32f32_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40
; GFX11-NEXT: s_clause 0x9
; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v185, s32
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12
; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10
; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8
@@ -73625,22 +74447,6 @@ define inreg <64 x i16> @bitcast_v32f32_to_v64i16_scalar(<32 x float> inreg %a,
; SI-LABEL: bitcast_v32f32_to_v64i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_mov_b32_e32 v31, s16
-; SI-NEXT: v_mov_b32_e32 v32, s17
-; SI-NEXT: v_mov_b32_e32 v29, s18
-; SI-NEXT: v_mov_b32_e32 v30, s19
-; SI-NEXT: v_mov_b32_e32 v27, s20
-; SI-NEXT: v_mov_b32_e32 v28, s21
-; SI-NEXT: v_mov_b32_e32 v25, s22
-; SI-NEXT: v_mov_b32_e32 v26, s23
-; SI-NEXT: v_mov_b32_e32 v23, s24
-; SI-NEXT: v_mov_b32_e32 v24, s25
-; SI-NEXT: v_mov_b32_e32 v21, s26
-; SI-NEXT: v_mov_b32_e32 v22, s27
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mov_b32_e32 v19, s28
-; SI-NEXT: v_mov_b32_e32 v20, s29
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -73657,6 +74463,22 @@ define inreg <64 x i16> @bitcast_v32f32_to_v64i16_scalar(<32 x float> inreg %a,
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
+; SI-NEXT: v_mov_b32_e32 v31, s16
+; SI-NEXT: v_mov_b32_e32 v32, s17
+; SI-NEXT: v_mov_b32_e32 v29, s18
+; SI-NEXT: v_mov_b32_e32 v30, s19
+; SI-NEXT: v_mov_b32_e32 v27, s20
+; SI-NEXT: v_mov_b32_e32 v28, s21
+; SI-NEXT: v_mov_b32_e32 v25, s22
+; SI-NEXT: v_mov_b32_e32 v26, s23
+; SI-NEXT: v_mov_b32_e32 v23, s24
+; SI-NEXT: v_mov_b32_e32 v24, s25
+; SI-NEXT: v_mov_b32_e32 v21, s26
+; SI-NEXT: v_mov_b32_e32 v22, s27
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_mov_b32_e32 v19, s28
+; SI-NEXT: v_mov_b32_e32 v20, s29
; SI-NEXT: s_cbranch_scc0 .LBB49_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_lshr_b64 v[36:37], v[17:18], 16
@@ -75816,84 +76638,155 @@ define inreg <32 x float> @bitcast_v64i16_to_v32f32_scalar(<64 x i16> inreg %a,
; GFX11-LABEL: bitcast_v64i16_to_v32f32_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40
; GFX11-NEXT: s_clause 0x9
; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v185, s32
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12
; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10
; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8
@@ -80714,24 +81607,43 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x13
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:88
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:84
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:80
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:76
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:72
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:68
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:64
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:60
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:56
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:52
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:48
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:44
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:40
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:36
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:32
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:28
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:24
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:20
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:16
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:12
; GFX11-FAKE16-NEXT: s_clause 0x2
; GFX11-FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
@@ -81465,8 +82377,9 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: v_writelane_b32 v20, s97, 31
; SI-NEXT: v_writelane_b32 v20, s98, 32
; SI-NEXT: v_writelane_b32 v20, s99, 33
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_writelane_b32 v20, s30, 34
+; SI-NEXT: v_writelane_b32 v20, s31, 35
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_readfirstlane_b32 s44, v1
; SI-NEXT: v_readfirstlane_b32 s45, v2
; SI-NEXT: v_readfirstlane_b32 s42, v3
@@ -81486,7 +82399,6 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v17
; SI-NEXT: s_and_b64 s[46:47], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v18
-; SI-NEXT: v_writelane_b32 v20, s31, 35
; SI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB57_4
@@ -82625,8 +83537,9 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_writelane_b32 v20, s85, 27
; VI-NEXT: v_writelane_b32 v20, s86, 28
; VI-NEXT: v_writelane_b32 v20, s87, 29
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; VI-NEXT: v_writelane_b32 v20, s30, 30
+; VI-NEXT: v_writelane_b32 v20, s31, 31
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: v_readfirstlane_b32 s45, v2
; VI-NEXT: v_readfirstlane_b32 s42, v3
@@ -82646,7 +83559,6 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s4, v17
; VI-NEXT: s_and_b64 s[46:47], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v18
-; VI-NEXT: v_writelane_b32 v20, s31, 31
; VI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; VI-NEXT: s_cbranch_scc0 .LBB57_4
; VI-NEXT: ; %bb.1: ; %cmp.false
@@ -83678,8 +84590,9 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_writelane_b32 v20, s97, 31
; GFX9-NEXT: v_writelane_b32 v20, s98, 32
; GFX9-NEXT: v_writelane_b32 v20, s99, 33
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; GFX9-NEXT: v_writelane_b32 v20, s30, 34
+; GFX9-NEXT: v_writelane_b32 v20, s31, 35
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; GFX9-NEXT: v_readfirstlane_b32 s44, v1
; GFX9-NEXT: v_readfirstlane_b32 s45, v2
; GFX9-NEXT: v_readfirstlane_b32 s42, v3
@@ -83699,7 +84612,6 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s4, v17
; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v18
-; GFX9-NEXT: v_writelane_b32 v20, s31, 35
; GFX9-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; GFX9-NEXT: s_cbranch_scc0 .LBB57_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
@@ -84638,42 +85550,14 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: scratch_store_b32 off, v19, s32 offset:12
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v16, s34, 0
-; GFX11-NEXT: v_writelane_b32 v17, s98, 0
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
-; GFX11-NEXT: v_readfirstlane_b32 s40, v1
-; GFX11-NEXT: v_readfirstlane_b32 s41, v2
; GFX11-NEXT: v_writelane_b32 v16, s35, 1
-; GFX11-NEXT: v_writelane_b32 v17, s99, 1
-; GFX11-NEXT: v_readfirstlane_b32 s14, v3
-; GFX11-NEXT: v_readfirstlane_b32 s15, v4
-; GFX11-NEXT: v_readfirstlane_b32 s12, v5
; GFX11-NEXT: v_writelane_b32 v16, s36, 2
-; GFX11-NEXT: v_writelane_b32 v17, s100, 2
-; GFX11-NEXT: v_readfirstlane_b32 s13, v6
-; GFX11-NEXT: v_readfirstlane_b32 s10, v7
-; GFX11-NEXT: v_readfirstlane_b32 s11, v8
; GFX11-NEXT: v_writelane_b32 v16, s37, 3
-; GFX11-NEXT: v_writelane_b32 v17, s101, 3
-; GFX11-NEXT: v_readfirstlane_b32 s8, v9
-; GFX11-NEXT: v_readfirstlane_b32 s9, v10
-; GFX11-NEXT: v_readfirstlane_b32 s6, v11
; GFX11-NEXT: v_writelane_b32 v16, s38, 4
-; GFX11-NEXT: v_writelane_b32 v17, s102, 4
-; GFX11-NEXT: v_readfirstlane_b32 s7, v12
-; GFX11-NEXT: v_readfirstlane_b32 s4, v13
-; GFX11-NEXT: v_readfirstlane_b32 s5, v14
; GFX11-NEXT: v_writelane_b32 v16, s39, 5
-; GFX11-NEXT: v_writelane_b32 v17, s103, 5
-; GFX11-NEXT: s_mov_b32 s101, 0
-; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
-; GFX11-NEXT: ; implicit-def: $vgpr19 : SGPR spill to VGPR lane
-; GFX11-NEXT: ; implicit-def: $vgpr18 : SGPR spill to VGPR lane
; GFX11-NEXT: v_writelane_b32 v16, s48, 6
-; GFX11-NEXT: v_writelane_b32 v17, s104, 6
; GFX11-NEXT: v_writelane_b32 v16, s49, 7
-; GFX11-NEXT: v_writelane_b32 v17, s30, 7
; GFX11-NEXT: v_writelane_b32 v16, s50, 8
-; GFX11-NEXT: v_writelane_b32 v17, s31, 8
; GFX11-NEXT: v_writelane_b32 v16, s51, 9
; GFX11-NEXT: v_writelane_b32 v16, s52, 10
; GFX11-NEXT: v_writelane_b32 v16, s53, 11
@@ -84697,6 +85581,34 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: v_writelane_b32 v16, s87, 29
; GFX11-NEXT: v_writelane_b32 v16, s96, 30
; GFX11-NEXT: v_writelane_b32 v16, s97, 31
+; GFX11-NEXT: v_writelane_b32 v17, s98, 0
+; GFX11-NEXT: v_writelane_b32 v17, s99, 1
+; GFX11-NEXT: v_writelane_b32 v17, s100, 2
+; GFX11-NEXT: v_writelane_b32 v17, s101, 3
+; GFX11-NEXT: v_writelane_b32 v17, s102, 4
+; GFX11-NEXT: v_writelane_b32 v17, s103, 5
+; GFX11-NEXT: v_writelane_b32 v17, s104, 6
+; GFX11-NEXT: v_writelane_b32 v17, s30, 7
+; GFX11-NEXT: v_writelane_b32 v17, s31, 8
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
+; GFX11-NEXT: v_readfirstlane_b32 s40, v1
+; GFX11-NEXT: v_readfirstlane_b32 s41, v2
+; GFX11-NEXT: v_readfirstlane_b32 s14, v3
+; GFX11-NEXT: v_readfirstlane_b32 s15, v4
+; GFX11-NEXT: v_readfirstlane_b32 s12, v5
+; GFX11-NEXT: v_readfirstlane_b32 s13, v6
+; GFX11-NEXT: v_readfirstlane_b32 s10, v7
+; GFX11-NEXT: v_readfirstlane_b32 s11, v8
+; GFX11-NEXT: v_readfirstlane_b32 s8, v9
+; GFX11-NEXT: v_readfirstlane_b32 s9, v10
+; GFX11-NEXT: v_readfirstlane_b32 s6, v11
+; GFX11-NEXT: v_readfirstlane_b32 s7, v12
+; GFX11-NEXT: v_readfirstlane_b32 s4, v13
+; GFX11-NEXT: v_readfirstlane_b32 s5, v14
+; GFX11-NEXT: s_mov_b32 s101, 0
+; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
+; GFX11-NEXT: ; implicit-def: $vgpr19 : SGPR spill to VGPR lane
+; GFX11-NEXT: ; implicit-def: $vgpr18 : SGPR spill to VGPR lane
; GFX11-NEXT: s_cbranch_scc0 .LBB57_2
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s43, s25, 8
@@ -90331,56 +91243,105 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:592
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:588
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:584
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:580
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:576
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:572
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:568
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:564
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:560
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:556
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:552
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:548
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:544
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:540
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:536
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:532
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:528
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:524
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:520
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:516
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:512
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:508
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:504
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:500
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:496
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:492
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:488
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:484
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:480
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:476
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:472
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:468
; GFX11-FAKE16-NEXT: s_clause 0x12
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:464
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:460
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:456
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:452
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:448
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:444
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:440
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:436
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:432
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:428
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:424
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:420
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:416
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:412
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:408
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:404
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:400
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:396
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:392
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
@@ -94652,45 +95613,83 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:476
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:472
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:468
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:464
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:460
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:456
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:452
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:448
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:444
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:440
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:436
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:432
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:428
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:424
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:420
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:416
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:412
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:408
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:404
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:400
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:396
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:392
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:388
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:384
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:380
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:376
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:372
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:368
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:364
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:360
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:356
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:352
; GFX11-TRUE16-NEXT: s_clause 0x7
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:348
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:344
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:340
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:336
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:332
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:328
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:324
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:320
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
@@ -95593,45 +96592,83 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:476
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:472
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:468
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:464
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:460
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:456
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:452
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:448
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:444
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:440
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:436
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:432
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:428
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:424
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:420
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:416
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:412
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:408
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:404
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:400
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:396
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:392
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:388
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:384
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:380
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:376
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:372
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:368
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:364
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:360
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:356
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:352
; GFX11-FAKE16-NEXT: s_clause 0x7
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:348
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:344
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:340
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:336
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:332
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:328
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:324
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:320
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
@@ -97498,8 +98535,9 @@ define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a
; SI-NEXT: v_writelane_b32 v20, s97, 31
; SI-NEXT: v_writelane_b32 v20, s98, 32
; SI-NEXT: v_writelane_b32 v20, s99, 33
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_writelane_b32 v20, s30, 34
+; SI-NEXT: v_writelane_b32 v20, s31, 35
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_readfirstlane_b32 s70, v1
; SI-NEXT: v_readfirstlane_b32 s71, v2
; SI-NEXT: v_readfirstlane_b32 s80, v3
@@ -97519,7 +98557,6 @@ define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a
; SI-NEXT: v_readfirstlane_b32 s8, v17
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v18
-; SI-NEXT: v_writelane_b32 v20, s31, 35
; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB61_4
; SI-NEXT: ; %bb.1: ; %cmp.false
@@ -100086,20 +101123,35 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
@@ -103135,81 +104187,149 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v16i64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:156
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:28
; GFX11-TRUE16-NEXT: s_clause 0x6
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v167, v13 :: v_dual_mov_b32 v176, v12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v177, v11 :: v_dual_mov_b32 v178, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v179, v9 :: v_dual_mov_b32 v180, v8
@@ -104109,83 +105229,153 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v16i64_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:288
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:284
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:280
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:276
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:272
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:268
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:264
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:260
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:256
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:252
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:248
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:244
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:240
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:236
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:232
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:228
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:224
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:220
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:216
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:212
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:208
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:204
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:200
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:196
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:192
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:188
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:184
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:180
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:176
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:172
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:168
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:164
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:160
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:156
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:152
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:148
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:144
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:140
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:136
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:132
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:128
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:124
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:120
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:116
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:112
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:108
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:104
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:100
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:96
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:92
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:88
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v139, s32 offset:84
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v140, s32 offset:80
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v141, s32 offset:76
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v142, s32 offset:72
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v143, s32 offset:68
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v152, s32 offset:64
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v153, s32 offset:60
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v154, s32 offset:56
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v155, s32 offset:52
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v156, s32 offset:48
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v157, s32 offset:44
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v158, s32 offset:40
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v159, s32 offset:36
; GFX11-FAKE16-NEXT: s_clause 0x8
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v168, s32 offset:32
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v169, s32 offset:28
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v170, s32 offset:24
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v171, s32 offset:20
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v172, s32 offset:16
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v173, s32 offset:12
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v174, s32 offset:8
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v175, s32 offset:4
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v184, s32
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v178, v13 :: v_dual_mov_b32 v179, v12
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v180, v11 :: v_dual_mov_b32 v181, v9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v182, v10 :: v_dual_mov_b32 v169, v7
@@ -105961,12 +107151,26 @@ define inreg <64 x half> @bitcast_v16i64_to_v64f16_scalar(<16 x i64> inreg %a, i
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_writelane_b32 v63, s34, 0
; SI-NEXT: v_writelane_b32 v63, s35, 1
; SI-NEXT: v_writelane_b32 v63, s30, 2
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_writelane_b32 v63, s31, 3
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_readfirstlane_b32 s46, v1
; SI-NEXT: v_readfirstlane_b32 s47, v2
; SI-NEXT: v_readfirstlane_b32 s44, v3
@@ -105986,21 +107190,6 @@ define inreg <64 x half> @bitcast_v16i64_to_v64f16_scalar(<16 x i64> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s6, v17
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v18
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB65_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -108699,84 +109888,155 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i
; GFX11-LABEL: bitcast_v64f16_to_v16i64_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40
; GFX11-NEXT: s_clause 0x9
; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v185, s32
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12
; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10
; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8
@@ -109558,8 +110818,9 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: v_writelane_b32 v20, s67, 17
; SI-NEXT: v_writelane_b32 v20, s68, 18
; SI-NEXT: v_writelane_b32 v20, s69, 19
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_writelane_b32 v20, s30, 20
+; SI-NEXT: v_writelane_b32 v20, s31, 21
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_readfirstlane_b32 s44, v1
; SI-NEXT: v_readfirstlane_b32 s45, v2
; SI-NEXT: v_readfirstlane_b32 s42, v3
@@ -109579,7 +110840,6 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v17
; SI-NEXT: s_and_b64 s[46:47], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v18
-; SI-NEXT: v_writelane_b32 v20, s31, 21
; SI-NEXT: s_cbranch_scc0 .LBB69_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s38, s5, 16
@@ -111763,84 +113023,155 @@ define inreg <16 x i64> @bitcast_v64i16_to_v16i64_scalar(<64 x i16> inreg %a, i3
; GFX11-LABEL: bitcast_v64i16_to_v16i64_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40
; GFX11-NEXT: s_clause 0x9
; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v185, s32
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12
; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10
; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8
@@ -115630,24 +116961,43 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x13
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:88
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:84
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:80
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:76
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:72
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:68
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:64
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:60
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:56
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:52
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:48
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:44
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:40
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:36
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:32
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:28
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:24
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:20
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:16
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:12
; GFX11-FAKE16-NEXT: s_clause 0x2
; GFX11-FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
@@ -116321,7 +117671,19 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_writelane_b32 v63, s34, 0
; SI-NEXT: v_writelane_b32 v63, s35, 1
; SI-NEXT: v_writelane_b32 v63, s36, 2
@@ -116357,8 +117719,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; SI-NEXT: v_writelane_b32 v63, s98, 32
; SI-NEXT: v_writelane_b32 v63, s99, 33
; SI-NEXT: v_writelane_b32 v63, s30, 34
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_writelane_b32 v63, s31, 35
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_readfirstlane_b32 s4, v1
; SI-NEXT: v_readfirstlane_b32 s5, v2
; SI-NEXT: v_readfirstlane_b32 s6, v3
@@ -116378,19 +117740,6 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; SI-NEXT: v_readfirstlane_b32 s44, v17
; SI-NEXT: s_and_b64 s[46:47], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s45, v18
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr61 : SGPR spill to VGPR lane
; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB73_3
@@ -118039,6 +119388,20 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_writelane_b32 v63, s34, 0
; VI-NEXT: v_writelane_b32 v63, s35, 1
; VI-NEXT: v_writelane_b32 v63, s36, 2
@@ -118070,8 +119433,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: v_writelane_b32 v63, s86, 28
; VI-NEXT: v_writelane_b32 v63, s87, 29
; VI-NEXT: v_writelane_b32 v63, s30, 30
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; VI-NEXT: v_writelane_b32 v63, s31, 31
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; VI-NEXT: v_readfirstlane_b32 s6, v1
; VI-NEXT: v_readfirstlane_b32 s7, v2
; VI-NEXT: v_readfirstlane_b32 s8, v3
@@ -118091,20 +119454,6 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: v_readfirstlane_b32 s4, v17
; VI-NEXT: s_and_b64 s[46:47], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v18
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; VI-NEXT: s_cbranch_scc0 .LBB73_3
; VI-NEXT: ; %bb.1: ; %cmp.false
@@ -119323,6 +120672,20 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_writelane_b32 v63, s34, 0
; GFX9-NEXT: v_writelane_b32 v63, s35, 1
; GFX9-NEXT: v_writelane_b32 v63, s36, 2
@@ -119358,8 +120721,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: v_writelane_b32 v63, s98, 32
; GFX9-NEXT: v_writelane_b32 v63, s99, 33
; GFX9-NEXT: v_writelane_b32 v63, s30, 34
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; GFX9-NEXT: v_writelane_b32 v63, s31, 35
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; GFX9-NEXT: v_readfirstlane_b32 s6, v1
; GFX9-NEXT: v_readfirstlane_b32 s7, v2
; GFX9-NEXT: v_readfirstlane_b32 s8, v3
@@ -119379,20 +120742,6 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: v_readfirstlane_b32 s4, v17
; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v18
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; GFX9-NEXT: s_cbranch_scc0 .LBB73_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
@@ -120605,64 +121954,55 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88
; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:92
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v76, s34, 0
-; GFX11-NEXT: v_writelane_b32 v77, s98, 0
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
-; GFX11-NEXT: v_readfirstlane_b32 s4, v1
-; GFX11-NEXT: v_readfirstlane_b32 s5, v2
-; GFX11-NEXT: v_writelane_b32 v76, s35, 1
-; GFX11-NEXT: v_writelane_b32 v77, s99, 1
-; GFX11-NEXT: v_readfirstlane_b32 s6, v3
-; GFX11-NEXT: v_readfirstlane_b32 s7, v4
-; GFX11-NEXT: v_readfirstlane_b32 s8, v5
-; GFX11-NEXT: v_writelane_b32 v76, s36, 2
-; GFX11-NEXT: v_writelane_b32 v77, s100, 2
-; GFX11-NEXT: v_readfirstlane_b32 s9, v6
-; GFX11-NEXT: v_readfirstlane_b32 s10, v7
-; GFX11-NEXT: v_readfirstlane_b32 s11, v8
-; GFX11-NEXT: v_writelane_b32 v76, s37, 3
-; GFX11-NEXT: v_writelane_b32 v77, s101, 3
-; GFX11-NEXT: v_readfirstlane_b32 s12, v9
-; GFX11-NEXT: v_readfirstlane_b32 s13, v10
-; GFX11-NEXT: v_readfirstlane_b32 s14, v11
-; GFX11-NEXT: v_writelane_b32 v76, s38, 4
-; GFX11-NEXT: v_writelane_b32 v77, s102, 4
-; GFX11-NEXT: v_readfirstlane_b32 s15, v12
-; GFX11-NEXT: v_readfirstlane_b32 s40, v13
-; GFX11-NEXT: v_readfirstlane_b32 s41, v14
-; GFX11-NEXT: v_writelane_b32 v76, s39, 5
-; GFX11-NEXT: v_writelane_b32 v77, s103, 5
-; GFX11-NEXT: s_mov_b32 vcc_hi, 0
-; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
; GFX11-NEXT: s_clause 0x13
; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:76
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:72
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:68
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:64
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:60
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:56
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:52
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:48
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:44
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:40
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:36
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:32
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:28
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:24
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:20
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:16
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v75, s32
+; GFX11-NEXT: v_writelane_b32 v76, s34, 0
+; GFX11-NEXT: v_writelane_b32 v76, s35, 1
+; GFX11-NEXT: v_writelane_b32 v76, s36, 2
+; GFX11-NEXT: v_writelane_b32 v76, s37, 3
+; GFX11-NEXT: v_writelane_b32 v76, s38, 4
+; GFX11-NEXT: v_writelane_b32 v76, s39, 5
; GFX11-NEXT: v_writelane_b32 v76, s48, 6
-; GFX11-NEXT: v_writelane_b32 v77, s104, 6
-; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane
-; GFX11-NEXT: ; implicit-def: $vgpr79 : SGPR spill to VGPR lane
; GFX11-NEXT: v_writelane_b32 v76, s49, 7
-; GFX11-NEXT: v_writelane_b32 v77, s30, 7
; GFX11-NEXT: v_writelane_b32 v76, s50, 8
-; GFX11-NEXT: v_writelane_b32 v77, s31, 8
; GFX11-NEXT: v_writelane_b32 v76, s51, 9
; GFX11-NEXT: v_writelane_b32 v76, s52, 10
; GFX11-NEXT: v_writelane_b32 v76, s53, 11
@@ -120686,6 +122026,34 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX11-NEXT: v_writelane_b32 v76, s87, 29
; GFX11-NEXT: v_writelane_b32 v76, s96, 30
; GFX11-NEXT: v_writelane_b32 v76, s97, 31
+; GFX11-NEXT: v_writelane_b32 v77, s98, 0
+; GFX11-NEXT: v_writelane_b32 v77, s99, 1
+; GFX11-NEXT: v_writelane_b32 v77, s100, 2
+; GFX11-NEXT: v_writelane_b32 v77, s101, 3
+; GFX11-NEXT: v_writelane_b32 v77, s102, 4
+; GFX11-NEXT: v_writelane_b32 v77, s103, 5
+; GFX11-NEXT: v_writelane_b32 v77, s104, 6
+; GFX11-NEXT: v_writelane_b32 v77, s30, 7
+; GFX11-NEXT: v_writelane_b32 v77, s31, 8
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
+; GFX11-NEXT: v_readfirstlane_b32 s4, v1
+; GFX11-NEXT: v_readfirstlane_b32 s5, v2
+; GFX11-NEXT: v_readfirstlane_b32 s6, v3
+; GFX11-NEXT: v_readfirstlane_b32 s7, v4
+; GFX11-NEXT: v_readfirstlane_b32 s8, v5
+; GFX11-NEXT: v_readfirstlane_b32 s9, v6
+; GFX11-NEXT: v_readfirstlane_b32 s10, v7
+; GFX11-NEXT: v_readfirstlane_b32 s11, v8
+; GFX11-NEXT: v_readfirstlane_b32 s12, v9
+; GFX11-NEXT: v_readfirstlane_b32 s13, v10
+; GFX11-NEXT: v_readfirstlane_b32 s14, v11
+; GFX11-NEXT: v_readfirstlane_b32 s15, v12
+; GFX11-NEXT: v_readfirstlane_b32 s40, v13
+; GFX11-NEXT: v_readfirstlane_b32 s41, v14
+; GFX11-NEXT: s_mov_b32 vcc_hi, 0
+; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
+; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane
+; GFX11-NEXT: ; implicit-def: $vgpr79 : SGPR spill to VGPR lane
; GFX11-NEXT: s_cbranch_scc0 .LBB73_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s13, 16
@@ -126370,56 +127738,105 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:592
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:588
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:584
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:580
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:576
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:572
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:568
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:564
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:560
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:556
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:552
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:548
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:544
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:540
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:536
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:532
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:528
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:524
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:520
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:516
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:512
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:508
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:504
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:500
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:496
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:492
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:488
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:484
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:480
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:476
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:472
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:468
; GFX11-FAKE16-NEXT: s_clause 0x12
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:464
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:460
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:456
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:452
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:448
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:444
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:440
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:436
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:432
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:428
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:424
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:420
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:416
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:412
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:408
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:404
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:400
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:396
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:392
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
@@ -130691,45 +132108,83 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:476
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:472
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:468
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:464
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:460
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:456
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:452
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:448
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:444
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:440
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:436
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:432
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:428
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:424
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:420
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:416
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:412
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:408
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:404
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:400
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:396
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:392
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:388
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:384
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:380
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:376
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:372
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:368
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:364
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:360
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:356
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:352
; GFX11-TRUE16-NEXT: s_clause 0x7
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:348
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:344
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:340
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:336
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:332
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:328
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:324
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:320
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
@@ -131632,45 +133087,83 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:476
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:472
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:468
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:464
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:460
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:456
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:452
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:448
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:444
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:440
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:436
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:432
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:428
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:424
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:420
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:416
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:412
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:408
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:404
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:400
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:396
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:392
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:388
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:384
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:380
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:376
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:372
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:368
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:364
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:360
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:356
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:352
; GFX11-FAKE16-NEXT: s_clause 0x7
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:348
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:344
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:340
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:336
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:332
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:328
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:324
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:320
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v28
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v26 :: v_dual_mov_b32 v35, v24
@@ -133410,7 +134903,20 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_writelane_b32 v63, s34, 0
; SI-NEXT: v_writelane_b32 v63, s35, 1
; SI-NEXT: v_writelane_b32 v63, s36, 2
@@ -133446,8 +134952,8 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg
; SI-NEXT: v_writelane_b32 v63, s98, 32
; SI-NEXT: v_writelane_b32 v63, s99, 33
; SI-NEXT: v_writelane_b32 v63, s30, 34
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_writelane_b32 v63, s31, 35
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_readfirstlane_b32 s44, v1
; SI-NEXT: v_readfirstlane_b32 s45, v2
; SI-NEXT: v_readfirstlane_b32 s42, v3
@@ -133467,20 +134973,6 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg
; SI-NEXT: v_readfirstlane_b32 s6, v17
; SI-NEXT: s_and_b64 s[46:47], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s7, v18
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB77_3
; SI-NEXT: ; %bb.1: ; %cmp.false
@@ -136073,20 +137565,35 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
@@ -139122,81 +140629,149 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v16f64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:156
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:28
; GFX11-TRUE16-NEXT: s_clause 0x6
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v167, v13 :: v_dual_mov_b32 v176, v12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v177, v11 :: v_dual_mov_b32 v178, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v179, v9 :: v_dual_mov_b32 v180, v8
@@ -140096,83 +141671,153 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg
; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v16f64_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:288
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:284
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:280
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:276
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:272
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:268
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:264
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:260
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:256
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:252
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:248
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:244
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:240
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:236
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:232
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:228
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:224
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:220
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:216
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:212
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:208
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:204
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:200
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:196
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:192
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:188
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:184
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:180
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:176
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:172
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:168
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:164
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:160
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:156
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:152
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:148
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:144
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:140
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:136
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:132
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:128
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:124
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:120
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:116
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:112
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:108
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:104
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:100
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:96
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:92
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:88
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v139, s32 offset:84
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v140, s32 offset:80
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v141, s32 offset:76
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v142, s32 offset:72
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v143, s32 offset:68
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v152, s32 offset:64
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v153, s32 offset:60
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v154, s32 offset:56
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v155, s32 offset:52
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v156, s32 offset:48
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v157, s32 offset:44
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v158, s32 offset:40
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v159, s32 offset:36
; GFX11-FAKE16-NEXT: s_clause 0x8
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v168, s32 offset:32
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v169, s32 offset:28
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v170, s32 offset:24
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v171, s32 offset:20
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v172, s32 offset:16
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v173, s32 offset:12
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v174, s32 offset:8
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v175, s32 offset:4
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v184, s32
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v178, v13 :: v_dual_mov_b32 v179, v12
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v180, v11 :: v_dual_mov_b32 v181, v9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v182, v10 :: v_dual_mov_b32 v169, v7
@@ -141855,6 +143500,22 @@ define inreg <64 x half> @bitcast_v16f64_to_v64f16_scalar(<16 x double> inreg %a
; SI-LABEL: bitcast_v16f64_to_v64f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_readfirstlane_b32 s44, v1
; SI-NEXT: v_readfirstlane_b32 s45, v2
@@ -141875,22 +143536,6 @@ define inreg <64 x half> @bitcast_v16f64_to_v64f16_scalar(<16 x double> inreg %a
; SI-NEXT: v_readfirstlane_b32 s4, v17
; SI-NEXT: s_and_b64 s[46:47], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v18
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB81_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s46, s5, 16
@@ -144566,84 +146211,155 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a
; GFX11-LABEL: bitcast_v64f16_to_v16f64_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40
; GFX11-NEXT: s_clause 0x9
; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v185, s32
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12
; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10
; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8
@@ -145331,22 +147047,6 @@ define inreg <64 x i16> @bitcast_v16f64_to_v64i16_scalar(<16 x double> inreg %a,
; SI-LABEL: bitcast_v16f64_to_v64i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_mov_b32_e32 v31, s16
-; SI-NEXT: v_mov_b32_e32 v32, s17
-; SI-NEXT: v_mov_b32_e32 v29, s18
-; SI-NEXT: v_mov_b32_e32 v30, s19
-; SI-NEXT: v_mov_b32_e32 v27, s20
-; SI-NEXT: v_mov_b32_e32 v28, s21
-; SI-NEXT: v_mov_b32_e32 v25, s22
-; SI-NEXT: v_mov_b32_e32 v26, s23
-; SI-NEXT: v_mov_b32_e32 v23, s24
-; SI-NEXT: v_mov_b32_e32 v24, s25
-; SI-NEXT: v_mov_b32_e32 v21, s26
-; SI-NEXT: v_mov_b32_e32 v22, s27
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mov_b32_e32 v19, s28
-; SI-NEXT: v_mov_b32_e32 v20, s29
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -145363,6 +147063,22 @@ define inreg <64 x i16> @bitcast_v16f64_to_v64i16_scalar(<16 x double> inreg %a,
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
+; SI-NEXT: v_mov_b32_e32 v31, s16
+; SI-NEXT: v_mov_b32_e32 v32, s17
+; SI-NEXT: v_mov_b32_e32 v29, s18
+; SI-NEXT: v_mov_b32_e32 v30, s19
+; SI-NEXT: v_mov_b32_e32 v27, s20
+; SI-NEXT: v_mov_b32_e32 v28, s21
+; SI-NEXT: v_mov_b32_e32 v25, s22
+; SI-NEXT: v_mov_b32_e32 v26, s23
+; SI-NEXT: v_mov_b32_e32 v23, s24
+; SI-NEXT: v_mov_b32_e32 v24, s25
+; SI-NEXT: v_mov_b32_e32 v21, s26
+; SI-NEXT: v_mov_b32_e32 v22, s27
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_mov_b32_e32 v19, s28
+; SI-NEXT: v_mov_b32_e32 v20, s29
; SI-NEXT: s_cbranch_scc0 .LBB85_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v18
@@ -147474,84 +149190,155 @@ define inreg <16 x double> @bitcast_v64i16_to_v16f64_scalar(<64 x i16> inreg %a,
; GFX11-LABEL: bitcast_v64i16_to_v16f64_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40
; GFX11-NEXT: s_clause 0x9
; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v185, s32
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12
; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10
; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8
@@ -153080,53 +154867,99 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:580
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:576
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:572
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:568
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:564
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:560
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:556
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:552
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:548
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:544
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:540
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:536
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:532
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:528
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:524
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:520
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:516
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:512
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:508
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:504
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:500
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:496
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:492
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:488
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:484
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:480
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:476
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:472
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:468
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:464
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:460
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:456
; GFX11-FAKE16-NEXT: s_clause 0xf
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:452
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:448
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:444
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:440
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:436
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:432
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:428
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:424
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:420
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:416
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:412
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:408
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:404
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:400
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:396
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:392
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v30 :: v_dual_mov_b32 v54, v24
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v55, v28 :: v_dual_mov_b32 v52, v26
@@ -154019,22 +155852,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:332
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:328
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:324
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:320
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:316
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:312
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:308
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:304
-; SI-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
-; SI-NEXT: s_mov_b32 s72, s21
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_writelane_b32 v43, s19, 0
-; SI-NEXT: v_writelane_b32 v43, s18, 1
-; SI-NEXT: v_writelane_b32 v43, s17, 2
-; SI-NEXT: v_writelane_b32 v43, s16, 3
-; SI-NEXT: s_mov_b32 s60, s24
+; SI-NEXT: s_waitcnt expcnt(3)
; SI-NEXT: v_writelane_b32 v41, s34, 0
; SI-NEXT: v_writelane_b32 v41, s35, 1
; SI-NEXT: v_writelane_b32 v41, s36, 2
@@ -154057,8 +155875,6 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: v_writelane_b32 v41, s69, 19
; SI-NEXT: v_writelane_b32 v41, s70, 20
; SI-NEXT: v_writelane_b32 v41, s71, 21
-; SI-NEXT: s_mov_b32 s77, s28
-; SI-NEXT: s_mov_b32 s76, s27
; SI-NEXT: v_writelane_b32 v41, s80, 22
; SI-NEXT: v_writelane_b32 v41, s81, 23
; SI-NEXT: v_writelane_b32 v41, s82, 24
@@ -154071,6 +155887,26 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: v_writelane_b32 v41, s97, 31
; SI-NEXT: v_writelane_b32 v41, s98, 32
; SI-NEXT: v_writelane_b32 v41, s99, 33
+; SI-NEXT: v_writelane_b32 v41, s30, 34
+; SI-NEXT: v_writelane_b32 v41, s31, 35
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:332
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:328
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:324
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:320
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:316
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:312
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:308
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:304
+; SI-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
+; SI-NEXT: s_mov_b32 s72, s21
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_writelane_b32 v43, s19, 0
+; SI-NEXT: v_writelane_b32 v43, s18, 1
+; SI-NEXT: v_writelane_b32 v43, s17, 2
+; SI-NEXT: v_writelane_b32 v43, s16, 3
+; SI-NEXT: s_mov_b32 s60, s24
+; SI-NEXT: s_mov_b32 s77, s28
+; SI-NEXT: s_mov_b32 s76, s27
; SI-NEXT: s_mov_b32 s79, s26
; SI-NEXT: v_readfirstlane_b32 s38, v20
; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
@@ -154102,6 +155938,15 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: v_readfirstlane_b32 s90, v9
; SI-NEXT: v_readfirstlane_b32 s91, v10
; SI-NEXT: v_readfirstlane_b32 s92, v8
+; SI-NEXT: v_readfirstlane_b32 s93, v7
+; SI-NEXT: v_readfirstlane_b32 s94, v13
+; SI-NEXT: v_readfirstlane_b32 s95, v14
+; SI-NEXT: v_readfirstlane_b32 s30, v17
+; SI-NEXT: v_readfirstlane_b32 s31, v18
+; SI-NEXT: v_readfirstlane_b32 s34, v16
+; SI-NEXT: v_readfirstlane_b32 s35, v15
+; SI-NEXT: v_readfirstlane_b32 s36, v21
+; SI-NEXT: v_readfirstlane_b32 s37, v22
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_readfirstlane_b32 s6, v31
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:300
@@ -154137,17 +155982,6 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s4, v38
; SI-NEXT: v_writelane_b32 v43, s4, 10
-; SI-NEXT: v_readfirstlane_b32 s93, v7
-; SI-NEXT: v_readfirstlane_b32 s94, v13
-; SI-NEXT: v_readfirstlane_b32 s95, v14
-; SI-NEXT: v_writelane_b32 v41, s30, 34
-; SI-NEXT: v_writelane_b32 v41, s31, 35
-; SI-NEXT: v_readfirstlane_b32 s30, v17
-; SI-NEXT: v_readfirstlane_b32 s31, v18
-; SI-NEXT: v_readfirstlane_b32 s34, v16
-; SI-NEXT: v_readfirstlane_b32 s35, v15
-; SI-NEXT: v_readfirstlane_b32 s36, v21
-; SI-NEXT: v_readfirstlane_b32 s37, v22
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_readfirstlane_b32 s4, v31
; SI-NEXT: v_writelane_b32 v43, s4, 11
@@ -157861,35 +159695,65 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1e
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:440
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:436
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:432
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:428
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:424
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:420
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:416
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:412
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:408
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:404
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:400
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:396
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:392
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:388
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:384
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:380
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:376
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:372
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:368
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:364
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:360
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:356
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:352
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:348
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:344
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:340
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:336
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:332
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:328
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:324
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:320
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, v30 :: v_dual_mov_b32 v51, v24
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v52, v28 :: v_dual_mov_b32 v55, v26
@@ -158633,35 +160497,65 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1e
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:440
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:436
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:432
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:428
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:424
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:420
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:416
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:412
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:408
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:404
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:400
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:396
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:392
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:388
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:384
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:380
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:376
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:372
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:368
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:364
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:360
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:356
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:352
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:348
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:344
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:340
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:336
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:332
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:328
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:324
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:320
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v30 :: v_dual_mov_b32 v51, v24
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v28 :: v_dual_mov_b32 v55, v26
@@ -164681,65 +166575,123 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:124
; GFX11-TRUE16-NEXT: s_clause 0x1b
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:8
@@ -165848,26 +167800,47 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x15
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:96
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:92
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:88
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:84
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:80
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:76
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:72
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:68
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:64
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:60
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:56
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:52
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:48
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:44
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:40
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:36
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:32
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:28
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:24
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:20
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:16
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:12
; GFX11-FAKE16-NEXT: s_clause 0x2
; GFX11-FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
@@ -167055,27 +169028,6 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:72
; SI-NEXT: v_writelane_b32 v63, s34, 0
; SI-NEXT: v_writelane_b32 v63, s35, 1
; SI-NEXT: v_writelane_b32 v63, s36, 2
@@ -167104,34 +169056,55 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: v_writelane_b32 v63, s83, 25
; SI-NEXT: v_writelane_b32 v63, s84, 26
; SI-NEXT: v_writelane_b32 v63, s85, 27
+; SI-NEXT: v_writelane_b32 v63, s86, 28
+; SI-NEXT: v_writelane_b32 v63, s87, 29
+; SI-NEXT: v_writelane_b32 v63, s96, 30
+; SI-NEXT: v_writelane_b32 v63, s97, 31
+; SI-NEXT: v_writelane_b32 v63, s98, 32
+; SI-NEXT: v_writelane_b32 v63, s99, 33
+; SI-NEXT: v_writelane_b32 v63, s30, 34
+; SI-NEXT: v_writelane_b32 v63, s31, 35
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:80
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:72
; SI-NEXT: s_waitcnt expcnt(5)
; SI-NEXT: v_mul_f32_e32 v56, 1.0, v2
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10
-; SI-NEXT: v_writelane_b32 v63, s86, 28
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v9
-; SI-NEXT: v_writelane_b32 v63, s87, 29
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v14
-; SI-NEXT: v_writelane_b32 v63, s96, 30
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15
-; SI-NEXT: v_writelane_b32 v63, s97, 31
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v18
-; SI-NEXT: v_writelane_b32 v63, s98, 32
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v26
-; SI-NEXT: v_writelane_b32 v63, s99, 33
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; SI-NEXT: v_writelane_b32 v63, s30, 34
; SI-NEXT: v_mov_b32_e32 v46, v21
-; SI-NEXT: v_writelane_b32 v63, s31, 35
; SI-NEXT: v_mul_f32_e32 v47, 1.0, v1
; SI-NEXT: v_mul_f32_e32 v32, 1.0, v4
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3
@@ -167141,8 +169114,6 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: v_mul_f32_e32 v61, 1.0, v7
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v12
; SI-NEXT: v_mul_f32_e32 v60, 1.0, v11
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
; SI-NEXT: v_mul_f32_e32 v21, 1.0, v16
; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
@@ -167150,18 +169121,29 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v19
; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
; SI-NEXT: v_mul_f32_e32 v20, 1.0, v46
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v48
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
; SI-NEXT: v_mul_f32_e32 v46, 1.0, v23
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v2, 1.0, v52
; SI-NEXT: v_mul_f32_e32 v26, 1.0, v25
; SI-NEXT: v_mul_f32_e32 v57, 1.0, v28
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v27
; SI-NEXT: v_mul_f32_e32 v28, 1.0, v30
; SI-NEXT: v_mul_f32_e32 v30, 1.0, v29
+; SI-NEXT: v_mul_f32_e64 v11, 1.0, s16
+; SI-NEXT: v_mul_f32_e64 v3, 1.0, s19
+; SI-NEXT: v_mul_f32_e64 v4, 1.0, s18
+; SI-NEXT: v_mul_f32_e64 v14, 1.0, s21
+; SI-NEXT: v_mul_f32_e64 v15, 1.0, s20
+; SI-NEXT: v_mul_f32_e64 v7, 1.0, s23
+; SI-NEXT: v_mul_f32_e64 v6, 1.0, s22
+; SI-NEXT: v_mul_f32_e64 v18, 1.0, s25
+; SI-NEXT: v_mul_f32_e64 v19, 1.0, s24
+; SI-NEXT: v_mul_f32_e64 v10, 1.0, s27
+; SI-NEXT: v_mul_f32_e64 v8, 1.0, s26
+; SI-NEXT: v_mul_f32_e64 v23, 1.0, s29
+; SI-NEXT: v_mul_f32_e64 v25, 1.0, s28
+; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
; SI-NEXT: v_mul_f32_e32 v31, 1.0, v33
; SI-NEXT: v_mul_f32_e32 v27, 1.0, v34
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
@@ -167169,8 +169151,13 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: v_mul_f32_e32 v36, 1.0, v36
; SI-NEXT: v_mul_f32_e32 v35, 1.0, v37
; SI-NEXT: v_mul_f32_e32 v34, 1.0, v38
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v48
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
; SI-NEXT: v_mul_f32_e32 v37, 1.0, v39
; SI-NEXT: v_mul_f32_e32 v48, 1.0, v49
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v2, 1.0, v52
; SI-NEXT: v_mul_f32_e32 v39, 1.0, v50
; SI-NEXT: v_mul_f32_e32 v33, 1.0, v51
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
@@ -167191,20 +169178,6 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; SI-NEXT: v_mul_f32_e32 v53, 1.0, v45
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s17
-; SI-NEXT: v_mul_f32_e64 v11, 1.0, s16
-; SI-NEXT: v_mul_f32_e64 v3, 1.0, s19
-; SI-NEXT: v_mul_f32_e64 v4, 1.0, s18
-; SI-NEXT: v_mul_f32_e64 v14, 1.0, s21
-; SI-NEXT: v_mul_f32_e64 v15, 1.0, s20
-; SI-NEXT: v_mul_f32_e64 v7, 1.0, s23
-; SI-NEXT: v_mul_f32_e64 v6, 1.0, s22
-; SI-NEXT: v_mul_f32_e64 v18, 1.0, s25
-; SI-NEXT: v_mul_f32_e64 v19, 1.0, s24
-; SI-NEXT: v_mul_f32_e64 v10, 1.0, s27
-; SI-NEXT: v_mul_f32_e64 v8, 1.0, s26
-; SI-NEXT: v_mul_f32_e64 v23, 1.0, s29
-; SI-NEXT: v_mul_f32_e64 v25, 1.0, s28
-; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
@@ -168736,6 +170709,20 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_writelane_b32 v63, s34, 0
; VI-NEXT: v_writelane_b32 v63, s35, 1
; VI-NEXT: v_writelane_b32 v63, s36, 2
@@ -168767,8 +170754,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_writelane_b32 v63, s86, 28
; VI-NEXT: v_writelane_b32 v63, s87, 29
; VI-NEXT: v_writelane_b32 v63, s30, 30
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; VI-NEXT: v_writelane_b32 v63, s31, 31
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; VI-NEXT: v_readfirstlane_b32 s44, v3
; VI-NEXT: v_readfirstlane_b32 s45, v4
; VI-NEXT: v_readfirstlane_b32 s42, v5
@@ -168788,20 +170775,6 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[46:47], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; VI-NEXT: s_cbranch_scc0 .LBB91_3
; VI-NEXT: ; %bb.1: ; %cmp.false
@@ -170590,6 +172563,20 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_writelane_b32 v63, s34, 0
; GFX9-NEXT: v_writelane_b32 v63, s35, 1
; GFX9-NEXT: v_writelane_b32 v63, s36, 2
@@ -170625,8 +172612,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_writelane_b32 v63, s98, 32
; GFX9-NEXT: v_writelane_b32 v63, s99, 33
; GFX9-NEXT: v_writelane_b32 v63, s30, 34
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; GFX9-NEXT: v_writelane_b32 v63, s31, 35
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; GFX9-NEXT: v_readfirstlane_b32 s76, v3
; GFX9-NEXT: v_readfirstlane_b32 s77, v4
; GFX9-NEXT: v_readfirstlane_b32 s74, v5
@@ -170646,20 +172633,6 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; GFX9-NEXT: s_cbranch_scc0 .LBB91_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
@@ -172201,42 +174174,14 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:12
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s4
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s34, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s98, 0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v2
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s35, 1
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s99, 1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v4
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v5
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s36, 2
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s100, 2
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v6
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v8
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s37, 3
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s101, 3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v11
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s38, 4
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s102, 4
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v12
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v14
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s39, 5
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s103, 5
-; GFX11-TRUE16-NEXT: s_mov_b32 vcc_hi, 0
-; GFX11-TRUE16-NEXT: s_and_b32 s4, vcc_lo, exec_lo
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s48, 6
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s104, 6
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s49, 7
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s30, 7
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s50, 8
-; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s31, 8
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s51, 9
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s52, 10
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s53, 11
@@ -172260,6 +174205,34 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s87, 29
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s96, 30
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s97, 31
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s98, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s99, 1
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s100, 2
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s101, 3
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s102, 4
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s103, 5
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s104, 6
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s30, 7
+; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s31, 8
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v2
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v3
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v4
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v5
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v6
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v7
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v8
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v9
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v10
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v11
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v12
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v13
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v14
+; GFX11-TRUE16-NEXT: s_mov_b32 vcc_hi, 0
+; GFX11-TRUE16-NEXT: s_and_b32 s4, vcc_lo, exec_lo
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB91_3
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s27, 24
@@ -173764,42 +175737,14 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:12
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s4
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s34, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s98, 0
-; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s72, v1
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v2
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s35, 1
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s99, 1
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s62, v3
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s63, v4
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v5
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s36, 2
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s100, 2
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v6
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v7
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s59, v8
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s37, 3
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s101, 3
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v9
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v10
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v11
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s38, 4
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s102, 4
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v12
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v13
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v14
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s39, 5
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s103, 5
-; GFX11-FAKE16-NEXT: s_mov_b32 vcc_hi, 0
-; GFX11-FAKE16-NEXT: s_and_b32 s4, vcc_lo, exec_lo
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s48, 6
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s104, 6
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s49, 7
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s30, 7
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s50, 8
-; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s31, 8
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s51, 9
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s52, 10
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s53, 11
@@ -173823,6 +175768,34 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s87, 29
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s96, 30
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s97, 31
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s98, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s99, 1
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s100, 2
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s101, 3
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s102, 4
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s103, 5
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s104, 6
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s30, 7
+; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s31, 8
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s72, v1
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v2
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s62, v3
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s63, v4
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v5
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v6
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v7
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s59, v8
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v9
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v10
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v11
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v12
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v13
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v14
+; GFX11-FAKE16-NEXT: s_mov_b32 vcc_hi, 0
+; GFX11-FAKE16-NEXT: s_and_b32 s4, vcc_lo, exec_lo
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB91_3
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s27, 24
@@ -180797,53 +182770,99 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:580
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:576
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:572
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:568
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:564
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:560
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:556
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:552
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:548
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:544
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:540
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:536
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:532
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:528
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:524
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:520
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:516
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:512
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:508
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:504
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:500
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:496
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:492
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:488
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:484
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:480
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:476
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:472
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:468
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:464
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:460
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:456
; GFX11-FAKE16-NEXT: s_clause 0xf
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:452
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:448
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:444
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:440
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:436
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:432
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:428
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:424
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:420
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:416
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:412
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:408
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:404
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:400
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:396
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:392
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v30 :: v_dual_mov_b32 v54, v24
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v55, v28 :: v_dual_mov_b32 v52, v26
@@ -181735,14 +183754,19 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:332
-; SI-NEXT: ; implicit-def: $vgpr61 : SGPR spill to VGPR lane
-; SI-NEXT: s_mov_b32 s10, s16
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_writelane_b32 v61, s29, 0
-; SI-NEXT: v_writelane_b32 v61, s28, 1
-; SI-NEXT: v_writelane_b32 v61, s27, 2
-; SI-NEXT: s_mov_b32 s61, s21
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; SI-NEXT: v_writelane_b32 v63, s34, 0
; SI-NEXT: v_writelane_b32 v63, s35, 1
; SI-NEXT: v_writelane_b32 v63, s36, 2
@@ -181775,12 +183799,19 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: v_writelane_b32 v63, s87, 29
; SI-NEXT: v_writelane_b32 v63, s96, 30
; SI-NEXT: v_writelane_b32 v63, s97, 31
-; SI-NEXT: s_mov_b32 s67, s19
-; SI-NEXT: s_mov_b32 s54, s17
; SI-NEXT: v_writelane_b32 v63, s98, 32
; SI-NEXT: v_writelane_b32 v63, s99, 33
; SI-NEXT: v_writelane_b32 v63, s30, 34
; SI-NEXT: v_writelane_b32 v63, s31, 35
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:332
+; SI-NEXT: ; implicit-def: $vgpr61 : SGPR spill to VGPR lane
+; SI-NEXT: s_mov_b32 s10, s16
+; SI-NEXT: v_writelane_b32 v61, s29, 0
+; SI-NEXT: v_writelane_b32 v61, s28, 1
+; SI-NEXT: v_writelane_b32 v61, s27, 2
+; SI-NEXT: s_mov_b32 s61, s21
+; SI-NEXT: s_mov_b32 s67, s19
+; SI-NEXT: s_mov_b32 s54, s17
; SI-NEXT: s_mov_b32 s35, s23
; SI-NEXT: s_mov_b32 s39, s26
; SI-NEXT: s_mov_b32 s62, s25
@@ -181788,7 +183819,6 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s74, v24
; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; SI-NEXT: v_readfirstlane_b32 s6, v23
-; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v62, s74, 0
; SI-NEXT: v_readfirstlane_b32 s12, v26
; SI-NEXT: v_writelane_b32 v62, s6, 1
@@ -181819,10 +183849,6 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s42, v20
; SI-NEXT: v_readfirstlane_b32 s43, v19
; SI-NEXT: v_readfirstlane_b32 s44, v22
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_readfirstlane_b32 s4, v31
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:328
-; SI-NEXT: v_writelane_b32 v61, s4, 3
; SI-NEXT: v_readfirstlane_b32 s45, v21
; SI-NEXT: v_readfirstlane_b32 s98, v10
; SI-NEXT: v_readfirstlane_b32 s90, v8
@@ -181830,28 +183856,19 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s91, v6
; SI-NEXT: v_readfirstlane_b32 s93, v4
; SI-NEXT: v_readfirstlane_b32 s55, v2
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_readfirstlane_b32 s4, v31
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:324
-; SI-NEXT: v_writelane_b32 v61, s4, 4
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:328
+; SI-NEXT: v_writelane_b32 v61, s4, 3
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_readfirstlane_b32 s4, v31
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:324
+; SI-NEXT: v_writelane_b32 v61, s4, 4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_readfirstlane_b32 s4, v31
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:320
; SI-NEXT: v_writelane_b32 v61, s4, 5
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -185482,35 +187499,65 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1e
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:440
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:436
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:432
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:428
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:424
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:420
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:416
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:412
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:408
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:404
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:400
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:396
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:392
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:388
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:384
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:380
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:376
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:372
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:368
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:364
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:360
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:356
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:352
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:348
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:344
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:340
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:336
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:332
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:328
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:324
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:320
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, v30 :: v_dual_mov_b32 v51, v24
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v52, v28 :: v_dual_mov_b32 v55, v26
@@ -186254,35 +188301,65 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1e
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:440
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:436
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:432
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:428
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:424
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:420
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:416
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:412
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:408
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:404
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:400
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:396
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:392
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:388
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:384
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:380
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:376
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:372
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:368
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:364
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:360
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:356
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:352
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:348
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:344
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:340
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:336
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:332
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:328
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:324
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:320
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v30 :: v_dual_mov_b32 v51, v24
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v28 :: v_dual_mov_b32 v55, v26
@@ -187095,7 +189172,6 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v64f16_to_v128i8:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
@@ -187112,6 +189188,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:136
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32
@@ -187140,16 +189217,16 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:80
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:92
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v33, v4
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v1, v3
-; SI-NEXT: v_cvt_f16_f32_e32 v33, v4
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
; SI-NEXT: v_cvt_f16_f32_e32 v31, v12
+; SI-NEXT: v_cvt_f16_f32_e32 v12, v16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v1, v6
-; SI-NEXT: v_cvt_f16_f32_e32 v12, v16
; SI-NEXT: v_cvt_f16_f32_e32 v32, v8
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -187185,26 +189262,27 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v1, v18
; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v34
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v1, v17
-; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_cvt_f16_f32_e32 v10, v35
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v34
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: v_cvt_f16_f32_e32 v8, v39
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v1, v19
-; SI-NEXT: v_cvt_f16_f32_e32 v8, v39
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: v_cvt_f16_f32_e32 v7, v51
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v1, v22
-; SI-NEXT: v_cvt_f16_f32_e32 v56, v53
; SI-NEXT: v_cvt_f16_f32_e32 v5, v55
+; SI-NEXT: v_cvt_f16_f32_e32 v56, v53
; SI-NEXT: v_cvt_f16_f32_e32 v47, v54
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -187217,6 +189295,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; SI-NEXT: v_cvt_f16_f32_e32 v1, v23
; SI-NEXT: v_cvt_f16_f32_e32 v62, v60
; SI-NEXT: v_cvt_f16_f32_e32 v61, v61
+; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_cvt_f16_f32_e32 v60, v45
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -187227,7 +189306,6 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr23
@@ -187285,7 +189363,6 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v1, v63
-; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_cvt_f16_f32_e32 v63, v46
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -191635,24 +193712,43 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x13
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:88
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:84
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:80
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:76
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:72
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:68
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:64
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:60
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:56
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:52
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:48
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:44
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:40
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:36
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:32
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:28
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:24
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:20
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:16
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:12
; GFX11-FAKE16-NEXT: s_clause 0x2
; GFX11-FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
@@ -192355,117 +194451,129 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:28
-; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:24
-; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:36
-; SI-NEXT: s_waitcnt expcnt(4)
-; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:32
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:44
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:72
; SI-NEXT: v_writelane_b32 v63, s34, 0
; SI-NEXT: v_writelane_b32 v63, s35, 1
; SI-NEXT: v_writelane_b32 v63, s36, 2
; SI-NEXT: v_writelane_b32 v63, s37, 3
; SI-NEXT: v_writelane_b32 v63, s38, 4
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_writelane_b32 v63, s39, 5
; SI-NEXT: v_writelane_b32 v63, s48, 6
; SI-NEXT: v_writelane_b32 v63, s49, 7
; SI-NEXT: v_writelane_b32 v63, s50, 8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v3
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v7
; SI-NEXT: v_writelane_b32 v63, s51, 9
; SI-NEXT: v_writelane_b32 v63, s52, 10
; SI-NEXT: v_writelane_b32 v63, s53, 11
; SI-NEXT: v_writelane_b32 v63, s54, 12
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v9
; SI-NEXT: v_writelane_b32 v63, s55, 13
; SI-NEXT: v_writelane_b32 v63, s64, 14
; SI-NEXT: v_writelane_b32 v63, s65, 15
; SI-NEXT: v_writelane_b32 v63, s66, 16
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v26
; SI-NEXT: v_writelane_b32 v63, s67, 17
; SI-NEXT: v_writelane_b32 v63, s68, 18
; SI-NEXT: v_writelane_b32 v63, s69, 19
; SI-NEXT: v_writelane_b32 v63, s70, 20
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v25
; SI-NEXT: v_writelane_b32 v63, s71, 21
; SI-NEXT: v_writelane_b32 v63, s80, 22
; SI-NEXT: v_writelane_b32 v63, s81, 23
; SI-NEXT: v_writelane_b32 v63, s82, 24
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v30
; SI-NEXT: v_writelane_b32 v63, s83, 25
; SI-NEXT: v_writelane_b32 v63, s84, 26
; SI-NEXT: v_writelane_b32 v63, s85, 27
; SI-NEXT: v_writelane_b32 v63, s86, 28
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: v_writelane_b32 v63, s87, 29
; SI-NEXT: v_writelane_b32 v63, s96, 30
; SI-NEXT: v_writelane_b32 v63, s97, 31
-; SI-NEXT: v_mov_b32_e32 v46, v29
; SI-NEXT: v_writelane_b32 v63, s98, 32
+; SI-NEXT: v_writelane_b32 v63, s99, 33
+; SI-NEXT: v_writelane_b32 v63, s30, 34
+; SI-NEXT: v_writelane_b32 v63, s31, 35
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:80
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:24
+; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:36
+; SI-NEXT: s_waitcnt expcnt(4)
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:32
+; SI-NEXT: s_waitcnt expcnt(2)
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:44
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:72
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_mov_b32_e32 v46, v29
; SI-NEXT: v_cvt_f16_f32_e32 v47, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v4
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v7
; SI-NEXT: v_cvt_f16_f32_e32 v33, v6
; SI-NEXT: v_cvt_f16_f32_e32 v43, v5
; SI-NEXT: v_cvt_f16_f32_e32 v5, v8
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v9
; SI-NEXT: v_cvt_f16_f32_e32 v32, v10
; SI-NEXT: v_cvt_f16_f32_e32 v7, v12
; SI-NEXT: v_cvt_f16_f32_e32 v29, v11
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v26
; SI-NEXT: v_cvt_f16_f32_e32 v31, v14
; SI-NEXT: v_cvt_f16_f32_e32 v6, v13
; SI-NEXT: v_cvt_f16_f32_e32 v58, v16
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v25
; SI-NEXT: v_cvt_f16_f32_e32 v13, v15
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v34
; SI-NEXT: v_cvt_f16_f32_e32 v10, v18
; SI-NEXT: v_cvt_f16_f32_e32 v11, v17
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v37
-; SI-NEXT: v_cvt_f16_f32_e32 v34, v20
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v30
; SI-NEXT: v_cvt_f16_f32_e32 v16, v19
; SI-NEXT: v_cvt_f16_f32_e32 v9, v22
; SI-NEXT: v_cvt_f16_f32_e32 v61, v21
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: v_cvt_f16_f32_e32 v21, v24
; SI-NEXT: v_cvt_f16_f32_e32 v24, v23
; SI-NEXT: v_cvt_f16_f32_e32 v44, v28
; SI-NEXT: v_cvt_f16_f32_e32 v42, v27
; SI-NEXT: v_cvt_f16_f32_e32 v46, v46
+; SI-NEXT: v_cvt_f16_f32_e32 v19, s17
+; SI-NEXT: v_cvt_f16_f32_e32 v18, s16
+; SI-NEXT: v_cvt_f16_f32_e32 v12, s19
+; SI-NEXT: v_cvt_f16_f32_e32 v17, s18
+; SI-NEXT: v_cvt_f16_f32_e32 v22, s22
+; SI-NEXT: v_cvt_f16_f32_e32 v15, s25
+; SI-NEXT: v_cvt_f16_f32_e32 v14, s24
+; SI-NEXT: v_cvt_f16_f32_e32 v30, s27
+; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v34
+; SI-NEXT: v_cvt_f16_f32_e32 v34, v20
; SI-NEXT: v_cvt_f16_f32_e32 v8, v35
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v37
; SI-NEXT: v_cvt_f16_f32_e32 v23, v36
+; SI-NEXT: v_cvt_f16_f32_e32 v27, v39
+; SI-NEXT: v_cvt_f16_f32_e32 v28, v48
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f16_f32_e32 v3, v38
-; SI-NEXT: v_cvt_f16_f32_e32 v27, v39
-; SI-NEXT: v_cvt_f16_f32_e32 v28, v48
; SI-NEXT: v_cvt_f16_f32_e32 v4, v49
; SI-NEXT: v_cvt_f16_f32_e32 v45, v45
; SI-NEXT: v_cvt_f16_f32_e32 v36, v56
@@ -192488,25 +194596,13 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v53, v40
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_cvt_f16_f32_e32 v55, v41
-; SI-NEXT: v_cvt_f16_f32_e32 v19, s17
-; SI-NEXT: v_cvt_f16_f32_e32 v18, s16
-; SI-NEXT: v_cvt_f16_f32_e32 v12, s19
-; SI-NEXT: v_cvt_f16_f32_e32 v17, s18
; SI-NEXT: v_cvt_f16_f32_e32 v38, s21
; SI-NEXT: v_cvt_f16_f32_e32 v37, s20
; SI-NEXT: v_cvt_f16_f32_e32 v48, s23
-; SI-NEXT: v_cvt_f16_f32_e32 v22, s22
-; SI-NEXT: v_cvt_f16_f32_e32 v15, s25
-; SI-NEXT: v_cvt_f16_f32_e32 v14, s24
-; SI-NEXT: v_cvt_f16_f32_e32 v30, s27
; SI-NEXT: v_cvt_f16_f32_e32 v39, s26
; SI-NEXT: v_cvt_f16_f32_e32 v35, s29
; SI-NEXT: v_cvt_f16_f32_e32 v20, s28
-; SI-NEXT: v_writelane_b32 v63, s99, 33
-; SI-NEXT: v_writelane_b32 v63, s30, 34
-; SI-NEXT: v_writelane_b32 v63, s31, 35
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
@@ -194051,6 +196147,20 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_writelane_b32 v63, s34, 0
; VI-NEXT: v_writelane_b32 v63, s35, 1
; VI-NEXT: v_writelane_b32 v63, s36, 2
@@ -194082,8 +196192,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_writelane_b32 v63, s86, 28
; VI-NEXT: v_writelane_b32 v63, s87, 29
; VI-NEXT: v_writelane_b32 v63, s30, 30
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; VI-NEXT: v_writelane_b32 v63, s31, 31
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; VI-NEXT: v_readfirstlane_b32 s44, v3
; VI-NEXT: v_readfirstlane_b32 s45, v4
; VI-NEXT: v_readfirstlane_b32 s42, v5
@@ -194103,20 +196213,6 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[46:47], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; VI-NEXT: s_cbranch_scc0 .LBB95_3
; VI-NEXT: ; %bb.1: ; %cmp.false
@@ -195410,6 +197506,20 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_writelane_b32 v63, s34, 0
; GFX9-NEXT: v_writelane_b32 v63, s35, 1
; GFX9-NEXT: v_writelane_b32 v63, s36, 2
@@ -195445,8 +197555,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: v_writelane_b32 v63, s98, 32
; GFX9-NEXT: v_writelane_b32 v63, s99, 33
; GFX9-NEXT: v_writelane_b32 v63, s30, 34
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; GFX9-NEXT: v_writelane_b32 v63, s31, 35
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; GFX9-NEXT: v_readfirstlane_b32 s44, v3
; GFX9-NEXT: v_readfirstlane_b32 s45, v4
; GFX9-NEXT: v_readfirstlane_b32 s42, v5
@@ -195466,20 +197576,6 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; GFX9-NEXT: s_cbranch_scc0 .LBB95_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
@@ -196721,63 +198817,53 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v75, s34, 0
-; GFX11-NEXT: v_writelane_b32 v76, s98, 0
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
-; GFX11-NEXT: v_readfirstlane_b32 s40, v1
-; GFX11-NEXT: v_readfirstlane_b32 s41, v2
-; GFX11-NEXT: v_writelane_b32 v75, s35, 1
-; GFX11-NEXT: v_writelane_b32 v76, s99, 1
-; GFX11-NEXT: v_readfirstlane_b32 s14, v3
-; GFX11-NEXT: v_readfirstlane_b32 s15, v4
-; GFX11-NEXT: v_readfirstlane_b32 s12, v5
-; GFX11-NEXT: v_writelane_b32 v75, s36, 2
-; GFX11-NEXT: v_writelane_b32 v76, s100, 2
-; GFX11-NEXT: v_readfirstlane_b32 s13, v6
-; GFX11-NEXT: v_readfirstlane_b32 s10, v7
-; GFX11-NEXT: v_readfirstlane_b32 s11, v8
-; GFX11-NEXT: v_writelane_b32 v75, s37, 3
-; GFX11-NEXT: v_writelane_b32 v76, s101, 3
-; GFX11-NEXT: v_readfirstlane_b32 s8, v9
-; GFX11-NEXT: v_readfirstlane_b32 s9, v10
-; GFX11-NEXT: v_readfirstlane_b32 s6, v11
-; GFX11-NEXT: v_writelane_b32 v75, s38, 4
-; GFX11-NEXT: v_writelane_b32 v76, s102, 4
-; GFX11-NEXT: v_readfirstlane_b32 s7, v12
-; GFX11-NEXT: v_readfirstlane_b32 s4, v13
-; GFX11-NEXT: v_readfirstlane_b32 s5, v14
-; GFX11-NEXT: v_writelane_b32 v75, s39, 5
-; GFX11-NEXT: v_writelane_b32 v76, s103, 5
-; GFX11-NEXT: s_mov_b32 s99, 0
-; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
; GFX11-NEXT: s_clause 0x12
; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:72
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:68
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:64
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:60
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:56
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:52
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:48
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:44
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:40
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:36
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:32
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:28
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:24
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:20
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:16
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v74, s32
+; GFX11-NEXT: v_writelane_b32 v75, s34, 0
+; GFX11-NEXT: v_writelane_b32 v75, s35, 1
+; GFX11-NEXT: v_writelane_b32 v75, s36, 2
+; GFX11-NEXT: v_writelane_b32 v75, s37, 3
+; GFX11-NEXT: v_writelane_b32 v75, s38, 4
+; GFX11-NEXT: v_writelane_b32 v75, s39, 5
; GFX11-NEXT: v_writelane_b32 v75, s48, 6
-; GFX11-NEXT: v_writelane_b32 v76, s104, 6
-; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane
-; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane
; GFX11-NEXT: v_writelane_b32 v75, s49, 7
-; GFX11-NEXT: v_writelane_b32 v76, s30, 7
; GFX11-NEXT: v_writelane_b32 v75, s50, 8
-; GFX11-NEXT: v_writelane_b32 v76, s31, 8
; GFX11-NEXT: v_writelane_b32 v75, s51, 9
; GFX11-NEXT: v_writelane_b32 v75, s52, 10
; GFX11-NEXT: v_writelane_b32 v75, s53, 11
@@ -196801,6 +198887,34 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX11-NEXT: v_writelane_b32 v75, s87, 29
; GFX11-NEXT: v_writelane_b32 v75, s96, 30
; GFX11-NEXT: v_writelane_b32 v75, s97, 31
+; GFX11-NEXT: v_writelane_b32 v76, s98, 0
+; GFX11-NEXT: v_writelane_b32 v76, s99, 1
+; GFX11-NEXT: v_writelane_b32 v76, s100, 2
+; GFX11-NEXT: v_writelane_b32 v76, s101, 3
+; GFX11-NEXT: v_writelane_b32 v76, s102, 4
+; GFX11-NEXT: v_writelane_b32 v76, s103, 5
+; GFX11-NEXT: v_writelane_b32 v76, s104, 6
+; GFX11-NEXT: v_writelane_b32 v76, s30, 7
+; GFX11-NEXT: v_writelane_b32 v76, s31, 8
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
+; GFX11-NEXT: v_readfirstlane_b32 s40, v1
+; GFX11-NEXT: v_readfirstlane_b32 s41, v2
+; GFX11-NEXT: v_readfirstlane_b32 s14, v3
+; GFX11-NEXT: v_readfirstlane_b32 s15, v4
+; GFX11-NEXT: v_readfirstlane_b32 s12, v5
+; GFX11-NEXT: v_readfirstlane_b32 s13, v6
+; GFX11-NEXT: v_readfirstlane_b32 s10, v7
+; GFX11-NEXT: v_readfirstlane_b32 s11, v8
+; GFX11-NEXT: v_readfirstlane_b32 s8, v9
+; GFX11-NEXT: v_readfirstlane_b32 s9, v10
+; GFX11-NEXT: v_readfirstlane_b32 s6, v11
+; GFX11-NEXT: v_readfirstlane_b32 s7, v12
+; GFX11-NEXT: v_readfirstlane_b32 s4, v13
+; GFX11-NEXT: v_readfirstlane_b32 s5, v14
+; GFX11-NEXT: s_mov_b32 s99, 0
+; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
+; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane
+; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane
; GFX11-NEXT: s_cbranch_scc0 .LBB95_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s27, 16
@@ -203149,53 +205263,99 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:580
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:576
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:572
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:568
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:564
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:560
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:556
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:552
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:548
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:544
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:540
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:536
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:532
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:528
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:524
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:520
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:516
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:512
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:508
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:504
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:500
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:496
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:492
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:488
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:484
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:480
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:476
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:472
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:468
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:464
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:460
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:456
; GFX11-FAKE16-NEXT: s_clause 0xf
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:452
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:448
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:444
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:440
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:436
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:432
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:428
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:424
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:420
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:416
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:412
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:408
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:404
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:400
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:396
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:392
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v30 :: v_dual_mov_b32 v54, v24
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v55, v28 :: v_dual_mov_b32 v52, v26
@@ -204088,32 +206248,8 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:332
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:328
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:324
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:320
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:316
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:312
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:308
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:304
-; SI-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
; SI-NEXT: s_waitcnt expcnt(3)
; SI-NEXT: v_writelane_b32 v41, s34, 0
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_writelane_b32 v43, s29, 0
-; SI-NEXT: v_writelane_b32 v43, s28, 1
-; SI-NEXT: v_writelane_b32 v43, s27, 2
-; SI-NEXT: v_writelane_b32 v43, s26, 3
-; SI-NEXT: v_writelane_b32 v43, s25, 4
-; SI-NEXT: v_writelane_b32 v43, s24, 5
-; SI-NEXT: v_writelane_b32 v43, s23, 6
-; SI-NEXT: v_writelane_b32 v43, s22, 7
-; SI-NEXT: v_writelane_b32 v43, s21, 8
-; SI-NEXT: v_writelane_b32 v43, s20, 9
-; SI-NEXT: v_writelane_b32 v43, s19, 10
-; SI-NEXT: v_writelane_b32 v43, s18, 11
-; SI-NEXT: v_writelane_b32 v43, s17, 12
-; SI-NEXT: v_writelane_b32 v43, s16, 13
; SI-NEXT: v_writelane_b32 v41, s35, 1
; SI-NEXT: v_writelane_b32 v41, s36, 2
; SI-NEXT: v_writelane_b32 v41, s37, 3
@@ -204149,7 +206285,31 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: v_writelane_b32 v41, s99, 33
; SI-NEXT: v_writelane_b32 v41, s30, 34
; SI-NEXT: v_writelane_b32 v41, s31, 35
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:332
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:328
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:324
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:320
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:316
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:312
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:308
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:304
+; SI-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
; SI-NEXT: v_readfirstlane_b32 s39, v26
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_writelane_b32 v43, s29, 0
+; SI-NEXT: v_writelane_b32 v43, s28, 1
+; SI-NEXT: v_writelane_b32 v43, s27, 2
+; SI-NEXT: v_writelane_b32 v43, s26, 3
+; SI-NEXT: v_writelane_b32 v43, s25, 4
+; SI-NEXT: v_writelane_b32 v43, s24, 5
+; SI-NEXT: v_writelane_b32 v43, s23, 6
+; SI-NEXT: v_writelane_b32 v43, s22, 7
+; SI-NEXT: v_writelane_b32 v43, s21, 8
+; SI-NEXT: v_writelane_b32 v43, s20, 9
+; SI-NEXT: v_writelane_b32 v43, s19, 10
+; SI-NEXT: v_writelane_b32 v43, s18, 11
+; SI-NEXT: v_writelane_b32 v43, s17, 12
+; SI-NEXT: v_writelane_b32 v43, s16, 13
; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
; SI-NEXT: v_readfirstlane_b32 s47, v12
; SI-NEXT: v_writelane_b32 v42, s39, 0
@@ -204172,6 +206332,19 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s60, v27
; SI-NEXT: v_readfirstlane_b32 s11, v1
; SI-NEXT: v_readfirstlane_b32 s12, v2
+; SI-NEXT: v_readfirstlane_b32 s13, v9
+; SI-NEXT: v_readfirstlane_b32 s14, v10
+; SI-NEXT: v_readfirstlane_b32 s15, v8
+; SI-NEXT: v_readfirstlane_b32 s18, v7
+; SI-NEXT: v_readfirstlane_b32 s21, v5
+; SI-NEXT: v_readfirstlane_b32 s22, v6
+; SI-NEXT: v_readfirstlane_b32 s40, v17
+; SI-NEXT: v_readfirstlane_b32 s41, v18
+; SI-NEXT: v_readfirstlane_b32 s42, v4
+; SI-NEXT: v_readfirstlane_b32 s43, v3
+; SI-NEXT: v_readfirstlane_b32 s76, v16
+; SI-NEXT: v_readfirstlane_b32 s77, v15
+; SI-NEXT: v_readfirstlane_b32 s38, v25
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_readfirstlane_b32 s4, v31
; SI-NEXT: v_writelane_b32 v43, s4, 14
@@ -204205,19 +206378,6 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:256
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s6, v38
-; SI-NEXT: v_readfirstlane_b32 s13, v9
-; SI-NEXT: v_readfirstlane_b32 s14, v10
-; SI-NEXT: v_readfirstlane_b32 s15, v8
-; SI-NEXT: v_readfirstlane_b32 s18, v7
-; SI-NEXT: v_readfirstlane_b32 s21, v5
-; SI-NEXT: v_readfirstlane_b32 s22, v6
-; SI-NEXT: v_readfirstlane_b32 s40, v17
-; SI-NEXT: v_readfirstlane_b32 s41, v18
-; SI-NEXT: v_readfirstlane_b32 s42, v4
-; SI-NEXT: v_readfirstlane_b32 s43, v3
-; SI-NEXT: v_readfirstlane_b32 s76, v16
-; SI-NEXT: v_readfirstlane_b32 s77, v15
-; SI-NEXT: v_readfirstlane_b32 s38, v25
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_readfirstlane_b32 s4, v31
; SI-NEXT: v_writelane_b32 v43, s4, 19
@@ -207905,35 +210065,65 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1e
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:440
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:436
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:432
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:428
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:424
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:420
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:416
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:412
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:408
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:404
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:400
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:396
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:392
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:388
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:384
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:380
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:376
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:372
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:368
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:364
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:360
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:356
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:352
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:348
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:344
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:340
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:336
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:332
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:328
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:324
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:320
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, v30 :: v_dual_mov_b32 v51, v24
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v52, v28 :: v_dual_mov_b32 v55, v26
@@ -208677,35 +210867,65 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1e
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:440
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:436
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:432
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:428
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:424
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:420
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:416
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:412
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:408
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:404
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:400
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:396
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:392
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:388
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:384
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:380
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:376
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:372
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:368
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:364
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:360
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:356
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:352
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:348
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:344
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:340
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:336
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:332
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:328
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:324
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:320
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v30 :: v_dual_mov_b32 v51, v24
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v28 :: v_dual_mov_b32 v55, v26
@@ -214217,24 +216437,43 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x13
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:88
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:84
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:80
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:76
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:72
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:68
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:64
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:60
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:56
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:52
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:48
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:44
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:40
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:36
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:32
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:28
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:24
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:20
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:16
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:12
; GFX11-FAKE16-NEXT: s_clause 0x2
; GFX11-FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
@@ -214925,14 +217164,6 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
; SI-NEXT: s_waitcnt expcnt(3)
; SI-NEXT: v_writelane_b32 v40, s34, 0
; SI-NEXT: v_writelane_b32 v40, s35, 1
@@ -214955,12 +217186,30 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: v_writelane_b32 v40, s68, 18
; SI-NEXT: v_writelane_b32 v40, s69, 19
; SI-NEXT: v_writelane_b32 v40, s70, 20
-; SI-NEXT: s_mov_b32 s88, s17
; SI-NEXT: v_writelane_b32 v40, s71, 21
; SI-NEXT: v_writelane_b32 v40, s80, 22
; SI-NEXT: v_writelane_b32 v40, s81, 23
; SI-NEXT: v_writelane_b32 v40, s82, 24
; SI-NEXT: v_writelane_b32 v40, s83, 25
+; SI-NEXT: v_writelane_b32 v40, s84, 26
+; SI-NEXT: v_writelane_b32 v40, s85, 27
+; SI-NEXT: v_writelane_b32 v40, s86, 28
+; SI-NEXT: v_writelane_b32 v40, s87, 29
+; SI-NEXT: v_writelane_b32 v40, s96, 30
+; SI-NEXT: v_writelane_b32 v40, s97, 31
+; SI-NEXT: v_writelane_b32 v40, s98, 32
+; SI-NEXT: v_writelane_b32 v40, s99, 33
+; SI-NEXT: v_writelane_b32 v40, s30, 34
+; SI-NEXT: v_writelane_b32 v40, s31, 35
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
+; SI-NEXT: s_mov_b32 s88, s17
; SI-NEXT: v_readfirstlane_b32 s6, v16
; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
; SI-NEXT: v_readfirstlane_b32 s7, v15
@@ -214972,30 +217221,20 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: v_writelane_b32 v41, s8, 2
; SI-NEXT: v_readfirstlane_b32 s10, v19
; SI-NEXT: v_writelane_b32 v41, s9, 3
-; SI-NEXT: v_writelane_b32 v40, s84, 26
; SI-NEXT: v_readfirstlane_b32 s11, v25
; SI-NEXT: v_writelane_b32 v41, s10, 4
-; SI-NEXT: v_writelane_b32 v40, s85, 27
; SI-NEXT: v_readfirstlane_b32 s12, v24
; SI-NEXT: v_writelane_b32 v41, s11, 5
-; SI-NEXT: v_writelane_b32 v40, s86, 28
; SI-NEXT: v_readfirstlane_b32 s13, v23
; SI-NEXT: v_writelane_b32 v41, s12, 6
-; SI-NEXT: v_writelane_b32 v40, s87, 29
; SI-NEXT: v_readfirstlane_b32 s15, v29
; SI-NEXT: v_writelane_b32 v41, s13, 7
-; SI-NEXT: v_writelane_b32 v40, s96, 30
; SI-NEXT: v_readfirstlane_b32 s14, v28
; SI-NEXT: v_writelane_b32 v41, s15, 8
-; SI-NEXT: v_writelane_b32 v40, s97, 31
; SI-NEXT: s_mov_b32 s79, s16
; SI-NEXT: v_readfirstlane_b32 s16, v27
; SI-NEXT: v_writelane_b32 v41, s14, 9
-; SI-NEXT: v_writelane_b32 v40, s98, 32
; SI-NEXT: v_writelane_b32 v41, s16, 10
-; SI-NEXT: v_writelane_b32 v40, s99, 33
-; SI-NEXT: v_writelane_b32 v40, s30, 34
-; SI-NEXT: v_writelane_b32 v40, s31, 35
; SI-NEXT: v_readfirstlane_b32 s98, v30
; SI-NEXT: v_readfirstlane_b32 s97, v26
; SI-NEXT: v_readfirstlane_b32 s96, v22
@@ -215008,6 +217247,15 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s85, v10
; SI-NEXT: v_readfirstlane_b32 s51, v9
; SI-NEXT: v_readfirstlane_b32 s53, v8
+; SI-NEXT: v_readfirstlane_b32 s65, v7
+; SI-NEXT: v_readfirstlane_b32 s84, v6
+; SI-NEXT: v_readfirstlane_b32 s31, v5
+; SI-NEXT: v_readfirstlane_b32 s37, v4
+; SI-NEXT: v_readfirstlane_b32 s49, v3
+; SI-NEXT: v_readfirstlane_b32 s78, v2
+; SI-NEXT: v_readfirstlane_b32 s39, v1
+; SI-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
+; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_readfirstlane_b32 s89, v31
; SI-NEXT: s_waitcnt vmcnt(6)
@@ -215037,15 +217285,6 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s83, v38
; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:80
-; SI-NEXT: v_readfirstlane_b32 s65, v7
-; SI-NEXT: v_readfirstlane_b32 s84, v6
-; SI-NEXT: v_readfirstlane_b32 s31, v5
-; SI-NEXT: v_readfirstlane_b32 s37, v4
-; SI-NEXT: v_readfirstlane_b32 s49, v3
-; SI-NEXT: v_readfirstlane_b32 s78, v2
-; SI-NEXT: v_readfirstlane_b32 s39, v1
-; SI-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane
-; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s77, v31
; SI-NEXT: s_waitcnt vmcnt(11)
@@ -216625,8 +218864,9 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_writelane_b32 v20, s85, 27
; VI-NEXT: v_writelane_b32 v20, s86, 28
; VI-NEXT: v_writelane_b32 v20, s87, 29
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; VI-NEXT: v_writelane_b32 v20, s30, 30
+; VI-NEXT: v_writelane_b32 v20, s31, 31
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; VI-NEXT: v_readfirstlane_b32 s42, v3
; VI-NEXT: v_readfirstlane_b32 s43, v4
; VI-NEXT: v_readfirstlane_b32 s40, v5
@@ -216646,7 +218886,6 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: s_and_b64 s[46:47], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s45, v2
-; VI-NEXT: v_writelane_b32 v20, s31, 31
; VI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane
; VI-NEXT: s_cbranch_scc0 .LBB99_4
; VI-NEXT: ; %bb.1: ; %cmp.false
@@ -217764,6 +220003,20 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_writelane_b32 v63, s34, 0
; GFX9-NEXT: v_writelane_b32 v63, s35, 1
; GFX9-NEXT: v_writelane_b32 v63, s36, 2
@@ -217799,8 +220052,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: v_writelane_b32 v63, s98, 32
; GFX9-NEXT: v_writelane_b32 v63, s99, 33
; GFX9-NEXT: v_writelane_b32 v63, s30, 34
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; GFX9-NEXT: v_writelane_b32 v63, s31, 35
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; GFX9-NEXT: v_readfirstlane_b32 s44, v3
; GFX9-NEXT: v_readfirstlane_b32 s45, v4
; GFX9-NEXT: v_readfirstlane_b32 s42, v5
@@ -217820,20 +220073,6 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane
; GFX9-NEXT: s_cbranch_scc0 .LBB99_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
@@ -219074,63 +221313,53 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84
; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: v_writelane_b32 v75, s34, 0
-; GFX11-NEXT: v_writelane_b32 v76, s98, 0
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
-; GFX11-NEXT: v_readfirstlane_b32 s40, v1
-; GFX11-NEXT: v_readfirstlane_b32 s41, v2
-; GFX11-NEXT: v_writelane_b32 v75, s35, 1
-; GFX11-NEXT: v_writelane_b32 v76, s99, 1
-; GFX11-NEXT: v_readfirstlane_b32 s14, v3
-; GFX11-NEXT: v_readfirstlane_b32 s15, v4
-; GFX11-NEXT: v_readfirstlane_b32 s12, v5
-; GFX11-NEXT: v_writelane_b32 v75, s36, 2
-; GFX11-NEXT: v_writelane_b32 v76, s100, 2
-; GFX11-NEXT: v_readfirstlane_b32 s13, v6
-; GFX11-NEXT: v_readfirstlane_b32 s10, v7
-; GFX11-NEXT: v_readfirstlane_b32 s11, v8
-; GFX11-NEXT: v_writelane_b32 v75, s37, 3
-; GFX11-NEXT: v_writelane_b32 v76, s101, 3
-; GFX11-NEXT: v_readfirstlane_b32 s8, v9
-; GFX11-NEXT: v_readfirstlane_b32 s9, v10
-; GFX11-NEXT: v_readfirstlane_b32 s6, v11
-; GFX11-NEXT: v_writelane_b32 v75, s38, 4
-; GFX11-NEXT: v_writelane_b32 v76, s102, 4
-; GFX11-NEXT: v_readfirstlane_b32 s7, v12
-; GFX11-NEXT: v_readfirstlane_b32 s4, v13
-; GFX11-NEXT: v_readfirstlane_b32 s5, v14
-; GFX11-NEXT: v_writelane_b32 v75, s39, 5
-; GFX11-NEXT: v_writelane_b32 v76, s103, 5
-; GFX11-NEXT: s_mov_b32 s99, 0
-; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
; GFX11-NEXT: s_clause 0x12
; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:72
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:68
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:64
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:60
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:56
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:52
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:48
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:44
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:40
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:36
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:32
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:28
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:24
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:20
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:16
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v74, s32
+; GFX11-NEXT: v_writelane_b32 v75, s34, 0
+; GFX11-NEXT: v_writelane_b32 v75, s35, 1
+; GFX11-NEXT: v_writelane_b32 v75, s36, 2
+; GFX11-NEXT: v_writelane_b32 v75, s37, 3
+; GFX11-NEXT: v_writelane_b32 v75, s38, 4
+; GFX11-NEXT: v_writelane_b32 v75, s39, 5
; GFX11-NEXT: v_writelane_b32 v75, s48, 6
-; GFX11-NEXT: v_writelane_b32 v76, s104, 6
-; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane
-; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane
; GFX11-NEXT: v_writelane_b32 v75, s49, 7
-; GFX11-NEXT: v_writelane_b32 v76, s30, 7
; GFX11-NEXT: v_writelane_b32 v75, s50, 8
-; GFX11-NEXT: v_writelane_b32 v76, s31, 8
; GFX11-NEXT: v_writelane_b32 v75, s51, 9
; GFX11-NEXT: v_writelane_b32 v75, s52, 10
; GFX11-NEXT: v_writelane_b32 v75, s53, 11
@@ -219154,6 +221383,34 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX11-NEXT: v_writelane_b32 v75, s87, 29
; GFX11-NEXT: v_writelane_b32 v75, s96, 30
; GFX11-NEXT: v_writelane_b32 v75, s97, 31
+; GFX11-NEXT: v_writelane_b32 v76, s98, 0
+; GFX11-NEXT: v_writelane_b32 v76, s99, 1
+; GFX11-NEXT: v_writelane_b32 v76, s100, 2
+; GFX11-NEXT: v_writelane_b32 v76, s101, 3
+; GFX11-NEXT: v_writelane_b32 v76, s102, 4
+; GFX11-NEXT: v_writelane_b32 v76, s103, 5
+; GFX11-NEXT: v_writelane_b32 v76, s104, 6
+; GFX11-NEXT: v_writelane_b32 v76, s30, 7
+; GFX11-NEXT: v_writelane_b32 v76, s31, 8
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
+; GFX11-NEXT: v_readfirstlane_b32 s40, v1
+; GFX11-NEXT: v_readfirstlane_b32 s41, v2
+; GFX11-NEXT: v_readfirstlane_b32 s14, v3
+; GFX11-NEXT: v_readfirstlane_b32 s15, v4
+; GFX11-NEXT: v_readfirstlane_b32 s12, v5
+; GFX11-NEXT: v_readfirstlane_b32 s13, v6
+; GFX11-NEXT: v_readfirstlane_b32 s10, v7
+; GFX11-NEXT: v_readfirstlane_b32 s11, v8
+; GFX11-NEXT: v_readfirstlane_b32 s8, v9
+; GFX11-NEXT: v_readfirstlane_b32 s9, v10
+; GFX11-NEXT: v_readfirstlane_b32 s6, v11
+; GFX11-NEXT: v_readfirstlane_b32 s7, v12
+; GFX11-NEXT: v_readfirstlane_b32 s4, v13
+; GFX11-NEXT: v_readfirstlane_b32 s5, v14
+; GFX11-NEXT: s_mov_b32 s99, 0
+; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo
+; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane
+; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane
; GFX11-NEXT: s_cbranch_scc0 .LBB99_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s27, 16
@@ -222643,20 +224900,35 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:8
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v48, v16
; GFX11-TRUE16-NEXT: s_clause 0x1
@@ -224991,9 +227263,11 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_writelane_b32 v42, s30, 0
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; VI-NEXT: v_writelane_b32 v42, s31, 1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; VI-NEXT: v_mov_b32_e32 v31, v17
; VI-NEXT: v_mov_b32_e32 v30, v16
; VI-NEXT: v_mov_b32_e32 v29, v15
@@ -225013,8 +227287,6 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; VI-NEXT: v_readfirstlane_b32 s30, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s31, v1
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB101_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB101_4
@@ -225634,9 +227906,12 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_writelane_b32 v43, s30, 0
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; GFX9-NEXT: v_writelane_b32 v43, s31, 1
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; GFX9-NEXT: v_mov_b32_e32 v31, v17
; GFX9-NEXT: v_mov_b32_e32 v30, v16
; GFX9-NEXT: v_mov_b32_e32 v29, v15
@@ -225656,9 +227931,6 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB101_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_cbranch_execnz .LBB101_4
@@ -235210,9 +237482,11 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_writelane_b32 v42, s30, 0
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; VI-NEXT: v_writelane_b32 v42, s31, 1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; VI-NEXT: v_mov_b32_e32 v31, v17
; VI-NEXT: v_mov_b32_e32 v30, v16
; VI-NEXT: v_mov_b32_e32 v29, v15
@@ -235232,8 +237506,6 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_readfirstlane_b32 s30, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s31, v1
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB105_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB105_4
@@ -235853,9 +238125,12 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_writelane_b32 v43, s30, 0
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; GFX9-NEXT: v_writelane_b32 v43, s31, 1
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; GFX9-NEXT: v_mov_b32_e32 v31, v17
; GFX9-NEXT: v_mov_b32_e32 v30, v16
; GFX9-NEXT: v_mov_b32_e32 v29, v15
@@ -235875,9 +238150,6 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB105_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_cbranch_execnz .LBB105_4
@@ -238840,14 +241112,6 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_writelane_b32 v40, s34, 0
; SI-NEXT: v_writelane_b32 v40, s35, 1
@@ -238879,6 +241143,20 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: v_writelane_b32 v40, s85, 27
; SI-NEXT: v_writelane_b32 v40, s86, 28
; SI-NEXT: v_writelane_b32 v40, s87, 29
+; SI-NEXT: v_writelane_b32 v40, s96, 30
+; SI-NEXT: v_writelane_b32 v40, s97, 31
+; SI-NEXT: v_writelane_b32 v40, s98, 32
+; SI-NEXT: v_writelane_b32 v40, s99, 33
+; SI-NEXT: v_writelane_b32 v40, s30, 34
+; SI-NEXT: v_writelane_b32 v40, s31, 35
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48
; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
; SI-NEXT: s_mov_b32 s60, s16
; SI-NEXT: s_waitcnt expcnt(0)
@@ -238914,15 +241192,36 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: v_writelane_b32 v41, s90, 17
; SI-NEXT: v_readfirstlane_b32 s34, v8
; SI-NEXT: v_writelane_b32 v41, s91, 18
-; SI-NEXT: v_writelane_b32 v40, s96, 30
; SI-NEXT: v_readfirstlane_b32 s35, v7
; SI-NEXT: v_writelane_b32 v41, s34, 19
-; SI-NEXT: v_writelane_b32 v40, s97, 31
; SI-NEXT: v_readfirstlane_b32 s36, v10
; SI-NEXT: v_writelane_b32 v41, s35, 20
-; SI-NEXT: v_writelane_b32 v40, s98, 32
; SI-NEXT: v_readfirstlane_b32 s37, v9
; SI-NEXT: v_writelane_b32 v41, s36, 21
+; SI-NEXT: v_readfirstlane_b32 s38, v12
+; SI-NEXT: v_writelane_b32 v41, s37, 22
+; SI-NEXT: v_readfirstlane_b32 s14, v30
+; SI-NEXT: v_readfirstlane_b32 s15, v29
+; SI-NEXT: v_readfirstlane_b32 s12, v28
+; SI-NEXT: v_readfirstlane_b32 s13, v27
+; SI-NEXT: v_readfirstlane_b32 s10, v26
+; SI-NEXT: v_readfirstlane_b32 s11, v25
+; SI-NEXT: v_readfirstlane_b32 s8, v24
+; SI-NEXT: v_readfirstlane_b32 s9, v23
+; SI-NEXT: v_readfirstlane_b32 s88, v22
+; SI-NEXT: v_readfirstlane_b32 s29, v21
+; SI-NEXT: v_readfirstlane_b32 s79, v20
+; SI-NEXT: v_readfirstlane_b32 s27, v19
+; SI-NEXT: v_readfirstlane_b32 s78, v18
+; SI-NEXT: v_readfirstlane_b32 s25, v17
+; SI-NEXT: v_readfirstlane_b32 s77, v16
+; SI-NEXT: v_readfirstlane_b32 s23, v15
+; SI-NEXT: v_readfirstlane_b32 s39, v14
+; SI-NEXT: v_readfirstlane_b32 s21, v13
+; SI-NEXT: v_readfirstlane_b32 s19, v11
+; SI-NEXT: v_readfirstlane_b32 s18, v1
+; SI-NEXT: v_writelane_b32 v41, s38, 23
+; SI-NEXT: v_writelane_b32 v41, s39, 24
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_readfirstlane_b32 s62, v31
; SI-NEXT: s_waitcnt vmcnt(6)
@@ -238951,33 +241250,6 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:8
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:4
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32
-; SI-NEXT: v_writelane_b32 v40, s99, 33
-; SI-NEXT: v_readfirstlane_b32 s38, v12
-; SI-NEXT: v_writelane_b32 v41, s37, 22
-; SI-NEXT: v_writelane_b32 v40, s30, 34
-; SI-NEXT: v_readfirstlane_b32 s14, v30
-; SI-NEXT: v_readfirstlane_b32 s15, v29
-; SI-NEXT: v_readfirstlane_b32 s12, v28
-; SI-NEXT: v_readfirstlane_b32 s13, v27
-; SI-NEXT: v_readfirstlane_b32 s10, v26
-; SI-NEXT: v_readfirstlane_b32 s11, v25
-; SI-NEXT: v_readfirstlane_b32 s8, v24
-; SI-NEXT: v_readfirstlane_b32 s9, v23
-; SI-NEXT: v_readfirstlane_b32 s88, v22
-; SI-NEXT: v_readfirstlane_b32 s29, v21
-; SI-NEXT: v_readfirstlane_b32 s79, v20
-; SI-NEXT: v_readfirstlane_b32 s27, v19
-; SI-NEXT: v_readfirstlane_b32 s78, v18
-; SI-NEXT: v_readfirstlane_b32 s25, v17
-; SI-NEXT: v_readfirstlane_b32 s77, v16
-; SI-NEXT: v_readfirstlane_b32 s23, v15
-; SI-NEXT: v_readfirstlane_b32 s39, v14
-; SI-NEXT: v_readfirstlane_b32 s21, v13
-; SI-NEXT: v_readfirstlane_b32 s19, v11
-; SI-NEXT: v_readfirstlane_b32 s18, v1
-; SI-NEXT: v_writelane_b32 v41, s38, 23
-; SI-NEXT: v_writelane_b32 v40, s31, 35
-; SI-NEXT: v_writelane_b32 v41, s39, 24
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_readfirstlane_b32 s58, v31
; SI-NEXT: s_waitcnt vmcnt(11)
@@ -239728,8 +242000,9 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; VI-NEXT: v_writelane_b32 v32, s37, 3
; VI-NEXT: v_writelane_b32 v32, s38, 4
; VI-NEXT: v_writelane_b32 v32, s39, 5
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; VI-NEXT: v_writelane_b32 v32, s30, 6
+; VI-NEXT: v_writelane_b32 v32, s31, 7
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; VI-NEXT: v_readfirstlane_b32 s47, v2
; VI-NEXT: v_readfirstlane_b32 s46, v3
; VI-NEXT: v_readfirstlane_b32 s45, v4
@@ -239749,7 +242022,6 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a
; VI-NEXT: v_readfirstlane_b32 s6, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v1
-; VI-NEXT: v_writelane_b32 v32, s31, 7
; VI-NEXT: s_cbranch_scc0 .LBB107_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB107_3
@@ -244363,8 +246635,9 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; VI-NEXT: v_writelane_b32 v32, s37, 3
; VI-NEXT: v_writelane_b32 v32, s38, 4
; VI-NEXT: v_writelane_b32 v32, s39, 5
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; VI-NEXT: v_writelane_b32 v32, s30, 6
+; VI-NEXT: v_writelane_b32 v32, s31, 7
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; VI-NEXT: v_readfirstlane_b32 s47, v2
; VI-NEXT: v_readfirstlane_b32 s46, v3
; VI-NEXT: v_readfirstlane_b32 s45, v4
@@ -244384,7 +246657,6 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s6, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v1
-; VI-NEXT: v_writelane_b32 v32, s31, 7
; VI-NEXT: s_cbranch_scc0 .LBB111_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB111_3
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
index 01e397d629ea9..a48eb27460f7d 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
@@ -30553,14 +30553,14 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) {
; SI-LABEL: bitcast_v16i16_to_v32i8:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v48, v15
-; SI-NEXT: v_mov_b32_e32 v49, v11
-; SI-NEXT: v_mov_b32_e32 v50, v7
-; SI-NEXT: v_mov_b32_e32 v51, v3
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v48, v15
+; SI-NEXT: v_mov_b32_e32 v49, v11
+; SI-NEXT: v_mov_b32_e32 v50, v7
+; SI-NEXT: v_mov_b32_e32 v51, v3
; SI-NEXT: v_mov_b32_e32 v32, v14
; SI-NEXT: v_mov_b32_e32 v37, v12
; SI-NEXT: v_mov_b32_e32 v33, v10
@@ -40102,11 +40102,11 @@ define inreg <32 x i8> @bitcast_v16bf16_to_v32i8_scalar(<16 x bfloat> inreg %a,
; SI-LABEL: bitcast_v16bf16_to_v32i8_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_mul_f32_e64 v24, 1.0, s17
; SI-NEXT: v_mul_f32_e64 v32, 1.0, s16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
index a431abbdeb288..7adaa6d3c3651 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
@@ -15733,6 +15733,10 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
; VI-LABEL: bitcast_v20i16_to_v40i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v9
@@ -15744,10 +15748,6 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) {
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v1
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr15
@@ -16534,8 +16534,9 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; SI-NEXT: v_writelane_b32 v8, s48, 6
; SI-NEXT: v_writelane_b32 v8, s49, 7
; SI-NEXT: v_writelane_b32 v8, s50, 8
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; SI-NEXT: v_writelane_b32 v8, s30, 9
+; SI-NEXT: v_writelane_b32 v8, s31, 10
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; SI-NEXT: v_readfirstlane_b32 s39, v6
; SI-NEXT: v_readfirstlane_b32 s48, v5
; SI-NEXT: v_readfirstlane_b32 s49, v4
@@ -16543,7 +16544,6 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; SI-NEXT: v_readfirstlane_b32 s35, v2
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s38, v1
-; SI-NEXT: v_writelane_b32 v8, s31, 10
; SI-NEXT: s_cbranch_scc0 .LBB49_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s4, s16, 0xffff
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index 6fb4517583e38..de18eec1ccc79 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -6673,8 +6673,8 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v19, s30, 0
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; VI-NEXT: v_writelane_b32 v19, s31, 1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; VI-NEXT: v_readfirstlane_b32 s30, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s31, v1
@@ -7007,8 +7007,8 @@ define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v20, s30, 0
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_writelane_b32 v20, s31, 1
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
@@ -8062,8 +8062,6 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) {
; SI-LABEL: bitcast_v16i32_to_v64i8:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -8080,6 +8078,8 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr46
@@ -8481,10 +8481,6 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) {
; VI-LABEL: bitcast_v16i32_to_v64i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; VI-NEXT: ; implicit-def: $vgpr17
-; VI-NEXT: ; kill: killed $vgpr17
-; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -8501,6 +8497,10 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; kill: killed $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr22
@@ -8812,10 +8812,6 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) {
; GFX9-LABEL: bitcast_v16i32_to_v64i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; GFX9-NEXT: ; implicit-def: $vgpr17
-; GFX9-NEXT: ; kill: killed $vgpr17
-; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -8832,6 +8828,10 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; GFX9-NEXT: ; implicit-def: $vgpr17
+; GFX9-NEXT: ; kill: killed $vgpr17
+; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr23
@@ -9735,12 +9735,12 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; SI-NEXT: v_writelane_b32 v4, s83, 25
; SI-NEXT: v_writelane_b32 v4, s84, 26
; SI-NEXT: v_writelane_b32 v4, s85, 27
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_writelane_b32 v4, s30, 28
+; SI-NEXT: v_writelane_b32 v4, s31, 29
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_readfirstlane_b32 s4, v1
; SI-NEXT: s_and_b64 s[6:7], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v2
-; SI-NEXT: v_writelane_b32 v4, s31, 29
; SI-NEXT: s_cbranch_scc0 .LBB25_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s38, s5, 24
@@ -10172,12 +10172,12 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; VI-NEXT: v_writelane_b32 v4, s65, 15
; VI-NEXT: v_writelane_b32 v4, s66, 16
; VI-NEXT: v_writelane_b32 v4, s67, 17
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: v_writelane_b32 v4, s30, 18
+; VI-NEXT: v_writelane_b32 v4, s31, 19
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
-; VI-NEXT: v_writelane_b32 v4, s31, 19
; VI-NEXT: s_cbranch_scc0 .LBB25_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s56, s5, 24
@@ -10582,12 +10582,12 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX9-NEXT: v_writelane_b32 v4, s53, 11
; GFX9-NEXT: v_writelane_b32 v4, s54, 12
; GFX9-NEXT: v_writelane_b32 v4, s55, 13
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_writelane_b32 v4, s30, 14
+; GFX9-NEXT: v_writelane_b32 v4, s31, 15
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: v_writelane_b32 v4, s31, 15
; GFX9-NEXT: s_cbranch_scc0 .LBB25_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
@@ -10960,8 +10960,6 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX11-NEXT: scratch_store_b32 off, v17, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v17, s34, 0
-; GFX11-NEXT: s_cmp_lg_u32 s28, 0
-; GFX11-NEXT: s_mov_b32 vcc_lo, 0
; GFX11-NEXT: v_writelane_b32 v17, s35, 1
; GFX11-NEXT: v_writelane_b32 v17, s36, 2
; GFX11-NEXT: v_writelane_b32 v17, s37, 3
@@ -10970,6 +10968,8 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX11-NEXT: v_writelane_b32 v17, s48, 6
; GFX11-NEXT: v_writelane_b32 v17, s30, 7
; GFX11-NEXT: v_writelane_b32 v17, s31, 8
+; GFX11-NEXT: s_cmp_lg_u32 s28, 0
+; GFX11-NEXT: s_mov_b32 vcc_lo, 0
; GFX11-NEXT: s_cbranch_scc0 .LBB25_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s27, 24
@@ -21564,8 +21564,8 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v19, s30, 0
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; VI-NEXT: v_writelane_b32 v19, s31, 1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; VI-NEXT: v_readfirstlane_b32 s30, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s31, v1
@@ -21898,8 +21898,8 @@ define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v20, s30, 0
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_writelane_b32 v20, s31, 1
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
@@ -22953,8 +22953,6 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) {
; SI-LABEL: bitcast_v16f32_to_v64i8:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -22971,6 +22969,8 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr46
@@ -23372,10 +23372,6 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) {
; VI-LABEL: bitcast_v16f32_to_v64i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; VI-NEXT: ; implicit-def: $vgpr17
-; VI-NEXT: ; kill: killed $vgpr17
-; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -23392,6 +23388,10 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; kill: killed $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr22
@@ -23703,10 +23703,6 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) {
; GFX9-LABEL: bitcast_v16f32_to_v64i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; GFX9-NEXT: ; implicit-def: $vgpr17
-; GFX9-NEXT: ; kill: killed $vgpr17
-; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -23723,6 +23719,10 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; GFX9-NEXT: ; implicit-def: $vgpr17
+; GFX9-NEXT: ; kill: killed $vgpr17
+; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr23
@@ -24610,12 +24610,12 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; SI-NEXT: v_writelane_b32 v40, s83, 25
; SI-NEXT: v_writelane_b32 v40, s84, 26
; SI-NEXT: v_writelane_b32 v40, s85, 27
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_writelane_b32 v40, s30, 28
+; SI-NEXT: v_writelane_b32 v40, s31, 29
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_readfirstlane_b32 s36, v1
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s37, v2
-; SI-NEXT: v_writelane_b32 v40, s31, 29
; SI-NEXT: s_cbranch_scc0 .LBB49_3
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s82, s37, 24
@@ -25073,6 +25073,21 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_writelane_b32 v63, s34, 0
; VI-NEXT: v_writelane_b32 v63, s35, 1
; VI-NEXT: v_writelane_b32 v63, s36, 2
@@ -25092,26 +25107,11 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; VI-NEXT: v_writelane_b32 v63, s66, 16
; VI-NEXT: v_writelane_b32 v63, s67, 17
; VI-NEXT: v_writelane_b32 v63, s30, 18
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: v_writelane_b32 v63, s31, 19
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB49_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s56, s5, 24
@@ -25517,6 +25517,21 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_writelane_b32 v63, s34, 0
; GFX9-NEXT: v_writelane_b32 v63, s35, 1
; GFX9-NEXT: v_writelane_b32 v63, s36, 2
@@ -25532,26 +25547,11 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX9-NEXT: v_writelane_b32 v63, s54, 12
; GFX9-NEXT: v_writelane_b32 v63, s55, 13
; GFX9-NEXT: v_writelane_b32 v63, s30, 14
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_writelane_b32 v63, s31, 15
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB49_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
@@ -25943,8 +25943,6 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX11-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v40, s34, 0
-; GFX11-NEXT: s_cmp_lg_u32 s28, 0
-; GFX11-NEXT: s_mov_b32 s42, 0
; GFX11-NEXT: v_writelane_b32 v40, s35, 1
; GFX11-NEXT: v_writelane_b32 v40, s36, 2
; GFX11-NEXT: v_writelane_b32 v40, s37, 3
@@ -25954,6 +25952,8 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX11-NEXT: v_writelane_b32 v40, s49, 7
; GFX11-NEXT: v_writelane_b32 v40, s30, 8
; GFX11-NEXT: v_writelane_b32 v40, s31, 9
+; GFX11-NEXT: s_cmp_lg_u32 s28, 0
+; GFX11-NEXT: s_mov_b32 s42, 0
; GFX11-NEXT: s_cbranch_scc0 .LBB49_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s43, s27, 24
@@ -35963,8 +35963,8 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v19, s30, 0
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; VI-NEXT: v_writelane_b32 v19, s31, 1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; VI-NEXT: v_readfirstlane_b32 s30, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s31, v1
@@ -36297,8 +36297,8 @@ define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a,
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v20, s30, 0
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_writelane_b32 v20, s31, 1
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
@@ -37352,8 +37352,6 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) {
; SI-LABEL: bitcast_v8i64_to_v64i8:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -37370,6 +37368,8 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr46
@@ -37771,10 +37771,6 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) {
; VI-LABEL: bitcast_v8i64_to_v64i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; VI-NEXT: ; implicit-def: $vgpr17
-; VI-NEXT: ; kill: killed $vgpr17
-; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -37791,6 +37787,10 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; kill: killed $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr22
@@ -38102,10 +38102,6 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) {
; GFX9-LABEL: bitcast_v8i64_to_v64i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; GFX9-NEXT: ; implicit-def: $vgpr17
-; GFX9-NEXT: ; kill: killed $vgpr17
-; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -38122,6 +38118,10 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; GFX9-NEXT: ; implicit-def: $vgpr17
+; GFX9-NEXT: ; kill: killed $vgpr17
+; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr23
@@ -39035,12 +39035,12 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; SI-NEXT: v_writelane_b32 v4, s83, 25
; SI-NEXT: v_writelane_b32 v4, s84, 26
; SI-NEXT: v_writelane_b32 v4, s85, 27
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_writelane_b32 v4, s30, 28
+; SI-NEXT: v_writelane_b32 v4, s31, 29
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_readfirstlane_b32 s4, v1
; SI-NEXT: s_and_b64 s[6:7], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v2
-; SI-NEXT: v_writelane_b32 v4, s31, 29
; SI-NEXT: s_cbranch_scc0 .LBB69_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s38, s5, 24
@@ -39472,12 +39472,12 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; VI-NEXT: v_writelane_b32 v4, s65, 15
; VI-NEXT: v_writelane_b32 v4, s66, 16
; VI-NEXT: v_writelane_b32 v4, s67, 17
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: v_writelane_b32 v4, s30, 18
+; VI-NEXT: v_writelane_b32 v4, s31, 19
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
-; VI-NEXT: v_writelane_b32 v4, s31, 19
; VI-NEXT: s_cbranch_scc0 .LBB69_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s56, s5, 24
@@ -39882,12 +39882,12 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX9-NEXT: v_writelane_b32 v4, s53, 11
; GFX9-NEXT: v_writelane_b32 v4, s54, 12
; GFX9-NEXT: v_writelane_b32 v4, s55, 13
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_writelane_b32 v4, s30, 14
+; GFX9-NEXT: v_writelane_b32 v4, s31, 15
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: v_writelane_b32 v4, s31, 15
; GFX9-NEXT: s_cbranch_scc0 .LBB69_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
@@ -40260,8 +40260,6 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX11-NEXT: scratch_store_b32 off, v17, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v17, s34, 0
-; GFX11-NEXT: s_cmp_lg_u32 s28, 0
-; GFX11-NEXT: s_mov_b32 vcc_lo, 0
; GFX11-NEXT: v_writelane_b32 v17, s35, 1
; GFX11-NEXT: v_writelane_b32 v17, s36, 2
; GFX11-NEXT: v_writelane_b32 v17, s37, 3
@@ -40270,6 +40268,8 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX11-NEXT: v_writelane_b32 v17, s48, 6
; GFX11-NEXT: v_writelane_b32 v17, s30, 7
; GFX11-NEXT: v_writelane_b32 v17, s31, 8
+; GFX11-NEXT: s_cmp_lg_u32 s28, 0
+; GFX11-NEXT: s_mov_b32 vcc_lo, 0
; GFX11-NEXT: s_cbranch_scc0 .LBB69_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s27, 24
@@ -49422,8 +49422,8 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v19, s30, 0
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; VI-NEXT: v_writelane_b32 v19, s31, 1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; VI-NEXT: v_readfirstlane_b32 s30, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s31, v1
@@ -49756,8 +49756,8 @@ define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v20, s30, 0
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_writelane_b32 v20, s31, 1
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
@@ -50811,8 +50811,6 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) {
; SI-LABEL: bitcast_v8f64_to_v64i8:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -50829,6 +50827,8 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr47
@@ -51222,10 +51222,6 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) {
; VI-LABEL: bitcast_v8f64_to_v64i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; VI-NEXT: ; implicit-def: $vgpr17
-; VI-NEXT: ; kill: killed $vgpr17
-; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -51242,6 +51238,10 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; kill: killed $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr22
@@ -51545,10 +51545,6 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) {
; GFX9-LABEL: bitcast_v8f64_to_v64i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; GFX9-NEXT: ; implicit-def: $vgpr17
-; GFX9-NEXT: ; kill: killed $vgpr17
-; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -51565,6 +51561,10 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; GFX9-NEXT: ; implicit-def: $vgpr17
+; GFX9-NEXT: ; kill: killed $vgpr17
+; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr23
@@ -52446,12 +52446,12 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; SI-NEXT: v_writelane_b32 v40, s85, 27
; SI-NEXT: v_writelane_b32 v40, s86, 28
; SI-NEXT: v_writelane_b32 v40, s87, 29
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_writelane_b32 v40, s30, 30
+; SI-NEXT: v_writelane_b32 v40, s31, 31
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; SI-NEXT: v_readfirstlane_b32 s4, v1
; SI-NEXT: s_and_b64 s[6:7], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v2
-; SI-NEXT: v_writelane_b32 v40, s31, 31
; SI-NEXT: s_cbranch_scc0 .LBB85_3
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s48, s5, 24
@@ -52913,12 +52913,12 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; VI-NEXT: v_writelane_b32 v40, s65, 15
; VI-NEXT: v_writelane_b32 v40, s66, 16
; VI-NEXT: v_writelane_b32 v40, s67, 17
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: v_writelane_b32 v40, s30, 18
+; VI-NEXT: v_writelane_b32 v40, s31, 19
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
-; VI-NEXT: v_writelane_b32 v40, s31, 19
; VI-NEXT: s_cbranch_scc0 .LBB85_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s56, s5, 24
@@ -53317,12 +53317,12 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX9-NEXT: v_writelane_b32 v40, s53, 11
; GFX9-NEXT: v_writelane_b32 v40, s54, 12
; GFX9-NEXT: v_writelane_b32 v40, s55, 13
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_writelane_b32 v40, s30, 14
+; GFX9-NEXT: v_writelane_b32 v40, s31, 15
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: v_writelane_b32 v40, s31, 15
; GFX9-NEXT: s_cbranch_scc0 .LBB85_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
@@ -53689,8 +53689,6 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX11-NEXT: scratch_store_b32 off, v33, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v33, s34, 0
-; GFX11-NEXT: s_cmp_lg_u32 s28, 0
-; GFX11-NEXT: s_mov_b32 s90, 0
; GFX11-NEXT: v_writelane_b32 v33, s35, 1
; GFX11-NEXT: v_writelane_b32 v33, s36, 2
; GFX11-NEXT: v_writelane_b32 v33, s37, 3
@@ -53700,6 +53698,8 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX11-NEXT: v_writelane_b32 v33, s49, 7
; GFX11-NEXT: v_writelane_b32 v33, s30, 8
; GFX11-NEXT: v_writelane_b32 v33, s31, 9
+; GFX11-NEXT: s_cmp_lg_u32 s28, 0
+; GFX11-NEXT: s_mov_b32 s90, 0
; GFX11-NEXT: s_cbranch_scc0 .LBB85_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s27, 24
@@ -58733,9 +58733,9 @@ define inreg <32 x half> @bitcast_v32i16_to_v32f16_scalar(<32 x i16> inreg %a, i
; SI-LABEL: bitcast_v32i16_to_v32f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; SI-NEXT: v_mov_b32_e32 v54, v17
; SI-NEXT: v_mov_b32_e32 v53, v16
; SI-NEXT: v_mov_b32_e32 v52, v15
@@ -61978,7 +61978,6 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; SI-LABEL: bitcast_v32bf16_to_v32i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -61995,6 +61994,7 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: s_waitcnt expcnt(6)
; SI-NEXT: v_mul_f32_e64 v57, 1.0, s16
@@ -62247,8 +62247,8 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v20, s30, 0
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; VI-NEXT: v_writelane_b32 v20, s31, 1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; VI-NEXT: v_readfirstlane_b32 s30, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s31, v1
@@ -62581,8 +62581,8 @@ define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v20, s30, 0
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_writelane_b32 v20, s31, 1
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
@@ -64359,8 +64359,24 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
;
; VI-LABEL: bitcast_v32i16_to_v64i8:
; VI: ; %bb.0:
-; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; kill: killed $vgpr19
@@ -64381,22 +64397,6 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; kill: killed $vgpr19
; VI-NEXT: ; implicit-def: $vgpr19
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; kill: killed $vgpr17
; VI-NEXT: ; implicit-def: $vgpr17
@@ -64829,10 +64829,6 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
; GFX9-LABEL: bitcast_v32i16_to_v64i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; GFX9-NEXT: ; implicit-def: $vgpr17
-; GFX9-NEXT: ; kill: killed $vgpr17
-; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -64849,6 +64845,10 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; GFX9-NEXT: ; implicit-def: $vgpr17
+; GFX9-NEXT: ; kill: killed $vgpr17
+; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr23
@@ -65760,8 +65760,8 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; SI-NEXT: v_writelane_b32 v20, s98, 32
; SI-NEXT: v_writelane_b32 v20, s99, 33
; SI-NEXT: v_writelane_b32 v20, s30, 34
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: v_writelane_b32 v20, s31, 35
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: s_mov_b32 s93, s18
; SI-NEXT: s_mov_b32 s31, s17
; SI-NEXT: v_readfirstlane_b32 s59, v18
@@ -66427,12 +66427,12 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; VI-NEXT: v_writelane_b32 v4, s65, 15
; VI-NEXT: v_writelane_b32 v4, s66, 16
; VI-NEXT: v_writelane_b32 v4, s67, 17
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: v_writelane_b32 v4, s30, 18
+; VI-NEXT: v_writelane_b32 v4, s31, 19
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
-; VI-NEXT: v_writelane_b32 v4, s31, 19
; VI-NEXT: s_cbranch_scc0 .LBB97_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s56, s5, 24
@@ -66887,6 +66887,21 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_writelane_b32 v63, s34, 0
; GFX9-NEXT: v_writelane_b32 v63, s35, 1
; GFX9-NEXT: v_writelane_b32 v63, s36, 2
@@ -66902,26 +66917,11 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX9-NEXT: v_writelane_b32 v63, s54, 12
; GFX9-NEXT: v_writelane_b32 v63, s55, 13
; GFX9-NEXT: v_writelane_b32 v63, s30, 14
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_writelane_b32 v63, s31, 15
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB97_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
@@ -67313,8 +67313,6 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX11-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v40, s34, 0
-; GFX11-NEXT: s_cmp_lg_u32 s28, 0
-; GFX11-NEXT: s_mov_b32 s42, 0
; GFX11-NEXT: v_writelane_b32 v40, s35, 1
; GFX11-NEXT: v_writelane_b32 v40, s36, 2
; GFX11-NEXT: v_writelane_b32 v40, s37, 3
@@ -67324,6 +67322,8 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX11-NEXT: v_writelane_b32 v40, s49, 7
; GFX11-NEXT: v_writelane_b32 v40, s30, 8
; GFX11-NEXT: v_writelane_b32 v40, s31, 9
+; GFX11-NEXT: s_cmp_lg_u32 s28, 0
+; GFX11-NEXT: s_mov_b32 s42, 0
; GFX11-NEXT: s_cbranch_scc0 .LBB97_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s43, s27, 24
@@ -74579,7 +74579,6 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; SI-LABEL: bitcast_v32bf16_to_v32f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -74596,6 +74595,7 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_mul_f32_e64 v32, 1.0, s16
; SI-NEXT: v_mul_f32_e64 v33, 1.0, s17
@@ -74893,8 +74893,8 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v20, s30, 0
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; VI-NEXT: v_writelane_b32 v20, s31, 1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; VI-NEXT: v_readfirstlane_b32 s30, v0
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s31, v1
@@ -75227,8 +75227,8 @@ define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v20, s30, 0
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_writelane_b32 v20, s31, 1
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
@@ -77045,6 +77045,22 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) {
; VI-LABEL: bitcast_v32f16_to_v64i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; kill: killed $vgpr17
@@ -77067,22 +77083,6 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) {
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1
; VI-NEXT: ; kill: killed $vgpr17
; VI-NEXT: ; implicit-def: $vgpr17
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: ; implicit-def: $vgpr22
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: ; implicit-def: $vgpr55
@@ -77397,10 +77397,6 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) {
; GFX9-LABEL: bitcast_v32f16_to_v64i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; GFX9-NEXT: ; implicit-def: $vgpr17
-; GFX9-NEXT: ; kill: killed $vgpr17
-; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -77417,6 +77413,10 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; GFX9-NEXT: ; implicit-def: $vgpr17
+; GFX9-NEXT: ; kill: killed $vgpr17
+; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr23
@@ -78295,6 +78295,10 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v40, s34, 0
; SI-NEXT: v_writelane_b32 v40, s35, 1
+; SI-NEXT: v_writelane_b32 v40, s36, 2
+; SI-NEXT: v_writelane_b32 v40, s37, 3
+; SI-NEXT: v_writelane_b32 v40, s30, 4
+; SI-NEXT: v_writelane_b32 v40, s31, 5
; SI-NEXT: v_cvt_f16_f32_e32 v21, s17
; SI-NEXT: v_cvt_f16_f32_e32 v20, v2
; SI-NEXT: v_cvt_f16_f32_e32 v22, v1
@@ -78327,12 +78331,8 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; SI-NEXT: v_cvt_f16_f32_e32 v13, s26
; SI-NEXT: v_cvt_f16_f32_e32 v17, s29
; SI-NEXT: v_cvt_f16_f32_e32 v16, s28
-; SI-NEXT: v_writelane_b32 v40, s36, 2
-; SI-NEXT: v_writelane_b32 v40, s37, 3
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
-; SI-NEXT: v_writelane_b32 v40, s30, 4
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_writelane_b32 v40, s31, 5
; SI-NEXT: s_cbranch_scc0 .LBB105_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_readfirstlane_b32 s4, v21
@@ -78902,6 +78902,21 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_writelane_b32 v63, s34, 0
; VI-NEXT: v_writelane_b32 v63, s35, 1
; VI-NEXT: v_writelane_b32 v63, s36, 2
@@ -78921,26 +78936,11 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; VI-NEXT: v_writelane_b32 v63, s66, 16
; VI-NEXT: v_writelane_b32 v63, s67, 17
; VI-NEXT: v_writelane_b32 v63, s30, 18
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: v_writelane_b32 v63, s31, 19
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB105_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s75, s5, 24
@@ -79399,6 +79399,21 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_writelane_b32 v63, s34, 0
; GFX9-NEXT: v_writelane_b32 v63, s35, 1
; GFX9-NEXT: v_writelane_b32 v63, s36, 2
@@ -79414,26 +79429,11 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX9-NEXT: v_writelane_b32 v63, s54, 12
; GFX9-NEXT: v_writelane_b32 v63, s55, 13
; GFX9-NEXT: v_writelane_b32 v63, s30, 14
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_writelane_b32 v63, s31, 15
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB105_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
@@ -79826,8 +79826,6 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX11-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v40, s34, 0
-; GFX11-NEXT: s_cmp_lg_u32 s28, 0
-; GFX11-NEXT: s_mov_b32 s42, 0
; GFX11-NEXT: v_writelane_b32 v40, s35, 1
; GFX11-NEXT: v_writelane_b32 v40, s36, 2
; GFX11-NEXT: v_writelane_b32 v40, s37, 3
@@ -79837,6 +79835,8 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX11-NEXT: v_writelane_b32 v40, s49, 7
; GFX11-NEXT: v_writelane_b32 v40, s30, 8
; GFX11-NEXT: v_writelane_b32 v40, s31, 9
+; GFX11-NEXT: s_cmp_lg_u32 s28, 0
+; GFX11-NEXT: s_mov_b32 s42, 0
; GFX11-NEXT: s_cbranch_scc0 .LBB105_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s43, s27, 24
@@ -82605,8 +82605,6 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:72
-; SI-NEXT: v_readfirstlane_b32 s46, v20
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v32, s34, 0
; SI-NEXT: v_writelane_b32 v32, s35, 1
@@ -82616,6 +82614,8 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; SI-NEXT: v_writelane_b32 v32, s39, 5
; SI-NEXT: v_writelane_b32 v32, s30, 6
; SI-NEXT: v_writelane_b32 v32, s31, 7
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:72
+; SI-NEXT: v_readfirstlane_b32 s46, v20
; SI-NEXT: v_readfirstlane_b32 s74, v30
; SI-NEXT: v_readfirstlane_b32 s61, v29
; SI-NEXT: v_readfirstlane_b32 s63, v28
@@ -85271,10 +85271,6 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) {
; VI-LABEL: bitcast_v32bf16_to_v64i8:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; VI-NEXT: ; implicit-def: $vgpr17
-; VI-NEXT: ; kill: killed $vgpr17
-; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -85291,6 +85287,10 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; VI-NEXT: ; implicit-def: $vgpr17
+; VI-NEXT: ; kill: killed $vgpr17
+; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr22
@@ -85875,12 +85875,6 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) {
; GFX9-LABEL: bitcast_v32bf16_to_v64i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; GFX9-NEXT: ; implicit-def: $vgpr17
-; GFX9-NEXT: ; kill: killed $vgpr17
-; GFX9-NEXT: ; implicit-def: $vgpr17
-; GFX9-NEXT: ; kill: killed $vgpr17
-; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -85897,6 +85891,12 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; GFX9-NEXT: ; implicit-def: $vgpr17
+; GFX9-NEXT: ; kill: killed $vgpr17
+; GFX9-NEXT: ; implicit-def: $vgpr17
+; GFX9-NEXT: ; kill: killed $vgpr17
+; GFX9-NEXT: ; implicit-def: $vgpr17
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr23
@@ -87562,7 +87562,6 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; SI-LABEL: bitcast_v32bf16_to_v64i8_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -87579,6 +87578,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_mul_f32_e64 v19, 1.0, s17
; SI-NEXT: v_mul_f32_e32 v33, 1.0, v2
@@ -88167,6 +88167,21 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_writelane_b32 v63, s34, 0
; VI-NEXT: v_writelane_b32 v63, s35, 1
; VI-NEXT: v_writelane_b32 v63, s36, 2
@@ -88186,26 +88201,11 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; VI-NEXT: v_writelane_b32 v63, s66, 16
; VI-NEXT: v_writelane_b32 v63, s67, 17
; VI-NEXT: v_writelane_b32 v63, s30, 18
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: v_writelane_b32 v63, s31, 19
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; VI-NEXT: v_readfirstlane_b32 s4, v1
; VI-NEXT: s_and_b64 s[6:7], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s5, v2
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB109_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s56, s5, 24
@@ -88898,12 +88898,12 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX9-NEXT: v_writelane_b32 v4, s53, 11
; GFX9-NEXT: v_writelane_b32 v4, s54, 12
; GFX9-NEXT: v_writelane_b32 v4, s55, 13
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_writelane_b32 v4, s30, 14
+; GFX9-NEXT: v_writelane_b32 v4, s31, 15
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: v_writelane_b32 v4, s31, 15
; GFX9-NEXT: s_cbranch_scc0 .LBB109_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s92, s5, 24
@@ -89621,8 +89621,6 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-NEXT: scratch_store_b32 off, v17, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v17, s34, 0
-; GFX11-NEXT: s_cmp_lg_u32 s28, 0
-; GFX11-NEXT: s_mov_b32 vcc_lo, 0
; GFX11-NEXT: v_writelane_b32 v17, s35, 1
; GFX11-NEXT: v_writelane_b32 v17, s36, 2
; GFX11-NEXT: v_writelane_b32 v17, s37, 3
@@ -89633,6 +89631,8 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-NEXT: v_writelane_b32 v17, s51, 8
; GFX11-NEXT: v_writelane_b32 v17, s30, 9
; GFX11-NEXT: v_writelane_b32 v17, s31, 10
+; GFX11-NEXT: s_cmp_lg_u32 s28, 0
+; GFX11-NEXT: s_mov_b32 vcc_lo, 0
; GFX11-NEXT: s_cbranch_scc0 .LBB109_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s62, s27, 24
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
index 5d4df4bde1af8..07c574944ad4e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
@@ -656,36 +656,36 @@ define inreg <18 x i32> @bitcast_v18f32_to_v18i32_scalar(<18 x float> inreg %a,
; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v32, s36, 0
+; GFX11-NEXT: v_writelane_b32 v32, s37, 1
+; GFX11-NEXT: v_writelane_b32 v32, s38, 2
+; GFX11-NEXT: v_writelane_b32 v32, s39, 3
+; GFX11-NEXT: v_writelane_b32 v32, s48, 4
+; GFX11-NEXT: v_writelane_b32 v32, s49, 5
+; GFX11-NEXT: v_writelane_b32 v32, s50, 6
+; GFX11-NEXT: v_writelane_b32 v32, s51, 7
+; GFX11-NEXT: v_writelane_b32 v32, s52, 8
+; GFX11-NEXT: v_writelane_b32 v32, s53, 9
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: s_mov_b32 s53, s29
+; GFX11-NEXT: s_mov_b32 s52, s28
+; GFX11-NEXT: s_mov_b32 s51, s27
+; GFX11-NEXT: s_mov_b32 s50, s26
+; GFX11-NEXT: s_mov_b32 s49, s25
+; GFX11-NEXT: s_mov_b32 s48, s24
; GFX11-NEXT: s_mov_b32 s47, s23
; GFX11-NEXT: s_mov_b32 s46, s22
; GFX11-NEXT: s_mov_b32 s45, s21
-; GFX11-NEXT: v_writelane_b32 v32, s37, 1
; GFX11-NEXT: s_mov_b32 s44, s20
; GFX11-NEXT: s_mov_b32 s43, s19
; GFX11-NEXT: s_mov_b32 s42, s18
; GFX11-NEXT: s_mov_b32 s41, s17
-; GFX11-NEXT: v_writelane_b32 v32, s38, 2
; GFX11-NEXT: s_mov_b32 s40, s16
+; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s38, s2
; GFX11-NEXT: s_mov_b32 s37, s1
; GFX11-NEXT: s_mov_b32 s36, s0
-; GFX11-NEXT: v_writelane_b32 v32, s39, 3
-; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s0, 0
; GFX11-NEXT: s_and_b32 s1, vcc_lo, exec_lo
-; GFX11-NEXT: v_writelane_b32 v32, s48, 4
-; GFX11-NEXT: s_mov_b32 s48, s24
-; GFX11-NEXT: v_writelane_b32 v32, s49, 5
-; GFX11-NEXT: s_mov_b32 s49, s25
-; GFX11-NEXT: v_writelane_b32 v32, s50, 6
-; GFX11-NEXT: s_mov_b32 s50, s26
-; GFX11-NEXT: v_writelane_b32 v32, s51, 7
-; GFX11-NEXT: s_mov_b32 s51, s27
-; GFX11-NEXT: v_writelane_b32 v32, s52, 8
-; GFX11-NEXT: s_mov_b32 s52, s28
-; GFX11-NEXT: v_writelane_b32 v32, s53, 9
-; GFX11-NEXT: s_mov_b32 s53, s29
; GFX11-NEXT: s_cbranch_scc0 .LBB3_3
; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
@@ -2075,36 +2075,36 @@ define inreg <18 x i32> @bitcast_v9f64_to_v18i32_scalar(<9 x double> inreg %a, i
; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v32, s36, 0
+; GFX11-NEXT: v_writelane_b32 v32, s37, 1
+; GFX11-NEXT: v_writelane_b32 v32, s38, 2
+; GFX11-NEXT: v_writelane_b32 v32, s39, 3
+; GFX11-NEXT: v_writelane_b32 v32, s48, 4
+; GFX11-NEXT: v_writelane_b32 v32, s49, 5
+; GFX11-NEXT: v_writelane_b32 v32, s50, 6
+; GFX11-NEXT: v_writelane_b32 v32, s51, 7
+; GFX11-NEXT: v_writelane_b32 v32, s52, 8
+; GFX11-NEXT: v_writelane_b32 v32, s53, 9
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: s_mov_b32 s53, s29
+; GFX11-NEXT: s_mov_b32 s52, s28
+; GFX11-NEXT: s_mov_b32 s51, s27
+; GFX11-NEXT: s_mov_b32 s50, s26
+; GFX11-NEXT: s_mov_b32 s49, s25
+; GFX11-NEXT: s_mov_b32 s48, s24
; GFX11-NEXT: s_mov_b32 s47, s23
; GFX11-NEXT: s_mov_b32 s46, s22
; GFX11-NEXT: s_mov_b32 s45, s21
-; GFX11-NEXT: v_writelane_b32 v32, s37, 1
; GFX11-NEXT: s_mov_b32 s44, s20
; GFX11-NEXT: s_mov_b32 s43, s19
; GFX11-NEXT: s_mov_b32 s42, s18
; GFX11-NEXT: s_mov_b32 s41, s17
-; GFX11-NEXT: v_writelane_b32 v32, s38, 2
; GFX11-NEXT: s_mov_b32 s40, s16
+; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s38, s2
; GFX11-NEXT: s_mov_b32 s37, s1
; GFX11-NEXT: s_mov_b32 s36, s0
-; GFX11-NEXT: v_writelane_b32 v32, s39, 3
-; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s0, 0
; GFX11-NEXT: s_and_b32 s1, vcc_lo, exec_lo
-; GFX11-NEXT: v_writelane_b32 v32, s48, 4
-; GFX11-NEXT: s_mov_b32 s48, s24
-; GFX11-NEXT: v_writelane_b32 v32, s49, 5
-; GFX11-NEXT: s_mov_b32 s49, s25
-; GFX11-NEXT: v_writelane_b32 v32, s50, 6
-; GFX11-NEXT: s_mov_b32 s50, s26
-; GFX11-NEXT: v_writelane_b32 v32, s51, 7
-; GFX11-NEXT: s_mov_b32 s51, s27
-; GFX11-NEXT: v_writelane_b32 v32, s52, 8
-; GFX11-NEXT: s_mov_b32 s52, s28
-; GFX11-NEXT: v_writelane_b32 v32, s53, 9
-; GFX11-NEXT: s_mov_b32 s53, s29
; GFX11-NEXT: s_cbranch_scc0 .LBB11_3
; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
@@ -3806,7 +3806,6 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) {
; GFX9-LABEL: bitcast_v36i16_to_v18i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -3823,6 +3822,7 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: v_mov_b32_e32 v33, v16
; GFX9-NEXT: v_mov_b32_e32 v41, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -4121,13 +4121,13 @@ define inreg <18 x i32> @bitcast_v36i16_to_v18i32_scalar(<36 x i16> inreg %a, i3
; SI-LABEL: bitcast_v36i16_to_v18i32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22
; SI-NEXT: v_mov_b32_e32 v32, v20
; SI-NEXT: v_mov_b32_e32 v33, v18
; SI-NEXT: v_mov_b32_e32 v34, v16
@@ -4710,7 +4710,6 @@ define <36 x half> @bitcast_v18i32_to_v36f16(<18 x i32> %a, i32 %b) {
; SI-LABEL: bitcast_v18i32_to_v36f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
@@ -4718,6 +4717,7 @@ define <36 x half> @bitcast_v18i32_to_v36f16(<18 x i32> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr43
@@ -6669,7 +6669,6 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) {
; GFX9-LABEL: bitcast_v36f16_to_v18i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -6686,6 +6685,7 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: v_mov_b32_e32 v33, v16
; GFX9-NEXT: v_mov_b32_e32 v41, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -7970,36 +7970,36 @@ define inreg <9 x i64> @bitcast_v18f32_to_v9i64_scalar(<18 x float> inreg %a, i3
; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v32, s36, 0
+; GFX11-NEXT: v_writelane_b32 v32, s37, 1
+; GFX11-NEXT: v_writelane_b32 v32, s38, 2
+; GFX11-NEXT: v_writelane_b32 v32, s39, 3
+; GFX11-NEXT: v_writelane_b32 v32, s48, 4
+; GFX11-NEXT: v_writelane_b32 v32, s49, 5
+; GFX11-NEXT: v_writelane_b32 v32, s50, 6
+; GFX11-NEXT: v_writelane_b32 v32, s51, 7
+; GFX11-NEXT: v_writelane_b32 v32, s52, 8
+; GFX11-NEXT: v_writelane_b32 v32, s53, 9
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: s_mov_b32 s53, s29
+; GFX11-NEXT: s_mov_b32 s52, s28
+; GFX11-NEXT: s_mov_b32 s51, s27
+; GFX11-NEXT: s_mov_b32 s50, s26
+; GFX11-NEXT: s_mov_b32 s49, s25
+; GFX11-NEXT: s_mov_b32 s48, s24
; GFX11-NEXT: s_mov_b32 s47, s23
; GFX11-NEXT: s_mov_b32 s46, s22
; GFX11-NEXT: s_mov_b32 s45, s21
-; GFX11-NEXT: v_writelane_b32 v32, s37, 1
; GFX11-NEXT: s_mov_b32 s44, s20
; GFX11-NEXT: s_mov_b32 s43, s19
; GFX11-NEXT: s_mov_b32 s42, s18
; GFX11-NEXT: s_mov_b32 s41, s17
-; GFX11-NEXT: v_writelane_b32 v32, s38, 2
; GFX11-NEXT: s_mov_b32 s40, s16
+; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s38, s2
; GFX11-NEXT: s_mov_b32 s37, s1
; GFX11-NEXT: s_mov_b32 s36, s0
-; GFX11-NEXT: v_writelane_b32 v32, s39, 3
-; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s0, 0
; GFX11-NEXT: s_and_b32 s1, vcc_lo, exec_lo
-; GFX11-NEXT: v_writelane_b32 v32, s48, 4
-; GFX11-NEXT: s_mov_b32 s48, s24
-; GFX11-NEXT: v_writelane_b32 v32, s49, 5
-; GFX11-NEXT: s_mov_b32 s49, s25
-; GFX11-NEXT: v_writelane_b32 v32, s50, 6
-; GFX11-NEXT: s_mov_b32 s50, s26
-; GFX11-NEXT: v_writelane_b32 v32, s51, 7
-; GFX11-NEXT: s_mov_b32 s51, s27
-; GFX11-NEXT: v_writelane_b32 v32, s52, 8
-; GFX11-NEXT: s_mov_b32 s52, s28
-; GFX11-NEXT: v_writelane_b32 v32, s53, 9
-; GFX11-NEXT: s_mov_b32 s53, s29
; GFX11-NEXT: s_cbranch_scc0 .LBB21_3
; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
@@ -8731,36 +8731,36 @@ define inreg <9 x double> @bitcast_v18f32_to_v9f64_scalar(<18 x float> inreg %a,
; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v32, s36, 0
+; GFX11-NEXT: v_writelane_b32 v32, s37, 1
+; GFX11-NEXT: v_writelane_b32 v32, s38, 2
+; GFX11-NEXT: v_writelane_b32 v32, s39, 3
+; GFX11-NEXT: v_writelane_b32 v32, s48, 4
+; GFX11-NEXT: v_writelane_b32 v32, s49, 5
+; GFX11-NEXT: v_writelane_b32 v32, s50, 6
+; GFX11-NEXT: v_writelane_b32 v32, s51, 7
+; GFX11-NEXT: v_writelane_b32 v32, s52, 8
+; GFX11-NEXT: v_writelane_b32 v32, s53, 9
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: s_mov_b32 s53, s29
+; GFX11-NEXT: s_mov_b32 s52, s28
+; GFX11-NEXT: s_mov_b32 s51, s27
+; GFX11-NEXT: s_mov_b32 s50, s26
+; GFX11-NEXT: s_mov_b32 s49, s25
+; GFX11-NEXT: s_mov_b32 s48, s24
; GFX11-NEXT: s_mov_b32 s47, s23
; GFX11-NEXT: s_mov_b32 s46, s22
; GFX11-NEXT: s_mov_b32 s45, s21
-; GFX11-NEXT: v_writelane_b32 v32, s37, 1
; GFX11-NEXT: s_mov_b32 s44, s20
; GFX11-NEXT: s_mov_b32 s43, s19
; GFX11-NEXT: s_mov_b32 s42, s18
; GFX11-NEXT: s_mov_b32 s41, s17
-; GFX11-NEXT: v_writelane_b32 v32, s38, 2
; GFX11-NEXT: s_mov_b32 s40, s16
+; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s38, s2
; GFX11-NEXT: s_mov_b32 s37, s1
; GFX11-NEXT: s_mov_b32 s36, s0
-; GFX11-NEXT: v_writelane_b32 v32, s39, 3
-; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s0, 0
; GFX11-NEXT: s_and_b32 s1, vcc_lo, exec_lo
-; GFX11-NEXT: v_writelane_b32 v32, s48, 4
-; GFX11-NEXT: s_mov_b32 s48, s24
-; GFX11-NEXT: v_writelane_b32 v32, s49, 5
-; GFX11-NEXT: s_mov_b32 s49, s25
-; GFX11-NEXT: v_writelane_b32 v32, s50, 6
-; GFX11-NEXT: s_mov_b32 s50, s26
-; GFX11-NEXT: v_writelane_b32 v32, s51, 7
-; GFX11-NEXT: s_mov_b32 s51, s27
-; GFX11-NEXT: v_writelane_b32 v32, s52, 8
-; GFX11-NEXT: s_mov_b32 s52, s28
-; GFX11-NEXT: v_writelane_b32 v32, s53, 9
-; GFX11-NEXT: s_mov_b32 s53, s29
; GFX11-NEXT: s_cbranch_scc0 .LBB25_3
; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
@@ -9077,36 +9077,36 @@ define inreg <18 x float> @bitcast_v9f64_to_v18f32_scalar(<9 x double> inreg %a,
; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v32, s36, 0
+; GFX11-NEXT: v_writelane_b32 v32, s37, 1
+; GFX11-NEXT: v_writelane_b32 v32, s38, 2
+; GFX11-NEXT: v_writelane_b32 v32, s39, 3
+; GFX11-NEXT: v_writelane_b32 v32, s48, 4
+; GFX11-NEXT: v_writelane_b32 v32, s49, 5
+; GFX11-NEXT: v_writelane_b32 v32, s50, 6
+; GFX11-NEXT: v_writelane_b32 v32, s51, 7
+; GFX11-NEXT: v_writelane_b32 v32, s52, 8
+; GFX11-NEXT: v_writelane_b32 v32, s53, 9
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: s_mov_b32 s53, s29
+; GFX11-NEXT: s_mov_b32 s52, s28
+; GFX11-NEXT: s_mov_b32 s51, s27
+; GFX11-NEXT: s_mov_b32 s50, s26
+; GFX11-NEXT: s_mov_b32 s49, s25
+; GFX11-NEXT: s_mov_b32 s48, s24
; GFX11-NEXT: s_mov_b32 s47, s23
; GFX11-NEXT: s_mov_b32 s46, s22
; GFX11-NEXT: s_mov_b32 s45, s21
-; GFX11-NEXT: v_writelane_b32 v32, s37, 1
; GFX11-NEXT: s_mov_b32 s44, s20
; GFX11-NEXT: s_mov_b32 s43, s19
; GFX11-NEXT: s_mov_b32 s42, s18
; GFX11-NEXT: s_mov_b32 s41, s17
-; GFX11-NEXT: v_writelane_b32 v32, s38, 2
; GFX11-NEXT: s_mov_b32 s40, s16
+; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s38, s2
; GFX11-NEXT: s_mov_b32 s37, s1
; GFX11-NEXT: s_mov_b32 s36, s0
-; GFX11-NEXT: v_writelane_b32 v32, s39, 3
-; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s0, 0
; GFX11-NEXT: s_and_b32 s1, vcc_lo, exec_lo
-; GFX11-NEXT: v_writelane_b32 v32, s48, 4
-; GFX11-NEXT: s_mov_b32 s48, s24
-; GFX11-NEXT: v_writelane_b32 v32, s49, 5
-; GFX11-NEXT: s_mov_b32 s49, s25
-; GFX11-NEXT: v_writelane_b32 v32, s50, 6
-; GFX11-NEXT: s_mov_b32 s50, s26
-; GFX11-NEXT: v_writelane_b32 v32, s51, 7
-; GFX11-NEXT: s_mov_b32 s51, s27
-; GFX11-NEXT: v_writelane_b32 v32, s52, 8
-; GFX11-NEXT: s_mov_b32 s52, s28
-; GFX11-NEXT: v_writelane_b32 v32, s53, 9
-; GFX11-NEXT: s_mov_b32 s53, s29
; GFX11-NEXT: s_cbranch_scc0 .LBB27_3
; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
@@ -10939,7 +10939,6 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) {
; GFX9-LABEL: bitcast_v36i16_to_v18f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -10956,6 +10955,7 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: v_mov_b32_e32 v33, v16
; GFX9-NEXT: v_mov_b32_e32 v41, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -11254,13 +11254,13 @@ define inreg <18 x float> @bitcast_v36i16_to_v18f32_scalar(<36 x i16> inreg %a,
; SI-LABEL: bitcast_v36i16_to_v18f32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22
; SI-NEXT: v_mov_b32_e32 v32, v20
; SI-NEXT: v_mov_b32_e32 v33, v18
; SI-NEXT: v_mov_b32_e32 v34, v16
@@ -11843,7 +11843,6 @@ define <36 x half> @bitcast_v18f32_to_v36f16(<18 x float> %a, i32 %b) {
; SI-LABEL: bitcast_v18f32_to_v36f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
@@ -11851,6 +11850,7 @@ define <36 x half> @bitcast_v18f32_to_v36f16(<18 x float> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr43
@@ -13940,7 +13940,6 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) {
; GFX9-LABEL: bitcast_v36f16_to_v18f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -13957,6 +13956,7 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: v_mov_b32_e32 v33, v16
; GFX9-NEXT: v_mov_b32_e32 v41, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -15547,36 +15547,36 @@ define inreg <9 x i64> @bitcast_v9f64_to_v9i64_scalar(<9 x double> inreg %a, i32
; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v32, s36, 0
+; GFX11-NEXT: v_writelane_b32 v32, s37, 1
+; GFX11-NEXT: v_writelane_b32 v32, s38, 2
+; GFX11-NEXT: v_writelane_b32 v32, s39, 3
+; GFX11-NEXT: v_writelane_b32 v32, s48, 4
+; GFX11-NEXT: v_writelane_b32 v32, s49, 5
+; GFX11-NEXT: v_writelane_b32 v32, s50, 6
+; GFX11-NEXT: v_writelane_b32 v32, s51, 7
+; GFX11-NEXT: v_writelane_b32 v32, s52, 8
+; GFX11-NEXT: v_writelane_b32 v32, s53, 9
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: s_mov_b32 s53, s29
+; GFX11-NEXT: s_mov_b32 s52, s28
+; GFX11-NEXT: s_mov_b32 s51, s27
+; GFX11-NEXT: s_mov_b32 s50, s26
+; GFX11-NEXT: s_mov_b32 s49, s25
+; GFX11-NEXT: s_mov_b32 s48, s24
; GFX11-NEXT: s_mov_b32 s47, s23
; GFX11-NEXT: s_mov_b32 s46, s22
; GFX11-NEXT: s_mov_b32 s45, s21
-; GFX11-NEXT: v_writelane_b32 v32, s37, 1
; GFX11-NEXT: s_mov_b32 s44, s20
; GFX11-NEXT: s_mov_b32 s43, s19
; GFX11-NEXT: s_mov_b32 s42, s18
; GFX11-NEXT: s_mov_b32 s41, s17
-; GFX11-NEXT: v_writelane_b32 v32, s38, 2
; GFX11-NEXT: s_mov_b32 s40, s16
+; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s38, s2
; GFX11-NEXT: s_mov_b32 s37, s1
; GFX11-NEXT: s_mov_b32 s36, s0
-; GFX11-NEXT: v_writelane_b32 v32, s39, 3
-; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s0, 0
; GFX11-NEXT: s_and_b32 s1, vcc_lo, exec_lo
-; GFX11-NEXT: v_writelane_b32 v32, s48, 4
-; GFX11-NEXT: s_mov_b32 s48, s24
-; GFX11-NEXT: v_writelane_b32 v32, s49, 5
-; GFX11-NEXT: s_mov_b32 s49, s25
-; GFX11-NEXT: v_writelane_b32 v32, s50, 6
-; GFX11-NEXT: s_mov_b32 s50, s26
-; GFX11-NEXT: v_writelane_b32 v32, s51, 7
-; GFX11-NEXT: s_mov_b32 s51, s27
-; GFX11-NEXT: v_writelane_b32 v32, s52, 8
-; GFX11-NEXT: s_mov_b32 s52, s28
-; GFX11-NEXT: v_writelane_b32 v32, s53, 9
-; GFX11-NEXT: s_mov_b32 s53, s29
; GFX11-NEXT: s_cbranch_scc0 .LBB39_3
; GFX11-NEXT: ; %bb.1: ; %Flow
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
@@ -17288,7 +17288,6 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) {
; GFX9-LABEL: bitcast_v36i16_to_v9i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -17305,6 +17304,7 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: v_mov_b32_e32 v33, v16
; GFX9-NEXT: v_mov_b32_e32 v41, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -17603,13 +17603,13 @@ define inreg <9 x i64> @bitcast_v36i16_to_v9i64_scalar(<36 x i16> inreg %a, i32
; SI-LABEL: bitcast_v36i16_to_v9i64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22
; SI-NEXT: v_mov_b32_e32 v32, v20
; SI-NEXT: v_mov_b32_e32 v33, v18
; SI-NEXT: v_mov_b32_e32 v34, v16
@@ -18192,7 +18192,6 @@ define <36 x half> @bitcast_v9i64_to_v36f16(<9 x i64> %a, i32 %b) {
; SI-LABEL: bitcast_v9i64_to_v36f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
@@ -18200,6 +18199,7 @@ define <36 x half> @bitcast_v9i64_to_v36f16(<9 x i64> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr43
@@ -20161,7 +20161,6 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) {
; GFX9-LABEL: bitcast_v36f16_to_v9i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -20178,6 +20177,7 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: v_mov_b32_e32 v33, v16
; GFX9-NEXT: v_mov_b32_e32 v41, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -22864,7 +22864,6 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) {
; GFX9-LABEL: bitcast_v36i16_to_v9f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -22881,6 +22880,7 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: v_mov_b32_e32 v33, v16
; GFX9-NEXT: v_mov_b32_e32 v41, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -23179,13 +23179,13 @@ define inreg <9 x double> @bitcast_v36i16_to_v9f64_scalar(<36 x i16> inreg %a, i
; SI-LABEL: bitcast_v36i16_to_v9f64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22
; SI-NEXT: v_mov_b32_e32 v32, v20
; SI-NEXT: v_mov_b32_e32 v33, v18
; SI-NEXT: v_mov_b32_e32 v34, v16
@@ -23768,7 +23768,6 @@ define <36 x half> @bitcast_v9f64_to_v36f16(<9 x double> %a, i32 %b) {
; SI-LABEL: bitcast_v9f64_to_v36f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
@@ -23776,6 +23775,7 @@ define <36 x half> @bitcast_v9f64_to_v36f16(<9 x double> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr43
@@ -25787,7 +25787,6 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) {
; GFX9-LABEL: bitcast_v36f16_to_v9f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -25804,6 +25803,7 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v17
; GFX9-NEXT: v_mov_b32_e32 v33, v16
; GFX9-NEXT: v_mov_b32_e32 v41, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -27586,8 +27586,6 @@ define inreg <36 x half> @bitcast_v36i16_to_v36f16_scalar(<36 x i16> inreg %a, i
; SI-LABEL: bitcast_v36i16_to_v36f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
@@ -27599,6 +27597,8 @@ define inreg <36 x half> @bitcast_v36i16_to_v36f16_scalar(<36 x i16> inreg %a, i
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: s_cbranch_scc0 .LBB57_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_waitcnt expcnt(4)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
index 44cfd6c28ca6a..1648368af460a 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
@@ -4019,7 +4019,6 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) {
; GFX9-LABEL: bitcast_v40i16_to_v20i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -4036,6 +4035,7 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: v_mov_b32_e32 v33, v18
; GFX9-NEXT: v_mov_b32_e32 v43, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -4376,7 +4376,6 @@ define inreg <20 x i32> @bitcast_v40i16_to_v20i32_scalar(<40 x i16> inreg %a, i3
; SI-LABEL: bitcast_v40i16_to_v20i32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
@@ -4387,6 +4386,7 @@ define inreg <20 x i32> @bitcast_v40i16_to_v20i32_scalar(<40 x i16> inreg %a, i3
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; SI-NEXT: v_mov_b32_e32 v32, v24
; SI-NEXT: v_mov_b32_e32 v33, v22
; SI-NEXT: v_mov_b32_e32 v34, v20
@@ -4913,85 +4913,157 @@ define inreg <20 x i32> @bitcast_v40i16_to_v20i32_scalar(<40 x i16> inreg %a, i3
; GFX11-TRUE16-LABEL: bitcast_v40i16_to_v20i32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44
; GFX11-TRUE16-NEXT: s_clause 0xa
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16
@@ -5289,7 +5361,6 @@ define <40 x half> @bitcast_v20i32_to_v40f16(<20 x i32> %a, i32 %b) {
; SI-LABEL: bitcast_v20i32_to_v40f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
@@ -5303,6 +5374,7 @@ define <40 x half> @bitcast_v20i32_to_v40f16(<20 x i32> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr57
@@ -7495,7 +7567,6 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) {
; GFX9-LABEL: bitcast_v40f16_to_v20i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -7512,6 +7583,7 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: v_mov_b32_e32 v33, v18
; GFX9-NEXT: v_mov_b32_e32 v43, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -8519,85 +8591,157 @@ define inreg <20 x i32> @bitcast_v40f16_to_v20i32_scalar(<40 x half> inreg %a, i
; GFX11-TRUE16-LABEL: bitcast_v40f16_to_v20i32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44
; GFX11-TRUE16-NEXT: s_clause 0xa
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16
@@ -12218,7 +12362,6 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) {
; GFX9-LABEL: bitcast_v40i16_to_v20f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -12235,6 +12378,7 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: v_mov_b32_e32 v33, v18
; GFX9-NEXT: v_mov_b32_e32 v43, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -12575,7 +12719,6 @@ define inreg <20 x float> @bitcast_v40i16_to_v20f32_scalar(<40 x i16> inreg %a,
; SI-LABEL: bitcast_v40i16_to_v20f32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
@@ -12586,6 +12729,7 @@ define inreg <20 x float> @bitcast_v40i16_to_v20f32_scalar(<40 x i16> inreg %a,
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; SI-NEXT: v_mov_b32_e32 v32, v24
; SI-NEXT: v_mov_b32_e32 v33, v22
; SI-NEXT: v_mov_b32_e32 v34, v20
@@ -13112,85 +13256,157 @@ define inreg <20 x float> @bitcast_v40i16_to_v20f32_scalar(<40 x i16> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v40i16_to_v20f32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44
; GFX11-TRUE16-NEXT: s_clause 0xa
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16
@@ -13488,7 +13704,6 @@ define <40 x half> @bitcast_v20f32_to_v40f16(<20 x float> %a, i32 %b) {
; SI-LABEL: bitcast_v20f32_to_v40f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
@@ -13502,6 +13717,7 @@ define <40 x half> @bitcast_v20f32_to_v40f16(<20 x float> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr57
@@ -14276,6 +14492,9 @@ define inreg <40 x half> @bitcast_v20f32_to_v40f16_scalar(<20 x float> inreg %a,
; SI-LABEL: bitcast_v20f32_to_v40f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; SI-NEXT: v_readfirstlane_b32 s11, v1
; SI-NEXT: v_readfirstlane_b32 s10, v2
@@ -14284,9 +14503,6 @@ define inreg <40 x half> @bitcast_v20f32_to_v40f16_scalar(<20 x float> inreg %a,
; SI-NEXT: v_readfirstlane_b32 s6, v5
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v6
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB33_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -15808,7 +16024,6 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) {
; GFX9-LABEL: bitcast_v40f16_to_v20f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -15825,6 +16040,7 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: v_mov_b32_e32 v33, v18
; GFX9-NEXT: v_mov_b32_e32 v43, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -16832,85 +17048,157 @@ define inreg <20 x float> @bitcast_v40f16_to_v20f32_scalar(<40 x half> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v40f16_to_v20f32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44
; GFX11-TRUE16-NEXT: s_clause 0xa
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16
@@ -19727,7 +20015,6 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) {
; GFX9-LABEL: bitcast_v40i16_to_v10i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -19744,6 +20031,7 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: v_mov_b32_e32 v33, v18
; GFX9-NEXT: v_mov_b32_e32 v43, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -20084,7 +20372,6 @@ define inreg <10 x i64> @bitcast_v40i16_to_v10i64_scalar(<40 x i16> inreg %a, i3
; SI-LABEL: bitcast_v40i16_to_v10i64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
@@ -20095,6 +20382,7 @@ define inreg <10 x i64> @bitcast_v40i16_to_v10i64_scalar(<40 x i16> inreg %a, i3
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; SI-NEXT: v_mov_b32_e32 v32, v24
; SI-NEXT: v_mov_b32_e32 v33, v22
; SI-NEXT: v_mov_b32_e32 v34, v20
@@ -20621,85 +20909,157 @@ define inreg <10 x i64> @bitcast_v40i16_to_v10i64_scalar(<40 x i16> inreg %a, i3
; GFX11-TRUE16-LABEL: bitcast_v40i16_to_v10i64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44
; GFX11-TRUE16-NEXT: s_clause 0xa
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16
@@ -20997,7 +21357,6 @@ define <40 x half> @bitcast_v10i64_to_v40f16(<10 x i64> %a, i32 %b) {
; SI-LABEL: bitcast_v10i64_to_v40f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
@@ -21011,6 +21370,7 @@ define <40 x half> @bitcast_v10i64_to_v40f16(<10 x i64> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr57
@@ -23213,7 +23573,6 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) {
; GFX9-LABEL: bitcast_v40f16_to_v10i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -23230,6 +23589,7 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: v_mov_b32_e32 v33, v18
; GFX9-NEXT: v_mov_b32_e32 v43, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -24237,85 +24597,157 @@ define inreg <10 x i64> @bitcast_v40f16_to_v10i64_scalar(<40 x half> inreg %a, i
; GFX11-TRUE16-LABEL: bitcast_v40f16_to_v10i64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44
; GFX11-TRUE16-NEXT: s_clause 0xa
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16
@@ -26466,7 +26898,6 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) {
; GFX9-LABEL: bitcast_v40i16_to_v10f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -26483,6 +26914,7 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: v_mov_b32_e32 v33, v18
; GFX9-NEXT: v_mov_b32_e32 v43, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -26823,7 +27255,6 @@ define inreg <10 x double> @bitcast_v40i16_to_v10f64_scalar(<40 x i16> inreg %a,
; SI-LABEL: bitcast_v40i16_to_v10f64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
@@ -26834,6 +27265,7 @@ define inreg <10 x double> @bitcast_v40i16_to_v10f64_scalar(<40 x i16> inreg %a,
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; SI-NEXT: v_mov_b32_e32 v32, v24
; SI-NEXT: v_mov_b32_e32 v33, v22
; SI-NEXT: v_mov_b32_e32 v34, v20
@@ -27360,85 +27792,157 @@ define inreg <10 x double> @bitcast_v40i16_to_v10f64_scalar(<40 x i16> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v40i16_to_v10f64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44
; GFX11-TRUE16-NEXT: s_clause 0xa
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16
@@ -27736,7 +28240,6 @@ define <40 x half> @bitcast_v10f64_to_v40f16(<10 x double> %a, i32 %b) {
; SI-LABEL: bitcast_v10f64_to_v40f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
@@ -27750,6 +28253,7 @@ define <40 x half> @bitcast_v10f64_to_v40f16(<10 x double> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v21
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr57
@@ -28484,6 +28988,10 @@ define inreg <40 x half> @bitcast_v10f64_to_v40f16_scalar(<10 x double> inreg %a
; SI-LABEL: bitcast_v10f64_to_v40f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; SI-NEXT: v_readfirstlane_b32 s8, v1
; SI-NEXT: v_readfirstlane_b32 s9, v2
@@ -28492,10 +29000,6 @@ define inreg <40 x half> @bitcast_v10f64_to_v40f16_scalar(<10 x double> inreg %a
; SI-NEXT: v_readfirstlane_b32 s4, v5
; SI-NEXT: s_and_b64 s[10:11], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v6
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB53_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s10, s5, 16
@@ -29989,7 +30493,6 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) {
; GFX9-LABEL: bitcast_v40f16_to_v10f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -30006,6 +30509,7 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v19
; GFX9-NEXT: v_mov_b32_e32 v33, v18
; GFX9-NEXT: v_mov_b32_e32 v43, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -31013,85 +31517,157 @@ define inreg <10 x double> @bitcast_v40f16_to_v10f64_scalar(<40 x half> inreg %a
; GFX11-TRUE16-LABEL: bitcast_v40f16_to_v10f64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44
; GFX11-TRUE16-NEXT: s_clause 0xa
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16
@@ -32303,8 +32879,6 @@ define inreg <40 x half> @bitcast_v40i16_to_v40f16_scalar(<40 x i16> inreg %a, i
; SI-LABEL: bitcast_v40i16_to_v40f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -32321,6 +32895,8 @@ define inreg <40 x half> @bitcast_v40i16_to_v40f16_scalar(<40 x i16> inreg %a, i
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: s_cbranch_scc0 .LBB57_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_cvt_f32_f16_e32 v30, v15
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
index 87d5157b3c340..010c7f18fa513 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
@@ -4340,7 +4340,6 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) {
; GFX9-LABEL: bitcast_v44i16_to_v22i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -4357,6 +4356,7 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: v_mov_b32_e32 v33, v20
; GFX9-NEXT: v_mov_b32_e32 v45, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -4739,7 +4739,6 @@ define inreg <22 x i32> @bitcast_v44i16_to_v22i32_scalar(<44 x i16> inreg %a, i3
; SI-LABEL: bitcast_v44i16_to_v22i32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
@@ -4754,6 +4753,7 @@ define inreg <22 x i32> @bitcast_v44i16_to_v22i32_scalar(<44 x i16> inreg %a, i3
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; SI-NEXT: v_mov_b32_e32 v32, v28
; SI-NEXT: v_mov_b32_e32 v33, v26
; SI-NEXT: v_mov_b32_e32 v34, v24
@@ -5328,87 +5328,161 @@ define inreg <22 x i32> @bitcast_v44i16_to_v22i32_scalar(<44 x i16> inreg %a, i3
; GFX11-TRUE16-LABEL: bitcast_v44i16_to_v22i32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52
; GFX11-TRUE16-NEXT: s_clause 0xc
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
@@ -5722,10 +5796,6 @@ define <44 x half> @bitcast_v22i32_to_v44f16(<22 x i32> %a, i32 %b) {
; SI-LABEL: bitcast_v22i32_to_v44f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -5742,6 +5812,10 @@ define <44 x half> @bitcast_v22i32_to_v44f16(<22 x i32> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr63
@@ -8182,7 +8256,6 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) {
; GFX9-LABEL: bitcast_v44f16_to_v22i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -8199,6 +8272,7 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: v_mov_b32_e32 v33, v20
; GFX9-NEXT: v_mov_b32_e32 v45, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -9310,87 +9384,161 @@ define inreg <22 x i32> @bitcast_v44f16_to_v22i32_scalar(<44 x half> inreg %a, i
; GFX11-TRUE16-LABEL: bitcast_v44f16_to_v22i32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52
; GFX11-TRUE16-NEXT: s_clause 0xc
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
@@ -13303,7 +13451,6 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) {
; GFX9-LABEL: bitcast_v44i16_to_v22f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -13320,6 +13467,7 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: v_mov_b32_e32 v33, v20
; GFX9-NEXT: v_mov_b32_e32 v45, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -13702,7 +13850,6 @@ define inreg <22 x float> @bitcast_v44i16_to_v22f32_scalar(<44 x i16> inreg %a,
; SI-LABEL: bitcast_v44i16_to_v22f32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
@@ -13717,6 +13864,7 @@ define inreg <22 x float> @bitcast_v44i16_to_v22f32_scalar(<44 x i16> inreg %a,
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; SI-NEXT: v_mov_b32_e32 v32, v28
; SI-NEXT: v_mov_b32_e32 v33, v26
; SI-NEXT: v_mov_b32_e32 v34, v24
@@ -14291,87 +14439,161 @@ define inreg <22 x float> @bitcast_v44i16_to_v22f32_scalar(<44 x i16> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v44i16_to_v22f32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52
; GFX11-TRUE16-NEXT: s_clause 0xc
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
@@ -14685,10 +14907,6 @@ define <44 x half> @bitcast_v22f32_to_v44f16(<22 x float> %a, i32 %b) {
; SI-LABEL: bitcast_v22f32_to_v44f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -14705,6 +14923,10 @@ define <44 x half> @bitcast_v22f32_to_v44f16(<22 x float> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr63
@@ -15560,6 +15782,14 @@ define inreg <44 x half> @bitcast_v22f32_to_v44f16_scalar(<22 x float> inreg %a,
; SI-LABEL: bitcast_v22f32_to_v44f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; SI-NEXT: v_readfirstlane_b32 s13, v1
; SI-NEXT: v_readfirstlane_b32 s12, v2
@@ -15570,14 +15800,6 @@ define inreg <44 x half> @bitcast_v22f32_to_v44f16_scalar(<22 x float> inreg %a,
; SI-NEXT: v_readfirstlane_b32 s6, v7
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v8
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB33_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -17278,7 +17500,6 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) {
; GFX9-LABEL: bitcast_v44f16_to_v22f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -17295,6 +17516,7 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: v_mov_b32_e32 v33, v20
; GFX9-NEXT: v_mov_b32_e32 v45, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -18406,87 +18628,161 @@ define inreg <22 x float> @bitcast_v44f16_to_v22f32_scalar(<44 x half> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v44f16_to_v22f32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52
; GFX11-TRUE16-NEXT: s_clause 0xc
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
@@ -21552,7 +21848,6 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) {
; GFX9-LABEL: bitcast_v44i16_to_v11i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -21569,6 +21864,7 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: v_mov_b32_e32 v33, v20
; GFX9-NEXT: v_mov_b32_e32 v45, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -21951,7 +22247,6 @@ define inreg <11 x i64> @bitcast_v44i16_to_v11i64_scalar(<44 x i16> inreg %a, i3
; SI-LABEL: bitcast_v44i16_to_v11i64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
@@ -21966,6 +22261,7 @@ define inreg <11 x i64> @bitcast_v44i16_to_v11i64_scalar(<44 x i16> inreg %a, i3
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; SI-NEXT: v_mov_b32_e32 v32, v28
; SI-NEXT: v_mov_b32_e32 v33, v26
; SI-NEXT: v_mov_b32_e32 v34, v24
@@ -22540,87 +22836,161 @@ define inreg <11 x i64> @bitcast_v44i16_to_v11i64_scalar(<44 x i16> inreg %a, i3
; GFX11-TRUE16-LABEL: bitcast_v44i16_to_v11i64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52
; GFX11-TRUE16-NEXT: s_clause 0xc
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
@@ -22934,10 +23304,6 @@ define <44 x half> @bitcast_v11i64_to_v44f16(<11 x i64> %a, i32 %b) {
; SI-LABEL: bitcast_v11i64_to_v44f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -22954,6 +23320,10 @@ define <44 x half> @bitcast_v11i64_to_v44f16(<11 x i64> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr63
@@ -25406,7 +25776,6 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) {
; GFX9-LABEL: bitcast_v44f16_to_v11i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -25423,6 +25792,7 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: v_mov_b32_e32 v33, v20
; GFX9-NEXT: v_mov_b32_e32 v45, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -26534,87 +26904,161 @@ define inreg <11 x i64> @bitcast_v44f16_to_v11i64_scalar(<44 x half> inreg %a, i
; GFX11-TRUE16-LABEL: bitcast_v44f16_to_v11i64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52
; GFX11-TRUE16-NEXT: s_clause 0xc
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
@@ -28968,7 +29412,6 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) {
; GFX9-LABEL: bitcast_v44i16_to_v11f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -28985,6 +29428,7 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: v_mov_b32_e32 v33, v20
; GFX9-NEXT: v_mov_b32_e32 v45, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -29367,7 +29811,6 @@ define inreg <11 x double> @bitcast_v44i16_to_v11f64_scalar(<44 x i16> inreg %a,
; SI-LABEL: bitcast_v44i16_to_v11f64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
@@ -29382,6 +29825,7 @@ define inreg <11 x double> @bitcast_v44i16_to_v11f64_scalar(<44 x i16> inreg %a,
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; SI-NEXT: v_mov_b32_e32 v32, v28
; SI-NEXT: v_mov_b32_e32 v33, v26
; SI-NEXT: v_mov_b32_e32 v34, v24
@@ -29956,87 +30400,161 @@ define inreg <11 x double> @bitcast_v44i16_to_v11f64_scalar(<44 x i16> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v44i16_to_v11f64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52
; GFX11-TRUE16-NEXT: s_clause 0xc
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
@@ -30350,10 +30868,6 @@ define <44 x half> @bitcast_v11f64_to_v44f16(<11 x double> %a, i32 %b) {
; SI-LABEL: bitcast_v11f64_to_v44f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -30370,6 +30884,10 @@ define <44 x half> @bitcast_v11f64_to_v44f16(<11 x double> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v23
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr63
@@ -31181,6 +31699,15 @@ define inreg <44 x half> @bitcast_v11f64_to_v44f16_scalar(<11 x double> inreg %a
; SI-LABEL: bitcast_v11f64_to_v44f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; SI-NEXT: v_readfirstlane_b32 s10, v1
; SI-NEXT: v_readfirstlane_b32 s11, v2
@@ -31191,15 +31718,6 @@ define inreg <44 x half> @bitcast_v11f64_to_v44f16_scalar(<11 x double> inreg %a
; SI-NEXT: v_readfirstlane_b32 s4, v7
; SI-NEXT: s_and_b64 s[12:13], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v8
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB53_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s12, s5, 16
@@ -32867,7 +33385,6 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) {
; GFX9-LABEL: bitcast_v44f16_to_v11f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -32884,6 +33401,7 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, v21
; GFX9-NEXT: v_mov_b32_e32 v33, v20
; GFX9-NEXT: v_mov_b32_e32 v45, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v32
@@ -33995,87 +34513,161 @@ define inreg <11 x double> @bitcast_v44f16_to_v11f64_scalar(<44 x half> inreg %a
; GFX11-TRUE16-LABEL: bitcast_v44f16_to_v11f64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:180
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:52
; GFX11-TRUE16-NEXT: s_clause 0xc
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v3 :: v_dual_mov_b32 v186, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v1 :: v_dual_mov_b32 v188, v0
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16
@@ -35429,7 +36021,6 @@ define inreg <44 x half> @bitcast_v44i16_to_v44f16_scalar(<44 x i16> inreg %a, i
; SI-LABEL: bitcast_v44i16_to_v44f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
@@ -35446,7 +36037,8 @@ define inreg <44 x half> @bitcast_v44i16_to_v44f16_scalar(<44 x i16> inreg %a, i
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: s_cbranch_scc0 .LBB57_4
@@ -37436,7 +38028,6 @@ define inreg <44 x i16> @bitcast_v44f16_to_v44i16_scalar(<44 x half> inreg %a, i
; SI-LABEL: bitcast_v44f16_to_v44i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
@@ -37453,6 +38044,7 @@ define inreg <44 x i16> @bitcast_v44f16_to_v44i16_scalar(<44 x half> inreg %a, i
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: s_waitcnt expcnt(6)
; SI-NEXT: v_cvt_f16_f32_e32 v57, v2
; SI-NEXT: s_waitcnt expcnt(5)
@@ -37500,7 +38092,7 @@ define inreg <44 x i16> @bitcast_v44f16_to_v44i16_scalar(<44 x half> inreg %a, i
; SI-NEXT: v_cvt_f16_f32_e32 v38, s25
; SI-NEXT: v_cvt_f16_f32_e32 v16, s26
; SI-NEXT: v_cvt_f16_f32_e32 v29, s29
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: s_cbranch_scc0 .LBB59_4
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
index 6c1f1249ffb7f..3fbedf74d9e3a 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
@@ -2440,8 +2440,8 @@ define <48 x i16> @bitcast_v24i32_to_v48i16(<24 x i32> %a, i32 %b) {
; SI-LABEL: bitcast_v24i32_to_v48i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr51
@@ -3195,8 +3195,9 @@ define inreg <48 x i16> @bitcast_v24i32_to_v48i16_scalar(<24 x i32> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v12, s34, 0
; SI-NEXT: v_writelane_b32 v12, s35, 1
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; SI-NEXT: v_writelane_b32 v12, s30, 2
+; SI-NEXT: v_writelane_b32 v12, s31, 3
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; SI-NEXT: v_readfirstlane_b32 s12, v1
; SI-NEXT: v_readfirstlane_b32 s13, v2
; SI-NEXT: v_readfirstlane_b32 s10, v3
@@ -3208,7 +3209,6 @@ define inreg <48 x i16> @bitcast_v24i32_to_v48i16_scalar(<24 x i32> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v9
; SI-NEXT: s_and_b64 s[14:15], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v10
-; SI-NEXT: v_writelane_b32 v12, s31, 3
; SI-NEXT: s_cbranch_scc0 .LBB13_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s88, s5, 16
@@ -5655,6 +5655,10 @@ define inreg <24 x i32> @bitcast_v48i16_to_v24i32_scalar(<48 x i16> inreg %a, i3
; GFX9-LABEL: bitcast_v48i16_to_v24i32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v9
; GFX9-NEXT: v_mov_b32_e32 v33, v8
; GFX9-NEXT: v_mov_b32_e32 v34, v7
@@ -5680,10 +5684,6 @@ define inreg <24 x i32> @bitcast_v48i16_to_v24i32_scalar(<48 x i16> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34
@@ -5805,89 +5805,165 @@ define inreg <24 x i32> @bitcast_v48i16_to_v24i32_scalar(<48 x i16> inreg %a, i3
; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v24i32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xe
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0
@@ -6216,16 +6292,7 @@ end:
define <48 x half> @bitcast_v24i32_to_v48f16(<24 x i32> %a, i32 %b) {
; SI-LABEL: bitcast_v24i32_to_v48f16:
; SI: ; %bb.0:
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; kill: killed $vgpr35
-; SI-NEXT: ; kill: killed $vgpr34
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; kill: killed $vgpr35
-; SI-NEXT: ; kill: killed $vgpr34
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -6246,6 +6313,11 @@ define <48 x half> @bitcast_v24i32_to_v48f16(<24 x i32> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; kill: killed $vgpr35
; SI-NEXT: ; kill: killed $vgpr34
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; kill: killed $vgpr34
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr30
@@ -6290,6 +6362,10 @@ define <48 x half> @bitcast_v24i32_to_v48f16(<24 x i32> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; kill: killed $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; kill: killed $vgpr35
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -7211,6 +7287,7 @@ define inreg <48 x half> @bitcast_v24i32_to_v48f16_scalar(<24 x i32> inreg %a, i
; SI-LABEL: bitcast_v24i32_to_v48f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; SI-NEXT: v_readfirstlane_b32 s15, v1
; SI-NEXT: v_readfirstlane_b32 s14, v2
@@ -7223,7 +7300,6 @@ define inreg <48 x half> @bitcast_v24i32_to_v48f16_scalar(<24 x i32> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s6, v9
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v10
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB17_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -10061,6 +10137,10 @@ define inreg <24 x i32> @bitcast_v48f16_to_v24i32_scalar(<48 x half> inreg %a, i
; GFX9-LABEL: bitcast_v48f16_to_v24i32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v9
; GFX9-NEXT: v_mov_b32_e32 v33, v8
; GFX9-NEXT: v_mov_b32_e32 v34, v7
@@ -10086,10 +10166,6 @@ define inreg <24 x i32> @bitcast_v48f16_to_v24i32_scalar(<48 x half> inreg %a, i
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34
@@ -10213,89 +10289,165 @@ define inreg <24 x i32> @bitcast_v48f16_to_v24i32_scalar(<48 x half> inreg %a, i
; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v24i32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xe
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0
@@ -12185,8 +12337,8 @@ define <48 x i16> @bitcast_v24f32_to_v48i16(<24 x float> %a, i32 %b) {
; SI-LABEL: bitcast_v24f32_to_v48i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr51
@@ -12910,6 +13062,9 @@ define inreg <48 x i16> @bitcast_v24f32_to_v48i16_scalar(<24 x float> inreg %a,
; SI-LABEL: bitcast_v24f32_to_v48i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; SI-NEXT: v_mov_b32_e32 v23, s16
; SI-NEXT: v_mov_b32_e32 v24, s17
@@ -12926,9 +13081,6 @@ define inreg <48 x i16> @bitcast_v24f32_to_v48i16_scalar(<24 x float> inreg %a,
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_mov_b32_e32 v11, s28
; SI-NEXT: v_mov_b32_e32 v12, s29
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB29_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_lshr_b64 v[25:26], v[9:10], 16
@@ -15492,6 +15644,10 @@ define inreg <24 x float> @bitcast_v48i16_to_v24f32_scalar(<48 x i16> inreg %a,
; GFX9-LABEL: bitcast_v48i16_to_v24f32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v9
; GFX9-NEXT: v_mov_b32_e32 v33, v8
; GFX9-NEXT: v_mov_b32_e32 v34, v7
@@ -15517,10 +15673,6 @@ define inreg <24 x float> @bitcast_v48i16_to_v24f32_scalar(<48 x i16> inreg %a,
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34
@@ -15642,89 +15794,165 @@ define inreg <24 x float> @bitcast_v48i16_to_v24f32_scalar(<48 x i16> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v24f32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xe
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0
@@ -16053,16 +16281,7 @@ end:
define <48 x half> @bitcast_v24f32_to_v48f16(<24 x float> %a, i32 %b) {
; SI-LABEL: bitcast_v24f32_to_v48f16:
; SI: ; %bb.0:
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; kill: killed $vgpr35
-; SI-NEXT: ; kill: killed $vgpr34
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; kill: killed $vgpr35
-; SI-NEXT: ; kill: killed $vgpr34
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -16083,6 +16302,11 @@ define <48 x half> @bitcast_v24f32_to_v48f16(<24 x float> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; kill: killed $vgpr35
; SI-NEXT: ; kill: killed $vgpr34
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; kill: killed $vgpr34
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr30
@@ -16127,6 +16351,10 @@ define <48 x half> @bitcast_v24f32_to_v48f16(<24 x float> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; kill: killed $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; kill: killed $vgpr35
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -17024,18 +17252,6 @@ define inreg <48 x half> @bitcast_v24f32_to_v48f16_scalar(<24 x float> inreg %a,
; SI-LABEL: bitcast_v24f32_to_v48f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
-; SI-NEXT: v_readfirstlane_b32 s15, v1
-; SI-NEXT: v_readfirstlane_b32 s14, v2
-; SI-NEXT: v_readfirstlane_b32 s13, v3
-; SI-NEXT: v_readfirstlane_b32 s12, v4
-; SI-NEXT: v_readfirstlane_b32 s11, v5
-; SI-NEXT: v_readfirstlane_b32 s10, v6
-; SI-NEXT: v_readfirstlane_b32 s8, v7
-; SI-NEXT: v_readfirstlane_b32 s7, v8
-; SI-NEXT: v_readfirstlane_b32 s6, v9
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s9, v10
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
@@ -17049,6 +17265,18 @@ define inreg <48 x half> @bitcast_v24f32_to_v48f16_scalar(<24 x float> inreg %a,
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
+; SI-NEXT: v_readfirstlane_b32 s15, v1
+; SI-NEXT: v_readfirstlane_b32 s14, v2
+; SI-NEXT: v_readfirstlane_b32 s13, v3
+; SI-NEXT: v_readfirstlane_b32 s12, v4
+; SI-NEXT: v_readfirstlane_b32 s11, v5
+; SI-NEXT: v_readfirstlane_b32 s10, v6
+; SI-NEXT: v_readfirstlane_b32 s8, v7
+; SI-NEXT: v_readfirstlane_b32 s7, v8
+; SI-NEXT: v_readfirstlane_b32 s6, v9
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s9, v10
; SI-NEXT: s_cbranch_scc0 .LBB33_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -20039,6 +20267,10 @@ define inreg <24 x float> @bitcast_v48f16_to_v24f32_scalar(<48 x half> inreg %a,
; GFX9-LABEL: bitcast_v48f16_to_v24f32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v9
; GFX9-NEXT: v_mov_b32_e32 v33, v8
; GFX9-NEXT: v_mov_b32_e32 v34, v7
@@ -20064,10 +20296,6 @@ define inreg <24 x float> @bitcast_v48f16_to_v24f32_scalar(<48 x half> inreg %a,
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34
@@ -20191,89 +20419,165 @@ define inreg <24 x float> @bitcast_v48f16_to_v24f32_scalar(<48 x half> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v24f32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xe
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0
@@ -21365,8 +21669,8 @@ define <48 x i16> @bitcast_v12i64_to_v48i16(<12 x i64> %a, i32 %b) {
; SI-LABEL: bitcast_v12i64_to_v48i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr50
@@ -22132,8 +22436,9 @@ define inreg <48 x i16> @bitcast_v12i64_to_v48i16_scalar(<12 x i64> inreg %a, i3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v12, s34, 0
; SI-NEXT: v_writelane_b32 v12, s35, 1
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; SI-NEXT: v_writelane_b32 v12, s30, 2
+; SI-NEXT: v_writelane_b32 v12, s31, 3
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; SI-NEXT: v_readfirstlane_b32 s12, v1
; SI-NEXT: v_readfirstlane_b32 s13, v2
; SI-NEXT: v_readfirstlane_b32 s10, v3
@@ -22145,7 +22450,6 @@ define inreg <48 x i16> @bitcast_v12i64_to_v48i16_scalar(<12 x i64> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v9
; SI-NEXT: s_and_b64 s[14:15], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v10
-; SI-NEXT: v_writelane_b32 v12, s31, 3
; SI-NEXT: s_cbranch_scc0 .LBB41_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s88, s5, 16
@@ -24592,6 +24896,10 @@ define inreg <12 x i64> @bitcast_v48i16_to_v12i64_scalar(<48 x i16> inreg %a, i3
; GFX9-LABEL: bitcast_v48i16_to_v12i64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v9
; GFX9-NEXT: v_mov_b32_e32 v33, v8
; GFX9-NEXT: v_mov_b32_e32 v34, v7
@@ -24617,10 +24925,6 @@ define inreg <12 x i64> @bitcast_v48i16_to_v12i64_scalar(<48 x i16> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34
@@ -24742,89 +25046,165 @@ define inreg <12 x i64> @bitcast_v48i16_to_v12i64_scalar(<48 x i16> inreg %a, i3
; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v12i64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xe
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0
@@ -25153,16 +25533,7 @@ end:
define <48 x half> @bitcast_v12i64_to_v48f16(<12 x i64> %a, i32 %b) {
; SI-LABEL: bitcast_v12i64_to_v48f16:
; SI: ; %bb.0:
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; kill: killed $vgpr35
-; SI-NEXT: ; kill: killed $vgpr34
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; kill: killed $vgpr35
-; SI-NEXT: ; kill: killed $vgpr34
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -25183,6 +25554,11 @@ define <48 x half> @bitcast_v12i64_to_v48f16(<12 x i64> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; kill: killed $vgpr35
; SI-NEXT: ; kill: killed $vgpr34
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; kill: killed $vgpr34
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr30
@@ -25227,6 +25603,10 @@ define <48 x half> @bitcast_v12i64_to_v48f16(<12 x i64> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; kill: killed $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; kill: killed $vgpr35
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -26160,6 +26540,7 @@ define inreg <48 x half> @bitcast_v12i64_to_v48f16_scalar(<12 x i64> inreg %a, i
; SI-LABEL: bitcast_v12i64_to_v48f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; SI-NEXT: v_readfirstlane_b32 s14, v1
; SI-NEXT: v_readfirstlane_b32 s15, v2
@@ -26172,7 +26553,6 @@ define inreg <48 x half> @bitcast_v12i64_to_v48f16_scalar(<12 x i64> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s6, v9
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v10
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB45_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -29010,6 +29390,10 @@ define inreg <12 x i64> @bitcast_v48f16_to_v12i64_scalar(<48 x half> inreg %a, i
; GFX9-LABEL: bitcast_v48f16_to_v12i64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v9
; GFX9-NEXT: v_mov_b32_e32 v33, v8
; GFX9-NEXT: v_mov_b32_e32 v34, v7
@@ -29035,10 +29419,6 @@ define inreg <12 x i64> @bitcast_v48f16_to_v12i64_scalar(<48 x half> inreg %a, i
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34
@@ -29162,89 +29542,165 @@ define inreg <12 x i64> @bitcast_v48f16_to_v12i64_scalar(<48 x half> inreg %a, i
; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v12i64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xe
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0
@@ -29574,8 +30030,8 @@ define <48 x i16> @bitcast_v12f64_to_v48i16(<12 x double> %a, i32 %b) {
; SI-LABEL: bitcast_v12f64_to_v48i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr50
@@ -30263,6 +30719,9 @@ define inreg <48 x i16> @bitcast_v12f64_to_v48i16_scalar(<12 x double> inreg %a,
; SI-LABEL: bitcast_v12f64_to_v48i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; SI-NEXT: v_mov_b32_e32 v23, s16
; SI-NEXT: v_mov_b32_e32 v24, s17
@@ -30279,9 +30738,6 @@ define inreg <48 x i16> @bitcast_v12f64_to_v48i16_scalar(<12 x double> inreg %a,
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_mov_b32_e32 v11, s28
; SI-NEXT: v_mov_b32_e32 v12, s29
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB49_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_lshr_b64 v[25:26], v[9:10], 16
@@ -32809,6 +33265,10 @@ define inreg <12 x double> @bitcast_v48i16_to_v12f64_scalar(<48 x i16> inreg %a,
; GFX9-LABEL: bitcast_v48i16_to_v12f64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v9
; GFX9-NEXT: v_mov_b32_e32 v33, v8
; GFX9-NEXT: v_mov_b32_e32 v34, v7
@@ -32834,10 +33294,6 @@ define inreg <12 x double> @bitcast_v48i16_to_v12f64_scalar(<48 x i16> inreg %a,
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34
@@ -32959,89 +33415,165 @@ define inreg <12 x double> @bitcast_v48i16_to_v12f64_scalar(<48 x i16> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v12f64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xe
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0
@@ -33370,16 +33902,7 @@ end:
define <48 x half> @bitcast_v12f64_to_v48f16(<12 x double> %a, i32 %b) {
; SI-LABEL: bitcast_v12f64_to_v48f16:
; SI: ; %bb.0:
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; kill: killed $vgpr35
-; SI-NEXT: ; kill: killed $vgpr34
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; kill: killed $vgpr35
-; SI-NEXT: ; kill: killed $vgpr34
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -33400,6 +33923,11 @@ define <48 x half> @bitcast_v12f64_to_v48f16(<12 x double> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; kill: killed $vgpr35
; SI-NEXT: ; kill: killed $vgpr34
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v25
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; kill: killed $vgpr34
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr30
@@ -33444,6 +33972,10 @@ define <48 x half> @bitcast_v12f64_to_v48f16(<12 x double> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; kill: killed $vgpr35
+; SI-NEXT: ; kill: killed $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; kill: killed $vgpr35
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -34293,18 +34825,6 @@ define inreg <48 x half> @bitcast_v12f64_to_v48f16_scalar(<12 x double> inreg %a
; SI-LABEL: bitcast_v12f64_to_v48f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
-; SI-NEXT: v_readfirstlane_b32 s12, v1
-; SI-NEXT: v_readfirstlane_b32 s13, v2
-; SI-NEXT: v_readfirstlane_b32 s10, v3
-; SI-NEXT: v_readfirstlane_b32 s11, v4
-; SI-NEXT: v_readfirstlane_b32 s8, v5
-; SI-NEXT: v_readfirstlane_b32 s9, v6
-; SI-NEXT: v_readfirstlane_b32 s6, v7
-; SI-NEXT: v_readfirstlane_b32 s7, v8
-; SI-NEXT: v_readfirstlane_b32 s4, v9
-; SI-NEXT: s_and_b64 s[14:15], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s5, v10
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
@@ -34319,6 +34839,18 @@ define inreg <48 x half> @bitcast_v12f64_to_v48f16_scalar(<12 x double> inreg %a
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
+; SI-NEXT: v_readfirstlane_b32 s12, v1
+; SI-NEXT: v_readfirstlane_b32 s13, v2
+; SI-NEXT: v_readfirstlane_b32 s10, v3
+; SI-NEXT: v_readfirstlane_b32 s11, v4
+; SI-NEXT: v_readfirstlane_b32 s8, v5
+; SI-NEXT: v_readfirstlane_b32 s9, v6
+; SI-NEXT: v_readfirstlane_b32 s6, v7
+; SI-NEXT: v_readfirstlane_b32 s7, v8
+; SI-NEXT: v_readfirstlane_b32 s4, v9
+; SI-NEXT: s_and_b64 s[14:15], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s5, v10
; SI-NEXT: s_cbranch_scc0 .LBB53_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s14, s5, 16
@@ -37274,6 +37806,10 @@ define inreg <12 x double> @bitcast_v48f16_to_v12f64_scalar(<48 x half> inreg %a
; GFX9-LABEL: bitcast_v48f16_to_v12f64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v9
; GFX9-NEXT: v_mov_b32_e32 v33, v8
; GFX9-NEXT: v_mov_b32_e32 v34, v7
@@ -37299,10 +37835,6 @@ define inreg <12 x double> @bitcast_v48f16_to_v12f64_scalar(<48 x half> inreg %a
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v34
@@ -37426,89 +37958,165 @@ define inreg <12 x double> @bitcast_v48f16_to_v12f64_scalar(<48 x half> inreg %a
; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v12f64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xe
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v5 :: v_dual_mov_b32 v186, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v3 :: v_dual_mov_b32 v188, v2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v1 :: v_dual_mov_b32 v190, v0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
index 58cfae21bd8d5..282e7a7953de6 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
@@ -2570,12 +2570,12 @@ define <52 x i16> @bitcast_v26i32_to_v52i16(<26 x i32> %a, i32 %b) {
; SI-LABEL: bitcast_v26i32_to_v52i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr54
@@ -2866,11 +2866,11 @@ define <52 x i16> @bitcast_v26i32_to_v52i16(<26 x i32> %a, i32 %b) {
; VI-LABEL: bitcast_v26i32_to_v52i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -3047,11 +3047,11 @@ define <52 x i16> @bitcast_v26i32_to_v52i16(<26 x i32> %a, i32 %b) {
; GFX9-LABEL: bitcast_v26i32_to_v52i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
@@ -3419,8 +3419,9 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3
; SI-NEXT: v_writelane_b32 v14, s38, 4
; SI-NEXT: v_writelane_b32 v14, s39, 5
; SI-NEXT: v_writelane_b32 v14, s48, 6
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; SI-NEXT: v_writelane_b32 v14, s30, 7
+; SI-NEXT: v_writelane_b32 v14, s31, 8
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; SI-NEXT: v_readfirstlane_b32 s14, v1
; SI-NEXT: v_readfirstlane_b32 s15, v2
; SI-NEXT: v_readfirstlane_b32 s12, v3
@@ -3434,7 +3435,6 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v11
; SI-NEXT: s_and_b64 s[40:41], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v12
-; SI-NEXT: v_writelane_b32 v14, s31, 8
; SI-NEXT: s_cbranch_scc0 .LBB13_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s92, s5, 16
@@ -6114,6 +6114,14 @@ define inreg <26 x i32> @bitcast_v52i16_to_v26i32_scalar(<52 x i16> inreg %a, i3
; GFX9-LABEL: bitcast_v52i16_to_v26i32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v11
; GFX9-NEXT: v_mov_b32_e32 v33, v10
; GFX9-NEXT: v_mov_b32_e32 v34, v9
@@ -6141,14 +6149,6 @@ define inreg <26 x i32> @bitcast_v52i16_to_v26i32_scalar(<52 x i16> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34
@@ -6286,90 +6286,167 @@ define inreg <26 x i32> @bitcast_v52i16_to_v26i32_scalar(<52 x i16> inreg %a, i3
; GFX11-TRUE16-LABEL: bitcast_v52i16_to_v26i32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2
@@ -6716,16 +6793,7 @@ end:
define <52 x half> @bitcast_v26i32_to_v52f16(<26 x i32> %a, i32 %b) {
; SI-LABEL: bitcast_v26i32_to_v52f16:
; SI: ; %bb.0:
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr51
-; SI-NEXT: ; kill: killed $vgpr50
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr51
-; SI-NEXT: ; kill: killed $vgpr50
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -6746,6 +6814,11 @@ define <52 x half> @bitcast_v26i32_to_v52f16(<26 x i32> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; kill: killed $vgpr51
; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; kill: killed $vgpr50
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr38
@@ -6800,6 +6873,10 @@ define <52 x half> @bitcast_v26i32_to_v52f16(<26 x i32> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr51
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -7290,11 +7367,11 @@ define <52 x half> @bitcast_v26i32_to_v52f16(<26 x i32> %a, i32 %b) {
; VI-LABEL: bitcast_v26i32_to_v52f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -7471,11 +7548,11 @@ define <52 x half> @bitcast_v26i32_to_v52f16(<26 x i32> %a, i32 %b) {
; GFX9-LABEL: bitcast_v26i32_to_v52f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
@@ -7832,6 +7909,11 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i
; SI-LABEL: bitcast_v26i32_to_v52f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; SI-NEXT: v_readfirstlane_b32 s41, v1
; SI-NEXT: v_readfirstlane_b32 s40, v2
@@ -7846,11 +7928,6 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s6, v11
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v12
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB17_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -10938,6 +11015,14 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i
; GFX9-LABEL: bitcast_v52f16_to_v26i32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v11
; GFX9-NEXT: v_mov_b32_e32 v33, v10
; GFX9-NEXT: v_mov_b32_e32 v34, v9
@@ -10965,14 +11050,6 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34
@@ -11112,90 +11189,167 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i
; GFX11-TRUE16-LABEL: bitcast_v52f16_to_v26i32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2
@@ -13185,12 +13339,12 @@ define <52 x i16> @bitcast_v26f32_to_v52i16(<26 x float> %a, i32 %b) {
; SI-LABEL: bitcast_v26f32_to_v52i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr54
@@ -13481,11 +13635,11 @@ define <52 x i16> @bitcast_v26f32_to_v52i16(<26 x float> %a, i32 %b) {
; VI-LABEL: bitcast_v26f32_to_v52i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -13662,11 +13816,11 @@ define <52 x i16> @bitcast_v26f32_to_v52i16(<26 x float> %a, i32 %b) {
; GFX9-LABEL: bitcast_v26f32_to_v52i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
@@ -13997,6 +14151,14 @@ define inreg <52 x i16> @bitcast_v26f32_to_v52i16_scalar(<26 x float> inreg %a,
; SI-LABEL: bitcast_v26f32_to_v52i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; SI-NEXT: v_mov_b32_e32 v25, s16
; SI-NEXT: v_mov_b32_e32 v26, s17
@@ -14013,14 +14175,6 @@ define inreg <52 x i16> @bitcast_v26f32_to_v52i16_scalar(<26 x float> inreg %a,
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_mov_b32_e32 v13, s28
; SI-NEXT: v_mov_b32_e32 v14, s29
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB29_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_lshr_b64 v[27:28], v[11:12], 16
@@ -14314,6 +14468,10 @@ define inreg <52 x i16> @bitcast_v26f32_to_v52i16_scalar(<26 x float> inreg %a,
; VI-LABEL: bitcast_v26f32_to_v52i16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; VI-NEXT: v_mov_b32_e32 v22, s16
; VI-NEXT: v_mov_b32_e32 v20, s17
@@ -14330,10 +14488,6 @@ define inreg <52 x i16> @bitcast_v26f32_to_v52i16_scalar(<26 x float> inreg %a,
; VI-NEXT: v_mov_b32_e32 v19, s27
; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v16, s29
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB29_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v11
@@ -14519,6 +14673,10 @@ define inreg <52 x i16> @bitcast_v26f32_to_v52i16_scalar(<26 x float> inreg %a,
; GFX9-LABEL: bitcast_v26f32_to_v52i16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: v_mov_b32_e32 v22, s16
; GFX9-NEXT: v_mov_b32_e32 v20, s17
@@ -14535,10 +14693,6 @@ define inreg <52 x i16> @bitcast_v26f32_to_v52i16_scalar(<26 x float> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v19, s27
; GFX9-NEXT: v_mov_b32_e32 v12, s28
; GFX9-NEXT: v_mov_b32_e32 v16, s29
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB29_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v11
@@ -16849,6 +17003,14 @@ define inreg <26 x float> @bitcast_v52i16_to_v26f32_scalar(<52 x i16> inreg %a,
; GFX9-LABEL: bitcast_v52i16_to_v26f32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v11
; GFX9-NEXT: v_mov_b32_e32 v33, v10
; GFX9-NEXT: v_mov_b32_e32 v34, v9
@@ -16876,14 +17038,6 @@ define inreg <26 x float> @bitcast_v52i16_to_v26f32_scalar(<52 x i16> inreg %a,
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34
@@ -17021,90 +17175,167 @@ define inreg <26 x float> @bitcast_v52i16_to_v26f32_scalar(<52 x i16> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v52i16_to_v26f32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2
@@ -17451,16 +17682,7 @@ end:
define <52 x half> @bitcast_v26f32_to_v52f16(<26 x float> %a, i32 %b) {
; SI-LABEL: bitcast_v26f32_to_v52f16:
; SI: ; %bb.0:
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr51
-; SI-NEXT: ; kill: killed $vgpr50
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr51
-; SI-NEXT: ; kill: killed $vgpr50
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -17481,6 +17703,11 @@ define <52 x half> @bitcast_v26f32_to_v52f16(<26 x float> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; kill: killed $vgpr51
; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; kill: killed $vgpr50
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr38
@@ -17535,6 +17762,10 @@ define <52 x half> @bitcast_v26f32_to_v52f16(<26 x float> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr51
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -18025,11 +18256,11 @@ define <52 x half> @bitcast_v26f32_to_v52f16(<26 x float> %a, i32 %b) {
; VI-LABEL: bitcast_v26f32_to_v52f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -18206,11 +18437,11 @@ define <52 x half> @bitcast_v26f32_to_v52f16(<26 x float> %a, i32 %b) {
; GFX9-LABEL: bitcast_v26f32_to_v52f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
@@ -18541,20 +18772,6 @@ define inreg <52 x half> @bitcast_v26f32_to_v52f16_scalar(<26 x float> inreg %a,
; SI-LABEL: bitcast_v26f32_to_v52f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
-; SI-NEXT: v_readfirstlane_b32 s41, v1
-; SI-NEXT: v_readfirstlane_b32 s40, v2
-; SI-NEXT: v_readfirstlane_b32 s15, v3
-; SI-NEXT: v_readfirstlane_b32 s14, v4
-; SI-NEXT: v_readfirstlane_b32 s13, v5
-; SI-NEXT: v_readfirstlane_b32 s12, v6
-; SI-NEXT: v_readfirstlane_b32 s11, v7
-; SI-NEXT: v_readfirstlane_b32 s10, v8
-; SI-NEXT: v_readfirstlane_b32 s8, v9
-; SI-NEXT: v_readfirstlane_b32 s7, v10
-; SI-NEXT: v_readfirstlane_b32 s6, v11
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s9, v12
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -18571,6 +18788,20 @@ define inreg <52 x half> @bitcast_v26f32_to_v52f16_scalar(<26 x float> inreg %a,
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
+; SI-NEXT: v_readfirstlane_b32 s41, v1
+; SI-NEXT: v_readfirstlane_b32 s40, v2
+; SI-NEXT: v_readfirstlane_b32 s15, v3
+; SI-NEXT: v_readfirstlane_b32 s14, v4
+; SI-NEXT: v_readfirstlane_b32 s13, v5
+; SI-NEXT: v_readfirstlane_b32 s12, v6
+; SI-NEXT: v_readfirstlane_b32 s11, v7
+; SI-NEXT: v_readfirstlane_b32 s10, v8
+; SI-NEXT: v_readfirstlane_b32 s8, v9
+; SI-NEXT: v_readfirstlane_b32 s7, v10
+; SI-NEXT: v_readfirstlane_b32 s6, v11
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s9, v12
; SI-NEXT: s_cbranch_scc0 .LBB33_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -19022,6 +19253,10 @@ define inreg <52 x half> @bitcast_v26f32_to_v52f16_scalar(<26 x float> inreg %a,
; VI-LABEL: bitcast_v26f32_to_v52f16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; VI-NEXT: v_mov_b32_e32 v22, s16
; VI-NEXT: v_mov_b32_e32 v20, s17
@@ -19038,10 +19273,6 @@ define inreg <52 x half> @bitcast_v26f32_to_v52f16_scalar(<26 x float> inreg %a,
; VI-NEXT: v_mov_b32_e32 v19, s27
; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v16, s29
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB33_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v11
@@ -19227,6 +19458,10 @@ define inreg <52 x half> @bitcast_v26f32_to_v52f16_scalar(<26 x float> inreg %a,
; GFX9-LABEL: bitcast_v26f32_to_v52f16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: v_mov_b32_e32 v22, s16
; GFX9-NEXT: v_mov_b32_e32 v20, s17
@@ -19243,10 +19478,6 @@ define inreg <52 x half> @bitcast_v26f32_to_v52f16_scalar(<26 x float> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v19, s27
; GFX9-NEXT: v_mov_b32_e32 v12, s28
; GFX9-NEXT: v_mov_b32_e32 v16, s29
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB33_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v11
@@ -21831,6 +22062,14 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a,
; GFX9-LABEL: bitcast_v52f16_to_v26f32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v11
; GFX9-NEXT: v_mov_b32_e32 v33, v10
; GFX9-NEXT: v_mov_b32_e32 v34, v9
@@ -21858,14 +22097,6 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a,
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34
@@ -22005,90 +22236,167 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v52f16_to_v26f32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2
@@ -23238,12 +23546,12 @@ define <52 x i16> @bitcast_v13i64_to_v52i16(<13 x i64> %a, i32 %b) {
; SI-LABEL: bitcast_v13i64_to_v52i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr54
@@ -23534,11 +23842,11 @@ define <52 x i16> @bitcast_v13i64_to_v52i16(<13 x i64> %a, i32 %b) {
; VI-LABEL: bitcast_v13i64_to_v52i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -23715,11 +24023,11 @@ define <52 x i16> @bitcast_v13i64_to_v52i16(<13 x i64> %a, i32 %b) {
; GFX9-LABEL: bitcast_v13i64_to_v52i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
@@ -24101,8 +24409,9 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3
; SI-NEXT: v_writelane_b32 v14, s38, 4
; SI-NEXT: v_writelane_b32 v14, s39, 5
; SI-NEXT: v_writelane_b32 v14, s48, 6
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; SI-NEXT: v_writelane_b32 v14, s30, 7
+; SI-NEXT: v_writelane_b32 v14, s31, 8
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; SI-NEXT: v_readfirstlane_b32 s14, v1
; SI-NEXT: v_readfirstlane_b32 s15, v2
; SI-NEXT: v_readfirstlane_b32 s12, v3
@@ -24116,7 +24425,6 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v11
; SI-NEXT: s_and_b64 s[40:41], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v12
-; SI-NEXT: v_writelane_b32 v14, s31, 8
; SI-NEXT: s_cbranch_scc0 .LBB41_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s92, s5, 16
@@ -26796,6 +27104,14 @@ define inreg <13 x i64> @bitcast_v52i16_to_v13i64_scalar(<52 x i16> inreg %a, i3
; GFX9-LABEL: bitcast_v52i16_to_v13i64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v11
; GFX9-NEXT: v_mov_b32_e32 v33, v10
; GFX9-NEXT: v_mov_b32_e32 v34, v9
@@ -26823,14 +27139,6 @@ define inreg <13 x i64> @bitcast_v52i16_to_v13i64_scalar(<52 x i16> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34
@@ -26968,90 +27276,167 @@ define inreg <13 x i64> @bitcast_v52i16_to_v13i64_scalar(<52 x i16> inreg %a, i3
; GFX11-TRUE16-LABEL: bitcast_v52i16_to_v13i64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2
@@ -27398,16 +27783,7 @@ end:
define <52 x half> @bitcast_v13i64_to_v52f16(<13 x i64> %a, i32 %b) {
; SI-LABEL: bitcast_v13i64_to_v52f16:
; SI: ; %bb.0:
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr51
-; SI-NEXT: ; kill: killed $vgpr50
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr51
-; SI-NEXT: ; kill: killed $vgpr50
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -27428,6 +27804,11 @@ define <52 x half> @bitcast_v13i64_to_v52f16(<13 x i64> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; kill: killed $vgpr51
; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; kill: killed $vgpr50
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr38
@@ -27482,6 +27863,10 @@ define <52 x half> @bitcast_v13i64_to_v52f16(<13 x i64> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr51
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -27973,11 +28358,11 @@ define <52 x half> @bitcast_v13i64_to_v52f16(<13 x i64> %a, i32 %b) {
; VI-LABEL: bitcast_v13i64_to_v52f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -28154,11 +28539,11 @@ define <52 x half> @bitcast_v13i64_to_v52f16(<13 x i64> %a, i32 %b) {
; GFX9-LABEL: bitcast_v13i64_to_v52f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
@@ -28529,6 +28914,11 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i
; SI-LABEL: bitcast_v13i64_to_v52f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; SI-NEXT: v_readfirstlane_b32 s40, v1
; SI-NEXT: v_readfirstlane_b32 s41, v2
@@ -28543,11 +28933,6 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s6, v11
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v12
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB45_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -31635,6 +32020,14 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i
; GFX9-LABEL: bitcast_v52f16_to_v13i64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v11
; GFX9-NEXT: v_mov_b32_e32 v33, v10
; GFX9-NEXT: v_mov_b32_e32 v34, v9
@@ -31662,14 +32055,6 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34
@@ -31809,90 +32194,167 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i
; GFX11-TRUE16-LABEL: bitcast_v52f16_to_v13i64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2
@@ -32240,12 +32702,12 @@ define <52 x i16> @bitcast_v13f64_to_v52i16(<13 x double> %a, i32 %b) {
; SI-LABEL: bitcast_v13f64_to_v52i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr54
@@ -32523,11 +32985,11 @@ define <52 x i16> @bitcast_v13f64_to_v52i16(<13 x double> %a, i32 %b) {
; VI-LABEL: bitcast_v13f64_to_v52i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -32691,11 +33153,11 @@ define <52 x i16> @bitcast_v13f64_to_v52i16(<13 x double> %a, i32 %b) {
; GFX9-LABEL: bitcast_v13f64_to_v52i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
@@ -33013,6 +33475,14 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a,
; SI-LABEL: bitcast_v13f64_to_v52i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; SI-NEXT: v_mov_b32_e32 v25, s16
; SI-NEXT: v_mov_b32_e32 v26, s17
@@ -33029,14 +33499,6 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a,
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_mov_b32_e32 v13, s28
; SI-NEXT: v_mov_b32_e32 v14, s29
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB49_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_lshr_b64 v[27:28], v[11:12], 16
@@ -33317,6 +33779,10 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a,
; VI-LABEL: bitcast_v13f64_to_v52i16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; VI-NEXT: v_mov_b32_e32 v21, s16
; VI-NEXT: v_mov_b32_e32 v22, s17
@@ -33333,10 +33799,6 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a,
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_mov_b32_e32 v15, s28
; VI-NEXT: v_mov_b32_e32 v16, s29
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB49_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v11
@@ -33509,6 +33971,10 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a,
; GFX9-LABEL: bitcast_v13f64_to_v52i16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: v_mov_b32_e32 v21, s16
; GFX9-NEXT: v_mov_b32_e32 v22, s17
@@ -33525,10 +33991,6 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a,
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_mov_b32_e32 v15, s28
; GFX9-NEXT: v_mov_b32_e32 v16, s29
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB49_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v11
@@ -35826,6 +36288,14 @@ define inreg <13 x double> @bitcast_v52i16_to_v13f64_scalar(<52 x i16> inreg %a,
; GFX9-LABEL: bitcast_v52i16_to_v13f64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v11
; GFX9-NEXT: v_mov_b32_e32 v33, v10
; GFX9-NEXT: v_mov_b32_e32 v34, v9
@@ -35853,14 +36323,6 @@ define inreg <13 x double> @bitcast_v52i16_to_v13f64_scalar(<52 x i16> inreg %a,
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34
@@ -35998,90 +36460,167 @@ define inreg <13 x double> @bitcast_v52i16_to_v13f64_scalar(<52 x i16> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v52i16_to_v13f64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2
@@ -36428,16 +36967,7 @@ end:
define <52 x half> @bitcast_v13f64_to_v52f16(<13 x double> %a, i32 %b) {
; SI-LABEL: bitcast_v13f64_to_v52f16:
; SI: ; %bb.0:
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr51
-; SI-NEXT: ; kill: killed $vgpr50
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr51
-; SI-NEXT: ; kill: killed $vgpr50
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -36458,6 +36988,11 @@ define <52 x half> @bitcast_v13f64_to_v52f16(<13 x double> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; kill: killed $vgpr51
; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v27
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; kill: killed $vgpr50
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr38
@@ -36512,6 +37047,10 @@ define <52 x half> @bitcast_v13f64_to_v52f16(<13 x double> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; kill: killed $vgpr51
+; SI-NEXT: ; kill: killed $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr51
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
@@ -36976,11 +37515,11 @@ define <52 x half> @bitcast_v13f64_to_v52f16(<13 x double> %a, i32 %b) {
; VI-LABEL: bitcast_v13f64_to_v52f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
@@ -37144,11 +37683,11 @@ define <52 x half> @bitcast_v13f64_to_v52f16(<13 x double> %a, i32 %b) {
; GFX9-LABEL: bitcast_v13f64_to_v52f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
@@ -37466,20 +38005,6 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a
; SI-LABEL: bitcast_v13f64_to_v52f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
-; SI-NEXT: v_readfirstlane_b32 s14, v1
-; SI-NEXT: v_readfirstlane_b32 s15, v2
-; SI-NEXT: v_readfirstlane_b32 s12, v3
-; SI-NEXT: v_readfirstlane_b32 s13, v4
-; SI-NEXT: v_readfirstlane_b32 s10, v5
-; SI-NEXT: v_readfirstlane_b32 s11, v6
-; SI-NEXT: v_readfirstlane_b32 s8, v7
-; SI-NEXT: v_readfirstlane_b32 s9, v8
-; SI-NEXT: v_readfirstlane_b32 s6, v9
-; SI-NEXT: v_readfirstlane_b32 s7, v10
-; SI-NEXT: v_readfirstlane_b32 s4, v11
-; SI-NEXT: s_and_b64 s[40:41], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s5, v12
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -37496,6 +38021,20 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
+; SI-NEXT: v_readfirstlane_b32 s14, v1
+; SI-NEXT: v_readfirstlane_b32 s15, v2
+; SI-NEXT: v_readfirstlane_b32 s12, v3
+; SI-NEXT: v_readfirstlane_b32 s13, v4
+; SI-NEXT: v_readfirstlane_b32 s10, v5
+; SI-NEXT: v_readfirstlane_b32 s11, v6
+; SI-NEXT: v_readfirstlane_b32 s8, v7
+; SI-NEXT: v_readfirstlane_b32 s9, v8
+; SI-NEXT: v_readfirstlane_b32 s6, v9
+; SI-NEXT: v_readfirstlane_b32 s7, v10
+; SI-NEXT: v_readfirstlane_b32 s4, v11
+; SI-NEXT: s_and_b64 s[40:41], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s5, v12
; SI-NEXT: s_cbranch_scc0 .LBB53_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s40, s5, 16
@@ -37934,6 +38473,10 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a
; VI-LABEL: bitcast_v13f64_to_v52f16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; VI-NEXT: v_mov_b32_e32 v21, s16
; VI-NEXT: v_mov_b32_e32 v22, s17
@@ -37950,10 +38493,6 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_mov_b32_e32 v15, s28
; VI-NEXT: v_mov_b32_e32 v16, s29
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB53_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v11
@@ -38126,6 +38665,10 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a
; GFX9-LABEL: bitcast_v13f64_to_v52f16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: v_mov_b32_e32 v21, s16
; GFX9-NEXT: v_mov_b32_e32 v22, s17
@@ -38142,10 +38685,6 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_mov_b32_e32 v15, s28
; GFX9-NEXT: v_mov_b32_e32 v16, s29
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB53_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v11
@@ -40717,6 +41256,14 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a
; GFX9-LABEL: bitcast_v52f16_to_v13f64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v11
; GFX9-NEXT: v_mov_b32_e32 v33, v10
; GFX9-NEXT: v_mov_b32_e32 v34, v9
@@ -40744,14 +41291,6 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v34
@@ -40891,90 +41430,167 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a
; GFX11-TRUE16-LABEL: bitcast_v52f16_to_v13f64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2
@@ -43549,6 +44165,10 @@ define inreg <52 x half> @bitcast_v52i16_to_v52f16_scalar(<52 x i16> inreg %a, i
; GFX9-LABEL: bitcast_v52i16_to_v52f16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: s_lshr_b32 s43, s29, 16
; GFX9-NEXT: s_lshr_b32 s42, s28, 16
@@ -43577,10 +44197,6 @@ define inreg <52 x half> @bitcast_v52i16_to_v52f16_scalar(<52 x i16> inreg %a, i
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v0
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB57_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_cbranch_execnz .LBB57_4
@@ -45783,6 +46399,10 @@ define inreg <52 x i16> @bitcast_v52f16_to_v52i16_scalar(<52 x half> inreg %a, i
; VI-LABEL: bitcast_v52f16_to_v52i16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; VI-NEXT: s_lshr_b32 s6, s29, 16
; VI-NEXT: s_lshr_b32 s7, s28, 16
@@ -45811,10 +46431,6 @@ define inreg <52 x i16> @bitcast_v52f16_to_v52i16_scalar(<52 x half> inreg %a, i
; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v0
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB59_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB59_4
@@ -45979,6 +46595,10 @@ define inreg <52 x i16> @bitcast_v52f16_to_v52i16_scalar(<52 x half> inreg %a, i
; GFX9-LABEL: bitcast_v52f16_to_v52i16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: s_lshr_b32 s43, s29, 16
; GFX9-NEXT: s_lshr_b32 s42, s28, 16
@@ -46007,10 +46627,6 @@ define inreg <52 x i16> @bitcast_v52f16_to_v52i16_scalar(<52 x half> inreg %a, i
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v0
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB59_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_cbranch_execnz .LBB59_4
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
index 7d04400ebe009..f6ff5be918706 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
@@ -2719,7 +2719,6 @@ define <56 x i16> @bitcast_v28i32_to_v56i16(<28 x i32> %a, i32 %b) {
; SI-LABEL: bitcast_v28i32_to_v56i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
@@ -2729,6 +2728,7 @@ define <56 x i16> @bitcast_v28i32_to_v56i16(<28 x i32> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr42
@@ -3045,7 +3045,6 @@ define <56 x i16> @bitcast_v28i32_to_v56i16(<28 x i32> %a, i32 %b) {
; VI-LABEL: bitcast_v28i32_to_v56i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -3054,6 +3053,7 @@ define <56 x i16> @bitcast_v28i32_to_v56i16(<28 x i32> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -3246,7 +3246,6 @@ define <56 x i16> @bitcast_v28i32_to_v56i16(<28 x i32> %a, i32 %b) {
; GFX9-LABEL: bitcast_v28i32_to_v56i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -3255,6 +3254,7 @@ define <56 x i16> @bitcast_v28i32_to_v56i16(<28 x i32> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
@@ -3653,8 +3653,9 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3
; SI-NEXT: v_writelane_b32 v16, s51, 9
; SI-NEXT: v_writelane_b32 v16, s52, 10
; SI-NEXT: v_writelane_b32 v16, s53, 11
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
; SI-NEXT: v_writelane_b32 v16, s30, 12
+; SI-NEXT: v_writelane_b32 v16, s31, 13
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
; SI-NEXT: v_readfirstlane_b32 s40, v1
; SI-NEXT: v_readfirstlane_b32 s41, v2
; SI-NEXT: v_readfirstlane_b32 s14, v3
@@ -3670,7 +3671,6 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v13
; SI-NEXT: s_and_b64 s[42:43], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v14
-; SI-NEXT: v_writelane_b32 v16, s31, 13
; SI-NEXT: s_cbranch_scc0 .LBB13_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s30, s5, 16
@@ -4009,8 +4009,9 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v28, s34, 0
; VI-NEXT: v_writelane_b32 v28, s35, 1
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; VI-NEXT: v_writelane_b32 v28, s30, 2
+; VI-NEXT: v_writelane_b32 v28, s31, 3
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; VI-NEXT: v_readfirstlane_b32 s43, v0
; VI-NEXT: v_readfirstlane_b32 s42, v1
; VI-NEXT: v_readfirstlane_b32 s41, v2
@@ -4026,7 +4027,6 @@ define inreg <56 x i16> @bitcast_v28i32_to_v56i16_scalar(<28 x i32> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s6, v12
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v13
-; VI-NEXT: v_writelane_b32 v28, s31, 3
; VI-NEXT: s_cbranch_scc0 .LBB13_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s44, s7, 16
@@ -6585,6 +6585,18 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; GFX9-LABEL: bitcast_v56i16_to_v28i32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v13
; GFX9-NEXT: v_mov_b32_e32 v33, v12
; GFX9-NEXT: v_mov_b32_e32 v34, v11
@@ -6614,18 +6626,6 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34
@@ -6779,90 +6779,167 @@ define inreg <28 x i32> @bitcast_v56i16_to_v28i32_scalar(<56 x i16> inreg %a, i3
; GFX11-TRUE16-LABEL: bitcast_v56i16_to_v28i32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3
@@ -7224,6 +7301,22 @@ define <56 x half> @bitcast_v28i32_to_v56f16(<28 x i32> %a, i32 %b) {
; SI-LABEL: bitcast_v28i32_to_v56f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; kill: killed $vgpr29
@@ -7266,22 +7359,6 @@ define <56 x half> @bitcast_v28i32_to_v56f16(<28 x i32> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; kill: killed $vgpr29
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr54
@@ -7867,7 +7944,6 @@ define <56 x half> @bitcast_v28i32_to_v56f16(<28 x i32> %a, i32 %b) {
; VI-LABEL: bitcast_v28i32_to_v56f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -7876,6 +7952,7 @@ define <56 x half> @bitcast_v28i32_to_v56f16(<28 x i32> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -8068,7 +8145,6 @@ define <56 x half> @bitcast_v28i32_to_v56f16(<28 x i32> %a, i32 %b) {
; GFX9-LABEL: bitcast_v28i32_to_v56f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -8077,6 +8153,7 @@ define <56 x half> @bitcast_v28i32_to_v56f16(<28 x i32> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
@@ -8459,6 +8536,15 @@ define inreg <56 x half> @bitcast_v28i32_to_v56f16_scalar(<28 x i32> inreg %a, i
; SI-LABEL: bitcast_v28i32_to_v56f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
; SI-NEXT: v_readfirstlane_b32 s43, v1
; SI-NEXT: v_readfirstlane_b32 s42, v2
@@ -8475,15 +8561,6 @@ define inreg <56 x half> @bitcast_v28i32_to_v56f16_scalar(<28 x i32> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s6, v13
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v14
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB17_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -8966,8 +9043,9 @@ define inreg <56 x half> @bitcast_v28i32_to_v56f16_scalar(<28 x i32> inreg %a, i
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v28, s34, 0
; VI-NEXT: v_writelane_b32 v28, s35, 1
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; VI-NEXT: v_writelane_b32 v28, s30, 2
+; VI-NEXT: v_writelane_b32 v28, s31, 3
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; VI-NEXT: v_readfirstlane_b32 s43, v0
; VI-NEXT: v_readfirstlane_b32 s42, v1
; VI-NEXT: v_readfirstlane_b32 s41, v2
@@ -8983,7 +9061,6 @@ define inreg <56 x half> @bitcast_v28i32_to_v56f16_scalar(<28 x i32> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s6, v12
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v13
-; VI-NEXT: v_writelane_b32 v28, s31, 3
; VI-NEXT: s_cbranch_scc0 .LBB17_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s44, s7, 16
@@ -11847,6 +11924,18 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; GFX9-LABEL: bitcast_v56f16_to_v28i32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v13
; GFX9-NEXT: v_mov_b32_e32 v33, v12
; GFX9-NEXT: v_mov_b32_e32 v34, v11
@@ -11876,18 +11965,6 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34
@@ -12043,90 +12120,167 @@ define inreg <28 x i32> @bitcast_v56f16_to_v28i32_scalar(<56 x half> inreg %a, i
; GFX11-TRUE16-LABEL: bitcast_v56f16_to_v28i32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3
@@ -14225,7 +14379,6 @@ define <56 x i16> @bitcast_v28f32_to_v56i16(<28 x float> %a, i32 %b) {
; SI-LABEL: bitcast_v28f32_to_v56i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
@@ -14235,6 +14388,7 @@ define <56 x i16> @bitcast_v28f32_to_v56i16(<28 x float> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr42
@@ -14551,7 +14705,6 @@ define <56 x i16> @bitcast_v28f32_to_v56i16(<28 x float> %a, i32 %b) {
; VI-LABEL: bitcast_v28f32_to_v56i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -14560,6 +14713,7 @@ define <56 x i16> @bitcast_v28f32_to_v56i16(<28 x float> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -14752,7 +14906,6 @@ define <56 x i16> @bitcast_v28f32_to_v56i16(<28 x float> %a, i32 %b) {
; GFX9-LABEL: bitcast_v28f32_to_v56i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -14761,6 +14914,7 @@ define <56 x i16> @bitcast_v28f32_to_v56i16(<28 x float> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
@@ -15115,6 +15269,18 @@ define inreg <56 x i16> @bitcast_v28f32_to_v56i16_scalar(<28 x float> inreg %a,
; SI-LABEL: bitcast_v28f32_to_v56i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
; SI-NEXT: v_mov_b32_e32 v27, s16
; SI-NEXT: v_mov_b32_e32 v28, s17
@@ -15131,18 +15297,6 @@ define inreg <56 x i16> @bitcast_v28f32_to_v56i16_scalar(<28 x float> inreg %a,
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_mov_b32_e32 v15, s28
; SI-NEXT: v_mov_b32_e32 v16, s29
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB29_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_lshr_b64 v[29:30], v[13:14], 16
@@ -15460,6 +15614,14 @@ define inreg <56 x i16> @bitcast_v28f32_to_v56i16_scalar(<28 x float> inreg %a,
; VI-LABEL: bitcast_v28f32_to_v56i16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; VI-NEXT: v_mov_b32_e32 v20, s16
; VI-NEXT: v_mov_b32_e32 v18, s17
@@ -15476,14 +15638,6 @@ define inreg <56 x i16> @bitcast_v28f32_to_v56i16_scalar(<28 x float> inreg %a,
; VI-NEXT: v_mov_b32_e32 v21, s27
; VI-NEXT: v_mov_b32_e32 v19, s28
; VI-NEXT: v_mov_b32_e32 v14, s29
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB29_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v13
@@ -15687,6 +15841,14 @@ define inreg <56 x i16> @bitcast_v28f32_to_v56i16_scalar(<28 x float> inreg %a,
; GFX9-LABEL: bitcast_v28f32_to_v56i16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; GFX9-NEXT: v_mov_b32_e32 v20, s16
; GFX9-NEXT: v_mov_b32_e32 v18, s17
@@ -15703,14 +15865,6 @@ define inreg <56 x i16> @bitcast_v28f32_to_v56i16_scalar(<28 x float> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v21, s27
; GFX9-NEXT: v_mov_b32_e32 v19, s28
; GFX9-NEXT: v_mov_b32_e32 v14, s29
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB29_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v13
@@ -18210,6 +18364,18 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; GFX9-LABEL: bitcast_v56i16_to_v28f32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v13
; GFX9-NEXT: v_mov_b32_e32 v33, v12
; GFX9-NEXT: v_mov_b32_e32 v34, v11
@@ -18239,18 +18405,6 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34
@@ -18404,90 +18558,167 @@ define inreg <28 x float> @bitcast_v56i16_to_v28f32_scalar(<56 x i16> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v56i16_to_v28f32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3
@@ -18849,6 +19080,22 @@ define <56 x half> @bitcast_v28f32_to_v56f16(<28 x float> %a, i32 %b) {
; SI-LABEL: bitcast_v28f32_to_v56f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; kill: killed $vgpr29
@@ -18891,22 +19138,6 @@ define <56 x half> @bitcast_v28f32_to_v56f16(<28 x float> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; kill: killed $vgpr29
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr54
@@ -19492,7 +19723,6 @@ define <56 x half> @bitcast_v28f32_to_v56f16(<28 x float> %a, i32 %b) {
; VI-LABEL: bitcast_v28f32_to_v56f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -19501,6 +19731,7 @@ define <56 x half> @bitcast_v28f32_to_v56f16(<28 x float> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -19693,7 +19924,6 @@ define <56 x half> @bitcast_v28f32_to_v56f16(<28 x float> %a, i32 %b) {
; GFX9-LABEL: bitcast_v28f32_to_v56f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -19702,6 +19932,7 @@ define <56 x half> @bitcast_v28f32_to_v56f16(<28 x float> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
@@ -20056,22 +20287,6 @@ define inreg <56 x half> @bitcast_v28f32_to_v56f16_scalar(<28 x float> inreg %a,
; SI-LABEL: bitcast_v28f32_to_v56f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
-; SI-NEXT: v_readfirstlane_b32 s43, v1
-; SI-NEXT: v_readfirstlane_b32 s42, v2
-; SI-NEXT: v_readfirstlane_b32 s41, v3
-; SI-NEXT: v_readfirstlane_b32 s40, v4
-; SI-NEXT: v_readfirstlane_b32 s15, v5
-; SI-NEXT: v_readfirstlane_b32 s14, v6
-; SI-NEXT: v_readfirstlane_b32 s13, v7
-; SI-NEXT: v_readfirstlane_b32 s12, v8
-; SI-NEXT: v_readfirstlane_b32 s11, v9
-; SI-NEXT: v_readfirstlane_b32 s10, v10
-; SI-NEXT: v_readfirstlane_b32 s8, v11
-; SI-NEXT: v_readfirstlane_b32 s7, v12
-; SI-NEXT: v_readfirstlane_b32 s6, v13
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s9, v14
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -20088,6 +20303,22 @@ define inreg <56 x half> @bitcast_v28f32_to_v56f16_scalar(<28 x float> inreg %a,
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
+; SI-NEXT: v_readfirstlane_b32 s43, v1
+; SI-NEXT: v_readfirstlane_b32 s42, v2
+; SI-NEXT: v_readfirstlane_b32 s41, v3
+; SI-NEXT: v_readfirstlane_b32 s40, v4
+; SI-NEXT: v_readfirstlane_b32 s15, v5
+; SI-NEXT: v_readfirstlane_b32 s14, v6
+; SI-NEXT: v_readfirstlane_b32 s13, v7
+; SI-NEXT: v_readfirstlane_b32 s12, v8
+; SI-NEXT: v_readfirstlane_b32 s11, v9
+; SI-NEXT: v_readfirstlane_b32 s10, v10
+; SI-NEXT: v_readfirstlane_b32 s8, v11
+; SI-NEXT: v_readfirstlane_b32 s7, v12
+; SI-NEXT: v_readfirstlane_b32 s6, v13
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s9, v14
; SI-NEXT: s_cbranch_scc0 .LBB33_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -20575,6 +20806,14 @@ define inreg <56 x half> @bitcast_v28f32_to_v56f16_scalar(<28 x float> inreg %a,
; VI-LABEL: bitcast_v28f32_to_v56f16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; VI-NEXT: v_mov_b32_e32 v20, s16
; VI-NEXT: v_mov_b32_e32 v18, s17
@@ -20591,14 +20830,6 @@ define inreg <56 x half> @bitcast_v28f32_to_v56f16_scalar(<28 x float> inreg %a,
; VI-NEXT: v_mov_b32_e32 v21, s27
; VI-NEXT: v_mov_b32_e32 v19, s28
; VI-NEXT: v_mov_b32_e32 v14, s29
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB33_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v13
@@ -20802,6 +21033,14 @@ define inreg <56 x half> @bitcast_v28f32_to_v56f16_scalar(<28 x float> inreg %a,
; GFX9-LABEL: bitcast_v28f32_to_v56f16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; GFX9-NEXT: v_mov_b32_e32 v20, s16
; GFX9-NEXT: v_mov_b32_e32 v18, s17
@@ -20818,14 +21057,6 @@ define inreg <56 x half> @bitcast_v28f32_to_v56f16_scalar(<28 x float> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v21, s27
; GFX9-NEXT: v_mov_b32_e32 v19, s28
; GFX9-NEXT: v_mov_b32_e32 v14, s29
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB33_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v13
@@ -23630,6 +23861,18 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; GFX9-LABEL: bitcast_v56f16_to_v28f32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v13
; GFX9-NEXT: v_mov_b32_e32 v33, v12
; GFX9-NEXT: v_mov_b32_e32 v34, v11
@@ -23659,18 +23902,6 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34
@@ -23826,90 +24057,167 @@ define inreg <28 x float> @bitcast_v56f16_to_v28f32_scalar(<56 x half> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v56f16_to_v28f32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3
@@ -25120,7 +25428,6 @@ define <56 x i16> @bitcast_v14i64_to_v56i16(<14 x i64> %a, i32 %b) {
; SI-LABEL: bitcast_v14i64_to_v56i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
@@ -25130,6 +25437,7 @@ define <56 x i16> @bitcast_v14i64_to_v56i16(<14 x i64> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr42
@@ -25446,7 +25754,6 @@ define <56 x i16> @bitcast_v14i64_to_v56i16(<14 x i64> %a, i32 %b) {
; VI-LABEL: bitcast_v14i64_to_v56i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -25455,6 +25762,7 @@ define <56 x i16> @bitcast_v14i64_to_v56i16(<14 x i64> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -25647,7 +25955,6 @@ define <56 x i16> @bitcast_v14i64_to_v56i16(<14 x i64> %a, i32 %b) {
; GFX9-LABEL: bitcast_v14i64_to_v56i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -25656,6 +25963,7 @@ define <56 x i16> @bitcast_v14i64_to_v56i16(<14 x i64> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
@@ -26068,8 +26376,9 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3
; SI-NEXT: v_writelane_b32 v16, s51, 9
; SI-NEXT: v_writelane_b32 v16, s52, 10
; SI-NEXT: v_writelane_b32 v16, s53, 11
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
; SI-NEXT: v_writelane_b32 v16, s30, 12
+; SI-NEXT: v_writelane_b32 v16, s31, 13
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
; SI-NEXT: v_readfirstlane_b32 s40, v1
; SI-NEXT: v_readfirstlane_b32 s41, v2
; SI-NEXT: v_readfirstlane_b32 s14, v3
@@ -26085,7 +26394,6 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v13
; SI-NEXT: s_and_b64 s[42:43], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v14
-; SI-NEXT: v_writelane_b32 v16, s31, 13
; SI-NEXT: s_cbranch_scc0 .LBB41_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s30, s5, 16
@@ -26424,8 +26732,9 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v28, s34, 0
; VI-NEXT: v_writelane_b32 v28, s35, 1
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; VI-NEXT: v_writelane_b32 v28, s30, 2
+; VI-NEXT: v_writelane_b32 v28, s31, 3
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; VI-NEXT: v_readfirstlane_b32 s43, v0
; VI-NEXT: v_readfirstlane_b32 s42, v1
; VI-NEXT: v_readfirstlane_b32 s41, v2
@@ -26441,7 +26750,6 @@ define inreg <56 x i16> @bitcast_v14i64_to_v56i16_scalar(<14 x i64> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s6, v12
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v13
-; VI-NEXT: v_writelane_b32 v28, s31, 3
; VI-NEXT: s_cbranch_scc0 .LBB41_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s44, s7, 16
@@ -29000,6 +29308,18 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; GFX9-LABEL: bitcast_v56i16_to_v14i64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v13
; GFX9-NEXT: v_mov_b32_e32 v33, v12
; GFX9-NEXT: v_mov_b32_e32 v34, v11
@@ -29029,18 +29349,6 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34
@@ -29194,90 +29502,167 @@ define inreg <14 x i64> @bitcast_v56i16_to_v14i64_scalar(<56 x i16> inreg %a, i3
; GFX11-TRUE16-LABEL: bitcast_v56i16_to_v14i64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3
@@ -29639,6 +30024,22 @@ define <56 x half> @bitcast_v14i64_to_v56f16(<14 x i64> %a, i32 %b) {
; SI-LABEL: bitcast_v14i64_to_v56f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; kill: killed $vgpr29
@@ -29681,22 +30082,6 @@ define <56 x half> @bitcast_v14i64_to_v56f16(<14 x i64> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; kill: killed $vgpr29
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr54
@@ -30282,7 +30667,6 @@ define <56 x half> @bitcast_v14i64_to_v56f16(<14 x i64> %a, i32 %b) {
; VI-LABEL: bitcast_v14i64_to_v56f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -30291,6 +30675,7 @@ define <56 x half> @bitcast_v14i64_to_v56f16(<14 x i64> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -30483,7 +30868,6 @@ define <56 x half> @bitcast_v14i64_to_v56f16(<14 x i64> %a, i32 %b) {
; GFX9-LABEL: bitcast_v14i64_to_v56f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -30492,6 +30876,7 @@ define <56 x half> @bitcast_v14i64_to_v56f16(<14 x i64> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
@@ -30888,6 +31273,15 @@ define inreg <56 x half> @bitcast_v14i64_to_v56f16_scalar(<14 x i64> inreg %a, i
; SI-LABEL: bitcast_v14i64_to_v56f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
; SI-NEXT: v_readfirstlane_b32 s42, v1
; SI-NEXT: v_readfirstlane_b32 s43, v2
@@ -30904,15 +31298,6 @@ define inreg <56 x half> @bitcast_v14i64_to_v56f16_scalar(<14 x i64> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s6, v13
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v14
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB45_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -31395,8 +31780,9 @@ define inreg <56 x half> @bitcast_v14i64_to_v56f16_scalar(<14 x i64> inreg %a, i
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v28, s34, 0
; VI-NEXT: v_writelane_b32 v28, s35, 1
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; VI-NEXT: v_writelane_b32 v28, s30, 2
+; VI-NEXT: v_writelane_b32 v28, s31, 3
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; VI-NEXT: v_readfirstlane_b32 s43, v0
; VI-NEXT: v_readfirstlane_b32 s42, v1
; VI-NEXT: v_readfirstlane_b32 s41, v2
@@ -31412,7 +31798,6 @@ define inreg <56 x half> @bitcast_v14i64_to_v56f16_scalar(<14 x i64> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s6, v12
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v13
-; VI-NEXT: v_writelane_b32 v28, s31, 3
; VI-NEXT: s_cbranch_scc0 .LBB45_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s44, s7, 16
@@ -34276,6 +34661,18 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; GFX9-LABEL: bitcast_v56f16_to_v14i64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v13
; GFX9-NEXT: v_mov_b32_e32 v33, v12
; GFX9-NEXT: v_mov_b32_e32 v34, v11
@@ -34305,18 +34702,6 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34
@@ -34472,90 +34857,167 @@ define inreg <14 x i64> @bitcast_v56f16_to_v14i64_scalar(<56 x half> inreg %a, i
; GFX11-TRUE16-LABEL: bitcast_v56f16_to_v14i64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3
@@ -34917,7 +35379,6 @@ define <56 x i16> @bitcast_v14f64_to_v56i16(<14 x double> %a, i32 %b) {
; SI-LABEL: bitcast_v14f64_to_v56i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
@@ -34927,6 +35388,7 @@ define <56 x i16> @bitcast_v14f64_to_v56i16(<14 x double> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr42
@@ -35229,7 +35691,6 @@ define <56 x i16> @bitcast_v14f64_to_v56i16(<14 x double> %a, i32 %b) {
; VI-LABEL: bitcast_v14f64_to_v56i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -35238,6 +35699,7 @@ define <56 x i16> @bitcast_v14f64_to_v56i16(<14 x double> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -35416,7 +35878,6 @@ define <56 x i16> @bitcast_v14f64_to_v56i16(<14 x double> %a, i32 %b) {
; GFX9-LABEL: bitcast_v14f64_to_v56i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -35425,6 +35886,7 @@ define <56 x i16> @bitcast_v14f64_to_v56i16(<14 x double> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
@@ -35765,6 +36227,18 @@ define inreg <56 x i16> @bitcast_v14f64_to_v56i16_scalar(<14 x double> inreg %a,
; SI-LABEL: bitcast_v14f64_to_v56i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
; SI-NEXT: v_mov_b32_e32 v27, s16
; SI-NEXT: v_mov_b32_e32 v28, s17
@@ -35781,18 +36255,6 @@ define inreg <56 x i16> @bitcast_v14f64_to_v56i16_scalar(<14 x double> inreg %a,
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_mov_b32_e32 v15, s28
; SI-NEXT: v_mov_b32_e32 v16, s29
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB49_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_lshr_b64 v[29:30], v[13:14], 16
@@ -36096,6 +36558,14 @@ define inreg <56 x i16> @bitcast_v14f64_to_v56i16_scalar(<14 x double> inreg %a,
; VI-LABEL: bitcast_v14f64_to_v56i16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; VI-NEXT: v_mov_b32_e32 v19, s16
; VI-NEXT: v_mov_b32_e32 v20, s17
@@ -36112,14 +36582,6 @@ define inreg <56 x i16> @bitcast_v14f64_to_v56i16_scalar(<14 x double> inreg %a,
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_mov_b32_e32 v17, s28
; VI-NEXT: v_mov_b32_e32 v18, s29
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB49_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v13
@@ -36309,6 +36771,14 @@ define inreg <56 x i16> @bitcast_v14f64_to_v56i16_scalar(<14 x double> inreg %a,
; GFX9-LABEL: bitcast_v14f64_to_v56i16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; GFX9-NEXT: v_mov_b32_e32 v19, s16
; GFX9-NEXT: v_mov_b32_e32 v20, s17
@@ -36325,14 +36795,6 @@ define inreg <56 x i16> @bitcast_v14f64_to_v56i16_scalar(<14 x double> inreg %a,
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_mov_b32_e32 v17, s28
; GFX9-NEXT: v_mov_b32_e32 v18, s29
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB49_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v13
@@ -38818,6 +39280,18 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; GFX9-LABEL: bitcast_v56i16_to_v14f64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v13
; GFX9-NEXT: v_mov_b32_e32 v33, v12
; GFX9-NEXT: v_mov_b32_e32 v34, v11
@@ -38847,18 +39321,6 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34
@@ -39012,90 +39474,167 @@ define inreg <14 x double> @bitcast_v56i16_to_v14f64_scalar(<56 x i16> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v56i16_to_v14f64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3
@@ -39457,6 +39996,22 @@ define <56 x half> @bitcast_v14f64_to_v56f16(<14 x double> %a, i32 %b) {
; SI-LABEL: bitcast_v14f64_to_v56f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v29
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; kill: killed $vgpr29
@@ -39499,22 +40054,6 @@ define <56 x half> @bitcast_v14f64_to_v56f16(<14 x double> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; kill: killed $vgpr29
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr40
@@ -40071,7 +40610,6 @@ define <56 x half> @bitcast_v14f64_to_v56f16(<14 x double> %a, i32 %b) {
; VI-LABEL: bitcast_v14f64_to_v56f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -40080,6 +40618,7 @@ define <56 x half> @bitcast_v14f64_to_v56f16(<14 x double> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
@@ -40258,7 +40797,6 @@ define <56 x half> @bitcast_v14f64_to_v56f16(<14 x double> %a, i32 %b) {
; GFX9-LABEL: bitcast_v14f64_to_v56f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -40267,6 +40805,7 @@ define <56 x half> @bitcast_v14f64_to_v56f16(<14 x double> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
@@ -40607,22 +41146,6 @@ define inreg <56 x half> @bitcast_v14f64_to_v56f16_scalar(<14 x double> inreg %a
; SI-LABEL: bitcast_v14f64_to_v56f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
-; SI-NEXT: v_readfirstlane_b32 s40, v1
-; SI-NEXT: v_readfirstlane_b32 s41, v2
-; SI-NEXT: v_readfirstlane_b32 s14, v3
-; SI-NEXT: v_readfirstlane_b32 s15, v4
-; SI-NEXT: v_readfirstlane_b32 s12, v5
-; SI-NEXT: v_readfirstlane_b32 s13, v6
-; SI-NEXT: v_readfirstlane_b32 s10, v7
-; SI-NEXT: v_readfirstlane_b32 s11, v8
-; SI-NEXT: v_readfirstlane_b32 s8, v9
-; SI-NEXT: v_readfirstlane_b32 s9, v10
-; SI-NEXT: v_readfirstlane_b32 s6, v11
-; SI-NEXT: v_readfirstlane_b32 s7, v12
-; SI-NEXT: v_readfirstlane_b32 s4, v13
-; SI-NEXT: s_and_b64 s[42:43], vcc, exec
-; SI-NEXT: v_readfirstlane_b32 s5, v14
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -40639,6 +41162,22 @@ define inreg <56 x half> @bitcast_v14f64_to_v56f16_scalar(<14 x double> inreg %a
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15
+; SI-NEXT: v_readfirstlane_b32 s40, v1
+; SI-NEXT: v_readfirstlane_b32 s41, v2
+; SI-NEXT: v_readfirstlane_b32 s14, v3
+; SI-NEXT: v_readfirstlane_b32 s15, v4
+; SI-NEXT: v_readfirstlane_b32 s12, v5
+; SI-NEXT: v_readfirstlane_b32 s13, v6
+; SI-NEXT: v_readfirstlane_b32 s10, v7
+; SI-NEXT: v_readfirstlane_b32 s11, v8
+; SI-NEXT: v_readfirstlane_b32 s8, v9
+; SI-NEXT: v_readfirstlane_b32 s9, v10
+; SI-NEXT: v_readfirstlane_b32 s6, v11
+; SI-NEXT: v_readfirstlane_b32 s7, v12
+; SI-NEXT: v_readfirstlane_b32 s4, v13
+; SI-NEXT: s_and_b64 s[42:43], vcc, exec
+; SI-NEXT: v_readfirstlane_b32 s5, v14
; SI-NEXT: s_cbranch_scc0 .LBB53_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s42, s5, 16
@@ -41120,6 +41659,14 @@ define inreg <56 x half> @bitcast_v14f64_to_v56f16_scalar(<14 x double> inreg %a
; VI-LABEL: bitcast_v14f64_to_v56f16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; VI-NEXT: v_mov_b32_e32 v19, s16
; VI-NEXT: v_mov_b32_e32 v20, s17
@@ -41136,14 +41683,6 @@ define inreg <56 x half> @bitcast_v14f64_to_v56f16_scalar(<14 x double> inreg %a
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_mov_b32_e32 v17, s28
; VI-NEXT: v_mov_b32_e32 v18, s29
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB53_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v13
@@ -41333,6 +41872,14 @@ define inreg <56 x half> @bitcast_v14f64_to_v56f16_scalar(<14 x double> inreg %a
; GFX9-LABEL: bitcast_v14f64_to_v56f16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; GFX9-NEXT: v_mov_b32_e32 v19, s16
; GFX9-NEXT: v_mov_b32_e32 v20, s17
@@ -41349,14 +41896,6 @@ define inreg <56 x half> @bitcast_v14f64_to_v56f16_scalar(<14 x double> inreg %a
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_mov_b32_e32 v17, s28
; GFX9-NEXT: v_mov_b32_e32 v18, s29
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB53_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v13
@@ -44147,6 +44686,18 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; GFX9-LABEL: bitcast_v56f16_to_v14f64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v13
; GFX9-NEXT: v_mov_b32_e32 v33, v12
; GFX9-NEXT: v_mov_b32_e32 v34, v11
@@ -44176,18 +44727,6 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v34
@@ -44343,90 +44882,167 @@ define inreg <14 x double> @bitcast_v56f16_to_v14f64_scalar(<56 x half> inreg %a
; GFX11-TRUE16-LABEL: bitcast_v56f16_to_v14f64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v189, v5
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v6 :: v_dual_mov_b32 v191, v3
@@ -47265,6 +47881,14 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; GFX9-LABEL: bitcast_v56i16_to_v56f16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; GFX9-NEXT: s_lshr_b32 s43, s29, 16
; GFX9-NEXT: s_lshr_b32 s42, s28, 16
@@ -47295,14 +47919,6 @@ define inreg <56 x half> @bitcast_v56i16_to_v56f16_scalar(<56 x i16> inreg %a, i
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v0
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB57_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_cbranch_execnz .LBB57_4
@@ -49736,6 +50352,14 @@ define inreg <56 x i16> @bitcast_v56f16_to_v56i16_scalar(<56 x half> inreg %a, i
; VI-LABEL: bitcast_v56f16_to_v56i16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; VI-NEXT: s_lshr_b32 s6, s29, 16
; VI-NEXT: s_lshr_b32 s7, s28, 16
@@ -49766,14 +50390,6 @@ define inreg <56 x i16> @bitcast_v56f16_to_v56i16_scalar(<56 x half> inreg %a, i
; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v0
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB59_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB59_4
@@ -49952,6 +50568,14 @@ define inreg <56 x i16> @bitcast_v56f16_to_v56i16_scalar(<56 x half> inreg %a, i
; GFX9-LABEL: bitcast_v56f16_to_v56i16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; GFX9-NEXT: s_lshr_b32 s43, s29, 16
; GFX9-NEXT: s_lshr_b32 s42, s28, 16
@@ -49982,14 +50606,6 @@ define inreg <56 x i16> @bitcast_v56f16_to_v56i16_scalar(<56 x half> inreg %a, i
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v0
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB59_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_cbranch_execnz .LBB59_4
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
index c23182f2b30b9..134980045bb53 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
@@ -2849,7 +2849,6 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) {
; SI-LABEL: bitcast_v30i32_to_v60i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
@@ -2863,6 +2862,7 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr46
@@ -2892,7 +2892,7 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -3205,7 +3205,6 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) {
; VI-LABEL: bitcast_v30i32_to_v60i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -3218,6 +3217,7 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -3426,7 +3426,6 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) {
; GFX9-LABEL: bitcast_v30i32_to_v60i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -3439,6 +3438,7 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr57
@@ -3866,8 +3866,9 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; SI-NEXT: v_writelane_b32 v18, s54, 12
; SI-NEXT: v_writelane_b32 v18, s55, 13
; SI-NEXT: v_writelane_b32 v18, s64, 14
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
; SI-NEXT: v_writelane_b32 v18, s30, 15
+; SI-NEXT: v_writelane_b32 v18, s31, 16
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
; SI-NEXT: v_readfirstlane_b32 s42, v1
; SI-NEXT: v_readfirstlane_b32 s43, v2
; SI-NEXT: v_readfirstlane_b32 s40, v3
@@ -3885,7 +3886,6 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v15
; SI-NEXT: s_and_b64 s[44:45], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v16
-; SI-NEXT: v_writelane_b32 v18, s31, 16
; SI-NEXT: s_cbranch_scc0 .LBB13_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s34, s5, 16
@@ -4251,8 +4251,9 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; VI-NEXT: v_writelane_b32 v30, s37, 3
; VI-NEXT: v_writelane_b32 v30, s38, 4
; VI-NEXT: v_writelane_b32 v30, s39, 5
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; VI-NEXT: v_writelane_b32 v30, s30, 6
+; VI-NEXT: v_writelane_b32 v30, s31, 7
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; VI-NEXT: v_readfirstlane_b32 s45, v0
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: v_readfirstlane_b32 s43, v2
@@ -4270,7 +4271,6 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s6, v14
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v15
-; VI-NEXT: v_writelane_b32 v30, s31, 7
; VI-NEXT: s_cbranch_scc0 .LBB13_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s46, s7, 16
@@ -4540,8 +4540,9 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v30, s34, 0
; GFX9-NEXT: v_writelane_b32 v30, s35, 1
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GFX9-NEXT: v_writelane_b32 v30, s30, 2
+; GFX9-NEXT: v_writelane_b32 v30, s31, 3
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GFX9-NEXT: v_readfirstlane_b32 s6, v0
; GFX9-NEXT: v_readfirstlane_b32 s7, v1
; GFX9-NEXT: v_readfirstlane_b32 s8, v2
@@ -4559,7 +4560,6 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s44, v14
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s45, v15
-; GFX9-NEXT: v_writelane_b32 v30, s31, 3
; GFX9-NEXT: s_cbranch_scc0 .LBB13_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s46, s45, 16
@@ -7024,6 +7024,22 @@ define inreg <30 x i32> @bitcast_v60i16_to_v30i32_scalar(<60 x i16> inreg %a, i3
; GFX9-LABEL: bitcast_v60i16_to_v30i32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v15
; GFX9-NEXT: v_mov_b32_e32 v33, v14
; GFX9-NEXT: v_mov_b32_e32 v34, v13
@@ -7055,22 +7071,6 @@ define inreg <30 x i32> @bitcast_v60i16_to_v30i32_scalar(<60 x i16> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34
@@ -7240,90 +7240,167 @@ define inreg <30 x i32> @bitcast_v60i16_to_v30i32_scalar(<60 x i16> inreg %a, i3
; GFX11-TRUE16-LABEL: bitcast_v60i16_to_v30i32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5
@@ -7701,6 +7778,22 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) {
; SI-LABEL: bitcast_v30i32_to_v60f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr32
@@ -7735,22 +7828,6 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr46
@@ -7784,7 +7861,7 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; kill: killed $vgpr31
@@ -8414,7 +8491,6 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) {
; VI-LABEL: bitcast_v30i32_to_v60f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -8427,6 +8503,7 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -8635,7 +8712,6 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) {
; GFX9-LABEL: bitcast_v30i32_to_v60f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -8648,6 +8724,7 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr57
@@ -9056,6 +9133,19 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i
; SI-LABEL: bitcast_v30i32_to_v60f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
; SI-NEXT: v_readfirstlane_b32 s45, v1
; SI-NEXT: v_readfirstlane_b32 s44, v2
@@ -9074,19 +9164,6 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s6, v15
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v16
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB17_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -9609,8 +9686,9 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i
; VI-NEXT: v_writelane_b32 v30, s37, 3
; VI-NEXT: v_writelane_b32 v30, s38, 4
; VI-NEXT: v_writelane_b32 v30, s39, 5
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; VI-NEXT: v_writelane_b32 v30, s30, 6
+; VI-NEXT: v_writelane_b32 v30, s31, 7
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; VI-NEXT: v_readfirstlane_b32 s45, v0
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: v_readfirstlane_b32 s43, v2
@@ -9628,7 +9706,6 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s6, v14
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v15
-; VI-NEXT: v_writelane_b32 v30, s31, 7
; VI-NEXT: s_cbranch_scc0 .LBB17_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s46, s7, 16
@@ -9898,8 +9975,9 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v30, s34, 0
; GFX9-NEXT: v_writelane_b32 v30, s35, 1
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GFX9-NEXT: v_writelane_b32 v30, s30, 2
+; GFX9-NEXT: v_writelane_b32 v30, s31, 3
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GFX9-NEXT: v_readfirstlane_b32 s6, v0
; GFX9-NEXT: v_readfirstlane_b32 s7, v1
; GFX9-NEXT: v_readfirstlane_b32 s8, v2
@@ -9917,7 +9995,6 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i
; GFX9-NEXT: v_readfirstlane_b32 s44, v14
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s45, v15
-; GFX9-NEXT: v_writelane_b32 v30, s31, 3
; GFX9-NEXT: s_cbranch_scc0 .LBB17_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s46, s45, 16
@@ -12774,6 +12851,22 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; GFX9-LABEL: bitcast_v60f16_to_v30i32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v15
; GFX9-NEXT: v_mov_b32_e32 v33, v14
; GFX9-NEXT: v_mov_b32_e32 v34, v13
@@ -12805,22 +12898,6 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34
@@ -12992,90 +13069,167 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i
; GFX11-TRUE16-LABEL: bitcast_v60f16_to_v30i32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5
@@ -15272,7 +15426,6 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) {
; SI-LABEL: bitcast_v30f32_to_v60i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
@@ -15286,6 +15439,7 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr46
@@ -15315,7 +15469,7 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -15628,7 +15782,6 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) {
; VI-LABEL: bitcast_v30f32_to_v60i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -15641,6 +15794,7 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -15849,7 +16003,6 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) {
; GFX9-LABEL: bitcast_v30f32_to_v60i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -15862,6 +16015,7 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr57
@@ -16240,6 +16394,21 @@ define inreg <60 x i16> @bitcast_v30f32_to_v60i16_scalar(<30 x float> inreg %a,
; SI-LABEL: bitcast_v30f32_to_v60i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
; SI-NEXT: v_mov_b32_e32 v27, s16
; SI-NEXT: v_mov_b32_e32 v28, s17
@@ -16256,21 +16425,6 @@ define inreg <60 x i16> @bitcast_v30f32_to_v60i16_scalar(<30 x float> inreg %a,
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_mov_b32_e32 v17, s28
; SI-NEXT: v_mov_b32_e32 v18, s29
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB29_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_lshr_b64 v[31:32], v[15:16], 16
@@ -16611,6 +16765,18 @@ define inreg <60 x i16> @bitcast_v30f32_to_v60i16_scalar(<30 x float> inreg %a,
; VI-LABEL: bitcast_v30f32_to_v60i16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; VI-NEXT: v_mov_b32_e32 v19, s16
; VI-NEXT: v_mov_b32_e32 v18, s17
@@ -16627,18 +16793,6 @@ define inreg <60 x i16> @bitcast_v30f32_to_v60i16_scalar(<30 x float> inreg %a,
; VI-NEXT: v_mov_b32_e32 v21, s27
; VI-NEXT: v_mov_b32_e32 v20, s28
; VI-NEXT: v_mov_b32_e32 v16, s29
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB29_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v15
@@ -16860,6 +17014,18 @@ define inreg <60 x i16> @bitcast_v30f32_to_v60i16_scalar(<30 x float> inreg %a,
; GFX9-LABEL: bitcast_v30f32_to_v60i16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GFX9-NEXT: v_mov_b32_e32 v19, s16
; GFX9-NEXT: v_mov_b32_e32 v18, s17
@@ -16876,18 +17042,6 @@ define inreg <60 x i16> @bitcast_v30f32_to_v60i16_scalar(<30 x float> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v21, s27
; GFX9-NEXT: v_mov_b32_e32 v20, s28
; GFX9-NEXT: v_mov_b32_e32 v16, s29
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB29_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v15
@@ -19562,6 +19716,22 @@ define inreg <30 x float> @bitcast_v60i16_to_v30f32_scalar(<60 x i16> inreg %a,
; GFX9-LABEL: bitcast_v60i16_to_v30f32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v15
; GFX9-NEXT: v_mov_b32_e32 v33, v14
; GFX9-NEXT: v_mov_b32_e32 v34, v13
@@ -19593,22 +19763,6 @@ define inreg <30 x float> @bitcast_v60i16_to_v30f32_scalar(<60 x i16> inreg %a,
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34
@@ -19778,90 +19932,167 @@ define inreg <30 x float> @bitcast_v60i16_to_v30f32_scalar(<60 x i16> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v60i16_to_v30f32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5
@@ -20239,6 +20470,22 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) {
; SI-LABEL: bitcast_v30f32_to_v60f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr32
@@ -20273,22 +20520,6 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr46
@@ -20322,7 +20553,7 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; kill: killed $vgpr31
@@ -20952,7 +21183,6 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) {
; VI-LABEL: bitcast_v30f32_to_v60f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -20965,6 +21195,7 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -21173,7 +21404,6 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) {
; GFX9-LABEL: bitcast_v30f32_to_v60f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -21186,6 +21416,7 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr57
@@ -21564,6 +21795,22 @@ define inreg <60 x half> @bitcast_v30f32_to_v60f16_scalar(<30 x float> inreg %a,
; SI-LABEL: bitcast_v30f32_to_v60f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
; SI-NEXT: v_readfirstlane_b32 s45, v1
; SI-NEXT: v_readfirstlane_b32 s44, v2
@@ -21582,22 +21829,6 @@ define inreg <60 x half> @bitcast_v30f32_to_v60f16_scalar(<30 x float> inreg %a,
; SI-NEXT: v_readfirstlane_b32 s6, v15
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v16
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB33_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -22130,6 +22361,18 @@ define inreg <60 x half> @bitcast_v30f32_to_v60f16_scalar(<30 x float> inreg %a,
; VI-LABEL: bitcast_v30f32_to_v60f16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; VI-NEXT: v_mov_b32_e32 v19, s16
; VI-NEXT: v_mov_b32_e32 v18, s17
@@ -22146,18 +22389,6 @@ define inreg <60 x half> @bitcast_v30f32_to_v60f16_scalar(<30 x float> inreg %a,
; VI-NEXT: v_mov_b32_e32 v21, s27
; VI-NEXT: v_mov_b32_e32 v20, s28
; VI-NEXT: v_mov_b32_e32 v16, s29
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB33_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v15
@@ -22379,6 +22610,18 @@ define inreg <60 x half> @bitcast_v30f32_to_v60f16_scalar(<30 x float> inreg %a,
; GFX9-LABEL: bitcast_v30f32_to_v60f16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GFX9-NEXT: v_mov_b32_e32 v19, s16
; GFX9-NEXT: v_mov_b32_e32 v18, s17
@@ -22395,18 +22638,6 @@ define inreg <60 x half> @bitcast_v30f32_to_v60f16_scalar(<30 x float> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v21, s27
; GFX9-NEXT: v_mov_b32_e32 v20, s28
; GFX9-NEXT: v_mov_b32_e32 v16, s29
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB33_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v15
@@ -25473,6 +25704,22 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; GFX9-LABEL: bitcast_v60f16_to_v30f32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v15
; GFX9-NEXT: v_mov_b32_e32 v33, v14
; GFX9-NEXT: v_mov_b32_e32 v34, v13
@@ -25504,22 +25751,6 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34
@@ -25691,90 +25922,167 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v60f16_to_v30f32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5
@@ -27041,7 +27349,6 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) {
; SI-LABEL: bitcast_v15i64_to_v60i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
@@ -27055,6 +27362,7 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr46
@@ -27084,7 +27392,7 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -27397,7 +27705,6 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) {
; VI-LABEL: bitcast_v15i64_to_v60i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -27410,6 +27717,7 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -27618,7 +27926,6 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) {
; GFX9-LABEL: bitcast_v15i64_to_v60i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -27631,6 +27938,7 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr57
@@ -28074,8 +28382,9 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; SI-NEXT: v_writelane_b32 v18, s54, 12
; SI-NEXT: v_writelane_b32 v18, s55, 13
; SI-NEXT: v_writelane_b32 v18, s64, 14
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
; SI-NEXT: v_writelane_b32 v18, s30, 15
+; SI-NEXT: v_writelane_b32 v18, s31, 16
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
; SI-NEXT: v_readfirstlane_b32 s42, v1
; SI-NEXT: v_readfirstlane_b32 s43, v2
; SI-NEXT: v_readfirstlane_b32 s40, v3
@@ -28093,7 +28402,6 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; SI-NEXT: v_readfirstlane_b32 s4, v15
; SI-NEXT: s_and_b64 s[44:45], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v16
-; SI-NEXT: v_writelane_b32 v18, s31, 16
; SI-NEXT: s_cbranch_scc0 .LBB41_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s34, s5, 16
@@ -28459,8 +28767,9 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; VI-NEXT: v_writelane_b32 v30, s37, 3
; VI-NEXT: v_writelane_b32 v30, s38, 4
; VI-NEXT: v_writelane_b32 v30, s39, 5
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; VI-NEXT: v_writelane_b32 v30, s30, 6
+; VI-NEXT: v_writelane_b32 v30, s31, 7
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; VI-NEXT: v_readfirstlane_b32 s45, v0
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: v_readfirstlane_b32 s43, v2
@@ -28478,7 +28787,6 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s6, v14
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v15
-; VI-NEXT: v_writelane_b32 v30, s31, 7
; VI-NEXT: s_cbranch_scc0 .LBB41_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s46, s7, 16
@@ -28748,8 +29056,9 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v30, s34, 0
; GFX9-NEXT: v_writelane_b32 v30, s35, 1
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GFX9-NEXT: v_writelane_b32 v30, s30, 2
+; GFX9-NEXT: v_writelane_b32 v30, s31, 3
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GFX9-NEXT: v_readfirstlane_b32 s6, v0
; GFX9-NEXT: v_readfirstlane_b32 s7, v1
; GFX9-NEXT: v_readfirstlane_b32 s8, v2
@@ -28767,7 +29076,6 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s44, v14
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s45, v15
-; GFX9-NEXT: v_writelane_b32 v30, s31, 3
; GFX9-NEXT: s_cbranch_scc0 .LBB41_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s46, s45, 16
@@ -31232,6 +31540,22 @@ define inreg <15 x i64> @bitcast_v60i16_to_v15i64_scalar(<60 x i16> inreg %a, i3
; GFX9-LABEL: bitcast_v60i16_to_v15i64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v15
; GFX9-NEXT: v_mov_b32_e32 v33, v14
; GFX9-NEXT: v_mov_b32_e32 v34, v13
@@ -31263,22 +31587,6 @@ define inreg <15 x i64> @bitcast_v60i16_to_v15i64_scalar(<60 x i16> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34
@@ -31448,90 +31756,167 @@ define inreg <15 x i64> @bitcast_v60i16_to_v15i64_scalar(<60 x i16> inreg %a, i3
; GFX11-TRUE16-LABEL: bitcast_v60i16_to_v15i64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5
@@ -31909,6 +32294,22 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) {
; SI-LABEL: bitcast_v15i64_to_v60f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr32
@@ -31943,22 +32344,6 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; kill: killed $vgpr32
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr46
@@ -31992,7 +32377,7 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; kill: killed $vgpr31
@@ -32623,7 +33008,6 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) {
; VI-LABEL: bitcast_v15i64_to_v60f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -32636,6 +33020,7 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -32844,7 +33229,6 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) {
; GFX9-LABEL: bitcast_v15i64_to_v60f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -32857,6 +33241,7 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr57
@@ -33281,6 +33666,19 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i
; SI-LABEL: bitcast_v15i64_to_v60f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
; SI-NEXT: v_readfirstlane_b32 s44, v1
; SI-NEXT: v_readfirstlane_b32 s45, v2
@@ -33299,19 +33697,6 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i
; SI-NEXT: v_readfirstlane_b32 s6, v15
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s9, v16
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB45_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s4, s9, 16
@@ -33834,8 +34219,9 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i
; VI-NEXT: v_writelane_b32 v30, s37, 3
; VI-NEXT: v_writelane_b32 v30, s38, 4
; VI-NEXT: v_writelane_b32 v30, s39, 5
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; VI-NEXT: v_writelane_b32 v30, s30, 6
+; VI-NEXT: v_writelane_b32 v30, s31, 7
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; VI-NEXT: v_readfirstlane_b32 s45, v0
; VI-NEXT: v_readfirstlane_b32 s44, v1
; VI-NEXT: v_readfirstlane_b32 s43, v2
@@ -33853,7 +34239,6 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i
; VI-NEXT: v_readfirstlane_b32 s6, v14
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_readfirstlane_b32 s7, v15
-; VI-NEXT: v_writelane_b32 v30, s31, 7
; VI-NEXT: s_cbranch_scc0 .LBB45_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s46, s7, 16
@@ -34123,8 +34508,9 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v30, s34, 0
; GFX9-NEXT: v_writelane_b32 v30, s35, 1
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GFX9-NEXT: v_writelane_b32 v30, s30, 2
+; GFX9-NEXT: v_writelane_b32 v30, s31, 3
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GFX9-NEXT: v_readfirstlane_b32 s6, v0
; GFX9-NEXT: v_readfirstlane_b32 s7, v1
; GFX9-NEXT: v_readfirstlane_b32 s8, v2
@@ -34142,7 +34528,6 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i
; GFX9-NEXT: v_readfirstlane_b32 s44, v14
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s45, v15
-; GFX9-NEXT: v_writelane_b32 v30, s31, 3
; GFX9-NEXT: s_cbranch_scc0 .LBB45_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s46, s45, 16
@@ -36999,6 +37384,22 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; GFX9-LABEL: bitcast_v60f16_to_v15i64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v15
; GFX9-NEXT: v_mov_b32_e32 v33, v14
; GFX9-NEXT: v_mov_b32_e32 v34, v13
@@ -37030,22 +37431,6 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34
@@ -37217,90 +37602,167 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i
; GFX11-TRUE16-LABEL: bitcast_v60f16_to_v15i64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5
@@ -37678,7 +38140,6 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) {
; SI-LABEL: bitcast_v15f64_to_v60i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
@@ -37692,6 +38153,7 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) {
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr46
@@ -37721,7 +38183,7 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -38019,7 +38481,6 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) {
; VI-LABEL: bitcast_v15f64_to_v60i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -38032,6 +38493,7 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -38225,7 +38687,6 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) {
; GFX9-LABEL: bitcast_v15f64_to_v60i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -38238,6 +38699,7 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr57
@@ -38601,22 +39063,6 @@ define inreg <60 x i16> @bitcast_v15f64_to_v60i16_scalar(<15 x double> inreg %a,
; SI-LABEL: bitcast_v15f64_to_v60i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
-; SI-NEXT: v_mov_b32_e32 v27, s16
-; SI-NEXT: v_mov_b32_e32 v28, s17
-; SI-NEXT: v_mov_b32_e32 v29, s18
-; SI-NEXT: v_mov_b32_e32 v30, s19
-; SI-NEXT: v_mov_b32_e32 v25, s20
-; SI-NEXT: v_mov_b32_e32 v26, s21
-; SI-NEXT: v_mov_b32_e32 v23, s22
-; SI-NEXT: v_mov_b32_e32 v24, s23
-; SI-NEXT: v_mov_b32_e32 v21, s24
-; SI-NEXT: v_mov_b32_e32 v22, s25
-; SI-NEXT: v_mov_b32_e32 v19, s26
-; SI-NEXT: v_mov_b32_e32 v20, s27
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mov_b32_e32 v17, s28
-; SI-NEXT: v_mov_b32_e32 v18, s29
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
@@ -38633,6 +39079,22 @@ define inreg <60 x i16> @bitcast_v15f64_to_v60i16_scalar(<15 x double> inreg %a,
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
+; SI-NEXT: v_mov_b32_e32 v27, s16
+; SI-NEXT: v_mov_b32_e32 v28, s17
+; SI-NEXT: v_mov_b32_e32 v29, s18
+; SI-NEXT: v_mov_b32_e32 v30, s19
+; SI-NEXT: v_mov_b32_e32 v25, s20
+; SI-NEXT: v_mov_b32_e32 v26, s21
+; SI-NEXT: v_mov_b32_e32 v23, s22
+; SI-NEXT: v_mov_b32_e32 v24, s23
+; SI-NEXT: v_mov_b32_e32 v21, s24
+; SI-NEXT: v_mov_b32_e32 v22, s25
+; SI-NEXT: v_mov_b32_e32 v19, s26
+; SI-NEXT: v_mov_b32_e32 v20, s27
+; SI-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-NEXT: v_mov_b32_e32 v17, s28
+; SI-NEXT: v_mov_b32_e32 v18, s29
; SI-NEXT: s_cbranch_scc0 .LBB49_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_lshr_b64 v[31:32], v[15:16], 16
@@ -38959,6 +39421,18 @@ define inreg <60 x i16> @bitcast_v15f64_to_v60i16_scalar(<15 x double> inreg %a,
; VI-LABEL: bitcast_v15f64_to_v60i16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; VI-NEXT: v_mov_b32_e32 v17, s16
; VI-NEXT: v_mov_b32_e32 v18, s17
@@ -38975,18 +39449,6 @@ define inreg <60 x i16> @bitcast_v15f64_to_v60i16_scalar(<15 x double> inreg %a,
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_mov_b32_e32 v19, s28
; VI-NEXT: v_mov_b32_e32 v20, s29
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB49_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v15
@@ -39193,6 +39655,18 @@ define inreg <60 x i16> @bitcast_v15f64_to_v60i16_scalar(<15 x double> inreg %a,
; GFX9-LABEL: bitcast_v15f64_to_v60i16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GFX9-NEXT: v_mov_b32_e32 v17, s16
; GFX9-NEXT: v_mov_b32_e32 v18, s17
@@ -39209,18 +39683,6 @@ define inreg <60 x i16> @bitcast_v15f64_to_v60i16_scalar(<15 x double> inreg %a,
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_mov_b32_e32 v19, s28
; GFX9-NEXT: v_mov_b32_e32 v20, s29
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB49_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v15
@@ -41880,6 +42342,22 @@ define inreg <15 x double> @bitcast_v60i16_to_v15f64_scalar(<60 x i16> inreg %a,
; GFX9-LABEL: bitcast_v60i16_to_v15f64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v15
; GFX9-NEXT: v_mov_b32_e32 v33, v14
; GFX9-NEXT: v_mov_b32_e32 v34, v13
@@ -41911,22 +42389,6 @@ define inreg <15 x double> @bitcast_v60i16_to_v15f64_scalar(<60 x i16> inreg %a,
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34
@@ -42096,90 +42558,167 @@ define inreg <15 x double> @bitcast_v60i16_to_v15f64_scalar(<60 x i16> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v60i16_to_v15f64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5
@@ -42557,6 +43096,22 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) {
; SI-LABEL: bitcast_v15f64_to_v60f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr38
@@ -42579,22 +43134,6 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) {
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; kill: killed $vgpr38
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr55
@@ -42627,7 +43166,7 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) {
; SI-NEXT: ; kill: killed $vgpr38
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; kill: killed $vgpr31
@@ -43240,7 +43779,6 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) {
; VI-LABEL: bitcast_v15f64_to_v60f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -43253,6 +43791,7 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) {
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; VI-NEXT: ; implicit-def: $vgpr59
; VI-NEXT: ; implicit-def: $vgpr58
; VI-NEXT: ; implicit-def: $vgpr57
@@ -43446,7 +43985,6 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) {
; GFX9-LABEL: bitcast_v15f64_to_v60f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
@@ -43459,6 +43997,7 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) {
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr57
@@ -43822,6 +44361,22 @@ define inreg <60 x half> @bitcast_v15f64_to_v60f16_scalar(<15 x double> inreg %a
; SI-LABEL: bitcast_v15f64_to_v60f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
; SI-NEXT: v_readfirstlane_b32 s42, v1
; SI-NEXT: v_readfirstlane_b32 s43, v2
@@ -43840,22 +44395,6 @@ define inreg <60 x half> @bitcast_v15f64_to_v60f16_scalar(<15 x double> inreg %a
; SI-NEXT: v_readfirstlane_b32 s4, v15
; SI-NEXT: s_and_b64 s[44:45], vcc, exec
; SI-NEXT: v_readfirstlane_b32 s5, v16
-; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_cbranch_scc0 .LBB53_4
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s44, s5, 16
@@ -44378,6 +44917,18 @@ define inreg <60 x half> @bitcast_v15f64_to_v60f16_scalar(<15 x double> inreg %a
; VI-LABEL: bitcast_v15f64_to_v60f16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; VI-NEXT: v_mov_b32_e32 v17, s16
; VI-NEXT: v_mov_b32_e32 v18, s17
@@ -44394,18 +44945,6 @@ define inreg <60 x half> @bitcast_v15f64_to_v60f16_scalar(<15 x double> inreg %a
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: v_mov_b32_e32 v19, s28
; VI-NEXT: v_mov_b32_e32 v20, s29
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB53_4
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v15
@@ -44612,6 +45151,18 @@ define inreg <60 x half> @bitcast_v15f64_to_v60f16_scalar(<15 x double> inreg %a
; GFX9-LABEL: bitcast_v15f64_to_v60f16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GFX9-NEXT: v_mov_b32_e32 v17, s16
; GFX9-NEXT: v_mov_b32_e32 v18, s17
@@ -44628,18 +45179,6 @@ define inreg <60 x half> @bitcast_v15f64_to_v60f16_scalar(<15 x double> inreg %a
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: v_mov_b32_e32 v19, s28
; GFX9-NEXT: v_mov_b32_e32 v20, s29
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB53_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v15
@@ -47691,6 +48230,22 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; GFX9-LABEL: bitcast_v60f16_to_v15f64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v32, v15
; GFX9-NEXT: v_mov_b32_e32 v33, v14
; GFX9-NEXT: v_mov_b32_e32 v34, v13
@@ -47722,22 +48277,6 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v33
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v34
@@ -47909,90 +48448,167 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a
; GFX11-TRUE16-LABEL: bitcast_v60f16_to_v15f64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5
@@ -51092,6 +51708,18 @@ define inreg <60 x half> @bitcast_v60i16_to_v60f16_scalar(<60 x i16> inreg %a, i
; GFX9-LABEL: bitcast_v60i16_to_v60f16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GFX9-NEXT: s_lshr_b32 s43, s29, 16
; GFX9-NEXT: s_lshr_b32 s42, s28, 16
@@ -51124,18 +51752,6 @@ define inreg <60 x half> @bitcast_v60i16_to_v60f16_scalar(<60 x i16> inreg %a, i
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v0
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB57_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_cbranch_execnz .LBB57_4
@@ -53772,6 +54388,18 @@ define inreg <60 x i16> @bitcast_v60f16_to_v60i16_scalar(<60 x half> inreg %a, i
; VI-LABEL: bitcast_v60f16_to_v60i16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; VI-NEXT: s_lshr_b32 s6, s29, 16
; VI-NEXT: s_lshr_b32 s7, s28, 16
@@ -53804,18 +54432,6 @@ define inreg <60 x i16> @bitcast_v60f16_to_v60i16_scalar(<60 x half> inreg %a, i
; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v0
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB59_3
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_cbranch_execnz .LBB59_4
@@ -54008,6 +54624,18 @@ define inreg <60 x i16> @bitcast_v60f16_to_v60i16_scalar(<60 x half> inreg %a, i
; GFX9-LABEL: bitcast_v60f16_to_v60i16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
; GFX9-NEXT: s_lshr_b32 s43, s29, 16
; GFX9-NEXT: s_lshr_b32 s42, s28, 16
@@ -54040,18 +54668,6 @@ define inreg <60 x i16> @bitcast_v60f16_to_v60i16_scalar(<60 x half> inreg %a, i
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v0
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB59_3
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_cbranch_execnz .LBB59_4
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
index 36e2db0c4879d..a4882f1119e70 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
@@ -420,6 +420,7 @@ define amdgpu_cs_chain_preserve void @chain_preserve_to_chain_use_all_v0_v7(<3 x
; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX11-NEXT: s_clause 0x1
; GISEL-GFX11-NEXT: scratch_store_b32 off, v11, off offset:4
+; GISEL-GFX11-NEXT: ; meta instruction
; GISEL-GFX11-NEXT: scratch_store_b32 off, v16, off
; GISEL-GFX11-NEXT: v_mov_b32_e32 v11, v8
; GISEL-GFX11-NEXT: s_mov_b32 s3, s0
@@ -461,6 +462,7 @@ define amdgpu_cs_chain_preserve void @chain_preserve_to_chain_use_all_v0_v7(<3 x
; DAGISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; DAGISEL-GFX11-NEXT: s_clause 0x1
; DAGISEL-GFX11-NEXT: scratch_store_b32 off, v11, off offset:4
+; DAGISEL-GFX11-NEXT: ; meta instruction
; DAGISEL-GFX11-NEXT: scratch_store_b32 off, v16, off
; DAGISEL-GFX11-NEXT: v_mov_b32_e32 v11, v8
; DAGISEL-GFX11-NEXT: s_mov_b32 s3, s0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
index 6bbfcc9f52d95..954812c09d19a 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
@@ -118,32 +118,32 @@ define double @test_pow_fast_f64__integral_y(double %x, i32 %y.i) {
; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
; CHECK-NEXT: v_writelane_b32 v43, s16, 14
+; CHECK-NEXT: s_addk_i32 s32, 0x800
+; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
; CHECK-NEXT: v_writelane_b32 v43, s34, 0
; CHECK-NEXT: v_writelane_b32 v43, s35, 1
; CHECK-NEXT: v_writelane_b32 v43, s36, 2
; CHECK-NEXT: v_writelane_b32 v43, s37, 3
; CHECK-NEXT: v_writelane_b32 v43, s38, 4
; CHECK-NEXT: v_writelane_b32 v43, s39, 5
-; CHECK-NEXT: s_addk_i32 s32, 0x800
; CHECK-NEXT: v_writelane_b32 v43, s48, 6
; CHECK-NEXT: v_writelane_b32 v43, s49, 7
+; CHECK-NEXT: v_writelane_b32 v43, s50, 8
+; CHECK-NEXT: v_writelane_b32 v43, s51, 9
+; CHECK-NEXT: v_writelane_b32 v43, s52, 10
+; CHECK-NEXT: v_writelane_b32 v43, s53, 11
+; CHECK-NEXT: v_writelane_b32 v43, s30, 12
+; CHECK-NEXT: v_writelane_b32 v43, s31, 13
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d at gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d at gotpcrel32@hi+12
-; CHECK-NEXT: v_writelane_b32 v43, s50, 8
; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; CHECK-NEXT: v_writelane_b32 v43, s51, 9
-; CHECK-NEXT: v_writelane_b32 v43, s52, 10
-; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
-; CHECK-NEXT: v_writelane_b32 v43, s53, 11
; CHECK-NEXT: v_mov_b32_e32 v42, v1
-; CHECK-NEXT: v_writelane_b32 v43, s30, 12
; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v42
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
-; CHECK-NEXT: v_writelane_b32 v43, s31, 13
; CHECK-NEXT: v_mov_b32_e32 v40, v31
; CHECK-NEXT: v_mov_b32_e32 v41, v2
; CHECK-NEXT: s_mov_b32 s50, s15
@@ -258,30 +258,30 @@ define double @test_powr_fast_f64(double %x, double %y) {
; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
; CHECK-NEXT: v_writelane_b32 v43, s16, 14
+; CHECK-NEXT: s_addk_i32 s32, 0x800
+; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
; CHECK-NEXT: v_writelane_b32 v43, s34, 0
; CHECK-NEXT: v_writelane_b32 v43, s35, 1
; CHECK-NEXT: v_writelane_b32 v43, s36, 2
; CHECK-NEXT: v_writelane_b32 v43, s37, 3
; CHECK-NEXT: v_writelane_b32 v43, s38, 4
; CHECK-NEXT: v_writelane_b32 v43, s39, 5
-; CHECK-NEXT: s_addk_i32 s32, 0x800
; CHECK-NEXT: v_writelane_b32 v43, s48, 6
; CHECK-NEXT: v_writelane_b32 v43, s49, 7
-; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
-; CHECK-NEXT: s_getpc_b64 s[4:5]
-; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d at gotpcrel32@lo+4
-; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d at gotpcrel32@hi+12
; CHECK-NEXT: v_writelane_b32 v43, s50, 8
-; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; CHECK-NEXT: v_writelane_b32 v43, s51, 9
; CHECK-NEXT: v_writelane_b32 v43, s52, 10
; CHECK-NEXT: v_writelane_b32 v43, s53, 11
; CHECK-NEXT: v_writelane_b32 v43, s30, 12
-; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
-; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
; CHECK-NEXT: v_writelane_b32 v43, s31, 13
+; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
+; CHECK-NEXT: s_getpc_b64 s[4:5]
+; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d at gotpcrel32@lo+4
+; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d at gotpcrel32@hi+12
+; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
+; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
; CHECK-NEXT: v_mov_b32_e32 v42, v31
; CHECK-NEXT: v_mov_b32_e32 v41, v3
; CHECK-NEXT: v_mov_b32_e32 v40, v2
@@ -400,32 +400,32 @@ define double @test_pown_fast_f64(double %x, i32 %y) {
; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
; CHECK-NEXT: v_writelane_b32 v43, s16, 14
+; CHECK-NEXT: s_addk_i32 s32, 0x800
+; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
; CHECK-NEXT: v_writelane_b32 v43, s34, 0
; CHECK-NEXT: v_writelane_b32 v43, s35, 1
; CHECK-NEXT: v_writelane_b32 v43, s36, 2
; CHECK-NEXT: v_writelane_b32 v43, s37, 3
; CHECK-NEXT: v_writelane_b32 v43, s38, 4
; CHECK-NEXT: v_writelane_b32 v43, s39, 5
-; CHECK-NEXT: s_addk_i32 s32, 0x800
; CHECK-NEXT: v_writelane_b32 v43, s48, 6
; CHECK-NEXT: v_writelane_b32 v43, s49, 7
+; CHECK-NEXT: v_writelane_b32 v43, s50, 8
+; CHECK-NEXT: v_writelane_b32 v43, s51, 9
+; CHECK-NEXT: v_writelane_b32 v43, s52, 10
+; CHECK-NEXT: v_writelane_b32 v43, s53, 11
+; CHECK-NEXT: v_writelane_b32 v43, s30, 12
+; CHECK-NEXT: v_writelane_b32 v43, s31, 13
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d at gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d at gotpcrel32@hi+12
-; CHECK-NEXT: v_writelane_b32 v43, s50, 8
; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; CHECK-NEXT: v_writelane_b32 v43, s51, 9
-; CHECK-NEXT: v_writelane_b32 v43, s52, 10
-; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
-; CHECK-NEXT: v_writelane_b32 v43, s53, 11
; CHECK-NEXT: v_mov_b32_e32 v42, v1
-; CHECK-NEXT: v_writelane_b32 v43, s30, 12
; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v42
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
-; CHECK-NEXT: v_writelane_b32 v43, s31, 13
; CHECK-NEXT: v_mov_b32_e32 v40, v31
; CHECK-NEXT: v_mov_b32_e32 v41, v2
; CHECK-NEXT: s_mov_b32 s50, s15
@@ -542,30 +542,30 @@ define double @test_pown_fast_f64_known_even(double %x, i32 %y.arg) {
; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
; CHECK-NEXT: v_writelane_b32 v42, s16, 14
+; CHECK-NEXT: s_addk_i32 s32, 0x400
+; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
; CHECK-NEXT: v_writelane_b32 v42, s34, 0
; CHECK-NEXT: v_writelane_b32 v42, s35, 1
; CHECK-NEXT: v_writelane_b32 v42, s36, 2
; CHECK-NEXT: v_writelane_b32 v42, s37, 3
; CHECK-NEXT: v_writelane_b32 v42, s38, 4
; CHECK-NEXT: v_writelane_b32 v42, s39, 5
-; CHECK-NEXT: s_addk_i32 s32, 0x400
; CHECK-NEXT: v_writelane_b32 v42, s48, 6
; CHECK-NEXT: v_writelane_b32 v42, s49, 7
-; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
-; CHECK-NEXT: s_getpc_b64 s[4:5]
-; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d at gotpcrel32@lo+4
-; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d at gotpcrel32@hi+12
; CHECK-NEXT: v_writelane_b32 v42, s50, 8
-; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; CHECK-NEXT: v_writelane_b32 v42, s51, 9
; CHECK-NEXT: v_writelane_b32 v42, s52, 10
; CHECK-NEXT: v_writelane_b32 v42, s53, 11
; CHECK-NEXT: v_writelane_b32 v42, s30, 12
+; CHECK-NEXT: v_writelane_b32 v42, s31, 13
+; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
+; CHECK-NEXT: s_getpc_b64 s[4:5]
+; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d at gotpcrel32@lo+4
+; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d at gotpcrel32@hi+12
+; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
-; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; CHECK-NEXT: v_writelane_b32 v42, s31, 13
; CHECK-NEXT: v_mov_b32_e32 v40, v31
; CHECK-NEXT: s_mov_b32 s50, s15
; CHECK-NEXT: s_mov_b32 s51, s14
@@ -683,32 +683,32 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) {
; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
; CHECK-NEXT: v_writelane_b32 v43, s16, 14
+; CHECK-NEXT: s_addk_i32 s32, 0x800
+; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
; CHECK-NEXT: v_writelane_b32 v43, s34, 0
; CHECK-NEXT: v_writelane_b32 v43, s35, 1
; CHECK-NEXT: v_writelane_b32 v43, s36, 2
; CHECK-NEXT: v_writelane_b32 v43, s37, 3
; CHECK-NEXT: v_writelane_b32 v43, s38, 4
; CHECK-NEXT: v_writelane_b32 v43, s39, 5
-; CHECK-NEXT: s_addk_i32 s32, 0x800
; CHECK-NEXT: v_writelane_b32 v43, s48, 6
; CHECK-NEXT: v_writelane_b32 v43, s49, 7
+; CHECK-NEXT: v_writelane_b32 v43, s50, 8
+; CHECK-NEXT: v_writelane_b32 v43, s51, 9
+; CHECK-NEXT: v_writelane_b32 v43, s52, 10
+; CHECK-NEXT: v_writelane_b32 v43, s53, 11
+; CHECK-NEXT: v_writelane_b32 v43, s30, 12
+; CHECK-NEXT: v_writelane_b32 v43, s31, 13
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, _Z4log2d at gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d at gotpcrel32@hi+12
-; CHECK-NEXT: v_writelane_b32 v43, s50, 8
; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; CHECK-NEXT: v_writelane_b32 v43, s51, 9
-; CHECK-NEXT: v_writelane_b32 v43, s52, 10
-; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
-; CHECK-NEXT: v_writelane_b32 v43, s53, 11
; CHECK-NEXT: v_mov_b32_e32 v41, v1
-; CHECK-NEXT: v_writelane_b32 v43, s30, 12
; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v41
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
-; CHECK-NEXT: v_writelane_b32 v43, s31, 13
; CHECK-NEXT: v_mov_b32_e32 v40, v31
; CHECK-NEXT: s_mov_b32 s50, s15
; CHECK-NEXT: s_mov_b32 s51, s14
diff --git a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
index 3bed751c979c3..d4b07768e92a2 100644
--- a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
+++ b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
@@ -205,13 +205,13 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
; GFX8-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX8-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[16:17]
+; GFX8-NEXT: v_writelane_b32 v3, s30, 0
; GFX8-NEXT: s_addk_i32 s32, 0x400
+; GFX8-NEXT: v_writelane_b32 v3, s31, 1
; GFX8-NEXT: s_getpc_b64 s[16:17]
; GFX8-NEXT: s_add_u32 s16, s16, with_private_to_flat_addrspacecast at gotpcrel32@lo+4
; GFX8-NEXT: s_addc_u32 s17, s17, with_private_to_flat_addrspacecast at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX8-NEXT: v_writelane_b32 v3, s30, 0
-; GFX8-NEXT: v_writelane_b32 v3, s31, 1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX8-NEXT: v_readlane_b32 s30, v3, 0
@@ -233,13 +233,13 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
; GFX8-ARCH-FLAT-NEXT: s_add_i32 s3, s33, 8
; GFX8-ARCH-FLAT-NEXT: scratch_store_dword off, v3, s3 ; 4-byte Folded Spill
; GFX8-ARCH-FLAT-NEXT: s_mov_b64 exec, s[0:1]
+; GFX8-ARCH-FLAT-NEXT: v_writelane_b32 v3, s30, 0
; GFX8-ARCH-FLAT-NEXT: s_add_i32 s32, s32, 16
+; GFX8-ARCH-FLAT-NEXT: v_writelane_b32 v3, s31, 1
; GFX8-ARCH-FLAT-NEXT: s_getpc_b64 s[0:1]
; GFX8-ARCH-FLAT-NEXT: s_add_u32 s0, s0, with_private_to_flat_addrspacecast at gotpcrel32@lo+4
; GFX8-ARCH-FLAT-NEXT: s_addc_u32 s1, s1, with_private_to_flat_addrspacecast at gotpcrel32@hi+12
; GFX8-ARCH-FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
-; GFX8-ARCH-FLAT-NEXT: v_writelane_b32 v3, s30, 0
-; GFX8-ARCH-FLAT-NEXT: v_writelane_b32 v3, s31, 1
; GFX8-ARCH-FLAT-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-ARCH-FLAT-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX8-ARCH-FLAT-NEXT: v_readlane_b32 s30, v3, 0
@@ -261,13 +261,13 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
; GFX9-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[16:17]
+; GFX9-NEXT: v_writelane_b32 v3, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v3, s31, 1
; GFX9-NEXT: s_getpc_b64 s[16:17]
; GFX9-NEXT: s_add_u32 s16, s16, with_private_to_flat_addrspacecast at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s17, s17, with_private_to_flat_addrspacecast at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX9-NEXT: v_writelane_b32 v3, s30, 0
-; GFX9-NEXT: v_writelane_b32 v3, s31, 1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX9-NEXT: v_readlane_b32 s30, v3, 0
@@ -288,13 +288,13 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
; GFX9-ARCH-FLAT-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX9-ARCH-FLAT-NEXT: scratch_store_dword off, v3, s33 ; 4-byte Folded Spill
; GFX9-ARCH-FLAT-NEXT: s_mov_b64 exec, s[0:1]
+; GFX9-ARCH-FLAT-NEXT: v_writelane_b32 v3, s30, 0
; GFX9-ARCH-FLAT-NEXT: s_add_i32 s32, s32, 16
+; GFX9-ARCH-FLAT-NEXT: v_writelane_b32 v3, s31, 1
; GFX9-ARCH-FLAT-NEXT: s_getpc_b64 s[0:1]
; GFX9-ARCH-FLAT-NEXT: s_add_u32 s0, s0, with_private_to_flat_addrspacecast at gotpcrel32@lo+4
; GFX9-ARCH-FLAT-NEXT: s_addc_u32 s1, s1, with_private_to_flat_addrspacecast at gotpcrel32@hi+12
; GFX9-ARCH-FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
-; GFX9-ARCH-FLAT-NEXT: v_writelane_b32 v3, s30, 0
-; GFX9-ARCH-FLAT-NEXT: v_writelane_b32 v3, s31, 1
; GFX9-ARCH-FLAT-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-ARCH-FLAT-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX9-ARCH-FLAT-NEXT: v_readlane_b32 s30, v3, 0
@@ -315,14 +315,14 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
; GFX942-ARCH-FLAT-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX942-ARCH-FLAT-NEXT: scratch_store_dword off, v3, s33 ; 4-byte Folded Spill
; GFX942-ARCH-FLAT-NEXT: s_mov_b64 exec, s[0:1]
+; GFX942-ARCH-FLAT-NEXT: v_writelane_b32 v3, s30, 0
; GFX942-ARCH-FLAT-NEXT: s_add_i32 s32, s32, 16
+; GFX942-ARCH-FLAT-NEXT: s_nop 0
+; GFX942-ARCH-FLAT-NEXT: v_writelane_b32 v3, s31, 1
; GFX942-ARCH-FLAT-NEXT: s_getpc_b64 s[0:1]
; GFX942-ARCH-FLAT-NEXT: s_add_u32 s0, s0, with_private_to_flat_addrspacecast at gotpcrel32@lo+4
; GFX942-ARCH-FLAT-NEXT: s_addc_u32 s1, s1, with_private_to_flat_addrspacecast at gotpcrel32@hi+12
; GFX942-ARCH-FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
-; GFX942-ARCH-FLAT-NEXT: v_writelane_b32 v3, s30, 0
-; GFX942-ARCH-FLAT-NEXT: s_nop 1
-; GFX942-ARCH-FLAT-NEXT: v_writelane_b32 v3, s31, 1
; GFX942-ARCH-FLAT-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-ARCH-FLAT-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX942-ARCH-FLAT-NEXT: v_readlane_b32 s30, v3, 0
@@ -344,13 +344,13 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s16
+; GFX10-NEXT: v_writelane_b32 v3, s30, 0
; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v3, s31, 1
; GFX10-NEXT: s_getpc_b64 s[16:17]
; GFX10-NEXT: s_add_u32 s16, s16, with_private_to_flat_addrspacecast at gotpcrel32@lo+4
; GFX10-NEXT: s_addc_u32 s17, s17, with_private_to_flat_addrspacecast at gotpcrel32@hi+12
-; GFX10-NEXT: v_writelane_b32 v3, s30, 0
; GFX10-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX10-NEXT: v_writelane_b32 v3, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX10-NEXT: v_readlane_b32 s30, v3, 0
diff --git a/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir b/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
index 4f1a6cb2c48d8..ceb271bd57233 100644
--- a/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
+++ b/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
@@ -496,17 +496,29 @@ body: |
; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr40, 4352
; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5
; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 2816
; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5)
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 2560
; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5)
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 2304
; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5)
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 2048
; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5)
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 1792
; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5)
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 1536
; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5)
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1280
; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5)
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1024
; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5)
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 768
; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5)
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 512
; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5)
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 256
; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5)
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 0
; GCN-NEXT: renamable $vgpr44 = COPY $vgpr13, implicit $exec
; GCN-NEXT: renamable $vgpr43 = COPY $vgpr12, implicit $exec
; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit undef $scc
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index ec430bb443b21..05b24bbc4cc97 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -4410,13 +4410,13 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX7-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX7-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[16:17]
+; GFX7-NEXT: v_writelane_b32 v2, s30, 0
; GFX7-NEXT: s_addk_i32 s32, 0x400
+; GFX7-NEXT: v_writelane_b32 v2, s31, 1
; GFX7-NEXT: s_getpc_b64 s[16:17]
; GFX7-NEXT: s_add_u32 s16, s16, test_arg_store at gotpcrel32@lo+4
; GFX7-NEXT: s_addc_u32 s17, s17, test_arg_store at gotpcrel32@hi+12
; GFX7-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX7-NEXT: v_writelane_b32 v2, s30, 0
-; GFX7-NEXT: v_writelane_b32 v2, s31, 1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0
@@ -4441,13 +4441,13 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX8-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX8-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[16:17]
+; GFX8-NEXT: v_writelane_b32 v2, s30, 0
; GFX8-NEXT: s_addk_i32 s32, 0x400
+; GFX8-NEXT: v_writelane_b32 v2, s31, 1
; GFX8-NEXT: s_getpc_b64 s[16:17]
; GFX8-NEXT: s_add_u32 s16, s16, test_arg_store at gotpcrel32@lo+4
; GFX8-NEXT: s_addc_u32 s17, s17, test_arg_store at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX8-NEXT: v_writelane_b32 v2, s30, 0
-; GFX8-NEXT: v_writelane_b32 v2, s31, 1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX8-NEXT: v_readlane_b32 s30, v2, 0
@@ -4470,13 +4470,13 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX900-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX900-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[16:17]
+; GFX900-NEXT: v_writelane_b32 v2, s30, 0
; GFX900-NEXT: s_addk_i32 s32, 0x400
+; GFX900-NEXT: v_writelane_b32 v2, s31, 1
; GFX900-NEXT: s_getpc_b64 s[16:17]
; GFX900-NEXT: s_add_u32 s16, s16, test_arg_store at gotpcrel32@lo+4
; GFX900-NEXT: s_addc_u32 s17, s17, test_arg_store at gotpcrel32@hi+12
; GFX900-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX900-NEXT: v_writelane_b32 v2, s30, 0
-; GFX900-NEXT: v_writelane_b32 v2, s31, 1
; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX900-NEXT: v_readlane_b32 s30, v2, 0
@@ -4499,14 +4499,14 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX950-NEXT: scratch_store_dword off, v4, s33 ; 4-byte Folded Spill
; GFX950-NEXT: s_mov_b64 exec, s[0:1]
+; GFX950-NEXT: v_writelane_b32 v4, s30, 0
; GFX950-NEXT: s_add_i32 s32, s32, 16
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_writelane_b32 v4, s31, 1
; GFX950-NEXT: s_getpc_b64 s[0:1]
; GFX950-NEXT: s_add_u32 s0, s0, test_arg_store at gotpcrel32@lo+4
; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store at gotpcrel32@hi+12
; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
-; GFX950-NEXT: v_writelane_b32 v4, s30, 0
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_writelane_b32 v4, s31, 1
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX950-NEXT: v_readlane_b32 s30, v4, 0
@@ -4530,13 +4530,13 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s16
+; GFX10-NEXT: v_writelane_b32 v2, s30, 0
; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v2, s31, 1
; GFX10-NEXT: s_getpc_b64 s[16:17]
; GFX10-NEXT: s_add_u32 s16, s16, test_arg_store at gotpcrel32@lo+4
; GFX10-NEXT: s_addc_u32 s17, s17, test_arg_store at gotpcrel32@hi+12
-; GFX10-NEXT: v_writelane_b32 v2, s30, 0
; GFX10-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX10-NEXT: v_writelane_b32 v2, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX10-NEXT: v_readlane_b32 s30, v2, 0
@@ -4560,16 +4560,15 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_store_b32 off, v2, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
+; GFX11-NEXT: v_writelane_b32 v2, s30, 0
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v2, s31, 1
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, test_arg_store at gotpcrel32@lo+4
; GFX11-NEXT: s_addc_u32 s1, s1, test_arg_store at gotpcrel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v2, s30, 0
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-NEXT: v_writelane_b32 v2, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v2, 0
; GFX11-NEXT: scratch_store_b16 v1, v0, off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
@@ -4592,15 +4591,14 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) {
; GFX1250-NEXT: scratch_store_b32 off, v4, s33 ; 4-byte Folded Spill
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_mov_b32 exec_lo, s0
-; GFX1250-NEXT: s_get_pc_i64 s[0:1]
-; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store at gotpcrel+4
; GFX1250-NEXT: v_writelane_b32 v4, s30, 0
-; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX1250-NEXT: s_add_co_i32 s32, s32, 16
; GFX1250-NEXT: v_writelane_b32 v4, s31, 1
+; GFX1250-NEXT: s_get_pc_i64 s[0:1]
+; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store at gotpcrel+4
+; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_readlane_b32 s30, v4, 0
; GFX1250-NEXT: scratch_store_b16 v1, v0, off scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
@@ -4666,13 +4664,13 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX7-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX7-NEXT: buffer_store_dword v4, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[16:17]
+; GFX7-NEXT: v_writelane_b32 v4, s30, 0
; GFX7-NEXT: s_addk_i32 s32, 0x400
+; GFX7-NEXT: v_writelane_b32 v4, s31, 1
; GFX7-NEXT: s_getpc_b64 s[16:17]
; GFX7-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX7-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX7-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX7-NEXT: v_writelane_b32 v4, s30, 0
-; GFX7-NEXT: v_writelane_b32 v4, s31, 1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v1
@@ -4702,13 +4700,13 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX8-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX8-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[16:17]
+; GFX8-NEXT: v_writelane_b32 v2, s30, 0
; GFX8-NEXT: s_addk_i32 s32, 0x400
+; GFX8-NEXT: v_writelane_b32 v2, s31, 1
; GFX8-NEXT: s_getpc_b64 s[16:17]
; GFX8-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX8-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX8-NEXT: v_writelane_b32 v2, s30, 0
-; GFX8-NEXT: v_writelane_b32 v2, s31, 1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX8-NEXT: v_readlane_b32 s30, v2, 0
@@ -4731,13 +4729,13 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX900-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX900-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[16:17]
+; GFX900-NEXT: v_writelane_b32 v2, s30, 0
; GFX900-NEXT: s_addk_i32 s32, 0x400
+; GFX900-NEXT: v_writelane_b32 v2, s31, 1
; GFX900-NEXT: s_getpc_b64 s[16:17]
; GFX900-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX900-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX900-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX900-NEXT: v_writelane_b32 v2, s30, 0
-; GFX900-NEXT: v_writelane_b32 v2, s31, 1
; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX900-NEXT: v_readlane_b32 s30, v2, 0
@@ -4760,14 +4758,14 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX950-NEXT: scratch_store_dword off, v4, s33 ; 4-byte Folded Spill
; GFX950-NEXT: s_mov_b64 exec, s[0:1]
+; GFX950-NEXT: v_writelane_b32 v4, s30, 0
; GFX950-NEXT: s_add_i32 s32, s32, 16
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_writelane_b32 v4, s31, 1
; GFX950-NEXT: s_getpc_b64 s[0:1]
; GFX950-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
-; GFX950-NEXT: v_writelane_b32 v4, s30, 0
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_writelane_b32 v4, s31, 1
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX950-NEXT: v_readlane_b32 s30, v4, 0
@@ -4791,13 +4789,13 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s16
+; GFX10-NEXT: v_writelane_b32 v2, s30, 0
; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v2, s31, 1
; GFX10-NEXT: s_getpc_b64 s[16:17]
; GFX10-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX10-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
-; GFX10-NEXT: v_writelane_b32 v2, s30, 0
; GFX10-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX10-NEXT: v_writelane_b32 v2, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX10-NEXT: v_readlane_b32 s30, v2, 0
@@ -4821,16 +4819,15 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_store_b32 off, v2, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
+; GFX11-NEXT: v_writelane_b32 v2, s30, 0
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v2, s31, 1
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX11-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16 at gotpcrel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v2, s30, 0
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-NEXT: v_writelane_b32 v2, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v2, 0
; GFX11-NEXT: scratch_store_b32 v1, v0, off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
@@ -4853,15 +4850,14 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) {
; GFX1250-NEXT: scratch_store_b32 off, v4, s33 ; 4-byte Folded Spill
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_mov_b32 exec_lo, s0
-; GFX1250-NEXT: s_get_pc_i64 s[0:1]
-; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16 at gotpcrel+4
; GFX1250-NEXT: v_writelane_b32 v4, s30, 0
-; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX1250-NEXT: s_add_co_i32 s32, s32, 16
; GFX1250-NEXT: v_writelane_b32 v4, s31, 1
+; GFX1250-NEXT: s_get_pc_i64 s[0:1]
+; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16 at gotpcrel+4
+; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_readlane_b32 s30, v4, 0
; GFX1250-NEXT: scratch_store_b32 v1, v0, off scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
@@ -4929,13 +4925,13 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX7-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX7-NEXT: buffer_store_dword v4, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[16:17]
+; GFX7-NEXT: v_writelane_b32 v4, s30, 0
; GFX7-NEXT: s_addk_i32 s32, 0x400
+; GFX7-NEXT: v_writelane_b32 v4, s31, 1
; GFX7-NEXT: s_getpc_b64 s[16:17]
; GFX7-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX7-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX7-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX7-NEXT: v_writelane_b32 v4, s30, 0
-; GFX7-NEXT: v_writelane_b32 v4, s31, 1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v1
@@ -4967,13 +4963,13 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX8-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX8-NEXT: buffer_store_dword v4, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[16:17]
+; GFX8-NEXT: v_writelane_b32 v4, s30, 0
; GFX8-NEXT: s_addk_i32 s32, 0x400
+; GFX8-NEXT: v_writelane_b32 v4, s31, 1
; GFX8-NEXT: s_getpc_b64 s[16:17]
; GFX8-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX8-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX8-NEXT: v_writelane_b32 v4, s30, 0
-; GFX8-NEXT: v_writelane_b32 v4, s31, 1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 4, v2
@@ -4999,13 +4995,13 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX900-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX900-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[16:17]
+; GFX900-NEXT: v_writelane_b32 v3, s30, 0
; GFX900-NEXT: s_addk_i32 s32, 0x400
+; GFX900-NEXT: v_writelane_b32 v3, s31, 1
; GFX900-NEXT: s_getpc_b64 s[16:17]
; GFX900-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX900-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX900-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX900-NEXT: v_writelane_b32 v3, s30, 0
-; GFX900-NEXT: v_writelane_b32 v3, s31, 1
; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX900-NEXT: v_readlane_b32 s30, v3, 0
@@ -5030,15 +5026,15 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX950-NEXT: scratch_store_dword off, v5, s33 ; 4-byte Folded Spill
; GFX950-NEXT: s_mov_b64 exec, s[0:1]
+; GFX950-NEXT: v_writelane_b32 v5, s30, 0
; GFX950-NEXT: s_add_i32 s32, s32, 16
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_writelane_b32 v5, s31, 1
; GFX950-NEXT: s_getpc_b64 s[0:1]
; GFX950-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
-; GFX950-NEXT: v_writelane_b32 v5, s30, 0
; GFX950-NEXT: v_mov_b32_e32 v4, v2
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_writelane_b32 v5, s31, 1
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX950-NEXT: v_readlane_b32 s30, v5, 0
@@ -5064,13 +5060,13 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s16
+; GFX10-NEXT: v_writelane_b32 v3, s30, 0
; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v3, s31, 1
; GFX10-NEXT: s_getpc_b64 s[16:17]
; GFX10-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX10-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
-; GFX10-NEXT: v_writelane_b32 v3, s30, 0
; GFX10-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX10-NEXT: v_writelane_b32 v3, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX10-NEXT: v_readlane_b32 s30, v3, 0
@@ -5096,16 +5092,15 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_store_b32 off, v3, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
+; GFX11-NEXT: v_writelane_b32 v3, s30, 0
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v3, s31, 1
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX11-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16 at gotpcrel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v3, s30, 0
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-NEXT: v_writelane_b32 v3, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v3, 0
; GFX11-NEXT: scratch_store_b16 v2, v1, off offset:4 dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
@@ -5130,16 +5125,15 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) {
; GFX1250-NEXT: scratch_store_b32 off, v5, s33 ; 4-byte Folded Spill
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_mov_b32 exec_lo, s0
-; GFX1250-NEXT: s_get_pc_i64 s[0:1]
-; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16 at gotpcrel+4
; GFX1250-NEXT: v_writelane_b32 v5, s30, 0
-; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX1250-NEXT: s_add_co_i32 s32, s32, 16
-; GFX1250-NEXT: v_mov_b32_e32 v4, v2
; GFX1250-NEXT: v_writelane_b32 v5, s31, 1
+; GFX1250-NEXT: s_get_pc_i64 s[0:1]
+; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16 at gotpcrel+4
+; GFX1250-NEXT: v_mov_b32_e32 v4, v2
+; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_readlane_b32 s30, v5, 0
; GFX1250-NEXT: scratch_store_b16 v4, v1, off offset:4 scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
@@ -5217,13 +5211,13 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX7-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX7-NEXT: buffer_store_dword v6, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[16:17]
+; GFX7-NEXT: v_writelane_b32 v6, s30, 0
; GFX7-NEXT: s_addk_i32 s32, 0x400
+; GFX7-NEXT: v_writelane_b32 v6, s31, 1
; GFX7-NEXT: s_getpc_b64 s[16:17]
; GFX7-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX7-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX7-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX7-NEXT: v_writelane_b32 v6, s30, 0
-; GFX7-NEXT: v_writelane_b32 v6, s31, 1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v3
@@ -5263,13 +5257,13 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX8-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX8-NEXT: buffer_store_dword v4, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[16:17]
+; GFX8-NEXT: v_writelane_b32 v4, s30, 0
; GFX8-NEXT: s_addk_i32 s32, 0x400
+; GFX8-NEXT: v_writelane_b32 v4, s31, 1
; GFX8-NEXT: s_getpc_b64 s[16:17]
; GFX8-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX8-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX8-NEXT: v_writelane_b32 v4, s30, 0
-; GFX8-NEXT: v_writelane_b32 v4, s31, 1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 4, v2
@@ -5295,13 +5289,13 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX900-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX900-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[16:17]
+; GFX900-NEXT: v_writelane_b32 v3, s30, 0
; GFX900-NEXT: s_addk_i32 s32, 0x400
+; GFX900-NEXT: v_writelane_b32 v3, s31, 1
; GFX900-NEXT: s_getpc_b64 s[16:17]
; GFX900-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX900-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX900-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX900-NEXT: v_writelane_b32 v3, s30, 0
-; GFX900-NEXT: v_writelane_b32 v3, s31, 1
; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX900-NEXT: v_readlane_b32 s30, v3, 0
@@ -5326,15 +5320,15 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX950-NEXT: scratch_store_dword off, v5, s33 ; 4-byte Folded Spill
; GFX950-NEXT: s_mov_b64 exec, s[0:1]
+; GFX950-NEXT: v_writelane_b32 v5, s30, 0
; GFX950-NEXT: s_add_i32 s32, s32, 16
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_writelane_b32 v5, s31, 1
; GFX950-NEXT: s_getpc_b64 s[0:1]
; GFX950-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
-; GFX950-NEXT: v_writelane_b32 v5, s30, 0
; GFX950-NEXT: v_mov_b32_e32 v4, v2
-; GFX950-NEXT: s_nop 0
-; GFX950-NEXT: v_writelane_b32 v5, s31, 1
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX950-NEXT: v_readlane_b32 s30, v5, 0
@@ -5358,13 +5352,13 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s16
+; GFX10-NEXT: v_writelane_b32 v3, s30, 0
; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v3, s31, 1
; GFX10-NEXT: s_getpc_b64 s[16:17]
; GFX10-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX10-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
-; GFX10-NEXT: v_writelane_b32 v3, s30, 0
; GFX10-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX10-NEXT: v_writelane_b32 v3, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX10-NEXT: v_readlane_b32 s30, v3, 0
@@ -5390,16 +5384,15 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_store_b32 off, v3, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
+; GFX11-NEXT: v_writelane_b32 v3, s30, 0
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v3, s31, 1
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX11-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16 at gotpcrel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v3, s30, 0
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-NEXT: v_writelane_b32 v3, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v3, 0
; GFX11-NEXT: scratch_store_b64 v2, v[0:1], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
@@ -5422,16 +5415,15 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX1250-NEXT: scratch_store_b32 off, v5, s33 ; 4-byte Folded Spill
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_mov_b32 exec_lo, s0
-; GFX1250-NEXT: s_get_pc_i64 s[0:1]
-; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16 at gotpcrel+4
; GFX1250-NEXT: v_writelane_b32 v5, s30, 0
-; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX1250-NEXT: s_add_co_i32 s32, s32, 16
-; GFX1250-NEXT: v_mov_b32_e32 v4, v2
; GFX1250-NEXT: v_writelane_b32 v5, s31, 1
+; GFX1250-NEXT: s_get_pc_i64 s[0:1]
+; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16 at gotpcrel+4
+; GFX1250-NEXT: v_mov_b32_e32 v4, v2
+; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_readlane_b32 s30, v5, 0
; GFX1250-NEXT: scratch_store_b64 v4, v[0:1], off scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
@@ -5527,13 +5519,13 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX7-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX7-NEXT: buffer_store_dword v10, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[16:17]
+; GFX7-NEXT: v_writelane_b32 v10, s30, 0
; GFX7-NEXT: s_addk_i32 s32, 0x400
+; GFX7-NEXT: v_writelane_b32 v10, s31, 1
; GFX7-NEXT: s_getpc_b64 s[16:17]
; GFX7-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX7-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX7-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX7-NEXT: v_writelane_b32 v10, s30, 0
-; GFX7-NEXT: v_writelane_b32 v10, s31, 1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX7-NEXT: v_mul_f32_e32 v7, 1.0, v7
@@ -5593,13 +5585,13 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX8-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX8-NEXT: buffer_store_dword v6, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[16:17]
+; GFX8-NEXT: v_writelane_b32 v6, s30, 0
; GFX8-NEXT: s_addk_i32 s32, 0x400
+; GFX8-NEXT: v_writelane_b32 v6, s31, 1
; GFX8-NEXT: s_getpc_b64 s[16:17]
; GFX8-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX8-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX8-NEXT: v_writelane_b32 v6, s30, 0
-; GFX8-NEXT: v_writelane_b32 v6, s31, 1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX8-NEXT: v_add_u32_e32 v5, vcc, 12, v4
@@ -5631,13 +5623,13 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX900-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX900-NEXT: buffer_store_dword v5, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[16:17]
+; GFX900-NEXT: v_writelane_b32 v5, s30, 0
; GFX900-NEXT: s_addk_i32 s32, 0x400
+; GFX900-NEXT: v_writelane_b32 v5, s31, 1
; GFX900-NEXT: s_getpc_b64 s[16:17]
; GFX900-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX900-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX900-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX900-NEXT: v_writelane_b32 v5, s30, 0
-; GFX900-NEXT: v_writelane_b32 v5, s31, 1
; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX900-NEXT: v_readlane_b32 s30, v5, 0
@@ -5666,14 +5658,14 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX950-NEXT: scratch_store_dword off, v5, s33 ; 4-byte Folded Spill
; GFX950-NEXT: s_mov_b64 exec, s[0:1]
+; GFX950-NEXT: v_writelane_b32 v5, s30, 0
; GFX950-NEXT: s_add_i32 s32, s32, 16
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_writelane_b32 v5, s31, 1
; GFX950-NEXT: s_getpc_b64 s[0:1]
; GFX950-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
-; GFX950-NEXT: v_writelane_b32 v5, s30, 0
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_writelane_b32 v5, s31, 1
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX950-NEXT: v_readlane_b32 s30, v5, 0
@@ -5697,13 +5689,13 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: buffer_store_dword v5, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s16
+; GFX10-NEXT: v_writelane_b32 v5, s30, 0
; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v5, s31, 1
; GFX10-NEXT: s_getpc_b64 s[16:17]
; GFX10-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX10-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
-; GFX10-NEXT: v_writelane_b32 v5, s30, 0
; GFX10-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX10-NEXT: v_writelane_b32 v5, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX10-NEXT: v_readlane_b32 s30, v5, 0
@@ -5733,16 +5725,15 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_store_b32 off, v5, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
+; GFX11-NEXT: v_writelane_b32 v5, s30, 0
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v5, s31, 1
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX11-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16 at gotpcrel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v5, s30, 0
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-NEXT: v_writelane_b32 v5, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v5, 0
; GFX11-NEXT: scratch_store_b128 v4, v[0:3], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
@@ -5765,15 +5756,14 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX1250-NEXT: scratch_store_b32 off, v5, s33 ; 4-byte Folded Spill
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_mov_b32 exec_lo, s0
-; GFX1250-NEXT: s_get_pc_i64 s[0:1]
-; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16 at gotpcrel+4
; GFX1250-NEXT: v_writelane_b32 v5, s30, 0
-; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX1250-NEXT: s_add_co_i32 s32, s32, 16
; GFX1250-NEXT: v_writelane_b32 v5, s31, 1
+; GFX1250-NEXT: s_get_pc_i64 s[0:1]
+; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16 at gotpcrel+4
+; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_readlane_b32 s30, v5, 0
; GFX1250-NEXT: scratch_store_b128 v4, v[0:3], off scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
@@ -5909,13 +5899,13 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX7-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX7-NEXT: buffer_store_dword v18, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[16:17]
+; GFX7-NEXT: v_writelane_b32 v18, s30, 0
; GFX7-NEXT: s_addk_i32 s32, 0x400
+; GFX7-NEXT: v_writelane_b32 v18, s31, 1
; GFX7-NEXT: s_getpc_b64 s[16:17]
; GFX7-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX7-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX7-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX7-NEXT: v_writelane_b32 v18, s30, 0
-; GFX7-NEXT: v_writelane_b32 v18, s31, 1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX7-NEXT: v_mul_f32_e32 v15, 1.0, v15
@@ -6015,13 +6005,13 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX8-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX8-NEXT: buffer_store_dword v10, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[16:17]
+; GFX8-NEXT: v_writelane_b32 v10, s30, 0
; GFX8-NEXT: s_addk_i32 s32, 0x400
+; GFX8-NEXT: v_writelane_b32 v10, s31, 1
; GFX8-NEXT: s_getpc_b64 s[16:17]
; GFX8-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX8-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX8-NEXT: v_writelane_b32 v10, s30, 0
-; GFX8-NEXT: v_writelane_b32 v10, s31, 1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX8-NEXT: v_add_u32_e32 v9, vcc, 28, v8
@@ -6065,13 +6055,13 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX900-NEXT: s_xor_saveexec_b64 s[16:17], -1
; GFX900-NEXT: buffer_store_dword v9, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[16:17]
+; GFX900-NEXT: v_writelane_b32 v9, s30, 0
; GFX900-NEXT: s_addk_i32 s32, 0x400
+; GFX900-NEXT: v_writelane_b32 v9, s31, 1
; GFX900-NEXT: s_getpc_b64 s[16:17]
; GFX900-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX900-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX900-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX900-NEXT: v_writelane_b32 v9, s30, 0
-; GFX900-NEXT: v_writelane_b32 v9, s31, 1
; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX900-NEXT: v_readlane_b32 s30, v9, 0
@@ -6108,14 +6098,14 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX950-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX950-NEXT: scratch_store_dword off, v9, s33 ; 4-byte Folded Spill
; GFX950-NEXT: s_mov_b64 exec, s[0:1]
+; GFX950-NEXT: v_writelane_b32 v9, s30, 0
; GFX950-NEXT: s_add_i32 s32, s32, 16
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_writelane_b32 v9, s31, 1
; GFX950-NEXT: s_getpc_b64 s[0:1]
; GFX950-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX950-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16 at gotpcrel32@hi+12
; GFX950-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
-; GFX950-NEXT: v_writelane_b32 v9, s30, 0
-; GFX950-NEXT: s_nop 1
-; GFX950-NEXT: v_writelane_b32 v9, s31, 1
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX950-NEXT: v_readlane_b32 s30, v9, 0
@@ -6141,13 +6131,13 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX10-NEXT: buffer_store_dword v9, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s16
+; GFX10-NEXT: v_writelane_b32 v9, s30, 0
; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v9, s31, 1
; GFX10-NEXT: s_getpc_b64 s[16:17]
; GFX10-NEXT: s_add_u32 s16, s16, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX10-NEXT: s_addc_u32 s17, s17, test_arg_store_v2bf16 at gotpcrel32@hi+12
-; GFX10-NEXT: v_writelane_b32 v9, s30, 0
; GFX10-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX10-NEXT: v_writelane_b32 v9, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX10-NEXT: v_readlane_b32 s30, v9, 0
@@ -6185,16 +6175,15 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_store_b32 off, v9, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
+; GFX11-NEXT: v_writelane_b32 v9, s30, 0
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v9, s31, 1
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, test_arg_store_v2bf16 at gotpcrel32@lo+4
; GFX11-NEXT: s_addc_u32 s1, s1, test_arg_store_v2bf16 at gotpcrel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v9, s30, 0
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-NEXT: v_writelane_b32 v9, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v9, 0
; GFX11-NEXT: scratch_store_b128 v8, v[4:7], off offset:16 dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
@@ -6219,15 +6208,14 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX1250-NEXT: scratch_store_b32 off, v9, s33 ; 4-byte Folded Spill
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_mov_b32 exec_lo, s0
-; GFX1250-NEXT: s_get_pc_i64 s[0:1]
-; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16 at gotpcrel+4
; GFX1250-NEXT: v_writelane_b32 v9, s30, 0
-; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX1250-NEXT: s_add_co_i32 s32, s32, 16
; GFX1250-NEXT: v_writelane_b32 v9, s31, 1
+; GFX1250-NEXT: s_get_pc_i64 s[0:1]
+; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], test_arg_store_v2bf16 at gotpcrel+4
+; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_readlane_b32 s30, v9, 0
; GFX1250-NEXT: scratch_store_b128 v8, v[4:7], off offset:16 scope:SCOPE_SYS
; GFX1250-NEXT: s_wait_storecnt 0x0
@@ -9536,6 +9524,17 @@ define <32 x double> @global_extload_v32bf16_to_v32f64(ptr addrspace(1) %ptr) {
; GFX8-LABEL: global_extload_v32bf16_to_v32f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v58, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 2, v1
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, 4, v1
@@ -9570,17 +9569,6 @@ define <32 x double> @global_extload_v32bf16_to_v32f64(ptr addrspace(1) %ptr) {
; GFX8-NEXT: v_addc_u32_e32 v34, vcc, 0, v2, vcc
; GFX8-NEXT: v_add_u32_e32 v35, vcc, 36, v1
; GFX8-NEXT: v_addc_u32_e32 v36, vcc, 0, v2, vcc
-; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v58, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX8-NEXT: v_add_u32_e32 v37, vcc, 38, v1
; GFX8-NEXT: flat_load_ushort v44, v[1:2]
; GFX8-NEXT: v_addc_u32_e32 v38, vcc, 0, v2, vcc
@@ -10039,16 +10027,21 @@ define <32 x double> @global_extload_v32bf16_to_v32f64(ptr addrspace(1) %ptr) {
; GFX950-LABEL: global_extload_v32bf16_to_v32f64:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_mov_b32_e32 v3, v2
-; GFX950-NEXT: v_mov_b32_e32 v2, v1
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a3, v43 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a4, v44 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a5, v45 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a6, v46 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse
+; GFX950-NEXT: v_mov_b32_e32 v3, v2
+; GFX950-NEXT: v_mov_b32_e32 v2, v1
; GFX950-NEXT: global_load_ushort v1, v[2:3], off offset:2
; GFX950-NEXT: global_load_ushort v4, v[2:3], off offset:12
; GFX950-NEXT: global_load_ushort v5, v[2:3], off offset:8
@@ -10081,11 +10074,6 @@ define <32 x double> @global_extload_v32bf16_to_v32f64(ptr addrspace(1) %ptr) {
; GFX950-NEXT: global_load_ushort v56, v[2:3], off offset:48
; GFX950-NEXT: global_load_ushort v57, v[2:3], off offset:54
; GFX950-NEXT: global_load_ushort v58, v[2:3], off offset:58
-; GFX950-NEXT: v_accvgpr_write_b32 a4, v44 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a5, v45 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse
; GFX950-NEXT: s_waitcnt vmcnt(31)
; GFX950-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX950-NEXT: s_waitcnt vmcnt(30)
@@ -14269,12 +14257,12 @@ define <32 x bfloat> @v_fadd_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) {
; GFX950-LABEL: v_fadd_v32bf16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
; GFX950-NEXT: scratch_load_dword v31, off, s32
; GFX950-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
; GFX950-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
; GFX950-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v7
@@ -19977,12 +19965,12 @@ define <32 x bfloat> @v_fmul_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) {
; GFX950-LABEL: v_fmul_v32bf16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
; GFX950-NEXT: scratch_load_dword v31, off, s32
; GFX950-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
; GFX950-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
; GFX950-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v7
@@ -25168,12 +25156,12 @@ define <32 x bfloat> @v_minnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) {
; GFX950-LABEL: v_minnum_v32bf16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
; GFX950-NEXT: scratch_load_dword v31, off, s32
; GFX950-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
; GFX950-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
; GFX950-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v7
@@ -29744,12 +29732,12 @@ define <32 x bfloat> @v_maxnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) {
; GFX950-LABEL: v_maxnum_v32bf16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
; GFX950-NEXT: scratch_load_dword v31, off, s32
; GFX950-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
; GFX950-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
; GFX950-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v7
@@ -48827,6 +48815,14 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
+; GFX8-NEXT: v_writelane_b32 v34, s34, 0
+; GFX8-NEXT: v_writelane_b32 v34, s35, 1
+; GFX8-NEXT: v_writelane_b32 v34, s36, 2
+; GFX8-NEXT: v_writelane_b32 v34, s37, 3
+; GFX8-NEXT: v_writelane_b32 v34, s38, 4
+; GFX8-NEXT: v_writelane_b32 v34, s39, 5
+; GFX8-NEXT: v_writelane_b32 v34, s30, 6
+; GFX8-NEXT: v_writelane_b32 v34, s31, 7
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v1
@@ -48870,28 +48866,20 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX8-NEXT: v_and_b32_e32 v0, 1, v20
; GFX8-NEXT: v_cmp_eq_u32_e64 s[60:61], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v21
-; GFX8-NEXT: v_writelane_b32 v34, s34, 0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[62:63], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v22
-; GFX8-NEXT: v_writelane_b32 v34, s35, 1
; GFX8-NEXT: v_cmp_eq_u32_e64 s[72:73], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v23
-; GFX8-NEXT: v_writelane_b32 v34, s36, 2
; GFX8-NEXT: v_cmp_eq_u32_e64 s[74:75], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v24
-; GFX8-NEXT: v_writelane_b32 v34, s37, 3
; GFX8-NEXT: v_cmp_eq_u32_e64 s[76:77], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v25
-; GFX8-NEXT: v_writelane_b32 v34, s38, 4
; GFX8-NEXT: v_cmp_eq_u32_e64 s[78:79], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v26
-; GFX8-NEXT: v_writelane_b32 v34, s39, 5
; GFX8-NEXT: v_cmp_eq_u32_e64 s[88:89], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v27
-; GFX8-NEXT: v_writelane_b32 v34, s30, 6
; GFX8-NEXT: v_cmp_eq_u32_e64 s[90:91], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v28
-; GFX8-NEXT: v_writelane_b32 v34, s31, 7
; GFX8-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v29
; GFX8-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v0
@@ -49051,6 +49039,10 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX900-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX900-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
+; GFX900-NEXT: v_writelane_b32 v33, s34, 0
+; GFX900-NEXT: v_writelane_b32 v33, s35, 1
+; GFX900-NEXT: v_writelane_b32 v33, s30, 2
+; GFX900-NEXT: v_writelane_b32 v33, s31, 3
; GFX900-NEXT: v_and_b32_e32 v0, 1, v0
; GFX900-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0
; GFX900-NEXT: v_and_b32_e32 v0, 1, v3
@@ -49110,10 +49102,6 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX900-NEXT: v_and_b32_e32 v0, 1, v28
; GFX900-NEXT: v_cmp_eq_u32_e64 s[94:95], 1, v0
; GFX900-NEXT: buffer_load_ushort v0, off, s[0:3], s32
-; GFX900-NEXT: v_writelane_b32 v33, s34, 0
-; GFX900-NEXT: v_writelane_b32 v33, s35, 1
-; GFX900-NEXT: v_writelane_b32 v33, s30, 2
-; GFX900-NEXT: v_writelane_b32 v33, s31, 3
; GFX900-NEXT: v_and_b32_e32 v1, 1, v1
; GFX900-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
; GFX900-NEXT: s_waitcnt vmcnt(0)
@@ -49254,6 +49242,12 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX950-NEXT: v_accvgpr_write_b32 a3, v43 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a4, v44 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a5, v45 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a6, v46 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse
; GFX950-NEXT: scratch_load_dword v31, off, s32 offset:60
; GFX950-NEXT: scratch_load_dword v32, off, s32 offset:124
; GFX950-NEXT: scratch_load_ushort v33, off, s32
@@ -49278,17 +49272,11 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX950-NEXT: scratch_load_dword v44, off, s32 offset:104
; GFX950-NEXT: scratch_load_dword v45, off, s32 offset:40
; GFX950-NEXT: v_and_b32_e32 v29, 1, v29
-; GFX950-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse
; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, 1, v29
; GFX950-NEXT: scratch_load_dword v29, off, s32 offset:84
; GFX950-NEXT: scratch_load_dword v56, off, s32 offset:20
; GFX950-NEXT: v_and_b32_e32 v28, 1, v28
-; GFX950-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse
; GFX950-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v28
-; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a6, v46 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse
; GFX950-NEXT: v_and_b32_e32 v26, 1, v26
; GFX950-NEXT: v_and_b32_e32 v27, 1, v27
; GFX950-NEXT: v_and_b32_e32 v24, 1, v24
@@ -54707,6 +54695,22 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX950-LABEL: v_fma_v32bf16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a3, v43 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a4, v44 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a5, v45 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a6, v46 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a13, v61 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a14, v62 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse
; GFX950-NEXT: scratch_load_dword v35, off, s32 offset:64
; GFX950-NEXT: scratch_load_dword v36, off, s32
; GFX950-NEXT: scratch_load_dword v38, off, s32 offset:60
@@ -54724,14 +54728,6 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX950-NEXT: scratch_load_dword v34, off, s32 offset:16
; GFX950-NEXT: scratch_load_dword v37, off, s32 offset:20
; GFX950-NEXT: scratch_load_dword v55, off, s32 offset:24
-; GFX950-NEXT: v_accvgpr_write_b32 a3, v43 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a5, v45 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a6, v46 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a13, v61 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a14, v62 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse
; GFX950-NEXT: v_and_b32_e32 v43, 0xffff0000, v14
; GFX950-NEXT: v_lshlrev_b32_e32 v45, 16, v14
; GFX950-NEXT: v_and_b32_e32 v46, 0xffff0000, v29
@@ -54740,20 +54736,12 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX950-NEXT: v_lshlrev_b32_e32 v61, 16, v12
; GFX950-NEXT: v_and_b32_e32 v62, 0xffff0000, v27
; GFX950-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a4, v44 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse
; GFX950-NEXT: v_and_b32_e32 v42, 0xffff0000, v30
; GFX950-NEXT: v_lshlrev_b32_e32 v44, 16, v30
; GFX950-NEXT: v_and_b32_e32 v47, 0xffff0000, v13
; GFX950-NEXT: v_lshlrev_b32_e32 v57, 16, v13
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse
; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v15
; GFX950-NEXT: v_lshlrev_b32_e32 v41, 16, v15
-; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse
; GFX950-NEXT: v_and_b32_e32 v58, 0xffff0000, v28
; GFX950-NEXT: v_lshlrev_b32_e32 v60, 16, v28
; GFX950-NEXT: s_waitcnt vmcnt(16)
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll b/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
index fb11d3b7d9d65..2f6f9e45cafbf 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
+++ b/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
@@ -939,10 +939,10 @@ define void @spill_func(ptr addrspace(1) %arg) #0 {
; CHECK-NEXT: v_writelane_b32 v0, s99, 34
; CHECK-NEXT: v_writelane_b32 v0, s100, 35
; CHECK-NEXT: v_writelane_b32 v0, s101, 36
-; CHECK-NEXT: s_mov_b32 s40, s12
; CHECK-NEXT: v_writelane_b32 v0, s30, 37
-; CHECK-NEXT: s_cmp_eq_u32 s40, 0
; CHECK-NEXT: v_writelane_b32 v0, s31, 38
+; CHECK-NEXT: s_mov_b32 s40, s12
+; CHECK-NEXT: s_cmp_eq_u32 s40, 0
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: s_mov_b32 s0, 0
; CHECK-NEXT: ;;#ASMEND
diff --git a/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll b/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
index 7f9b09350886a..38bb274664664 100644
--- a/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
@@ -41,13 +41,13 @@ define void @test_call_external_void_func_i8_inreg(i8 inreg %arg) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-NEXT: v_writelane_b32 v40, s17, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_i8_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_i8_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -70,13 +70,13 @@ define void @test_call_external_void_func_i8_inreg(i8 inreg %arg) #0 {
; GFX11-NEXT: s_mov_b32 exec_lo, s2
; GFX11-NEXT: v_writelane_b32 v40, s1, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_i8_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_i8_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -101,13 +101,13 @@ define void @test_call_external_void_func_i16_inreg(i16 inreg %arg) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-NEXT: v_writelane_b32 v40, s17, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_i16_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_i16_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -130,13 +130,13 @@ define void @test_call_external_void_func_i16_inreg(i16 inreg %arg) #0 {
; GFX11-NEXT: s_mov_b32 exec_lo, s2
; GFX11-NEXT: v_writelane_b32 v40, s1, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_i16_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_i16_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -161,13 +161,13 @@ define void @test_call_external_void_func_i32_inreg(i32 inreg %arg) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-NEXT: v_writelane_b32 v40, s17, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_i32_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_i32_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -190,13 +190,13 @@ define void @test_call_external_void_func_i32_inreg(i32 inreg %arg) #0 {
; GFX11-NEXT: s_mov_b32 exec_lo, s2
; GFX11-NEXT: v_writelane_b32 v40, s1, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_i32_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_i32_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -221,14 +221,14 @@ define void @test_call_external_void_func_i64_inreg(i64 inreg %arg) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[20:21]
; GFX9-NEXT: v_writelane_b32 v40, s18, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_i64_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_i64_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s1, s17
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -251,13 +251,13 @@ define void @test_call_external_void_func_i64_inreg(i64 inreg %arg) #0 {
; GFX11-NEXT: s_mov_b32 exec_lo, s3
; GFX11-NEXT: v_writelane_b32 v40, s2, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_i64_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_i64_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -282,14 +282,14 @@ define void @test_call_external_void_func_v2i32_inreg(<2 x i32> inreg %arg) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[20:21]
; GFX9-NEXT: v_writelane_b32 v40, s18, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_v2i32_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_v2i32_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s1, s17
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -312,13 +312,13 @@ define void @test_call_external_void_func_v2i32_inreg(<2 x i32> inreg %arg) #0 {
; GFX11-NEXT: s_mov_b32 exec_lo, s3
; GFX11-NEXT: v_writelane_b32 v40, s2, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v2i32_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v2i32_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -343,15 +343,15 @@ define void @test_call_external_void_func_v3i32_inreg(<3 x i32> inreg %arg) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[20:21]
; GFX9-NEXT: v_writelane_b32 v40, s19, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[20:21]
; GFX9-NEXT: s_add_u32 s20, s20, external_void_func_v3i32_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s21, s21, external_void_func_v3i32_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s2, s18
; GFX9-NEXT: s_mov_b32 s1, s17
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[20:21]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -374,13 +374,13 @@ define void @test_call_external_void_func_v3i32_inreg(<3 x i32> inreg %arg) #0 {
; GFX11-NEXT: s_mov_b32 exec_lo, s16
; GFX11-NEXT: v_writelane_b32 v40, s3, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[16:17]
; GFX11-NEXT: s_add_u32 s16, s16, external_void_func_v3i32_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s17, s17, external_void_func_v3i32_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -405,8 +405,9 @@ define void @test_call_external_void_func_v4i32_inreg(<4 x i32> inreg %arg) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[22:23]
; GFX9-NEXT: v_writelane_b32 v40, s20, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[20:21]
; GFX9-NEXT: s_add_u32 s20, s20, external_void_func_v4i32_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s21, s21, external_void_func_v4i32_inreg at rel32@hi+12
@@ -414,7 +415,6 @@ define void @test_call_external_void_func_v4i32_inreg(<4 x i32> inreg %arg) #0 {
; GFX9-NEXT: s_mov_b32 s2, s18
; GFX9-NEXT: s_mov_b32 s1, s17
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[20:21]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -437,13 +437,13 @@ define void @test_call_external_void_func_v4i32_inreg(<4 x i32> inreg %arg) #0 {
; GFX11-NEXT: s_mov_b32 exec_lo, s17
; GFX11-NEXT: v_writelane_b32 v40, s16, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[16:17]
; GFX11-NEXT: s_add_u32 s16, s16, external_void_func_v4i32_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s17, s17, external_void_func_v4i32_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -468,8 +468,9 @@ define void @test_call_external_void_func_v8i32_inreg(<8 x i32> inreg %arg) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[26:27]
; GFX9-NEXT: v_writelane_b32 v40, s24, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[24:25]
; GFX9-NEXT: s_add_u32 s24, s24, external_void_func_v8i32_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s25, s25, external_void_func_v8i32_inreg at rel32@hi+12
@@ -481,7 +482,6 @@ define void @test_call_external_void_func_v8i32_inreg(<8 x i32> inreg %arg) #0 {
; GFX9-NEXT: s_mov_b32 s17, s21
; GFX9-NEXT: s_mov_b32 s18, s22
; GFX9-NEXT: s_mov_b32 s19, s23
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[24:25]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -504,13 +504,13 @@ define void @test_call_external_void_func_v8i32_inreg(<8 x i32> inreg %arg) #0 {
; GFX11-NEXT: s_mov_b32 exec_lo, s21
; GFX11-NEXT: v_writelane_b32 v40, s20, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[20:21]
; GFX11-NEXT: s_add_u32 s20, s20, external_void_func_v8i32_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s21, s21, external_void_func_v8i32_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[20:21]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -535,13 +535,13 @@ define void @test_call_external_void_func_f16_inreg(half inreg %arg) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-NEXT: v_writelane_b32 v40, s17, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_f16_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_f16_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -564,13 +564,13 @@ define void @test_call_external_void_func_f16_inreg(half inreg %arg) #0 {
; GFX11-NEXT: s_mov_b32 exec_lo, s2
; GFX11-NEXT: v_writelane_b32 v40, s1, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_f16_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_f16_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -595,13 +595,13 @@ define void @test_call_external_void_func_bf16_inreg(bfloat inreg %arg) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-NEXT: v_writelane_b32 v40, s17, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_bf16_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_bf16_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -624,13 +624,13 @@ define void @test_call_external_void_func_bf16_inreg(bfloat inreg %arg) #0 {
; GFX11-NEXT: s_mov_b32 exec_lo, s2
; GFX11-NEXT: v_writelane_b32 v40, s1, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_bf16_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_bf16_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -655,13 +655,13 @@ define void @test_call_external_void_func_f32_inreg(float inreg %arg) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-NEXT: v_writelane_b32 v40, s17, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_f32_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_f32_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -684,13 +684,13 @@ define void @test_call_external_void_func_f32_inreg(float inreg %arg) #0 {
; GFX11-NEXT: s_mov_b32 exec_lo, s2
; GFX11-NEXT: v_writelane_b32 v40, s1, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_f32_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_f32_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -715,14 +715,14 @@ define void @test_call_external_void_func_f64_inreg(double inreg %arg) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[20:21]
; GFX9-NEXT: v_writelane_b32 v40, s18, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_f64_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_f64_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s1, s17
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -745,13 +745,13 @@ define void @test_call_external_void_func_f64_inreg(double inreg %arg) #0 {
; GFX11-NEXT: s_mov_b32 exec_lo, s3
; GFX11-NEXT: v_writelane_b32 v40, s2, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_f64_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_f64_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -776,13 +776,13 @@ define void @test_call_external_void_func_v2f16_inreg(<2 x half> inreg %arg) #0
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-NEXT: v_writelane_b32 v40, s17, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_v2f16_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_v2f16_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -805,13 +805,13 @@ define void @test_call_external_void_func_v2f16_inreg(<2 x half> inreg %arg) #0
; GFX11-NEXT: s_mov_b32 exec_lo, s2
; GFX11-NEXT: v_writelane_b32 v40, s1, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v2f16_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v2f16_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -837,13 +837,13 @@ define void @test_call_external_void_func_v2bf16_inreg(<2 x bfloat> inreg %arg)
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-NEXT: v_writelane_b32 v40, s17, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_v2bf16_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_v2bf16_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -866,13 +866,13 @@ define void @test_call_external_void_func_v2bf16_inreg(<2 x bfloat> inreg %arg)
; GFX11-NEXT: s_mov_b32 exec_lo, s2
; GFX11-NEXT: v_writelane_b32 v40, s1, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v2bf16_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v2bf16_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -897,14 +897,14 @@ define void @test_call_external_void_func_v3f16_inreg(<3 x half> inreg %arg) #0
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[20:21]
; GFX9-NEXT: v_writelane_b32 v40, s18, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_v3f16_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_v3f16_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s1, s17
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -927,13 +927,13 @@ define void @test_call_external_void_func_v3f16_inreg(<3 x half> inreg %arg) #0
; GFX11-NEXT: s_mov_b32 exec_lo, s3
; GFX11-NEXT: v_writelane_b32 v40, s2, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v3f16_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v3f16_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -958,14 +958,14 @@ define void @test_call_external_void_func_v4f16_inreg(<4 x half> inreg %arg) #0
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[20:21]
; GFX9-NEXT: v_writelane_b32 v40, s18, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_v4f16_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_v4f16_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s1, s17
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -988,13 +988,13 @@ define void @test_call_external_void_func_v4f16_inreg(<4 x half> inreg %arg) #0
; GFX11-NEXT: s_mov_b32 exec_lo, s3
; GFX11-NEXT: v_writelane_b32 v40, s2, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v4f16_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v4f16_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -1019,14 +1019,14 @@ define void @test_call_external_void_func_p0_inreg(ptr inreg %arg) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[20:21]
; GFX9-NEXT: v_writelane_b32 v40, s18, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_p0_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_p0_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s1, s17
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -1049,13 +1049,13 @@ define void @test_call_external_void_func_p0_inreg(ptr inreg %arg) #0 {
; GFX11-NEXT: s_mov_b32 exec_lo, s3
; GFX11-NEXT: v_writelane_b32 v40, s2, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_p0_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_p0_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -1080,14 +1080,14 @@ define void @test_call_external_void_func_p1_inreg(ptr addrspace(1) inreg %arg)
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[20:21]
; GFX9-NEXT: v_writelane_b32 v40, s18, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_p1_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_p1_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s1, s17
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -1110,13 +1110,13 @@ define void @test_call_external_void_func_p1_inreg(ptr addrspace(1) inreg %arg)
; GFX11-NEXT: s_mov_b32 exec_lo, s3
; GFX11-NEXT: v_writelane_b32 v40, s2, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_p1_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_p1_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -1141,13 +1141,13 @@ define void @test_call_external_void_func_p3_inreg(ptr addrspace(3) inreg %arg)
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-NEXT: v_writelane_b32 v40, s17, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_p3_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_p3_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -1170,13 +1170,13 @@ define void @test_call_external_void_func_p3_inreg(ptr addrspace(3) inreg %arg)
; GFX11-NEXT: s_mov_b32 exec_lo, s2
; GFX11-NEXT: v_writelane_b32 v40, s1, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_p3_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_p3_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -1201,8 +1201,9 @@ define void @test_call_external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inre
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[22:23]
; GFX9-NEXT: v_writelane_b32 v40, s20, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[20:21]
; GFX9-NEXT: s_add_u32 s20, s20, external_void_func_v2p1_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s21, s21, external_void_func_v2p1_inreg at rel32@hi+12
@@ -1210,7 +1211,6 @@ define void @test_call_external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inre
; GFX9-NEXT: s_mov_b32 s2, s18
; GFX9-NEXT: s_mov_b32 s1, s17
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[20:21]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -1233,13 +1233,13 @@ define void @test_call_external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inre
; GFX11-NEXT: s_mov_b32 exec_lo, s17
; GFX11-NEXT: v_writelane_b32 v40, s16, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[16:17]
; GFX11-NEXT: s_add_u32 s16, s16, external_void_func_v2p1_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s17, s17, external_void_func_v2p1_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -1264,14 +1264,14 @@ define void @test_call_external_void_func_v2p5_inreg(<2 x ptr addrspace(5)> inre
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[20:21]
; GFX9-NEXT: v_writelane_b32 v40, s18, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[18:19]
; GFX9-NEXT: s_add_u32 s18, s18, external_void_func_v2p5_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s19, s19, external_void_func_v2p5_inreg at rel32@hi+12
; GFX9-NEXT: s_mov_b32 s1, s17
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -1294,13 +1294,13 @@ define void @test_call_external_void_func_v2p5_inreg(<2 x ptr addrspace(5)> inre
; GFX11-NEXT: s_mov_b32 exec_lo, s3
; GFX11-NEXT: v_writelane_b32 v40, s2, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v2p5_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v2p5_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -1325,8 +1325,9 @@ define void @test_call_external_void_func_i64_inreg_i32_inreg_i64_inreg(i64 inre
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[22:23]
; GFX9-NEXT: v_writelane_b32 v40, s21, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[22:23]
; GFX9-NEXT: s_add_u32 s22, s22, external_void_func_i64_inreg_i32_inreg_i64_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s23, s23, external_void_func_i64_inreg_i32_inreg_i64_inreg at rel32@hi+12
@@ -1335,7 +1336,6 @@ define void @test_call_external_void_func_i64_inreg_i32_inreg_i64_inreg(i64 inre
; GFX9-NEXT: s_mov_b32 s1, s17
; GFX9-NEXT: s_mov_b32 s0, s16
; GFX9-NEXT: s_mov_b32 s16, s20
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[22:23]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -1358,13 +1358,13 @@ define void @test_call_external_void_func_i64_inreg_i32_inreg_i64_inreg(i64 inre
; GFX11-NEXT: s_mov_b32 exec_lo, s18
; GFX11-NEXT: v_writelane_b32 v40, s17, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[18:19]
; GFX11-NEXT: s_add_u32 s18, s18, external_void_func_i64_inreg_i32_inreg_i64_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s19, s19, external_void_func_i64_inreg_i32_inreg_i64_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -1389,8 +1389,9 @@ define void @test_call_external_void_func_a15i32_inreg([13 x i32] inreg %arg0) #
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[40:41]
; GFX9-NEXT: v_writelane_b32 v40, s29, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[40:41]
; GFX9-NEXT: s_add_u32 s40, s40, external_void_func_a15i32_inreg at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s41, s41, external_void_func_a15i32_inreg at rel32@hi+12
@@ -1407,7 +1408,6 @@ define void @test_call_external_void_func_a15i32_inreg([13 x i32] inreg %arg0) #
; GFX9-NEXT: s_mov_b32 s22, s26
; GFX9-NEXT: s_mov_b32 s23, s27
; GFX9-NEXT: s_mov_b32 s24, s28
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[40:41]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -1430,13 +1430,13 @@ define void @test_call_external_void_func_a15i32_inreg([13 x i32] inreg %arg0) #
; GFX11-NEXT: s_mov_b32 exec_lo, s26
; GFX11-NEXT: v_writelane_b32 v40, s25, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[26:27]
; GFX11-NEXT: s_add_u32 s26, s26, external_void_func_a15i32_inreg at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s27, s27, external_void_func_a15i32_inreg at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[26:27]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -1463,8 +1463,9 @@ define void @test_call_external_void_func_a15i32_inreg_i32_inreg([13 x i32] inre
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[22:23]
; GFX9-NEXT: v_writelane_b32 v40, s21, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[22:23]
; GFX9-NEXT: s_add_u32 s22, s22, external_void_func_a15i32_inreg_i32_inreg__noimplicit at rel32@lo+4
; GFX9-NEXT: s_addc_u32 s23, s23, external_void_func_a15i32_inreg_i32_inreg__noimplicit at rel32@hi+12
@@ -1482,7 +1483,6 @@ define void @test_call_external_void_func_a15i32_inreg_i32_inreg([13 x i32] inre
; GFX9-NEXT: s_mov_b32 s11, s18
; GFX9-NEXT: s_mov_b32 s15, s19
; GFX9-NEXT: s_mov_b32 s16, s20
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[22:23]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -1505,13 +1505,13 @@ define void @test_call_external_void_func_a15i32_inreg_i32_inreg([13 x i32] inre
; GFX11-NEXT: s_mov_b32 exec_lo, s18
; GFX11-NEXT: v_writelane_b32 v40, s17, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[18:19]
; GFX11-NEXT: s_add_u32 s18, s18, external_void_func_a15i32_inreg_i32_inreg__noimplicit at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s19, s19, external_void_func_a15i32_inreg_i32_inreg__noimplicit at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[18:19]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
diff --git a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
index 2ee71c403416a..5f7718ce3d25f 100644
--- a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
@@ -5852,7 +5852,10 @@ define void @stack_12xv3i32() #0 {
; VI-NEXT: s_or_saveexec_b64 s[8:9], -1
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[8:9]
+; VI-NEXT: v_writelane_b32 v40, s4, 2
+; VI-NEXT: v_writelane_b32 v40, s30, 0
; VI-NEXT: s_addk_i32 s32, 0x400
+; VI-NEXT: v_writelane_b32 v40, s31, 1
; VI-NEXT: v_mov_b32_e32 v0, 11
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32
; VI-NEXT: v_mov_b32_e32 v0, 12
@@ -5860,10 +5863,8 @@ define void @stack_12xv3i32() #0 {
; VI-NEXT: v_mov_b32_e32 v0, 13
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8
; VI-NEXT: v_mov_b32_e32 v0, 14
-; VI-NEXT: v_writelane_b32 v40, s4, 2
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12
; VI-NEXT: v_mov_b32_e32 v0, 15
-; VI-NEXT: v_writelane_b32 v40, s30, 0
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_12xv3i32 at rel32@lo+4
@@ -5899,7 +5900,6 @@ define void @stack_12xv3i32() #0 {
; VI-NEXT: v_mov_b32_e32 v28, 9
; VI-NEXT: v_mov_b32_e32 v29, 9
; VI-NEXT: v_mov_b32_e32 v30, 10
-; VI-NEXT: v_writelane_b32 v40, s31, 1
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
; VI-NEXT: v_readlane_b32 s30, v40, 0
; VI-NEXT: v_readlane_b32 s31, v40, 1
@@ -5920,7 +5920,10 @@ define void @stack_12xv3i32() #0 {
; CI-NEXT: s_or_saveexec_b64 s[8:9], -1
; CI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; CI-NEXT: s_mov_b64 exec, s[8:9]
+; CI-NEXT: v_writelane_b32 v40, s4, 2
+; CI-NEXT: v_writelane_b32 v40, s30, 0
; CI-NEXT: s_addk_i32 s32, 0x400
+; CI-NEXT: v_writelane_b32 v40, s31, 1
; CI-NEXT: v_mov_b32_e32 v0, 11
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32
; CI-NEXT: v_mov_b32_e32 v0, 12
@@ -5928,10 +5931,8 @@ define void @stack_12xv3i32() #0 {
; CI-NEXT: v_mov_b32_e32 v0, 13
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8
; CI-NEXT: v_mov_b32_e32 v0, 14
-; CI-NEXT: v_writelane_b32 v40, s4, 2
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12
; CI-NEXT: v_mov_b32_e32 v0, 15
-; CI-NEXT: v_writelane_b32 v40, s30, 0
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_12xv3i32 at rel32@lo+4
@@ -5967,7 +5968,6 @@ define void @stack_12xv3i32() #0 {
; CI-NEXT: v_mov_b32_e32 v28, 9
; CI-NEXT: v_mov_b32_e32 v29, 9
; CI-NEXT: v_mov_b32_e32 v30, 10
-; CI-NEXT: v_writelane_b32 v40, s31, 1
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
; CI-NEXT: v_readlane_b32 s30, v40, 0
; CI-NEXT: v_readlane_b32 s31, v40, 1
@@ -5988,7 +5988,10 @@ define void @stack_12xv3i32() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[8:9], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[8:9]
+; GFX9-NEXT: v_writelane_b32 v40, s4, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 11
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX9-NEXT: v_mov_b32_e32 v0, 12
@@ -5996,10 +5999,8 @@ define void @stack_12xv3i32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v0, 13
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8
; GFX9-NEXT: v_mov_b32_e32 v0, 14
-; GFX9-NEXT: v_writelane_b32 v40, s4, 2
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12
; GFX9-NEXT: v_mov_b32_e32 v0, 15
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_12xv3i32 at rel32@lo+4
@@ -6035,7 +6036,6 @@ define void @stack_12xv3i32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v28, 9
; GFX9-NEXT: v_mov_b32_e32 v29, 9
; GFX9-NEXT: v_mov_b32_e32 v30, 10
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -6057,11 +6057,12 @@ define void @stack_12xv3i32() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 11 :: v_dual_mov_b32 v1, 12
; GFX11-NEXT: v_dual_mov_b32 v2, 13 :: v_dual_mov_b32 v3, 14
; GFX11-NEXT: v_mov_b32_e32 v4, 15
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_add_i32 s0, s32, 16
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32
; GFX11-NEXT: scratch_store_b32 off, v4, s0
@@ -6084,9 +6085,8 @@ define void @stack_12xv3i32() #0 {
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, external_void_func_12xv3i32 at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s1, s1, external_void_func_12xv3i32 at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -6106,7 +6106,10 @@ define void @stack_12xv3i32() #0 {
; HSA-NEXT: s_or_saveexec_b64 s[8:9], -1
; HSA-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; HSA-NEXT: s_mov_b64 exec, s[8:9]
+; HSA-NEXT: v_writelane_b32 v40, s4, 2
+; HSA-NEXT: v_writelane_b32 v40, s30, 0
; HSA-NEXT: s_addk_i32 s32, 0x400
+; HSA-NEXT: v_writelane_b32 v40, s31, 1
; HSA-NEXT: v_mov_b32_e32 v0, 11
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32
; HSA-NEXT: v_mov_b32_e32 v0, 12
@@ -6114,10 +6117,8 @@ define void @stack_12xv3i32() #0 {
; HSA-NEXT: v_mov_b32_e32 v0, 13
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8
; HSA-NEXT: v_mov_b32_e32 v0, 14
-; HSA-NEXT: v_writelane_b32 v40, s4, 2
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12
; HSA-NEXT: v_mov_b32_e32 v0, 15
-; HSA-NEXT: v_writelane_b32 v40, s30, 0
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
; HSA-NEXT: s_getpc_b64 s[4:5]
; HSA-NEXT: s_add_u32 s4, s4, external_void_func_12xv3i32 at rel32@lo+4
@@ -6153,7 +6154,6 @@ define void @stack_12xv3i32() #0 {
; HSA-NEXT: v_mov_b32_e32 v28, 9
; HSA-NEXT: v_mov_b32_e32 v29, 9
; HSA-NEXT: v_mov_b32_e32 v30, 10
-; HSA-NEXT: v_writelane_b32 v40, s31, 1
; HSA-NEXT: s_swappc_b64 s[30:31], s[4:5]
; HSA-NEXT: v_readlane_b32 s30, v40, 0
; HSA-NEXT: v_readlane_b32 s31, v40, 1
@@ -6191,7 +6191,10 @@ define void @stack_12xv3f32() #0 {
; VI-NEXT: s_or_saveexec_b64 s[8:9], -1
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[8:9]
+; VI-NEXT: v_writelane_b32 v40, s4, 2
+; VI-NEXT: v_writelane_b32 v40, s30, 0
; VI-NEXT: s_addk_i32 s32, 0x400
+; VI-NEXT: v_writelane_b32 v40, s31, 1
; VI-NEXT: v_mov_b32_e32 v0, 0x41300000
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32
; VI-NEXT: v_mov_b32_e32 v0, 0x41400000
@@ -6199,10 +6202,8 @@ define void @stack_12xv3f32() #0 {
; VI-NEXT: v_mov_b32_e32 v0, 0x41500000
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8
; VI-NEXT: v_mov_b32_e32 v0, 0x41600000
-; VI-NEXT: v_writelane_b32 v40, s4, 2
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12
; VI-NEXT: v_mov_b32_e32 v0, 0x41700000
-; VI-NEXT: v_writelane_b32 v40, s30, 0
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_12xv3f32 at rel32@lo+4
@@ -6238,7 +6239,6 @@ define void @stack_12xv3f32() #0 {
; VI-NEXT: v_mov_b32_e32 v28, 0x41100000
; VI-NEXT: v_mov_b32_e32 v29, 0x41100000
; VI-NEXT: v_mov_b32_e32 v30, 0x41200000
-; VI-NEXT: v_writelane_b32 v40, s31, 1
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
; VI-NEXT: v_readlane_b32 s30, v40, 0
; VI-NEXT: v_readlane_b32 s31, v40, 1
@@ -6259,7 +6259,10 @@ define void @stack_12xv3f32() #0 {
; CI-NEXT: s_or_saveexec_b64 s[8:9], -1
; CI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; CI-NEXT: s_mov_b64 exec, s[8:9]
+; CI-NEXT: v_writelane_b32 v40, s4, 2
+; CI-NEXT: v_writelane_b32 v40, s30, 0
; CI-NEXT: s_addk_i32 s32, 0x400
+; CI-NEXT: v_writelane_b32 v40, s31, 1
; CI-NEXT: v_mov_b32_e32 v0, 0x41300000
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32
; CI-NEXT: v_mov_b32_e32 v0, 0x41400000
@@ -6267,10 +6270,8 @@ define void @stack_12xv3f32() #0 {
; CI-NEXT: v_mov_b32_e32 v0, 0x41500000
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8
; CI-NEXT: v_mov_b32_e32 v0, 0x41600000
-; CI-NEXT: v_writelane_b32 v40, s4, 2
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12
; CI-NEXT: v_mov_b32_e32 v0, 0x41700000
-; CI-NEXT: v_writelane_b32 v40, s30, 0
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_12xv3f32 at rel32@lo+4
@@ -6306,7 +6307,6 @@ define void @stack_12xv3f32() #0 {
; CI-NEXT: v_mov_b32_e32 v28, 0x41100000
; CI-NEXT: v_mov_b32_e32 v29, 0x41100000
; CI-NEXT: v_mov_b32_e32 v30, 0x41200000
-; CI-NEXT: v_writelane_b32 v40, s31, 1
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
; CI-NEXT: v_readlane_b32 s30, v40, 0
; CI-NEXT: v_readlane_b32 s31, v40, 1
@@ -6327,7 +6327,10 @@ define void @stack_12xv3f32() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[8:9], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[8:9]
+; GFX9-NEXT: v_writelane_b32 v40, s4, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 0x41300000
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX9-NEXT: v_mov_b32_e32 v0, 0x41400000
@@ -6335,10 +6338,8 @@ define void @stack_12xv3f32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v0, 0x41500000
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8
; GFX9-NEXT: v_mov_b32_e32 v0, 0x41600000
-; GFX9-NEXT: v_writelane_b32 v40, s4, 2
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12
; GFX9-NEXT: v_mov_b32_e32 v0, 0x41700000
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_12xv3f32 at rel32@lo+4
@@ -6374,7 +6375,6 @@ define void @stack_12xv3f32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v28, 0x41100000
; GFX9-NEXT: v_mov_b32_e32 v29, 0x41100000
; GFX9-NEXT: v_mov_b32_e32 v30, 0x41200000
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -6396,13 +6396,14 @@ define void @stack_12xv3f32() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_mov_b32_e32 v0, 0x41300000
; GFX11-NEXT: v_mov_b32_e32 v1, 0x41400000
; GFX11-NEXT: v_mov_b32_e32 v2, 0x41500000
; GFX11-NEXT: v_mov_b32_e32 v3, 0x41600000
; GFX11-NEXT: v_dual_mov_b32 v4, 0x41700000 :: v_dual_mov_b32 v5, 1.0
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_add_i32 s0, s32, 16
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32
; GFX11-NEXT: scratch_store_b32 off, v4, s0
@@ -6427,9 +6428,8 @@ define void @stack_12xv3f32() #0 {
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, external_void_func_12xv3f32 at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s1, s1, external_void_func_12xv3f32 at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -6449,7 +6449,10 @@ define void @stack_12xv3f32() #0 {
; HSA-NEXT: s_or_saveexec_b64 s[8:9], -1
; HSA-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; HSA-NEXT: s_mov_b64 exec, s[8:9]
+; HSA-NEXT: v_writelane_b32 v40, s4, 2
+; HSA-NEXT: v_writelane_b32 v40, s30, 0
; HSA-NEXT: s_addk_i32 s32, 0x400
+; HSA-NEXT: v_writelane_b32 v40, s31, 1
; HSA-NEXT: v_mov_b32_e32 v0, 0x41300000
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32
; HSA-NEXT: v_mov_b32_e32 v0, 0x41400000
@@ -6457,10 +6460,8 @@ define void @stack_12xv3f32() #0 {
; HSA-NEXT: v_mov_b32_e32 v0, 0x41500000
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8
; HSA-NEXT: v_mov_b32_e32 v0, 0x41600000
-; HSA-NEXT: v_writelane_b32 v40, s4, 2
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12
; HSA-NEXT: v_mov_b32_e32 v0, 0x41700000
-; HSA-NEXT: v_writelane_b32 v40, s30, 0
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
; HSA-NEXT: s_getpc_b64 s[4:5]
; HSA-NEXT: s_add_u32 s4, s4, external_void_func_12xv3f32 at rel32@lo+4
@@ -6496,7 +6497,6 @@ define void @stack_12xv3f32() #0 {
; HSA-NEXT: v_mov_b32_e32 v28, 0x41100000
; HSA-NEXT: v_mov_b32_e32 v29, 0x41100000
; HSA-NEXT: v_mov_b32_e32 v30, 0x41200000
-; HSA-NEXT: v_writelane_b32 v40, s31, 1
; HSA-NEXT: s_swappc_b64 s[30:31], s[4:5]
; HSA-NEXT: v_readlane_b32 s30, v40, 0
; HSA-NEXT: v_readlane_b32 s31, v40, 1
@@ -6534,7 +6534,10 @@ define void @stack_8xv5i32() #0 {
; VI-NEXT: s_or_saveexec_b64 s[8:9], -1
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[8:9]
+; VI-NEXT: v_writelane_b32 v40, s4, 2
+; VI-NEXT: v_writelane_b32 v40, s30, 0
; VI-NEXT: s_addk_i32 s32, 0x400
+; VI-NEXT: v_writelane_b32 v40, s31, 1
; VI-NEXT: v_mov_b32_e32 v0, 7
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32
; VI-NEXT: v_mov_b32_e32 v0, 8
@@ -6550,10 +6553,8 @@ define void @stack_8xv5i32() #0 {
; VI-NEXT: v_mov_b32_e32 v0, 13
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24
; VI-NEXT: v_mov_b32_e32 v0, 14
-; VI-NEXT: v_writelane_b32 v40, s4, 2
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28
; VI-NEXT: v_mov_b32_e32 v0, 15
-; VI-NEXT: v_writelane_b32 v40, s30, 0
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_8xv5i32 at rel32@lo+4
@@ -6589,7 +6590,6 @@ define void @stack_8xv5i32() #0 {
; VI-NEXT: v_mov_b32_e32 v28, 5
; VI-NEXT: v_mov_b32_e32 v29, 5
; VI-NEXT: v_mov_b32_e32 v30, 6
-; VI-NEXT: v_writelane_b32 v40, s31, 1
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
; VI-NEXT: v_readlane_b32 s30, v40, 0
; VI-NEXT: v_readlane_b32 s31, v40, 1
@@ -6610,7 +6610,10 @@ define void @stack_8xv5i32() #0 {
; CI-NEXT: s_or_saveexec_b64 s[8:9], -1
; CI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; CI-NEXT: s_mov_b64 exec, s[8:9]
+; CI-NEXT: v_writelane_b32 v40, s4, 2
+; CI-NEXT: v_writelane_b32 v40, s30, 0
; CI-NEXT: s_addk_i32 s32, 0x400
+; CI-NEXT: v_writelane_b32 v40, s31, 1
; CI-NEXT: v_mov_b32_e32 v0, 7
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32
; CI-NEXT: v_mov_b32_e32 v0, 8
@@ -6626,10 +6629,8 @@ define void @stack_8xv5i32() #0 {
; CI-NEXT: v_mov_b32_e32 v0, 13
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24
; CI-NEXT: v_mov_b32_e32 v0, 14
-; CI-NEXT: v_writelane_b32 v40, s4, 2
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28
; CI-NEXT: v_mov_b32_e32 v0, 15
-; CI-NEXT: v_writelane_b32 v40, s30, 0
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_8xv5i32 at rel32@lo+4
@@ -6665,7 +6666,6 @@ define void @stack_8xv5i32() #0 {
; CI-NEXT: v_mov_b32_e32 v28, 5
; CI-NEXT: v_mov_b32_e32 v29, 5
; CI-NEXT: v_mov_b32_e32 v30, 6
-; CI-NEXT: v_writelane_b32 v40, s31, 1
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
; CI-NEXT: v_readlane_b32 s30, v40, 0
; CI-NEXT: v_readlane_b32 s31, v40, 1
@@ -6686,7 +6686,10 @@ define void @stack_8xv5i32() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[8:9], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[8:9]
+; GFX9-NEXT: v_writelane_b32 v40, s4, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 7
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX9-NEXT: v_mov_b32_e32 v0, 8
@@ -6702,10 +6705,8 @@ define void @stack_8xv5i32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v0, 13
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24
; GFX9-NEXT: v_mov_b32_e32 v0, 14
-; GFX9-NEXT: v_writelane_b32 v40, s4, 2
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28
; GFX9-NEXT: v_mov_b32_e32 v0, 15
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32
; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_8xv5i32 at rel32@lo+4
@@ -6741,7 +6742,6 @@ define void @stack_8xv5i32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v28, 5
; GFX9-NEXT: v_mov_b32_e32 v29, 5
; GFX9-NEXT: v_mov_b32_e32 v30, 6
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -6763,15 +6763,16 @@ define void @stack_8xv5i32() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 7 :: v_dual_mov_b32 v1, 8
; GFX11-NEXT: v_dual_mov_b32 v2, 9 :: v_dual_mov_b32 v3, 10
; GFX11-NEXT: v_dual_mov_b32 v8, 15 :: v_dual_mov_b32 v5, 12
-; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_dual_mov_b32 v4, 11 :: v_dual_mov_b32 v7, 14
; GFX11-NEXT: v_mov_b32_e32 v6, 13
; GFX11-NEXT: s_add_i32 s0, s32, 32
; GFX11-NEXT: s_add_i32 s1, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, 0
; GFX11-NEXT: v_mov_b32_e32 v1, 0
@@ -6795,9 +6796,8 @@ define void @stack_8xv5i32() #0 {
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, external_void_func_8xv5i32 at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s1, s1, external_void_func_8xv5i32 at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -6817,7 +6817,10 @@ define void @stack_8xv5i32() #0 {
; HSA-NEXT: s_or_saveexec_b64 s[8:9], -1
; HSA-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; HSA-NEXT: s_mov_b64 exec, s[8:9]
+; HSA-NEXT: v_writelane_b32 v40, s4, 2
+; HSA-NEXT: v_writelane_b32 v40, s30, 0
; HSA-NEXT: s_addk_i32 s32, 0x400
+; HSA-NEXT: v_writelane_b32 v40, s31, 1
; HSA-NEXT: v_mov_b32_e32 v0, 7
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32
; HSA-NEXT: v_mov_b32_e32 v0, 8
@@ -6833,10 +6836,8 @@ define void @stack_8xv5i32() #0 {
; HSA-NEXT: v_mov_b32_e32 v0, 13
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24
; HSA-NEXT: v_mov_b32_e32 v0, 14
-; HSA-NEXT: v_writelane_b32 v40, s4, 2
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28
; HSA-NEXT: v_mov_b32_e32 v0, 15
-; HSA-NEXT: v_writelane_b32 v40, s30, 0
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32
; HSA-NEXT: s_getpc_b64 s[4:5]
; HSA-NEXT: s_add_u32 s4, s4, external_void_func_8xv5i32 at rel32@lo+4
@@ -6872,7 +6873,6 @@ define void @stack_8xv5i32() #0 {
; HSA-NEXT: v_mov_b32_e32 v28, 5
; HSA-NEXT: v_mov_b32_e32 v29, 5
; HSA-NEXT: v_mov_b32_e32 v30, 6
-; HSA-NEXT: v_writelane_b32 v40, s31, 1
; HSA-NEXT: s_swappc_b64 s[30:31], s[4:5]
; HSA-NEXT: v_readlane_b32 s30, v40, 0
; HSA-NEXT: v_readlane_b32 s31, v40, 1
@@ -6906,7 +6906,10 @@ define void @stack_8xv5f32() #0 {
; VI-NEXT: s_or_saveexec_b64 s[8:9], -1
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[8:9]
+; VI-NEXT: v_writelane_b32 v40, s4, 2
+; VI-NEXT: v_writelane_b32 v40, s30, 0
; VI-NEXT: s_addk_i32 s32, 0x400
+; VI-NEXT: v_writelane_b32 v40, s31, 1
; VI-NEXT: v_mov_b32_e32 v0, 0x40e00000
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32
; VI-NEXT: v_mov_b32_e32 v0, 0x41000000
@@ -6922,10 +6925,8 @@ define void @stack_8xv5f32() #0 {
; VI-NEXT: v_mov_b32_e32 v0, 0x41500000
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24
; VI-NEXT: v_mov_b32_e32 v0, 0x41600000
-; VI-NEXT: v_writelane_b32 v40, s4, 2
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28
; VI-NEXT: v_mov_b32_e32 v0, 0x41700000
-; VI-NEXT: v_writelane_b32 v40, s30, 0
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32
; VI-NEXT: s_getpc_b64 s[4:5]
; VI-NEXT: s_add_u32 s4, s4, external_void_func_8xv5f32 at rel32@lo+4
@@ -6961,7 +6962,6 @@ define void @stack_8xv5f32() #0 {
; VI-NEXT: v_mov_b32_e32 v28, 0x40a00000
; VI-NEXT: v_mov_b32_e32 v29, 0x40a00000
; VI-NEXT: v_mov_b32_e32 v30, 0x40c00000
-; VI-NEXT: v_writelane_b32 v40, s31, 1
; VI-NEXT: s_swappc_b64 s[30:31], s[4:5]
; VI-NEXT: v_readlane_b32 s30, v40, 0
; VI-NEXT: v_readlane_b32 s31, v40, 1
@@ -6982,7 +6982,10 @@ define void @stack_8xv5f32() #0 {
; CI-NEXT: s_or_saveexec_b64 s[8:9], -1
; CI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; CI-NEXT: s_mov_b64 exec, s[8:9]
+; CI-NEXT: v_writelane_b32 v40, s4, 2
+; CI-NEXT: v_writelane_b32 v40, s30, 0
; CI-NEXT: s_addk_i32 s32, 0x400
+; CI-NEXT: v_writelane_b32 v40, s31, 1
; CI-NEXT: v_mov_b32_e32 v0, 0x40e00000
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32
; CI-NEXT: v_mov_b32_e32 v0, 0x41000000
@@ -6998,10 +7001,8 @@ define void @stack_8xv5f32() #0 {
; CI-NEXT: v_mov_b32_e32 v0, 0x41500000
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24
; CI-NEXT: v_mov_b32_e32 v0, 0x41600000
-; CI-NEXT: v_writelane_b32 v40, s4, 2
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28
; CI-NEXT: v_mov_b32_e32 v0, 0x41700000
-; CI-NEXT: v_writelane_b32 v40, s30, 0
; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32
; CI-NEXT: s_getpc_b64 s[4:5]
; CI-NEXT: s_add_u32 s4, s4, external_void_func_8xv5f32 at rel32@lo+4
@@ -7037,7 +7038,6 @@ define void @stack_8xv5f32() #0 {
; CI-NEXT: v_mov_b32_e32 v28, 0x40a00000
; CI-NEXT: v_mov_b32_e32 v29, 0x40a00000
; CI-NEXT: v_mov_b32_e32 v30, 0x40c00000
-; CI-NEXT: v_writelane_b32 v40, s31, 1
; CI-NEXT: s_swappc_b64 s[30:31], s[4:5]
; CI-NEXT: v_readlane_b32 s30, v40, 0
; CI-NEXT: v_readlane_b32 s31, v40, 1
@@ -7058,7 +7058,10 @@ define void @stack_8xv5f32() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[8:9], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[8:9]
+; GFX9-NEXT: v_writelane_b32 v40, s4, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 0x40e00000
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX9-NEXT: v_mov_b32_e32 v0, 0x41000000
@@ -7074,10 +7077,8 @@ define void @stack_8xv5f32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v0, 0x41500000
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24
; GFX9-NEXT: v_mov_b32_e32 v0, 0x41600000
-; GFX9-NEXT: v_writelane_b32 v40, s4, 2
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28
; GFX9-NEXT: v_mov_b32_e32 v0, 0x41700000
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32
; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_8xv5f32 at rel32@lo+4
@@ -7113,7 +7114,6 @@ define void @stack_8xv5f32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v28, 0x40a00000
; GFX9-NEXT: v_mov_b32_e32 v29, 0x40a00000
; GFX9-NEXT: v_mov_b32_e32 v30, 0x40c00000
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -7135,19 +7135,20 @@ define void @stack_8xv5f32() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_mov_b32_e32 v0, 0x40e00000
; GFX11-NEXT: v_mov_b32_e32 v1, 0x41000000
; GFX11-NEXT: v_mov_b32_e32 v2, 0x41100000
; GFX11-NEXT: v_mov_b32_e32 v3, 0x41200000
; GFX11-NEXT: v_mov_b32_e32 v8, 0x41700000
-; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_mov_b32_e32 v4, 0x41300000
; GFX11-NEXT: v_mov_b32_e32 v5, 0x41400000
; GFX11-NEXT: v_dual_mov_b32 v6, 0x41500000 :: v_dual_mov_b32 v9, 1.0
; GFX11-NEXT: v_mov_b32_e32 v7, 0x41600000
; GFX11-NEXT: s_add_i32 s0, s32, 32
; GFX11-NEXT: s_add_i32 s1, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32
; GFX11-NEXT: scratch_store_b32 off, v8, s0
; GFX11-NEXT: scratch_store_b128 off, v[4:7], s1
@@ -7170,9 +7171,8 @@ define void @stack_8xv5f32() #0 {
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, external_void_func_8xv5f32 at rel32@lo+4
; GFX11-NEXT: s_addc_u32 s1, s1, external_void_func_8xv5f32 at rel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -7192,7 +7192,10 @@ define void @stack_8xv5f32() #0 {
; HSA-NEXT: s_or_saveexec_b64 s[8:9], -1
; HSA-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; HSA-NEXT: s_mov_b64 exec, s[8:9]
+; HSA-NEXT: v_writelane_b32 v40, s4, 2
+; HSA-NEXT: v_writelane_b32 v40, s30, 0
; HSA-NEXT: s_addk_i32 s32, 0x400
+; HSA-NEXT: v_writelane_b32 v40, s31, 1
; HSA-NEXT: v_mov_b32_e32 v0, 0x40e00000
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32
; HSA-NEXT: v_mov_b32_e32 v0, 0x41000000
@@ -7208,10 +7211,8 @@ define void @stack_8xv5f32() #0 {
; HSA-NEXT: v_mov_b32_e32 v0, 0x41500000
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24
; HSA-NEXT: v_mov_b32_e32 v0, 0x41600000
-; HSA-NEXT: v_writelane_b32 v40, s4, 2
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28
; HSA-NEXT: v_mov_b32_e32 v0, 0x41700000
-; HSA-NEXT: v_writelane_b32 v40, s30, 0
; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32
; HSA-NEXT: s_getpc_b64 s[4:5]
; HSA-NEXT: s_add_u32 s4, s4, external_void_func_8xv5f32 at rel32@lo+4
@@ -7247,7 +7248,6 @@ define void @stack_8xv5f32() #0 {
; HSA-NEXT: v_mov_b32_e32 v28, 0x40a00000
; HSA-NEXT: v_mov_b32_e32 v29, 0x40a00000
; HSA-NEXT: v_mov_b32_e32 v30, 0x40c00000
-; HSA-NEXT: v_writelane_b32 v40, s31, 1
; HSA-NEXT: s_swappc_b64 s[30:31], s[4:5]
; HSA-NEXT: v_readlane_b32 s30, v40, 0
; HSA-NEXT: v_readlane_b32 s31, v40, 1
diff --git a/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll b/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
index eef727b1a31b6..8c0991fd32849 100644
--- a/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
@@ -36,14 +36,14 @@ define void @test_func_call_external_void_func_void_clobber_s30_s31_call_externa
; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[6:7]
; MUBUF-NEXT: v_writelane_b32 v40, s4, 4
-; MUBUF-NEXT: v_writelane_b32 v40, s34, 0
; MUBUF-NEXT: s_addk_i32 s32, 0x400
+; MUBUF-NEXT: v_writelane_b32 v40, s34, 0
; MUBUF-NEXT: v_writelane_b32 v40, s35, 1
; MUBUF-NEXT: v_writelane_b32 v40, s30, 2
+; MUBUF-NEXT: v_writelane_b32 v40, s31, 3
; MUBUF-NEXT: s_getpc_b64 s[34:35]
; MUBUF-NEXT: s_add_u32 s34, s34, external_void_func_void at rel32@lo+4
; MUBUF-NEXT: s_addc_u32 s35, s35, external_void_func_void at rel32@hi+12
-; MUBUF-NEXT: v_writelane_b32 v40, s31, 3
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[34:35]
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ;;#ASMEND
@@ -70,14 +70,14 @@ define void @test_func_call_external_void_func_void_clobber_s30_s31_call_externa
; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
; FLATSCR-NEXT: v_writelane_b32 v40, s0, 4
-; FLATSCR-NEXT: v_writelane_b32 v40, s34, 0
; FLATSCR-NEXT: s_add_i32 s32, s32, 16
+; FLATSCR-NEXT: v_writelane_b32 v40, s34, 0
; FLATSCR-NEXT: v_writelane_b32 v40, s35, 1
; FLATSCR-NEXT: v_writelane_b32 v40, s30, 2
+; FLATSCR-NEXT: v_writelane_b32 v40, s31, 3
; FLATSCR-NEXT: s_getpc_b64 s[34:35]
; FLATSCR-NEXT: s_add_u32 s34, s34, external_void_func_void at rel32@lo+4
; FLATSCR-NEXT: s_addc_u32 s35, s35, external_void_func_void at rel32@hi+12
-; FLATSCR-NEXT: v_writelane_b32 v40, s31, 3
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[34:35]
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ;;#ASMEND
@@ -110,14 +110,14 @@ define void @test_func_call_external_void_funcx2() #0 {
; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[6:7]
; MUBUF-NEXT: v_writelane_b32 v40, s4, 4
-; MUBUF-NEXT: v_writelane_b32 v40, s34, 0
; MUBUF-NEXT: s_addk_i32 s32, 0x400
+; MUBUF-NEXT: v_writelane_b32 v40, s34, 0
; MUBUF-NEXT: v_writelane_b32 v40, s35, 1
; MUBUF-NEXT: v_writelane_b32 v40, s30, 2
+; MUBUF-NEXT: v_writelane_b32 v40, s31, 3
; MUBUF-NEXT: s_getpc_b64 s[34:35]
; MUBUF-NEXT: s_add_u32 s34, s34, external_void_func_void at rel32@lo+4
; MUBUF-NEXT: s_addc_u32 s35, s35, external_void_func_void at rel32@hi+12
-; MUBUF-NEXT: v_writelane_b32 v40, s31, 3
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[34:35]
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[34:35]
; MUBUF-NEXT: v_readlane_b32 s30, v40, 2
@@ -142,14 +142,14 @@ define void @test_func_call_external_void_funcx2() #0 {
; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
; FLATSCR-NEXT: v_writelane_b32 v40, s0, 4
-; FLATSCR-NEXT: v_writelane_b32 v40, s34, 0
; FLATSCR-NEXT: s_add_i32 s32, s32, 16
+; FLATSCR-NEXT: v_writelane_b32 v40, s34, 0
; FLATSCR-NEXT: v_writelane_b32 v40, s35, 1
; FLATSCR-NEXT: v_writelane_b32 v40, s30, 2
+; FLATSCR-NEXT: v_writelane_b32 v40, s31, 3
; FLATSCR-NEXT: s_getpc_b64 s[34:35]
; FLATSCR-NEXT: s_add_u32 s34, s34, external_void_func_void at rel32@lo+4
; FLATSCR-NEXT: s_addc_u32 s35, s35, external_void_func_void at rel32@hi+12
-; FLATSCR-NEXT: v_writelane_b32 v40, s31, 3
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[34:35]
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[34:35]
; FLATSCR-NEXT: v_readlane_b32 s30, v40, 2
@@ -525,10 +525,10 @@ define void @callee_saved_sgpr_func() #2 {
; MUBUF-NEXT: s_addk_i32 s32, 0x400
; MUBUF-NEXT: v_writelane_b32 v40, s34, 0
; MUBUF-NEXT: v_writelane_b32 v40, s30, 1
+; MUBUF-NEXT: v_writelane_b32 v40, s31, 2
; MUBUF-NEXT: s_getpc_b64 s[4:5]
; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_void at rel32@lo+4
; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_void at rel32@hi+12
-; MUBUF-NEXT: v_writelane_b32 v40, s31, 2
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; def s40
; MUBUF-NEXT: ;;#ASMEND
@@ -561,10 +561,10 @@ define void @callee_saved_sgpr_func() #2 {
; FLATSCR-NEXT: s_add_i32 s32, s32, 16
; FLATSCR-NEXT: v_writelane_b32 v40, s34, 0
; FLATSCR-NEXT: v_writelane_b32 v40, s30, 1
+; FLATSCR-NEXT: v_writelane_b32 v40, s31, 2
; FLATSCR-NEXT: s_getpc_b64 s[0:1]
; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_void at rel32@lo+4
; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_void at rel32@hi+12
-; FLATSCR-NEXT: v_writelane_b32 v40, s31, 2
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; def s40
; FLATSCR-NEXT: ;;#ASMEND
@@ -626,13 +626,13 @@ define void @callee_saved_sgpr_vgpr_func() #2 {
; MUBUF-NEXT: s_mov_b64 exec, s[6:7]
; MUBUF-NEXT: v_writelane_b32 v41, s4, 3
; MUBUF-NEXT: s_addk_i32 s32, 0x400
+; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; MUBUF-NEXT: v_writelane_b32 v41, s34, 0
; MUBUF-NEXT: v_writelane_b32 v41, s30, 1
+; MUBUF-NEXT: v_writelane_b32 v41, s31, 2
; MUBUF-NEXT: s_getpc_b64 s[4:5]
; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_void at rel32@lo+4
; MUBUF-NEXT: s_addc_u32 s5, s5, external_void_func_void at rel32@hi+12
-; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; MUBUF-NEXT: v_writelane_b32 v41, s31, 2
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; def s40
; MUBUF-NEXT: ;;#ASMEND
@@ -670,13 +670,13 @@ define void @callee_saved_sgpr_vgpr_func() #2 {
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
; FLATSCR-NEXT: v_writelane_b32 v41, s0, 3
; FLATSCR-NEXT: s_add_i32 s32, s32, 16
+; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; FLATSCR-NEXT: v_writelane_b32 v41, s34, 0
; FLATSCR-NEXT: v_writelane_b32 v41, s30, 1
+; FLATSCR-NEXT: v_writelane_b32 v41, s31, 2
; FLATSCR-NEXT: s_getpc_b64 s[0:1]
; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_void at rel32@lo+4
; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_void at rel32@hi+12
-; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
-; FLATSCR-NEXT: v_writelane_b32 v41, s31, 2
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; def s40
; FLATSCR-NEXT: ;;#ASMEND
diff --git a/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll b/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
index 07f58df81c502..eb3ef69848a88 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
@@ -122,13 +122,13 @@ define void @callee_with_stack_and_call() #0 {
; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[18:19]
; MUBUF-NEXT: v_writelane_b32 v40, s16, 2
-; MUBUF-NEXT: s_addk_i32 s32, 0x400
; MUBUF-NEXT: v_writelane_b32 v40, s30, 0
+; MUBUF-NEXT: s_addk_i32 s32, 0x400
+; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: s_getpc_b64 s[16:17]
; MUBUF-NEXT: s_add_u32 s16, s16, external_void_func_void at rel32@lo+4
; MUBUF-NEXT: s_addc_u32 s17, s17, external_void_func_void at rel32@hi+12
-; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[16:17]
@@ -152,13 +152,13 @@ define void @callee_with_stack_and_call() #0 {
; FLATSCR-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
; FLATSCR-NEXT: v_writelane_b32 v40, s0, 2
-; FLATSCR-NEXT: s_add_i32 s32, s32, 16
; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0
+; FLATSCR-NEXT: s_add_i32 s32, s32, 16
+; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: s_getpc_b64 s[0:1]
; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_void at rel32@lo+4
; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_void at rel32@hi+12
-; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
; FLATSCR-NEXT: scratch_store_dword off, v0, s33
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -194,12 +194,12 @@ define void @callee_no_stack_with_call() #0 {
; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[18:19]
; MUBUF-NEXT: v_writelane_b32 v40, s16, 2
-; MUBUF-NEXT: s_addk_i32 s32, 0x400
; MUBUF-NEXT: v_writelane_b32 v40, s30, 0
+; MUBUF-NEXT: s_addk_i32 s32, 0x400
+; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
; MUBUF-NEXT: s_getpc_b64 s[16:17]
; MUBUF-NEXT: s_add_u32 s16, s16, external_void_func_void at rel32@lo+4
; MUBUF-NEXT: s_addc_u32 s17, s17, external_void_func_void at rel32@hi+12
-; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[16:17]
; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
; MUBUF-NEXT: v_readlane_b32 s31, v40, 1
@@ -221,12 +221,12 @@ define void @callee_no_stack_with_call() #0 {
; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
; FLATSCR-NEXT: v_writelane_b32 v40, s0, 2
-; FLATSCR-NEXT: s_add_i32 s32, s32, 16
; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0
+; FLATSCR-NEXT: s_add_i32 s32, s32, 16
+; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
; FLATSCR-NEXT: s_getpc_b64 s[0:1]
; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_void at rel32@lo+4
; FLATSCR-NEXT: s_addc_u32 s1, s1, external_void_func_void at rel32@hi+12
-; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1]
; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
; FLATSCR-NEXT: v_readlane_b32 s31, v40, 1
@@ -489,15 +489,15 @@ define void @callee_with_stack_no_fp_elim_csr_vgpr() #1 {
; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; MUBUF-NEXT: s_mov_b32 s4, s33
; MUBUF-NEXT: s_mov_b32 s33, s32
-; MUBUF-NEXT: v_mov_b32_e32 v0, 0
+; MUBUF-NEXT: s_addk_i32 s32, 0x300
; MUBUF-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; clobber v41
; MUBUF-NEXT: ;;#ASMEND
; MUBUF-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
-; MUBUF-NEXT: s_addk_i32 s32, 0x300
; MUBUF-NEXT: s_mov_b32 s32, s33
; MUBUF-NEXT: s_mov_b32 s33, s4
; MUBUF-NEXT: s_waitcnt vmcnt(0)
@@ -508,15 +508,15 @@ define void @callee_with_stack_no_fp_elim_csr_vgpr() #1 {
; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; FLATSCR-NEXT: s_mov_b32 s0, s33
; FLATSCR-NEXT: s_mov_b32 s33, s32
-; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
+; FLATSCR-NEXT: s_add_i32 s32, s32, 12
; FLATSCR-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
+; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: scratch_store_dword off, v0, s33 offset:4
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; clobber v41
; FLATSCR-NEXT: ;;#ASMEND
; FLATSCR-NEXT: scratch_load_dword v41, off, s33 ; 4-byte Folded Reload
-; FLATSCR-NEXT: s_add_i32 s32, s32, 12
; FLATSCR-NEXT: s_mov_b32 s32, s33
; FLATSCR-NEXT: s_mov_b32 s33, s0
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
@@ -537,6 +537,8 @@ define void @last_lane_vgpr_for_fp_csr() #1 {
; MUBUF-NEXT: s_xor_saveexec_b64 s[6:7], -1
; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[6:7]
+; MUBUF-NEXT: s_addk_i32 s32, 0x400
+; MUBUF-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
; MUBUF-NEXT: v_writelane_b32 v1, s48, 0
; MUBUF-NEXT: v_writelane_b32 v1, s49, 1
; MUBUF-NEXT: v_writelane_b32 v1, s50, 2
@@ -566,19 +568,17 @@ define void @last_lane_vgpr_for_fp_csr() #1 {
; MUBUF-NEXT: v_writelane_b32 v1, s98, 26
; MUBUF-NEXT: v_writelane_b32 v1, s99, 27
; MUBUF-NEXT: v_writelane_b32 v1, s100, 28
-; MUBUF-NEXT: v_mov_b32_e32 v0, 0
-; MUBUF-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
; MUBUF-NEXT: v_writelane_b32 v1, s101, 29
+; MUBUF-NEXT: v_writelane_b32 v1, s102, 30
+; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; clobber v41
; MUBUF-NEXT: ;;#ASMEND
-; MUBUF-NEXT: v_writelane_b32 v1, s102, 30
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ;;#ASMEND
; MUBUF-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
-; MUBUF-NEXT: s_addk_i32 s32, 0x400
; MUBUF-NEXT: v_readlane_b32 s102, v1, 30
; MUBUF-NEXT: v_readlane_b32 s101, v1, 29
; MUBUF-NEXT: v_readlane_b32 s100, v1, 28
@@ -626,6 +626,8 @@ define void @last_lane_vgpr_for_fp_csr() #1 {
; FLATSCR-NEXT: s_xor_saveexec_b64 s[2:3], -1
; FLATSCR-NEXT: scratch_store_dword off, v1, s33 offset:8 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
+; FLATSCR-NEXT: s_add_i32 s32, s32, 16
+; FLATSCR-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
; FLATSCR-NEXT: v_writelane_b32 v1, s48, 0
; FLATSCR-NEXT: v_writelane_b32 v1, s49, 1
; FLATSCR-NEXT: v_writelane_b32 v1, s50, 2
@@ -655,19 +657,17 @@ define void @last_lane_vgpr_for_fp_csr() #1 {
; FLATSCR-NEXT: v_writelane_b32 v1, s98, 26
; FLATSCR-NEXT: v_writelane_b32 v1, s99, 27
; FLATSCR-NEXT: v_writelane_b32 v1, s100, 28
-; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
-; FLATSCR-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
; FLATSCR-NEXT: v_writelane_b32 v1, s101, 29
+; FLATSCR-NEXT: v_writelane_b32 v1, s102, 30
+; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: scratch_store_dword off, v0, s33 offset:4
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; clobber v41
; FLATSCR-NEXT: ;;#ASMEND
-; FLATSCR-NEXT: v_writelane_b32 v1, s102, 30
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ;;#ASMEND
; FLATSCR-NEXT: scratch_load_dword v41, off, s33 ; 4-byte Folded Reload
-; FLATSCR-NEXT: s_add_i32 s32, s32, 16
; FLATSCR-NEXT: v_readlane_b32 s102, v1, 30
; FLATSCR-NEXT: v_readlane_b32 s101, v1, 29
; FLATSCR-NEXT: v_readlane_b32 s100, v1, 28
@@ -731,6 +731,8 @@ define void @no_new_vgpr_for_fp_csr() #1 {
; MUBUF-NEXT: s_xor_saveexec_b64 s[6:7], -1
; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[6:7]
+; MUBUF-NEXT: s_addk_i32 s32, 0x400
+; MUBUF-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
; MUBUF-NEXT: v_writelane_b32 v1, s39, 0
; MUBUF-NEXT: v_writelane_b32 v1, s48, 1
; MUBUF-NEXT: v_writelane_b32 v1, s49, 2
@@ -761,19 +763,17 @@ define void @no_new_vgpr_for_fp_csr() #1 {
; MUBUF-NEXT: v_writelane_b32 v1, s98, 27
; MUBUF-NEXT: v_writelane_b32 v1, s99, 28
; MUBUF-NEXT: v_writelane_b32 v1, s100, 29
-; MUBUF-NEXT: v_mov_b32_e32 v0, 0
-; MUBUF-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
; MUBUF-NEXT: v_writelane_b32 v1, s101, 30
+; MUBUF-NEXT: v_writelane_b32 v1, s102, 31
+; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; clobber v41
; MUBUF-NEXT: ;;#ASMEND
-; MUBUF-NEXT: v_writelane_b32 v1, s102, 31
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ;;#ASMEND
; MUBUF-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
-; MUBUF-NEXT: s_addk_i32 s32, 0x400
; MUBUF-NEXT: v_readlane_b32 s102, v1, 31
; MUBUF-NEXT: v_readlane_b32 s101, v1, 30
; MUBUF-NEXT: v_readlane_b32 s100, v1, 29
@@ -822,6 +822,8 @@ define void @no_new_vgpr_for_fp_csr() #1 {
; FLATSCR-NEXT: s_xor_saveexec_b64 s[2:3], -1
; FLATSCR-NEXT: scratch_store_dword off, v1, s33 offset:8 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
+; FLATSCR-NEXT: s_add_i32 s32, s32, 16
+; FLATSCR-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
; FLATSCR-NEXT: v_writelane_b32 v1, s39, 0
; FLATSCR-NEXT: v_writelane_b32 v1, s48, 1
; FLATSCR-NEXT: v_writelane_b32 v1, s49, 2
@@ -852,19 +854,17 @@ define void @no_new_vgpr_for_fp_csr() #1 {
; FLATSCR-NEXT: v_writelane_b32 v1, s98, 27
; FLATSCR-NEXT: v_writelane_b32 v1, s99, 28
; FLATSCR-NEXT: v_writelane_b32 v1, s100, 29
-; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
-; FLATSCR-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
; FLATSCR-NEXT: v_writelane_b32 v1, s101, 30
+; FLATSCR-NEXT: v_writelane_b32 v1, s102, 31
+; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: scratch_store_dword off, v0, s33 offset:4
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; clobber v41
; FLATSCR-NEXT: ;;#ASMEND
-; FLATSCR-NEXT: v_writelane_b32 v1, s102, 31
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ;;#ASMEND
; FLATSCR-NEXT: scratch_load_dword v41, off, s33 ; 4-byte Folded Reload
-; FLATSCR-NEXT: s_add_i32 s32, s32, 16
; FLATSCR-NEXT: v_readlane_b32 s102, v1, 31
; FLATSCR-NEXT: v_readlane_b32 s101, v1, 30
; FLATSCR-NEXT: v_readlane_b32 s100, v1, 29
@@ -970,13 +970,13 @@ define void @no_unused_non_csr_sgpr_for_fp() #1 {
; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[4:5]
; MUBUF-NEXT: v_writelane_b32 v1, s30, 0
-; MUBUF-NEXT: v_mov_b32_e32 v0, 0
+; MUBUF-NEXT: s_addk_i32 s32, 0x300
; MUBUF-NEXT: v_writelane_b32 v1, s31, 1
+; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ;;#ASMEND
-; MUBUF-NEXT: s_addk_i32 s32, 0x300
; MUBUF-NEXT: v_readlane_b32 s30, v1, 0
; MUBUF-NEXT: v_readlane_b32 s31, v1, 1
; MUBUF-NEXT: s_mov_b32 s32, s33
@@ -996,13 +996,13 @@ define void @no_unused_non_csr_sgpr_for_fp() #1 {
; FLATSCR-NEXT: scratch_store_dword off, v1, s33 offset:4 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[0:1]
; FLATSCR-NEXT: v_writelane_b32 v1, s30, 0
-; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
+; FLATSCR-NEXT: s_add_i32 s32, s32, 12
; FLATSCR-NEXT: v_writelane_b32 v1, s31, 1
+; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: scratch_store_dword off, v0, s33
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ;;#ASMEND
-; FLATSCR-NEXT: s_add_i32 s32, s32, 12
; FLATSCR-NEXT: v_readlane_b32 s30, v1, 0
; FLATSCR-NEXT: v_readlane_b32 s31, v1, 1
; FLATSCR-NEXT: s_mov_b32 s32, s33
@@ -1036,13 +1036,13 @@ define void @no_unused_non_csr_sgpr_for_fp_no_scratch_vgpr() #1 {
; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[4:5]
; MUBUF-NEXT: v_writelane_b32 v40, s30, 0
-; MUBUF-NEXT: v_mov_b32_e32 v0, 0
+; MUBUF-NEXT: s_addk_i32 s32, 0x300
; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
+; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ;;#ASMEND
-; MUBUF-NEXT: s_addk_i32 s32, 0x300
; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; clobber nonpreserved initial VGPRs
@@ -1065,13 +1065,13 @@ define void @no_unused_non_csr_sgpr_for_fp_no_scratch_vgpr() #1 {
; FLATSCR-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[0:1]
; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0
-; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
+; FLATSCR-NEXT: s_add_i32 s32, s32, 12
; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
+; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: scratch_store_dword off, v0, s33
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ;;#ASMEND
-; FLATSCR-NEXT: s_add_i32 s32, s32, 12
; FLATSCR-NEXT: v_readlane_b32 s30, v40, 0
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; clobber nonpreserved initial VGPRs
@@ -1116,15 +1116,15 @@ define void @scratch_reg_needed_mubuf_offset(ptr addrspace(5) byval([4096 x i8])
; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s6 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[4:5]
; MUBUF-NEXT: v_writelane_b32 v40, s30, 0
+; MUBUF-NEXT: s_add_i32 s32, s32, 0x40300
+; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: v_mov_b32_e32 v1, 0x1000
-; MUBUF-NEXT: v_writelane_b32 v40, s31, 1
; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], s33 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; clobber nonpreserved SGPRs
; MUBUF-NEXT: ;;#ASMEND
-; MUBUF-NEXT: s_add_i32 s32, s32, 0x40300
; MUBUF-NEXT: v_readlane_b32 s30, v40, 0
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; clobber nonpreserved VGPRs
@@ -1148,11 +1148,11 @@ define void @scratch_reg_needed_mubuf_offset(ptr addrspace(5) byval([4096 x i8])
; FLATSCR-NEXT: s_add_i32 s2, s33, 0x1004
; FLATSCR-NEXT: scratch_store_dword off, v40, s2 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[0:1]
-; FLATSCR-NEXT: s_addk_i32 s32, 0x100c
; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0
+; FLATSCR-NEXT: s_addk_i32 s32, 0x100c
+; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: s_add_i32 s0, s33, 0x1000
-; FLATSCR-NEXT: v_writelane_b32 v40, s31, 1
; FLATSCR-NEXT: scratch_store_dword off, v0, s0
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: ;;#ASMSTART
@@ -1210,13 +1210,13 @@ define void @ipra_call_with_stack() #0 {
; MUBUF-NEXT: s_xor_saveexec_b64 s[16:17], -1
; MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[16:17]
-; MUBUF-NEXT: s_addk_i32 s32, 0x400
; MUBUF-NEXT: v_writelane_b32 v1, s30, 0
+; MUBUF-NEXT: s_addk_i32 s32, 0x400
+; MUBUF-NEXT: v_writelane_b32 v1, s31, 1
; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: s_getpc_b64 s[16:17]
; MUBUF-NEXT: s_add_u32 s16, s16, local_empty_func at rel32@lo+4
; MUBUF-NEXT: s_addc_u32 s17, s17, local_empty_func at rel32@hi+12
-; MUBUF-NEXT: v_writelane_b32 v1, s31, 1
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_swappc_b64 s[30:31], s[16:17]
@@ -1238,13 +1238,13 @@ define void @ipra_call_with_stack() #0 {
; FLATSCR-NEXT: s_xor_saveexec_b64 s[0:1], -1
; FLATSCR-NEXT: scratch_store_dword off, v1, s33 offset:4 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[0:1]
-; FLATSCR-NEXT: s_add_i32 s32, s32, 16
; FLATSCR-NEXT: v_writelane_b32 v1, s30, 0
+; FLATSCR-NEXT: s_add_i32 s32, s32, 16
+; FLATSCR-NEXT: v_writelane_b32 v1, s31, 1
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: s_getpc_b64 s[0:1]
; FLATSCR-NEXT: s_add_u32 s0, s0, local_empty_func at rel32@lo+4
; FLATSCR-NEXT: s_addc_u32 s1, s1, local_empty_func at rel32@hi+12
-; FLATSCR-NEXT: v_writelane_b32 v1, s31, 1
; FLATSCR-NEXT: scratch_store_dword off, v0, s33
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -1319,6 +1319,7 @@ define void @callee_need_to_spill_fp_to_memory_full_reserved_vgpr() #3 {
; MUBUF-NEXT: buffer_store_dword v39, off, s[0:3], s33 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[6:7]
; MUBUF-NEXT: v_writelane_b32 v39, s4, 32
+; MUBUF-NEXT: s_addk_i32 s32, 0x200
; MUBUF-NEXT: v_writelane_b32 v39, s39, 0
; MUBUF-NEXT: v_writelane_b32 v39, s48, 1
; MUBUF-NEXT: v_writelane_b32 v39, s49, 2
@@ -1350,7 +1351,6 @@ define void @callee_need_to_spill_fp_to_memory_full_reserved_vgpr() #3 {
; MUBUF-NEXT: v_writelane_b32 v39, s99, 28
; MUBUF-NEXT: v_writelane_b32 v39, s100, 29
; MUBUF-NEXT: v_writelane_b32 v39, s101, 30
-; MUBUF-NEXT: s_addk_i32 s32, 0x200
; MUBUF-NEXT: v_writelane_b32 v39, s102, 31
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; clobber nonpreserved SGPRs and 64 CSRs
@@ -1407,6 +1407,7 @@ define void @callee_need_to_spill_fp_to_memory_full_reserved_vgpr() #3 {
; FLATSCR-NEXT: s_xor_saveexec_b64 s[2:3], -1
; FLATSCR-NEXT: scratch_store_dword off, v39, s33 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
+; FLATSCR-NEXT: s_add_i32 s32, s32, 8
; FLATSCR-NEXT: v_writelane_b32 v39, s39, 0
; FLATSCR-NEXT: v_writelane_b32 v39, s48, 1
; FLATSCR-NEXT: v_writelane_b32 v39, s49, 2
@@ -1438,7 +1439,6 @@ define void @callee_need_to_spill_fp_to_memory_full_reserved_vgpr() #3 {
; FLATSCR-NEXT: v_writelane_b32 v39, s99, 28
; FLATSCR-NEXT: v_writelane_b32 v39, s100, 29
; FLATSCR-NEXT: v_writelane_b32 v39, s101, 30
-; FLATSCR-NEXT: s_add_i32 s32, s32, 8
; FLATSCR-NEXT: v_writelane_b32 v39, s102, 31
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; clobber nonpreserved SGPRs and 64 CSRs
@@ -1519,6 +1519,7 @@ define void @callee_need_to_spill_fp_to_reg() #1 {
; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[6:7]
; MUBUF-NEXT: v_writelane_b32 v40, s4, 32
+; MUBUF-NEXT: s_addk_i32 s32, 0x200
; MUBUF-NEXT: v_writelane_b32 v40, s39, 0
; MUBUF-NEXT: v_writelane_b32 v40, s48, 1
; MUBUF-NEXT: v_writelane_b32 v40, s49, 2
@@ -1550,7 +1551,6 @@ define void @callee_need_to_spill_fp_to_reg() #1 {
; MUBUF-NEXT: v_writelane_b32 v40, s99, 28
; MUBUF-NEXT: v_writelane_b32 v40, s100, 29
; MUBUF-NEXT: v_writelane_b32 v40, s101, 30
-; MUBUF-NEXT: s_addk_i32 s32, 0x200
; MUBUF-NEXT: v_writelane_b32 v40, s102, 31
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ; clobber nonpreserved SGPRs and 64 CSRs
@@ -1607,6 +1607,7 @@ define void @callee_need_to_spill_fp_to_reg() #1 {
; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1
; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
+; FLATSCR-NEXT: s_add_i32 s32, s32, 8
; FLATSCR-NEXT: v_writelane_b32 v40, s39, 0
; FLATSCR-NEXT: v_writelane_b32 v40, s48, 1
; FLATSCR-NEXT: v_writelane_b32 v40, s49, 2
@@ -1638,7 +1639,6 @@ define void @callee_need_to_spill_fp_to_reg() #1 {
; FLATSCR-NEXT: v_writelane_b32 v40, s99, 28
; FLATSCR-NEXT: v_writelane_b32 v40, s100, 29
; FLATSCR-NEXT: v_writelane_b32 v40, s101, 30
-; FLATSCR-NEXT: s_add_i32 s32, s32, 8
; FLATSCR-NEXT: v_writelane_b32 v40, s102, 31
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ; clobber nonpreserved SGPRs and 64 CSRs
@@ -1718,6 +1718,7 @@ define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset(ptr addrspace(5)
; MUBUF-NEXT: buffer_store_dword v39, off, s[0:3], s5 ; 4-byte Folded Spill
; MUBUF-NEXT: s_mov_b64 exec, s[6:7]
; MUBUF-NEXT: v_writelane_b32 v39, s4, 32
+; MUBUF-NEXT: s_add_i32 s32, s32, 0x40300
; MUBUF-NEXT: v_writelane_b32 v39, s39, 0
; MUBUF-NEXT: v_writelane_b32 v39, s48, 1
; MUBUF-NEXT: v_writelane_b32 v39, s49, 2
@@ -1749,10 +1750,9 @@ define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset(ptr addrspace(5)
; MUBUF-NEXT: v_writelane_b32 v39, s99, 28
; MUBUF-NEXT: v_writelane_b32 v39, s100, 29
; MUBUF-NEXT: v_writelane_b32 v39, s101, 30
+; MUBUF-NEXT: v_writelane_b32 v39, s102, 31
; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: v_mov_b32_e32 v1, 0x1000
-; MUBUF-NEXT: s_add_i32 s32, s32, 0x40300
-; MUBUF-NEXT: v_writelane_b32 v39, s102, 31
; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], s33 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: ;;#ASMSTART
@@ -1812,6 +1812,7 @@ define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset(ptr addrspace(5)
; FLATSCR-NEXT: s_add_i32 s1, s33, 0x1004
; FLATSCR-NEXT: scratch_store_dword off, v39, s1 ; 4-byte Folded Spill
; FLATSCR-NEXT: s_mov_b64 exec, s[2:3]
+; FLATSCR-NEXT: s_addk_i32 s32, 0x100c
; FLATSCR-NEXT: v_writelane_b32 v39, s39, 0
; FLATSCR-NEXT: v_writelane_b32 v39, s48, 1
; FLATSCR-NEXT: v_writelane_b32 v39, s49, 2
@@ -1841,12 +1842,11 @@ define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset(ptr addrspace(5)
; FLATSCR-NEXT: v_writelane_b32 v39, s97, 26
; FLATSCR-NEXT: v_writelane_b32 v39, s98, 27
; FLATSCR-NEXT: v_writelane_b32 v39, s99, 28
-; FLATSCR-NEXT: s_addk_i32 s32, 0x100c
; FLATSCR-NEXT: v_writelane_b32 v39, s100, 29
; FLATSCR-NEXT: v_writelane_b32 v39, s101, 30
+; FLATSCR-NEXT: v_writelane_b32 v39, s102, 31
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: s_add_i32 s1, s33, 0x1000
-; FLATSCR-NEXT: v_writelane_b32 v39, s102, 31
; FLATSCR-NEXT: scratch_store_dword off, v0, s1
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
index ce2ce4380d3b7..7abde5b74367d 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
@@ -420,14 +420,14 @@ define void @func_indirect_use_workitem_id_x() #1 {
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[6:7]
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s4, 2
+; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_x at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_x at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GCN-NEXT: v_readlane_b32 s30, v40, 0
@@ -453,14 +453,14 @@ define void @func_indirect_use_workitem_id_y() #1 {
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[6:7]
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s4, 2
+; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_y at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_y at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GCN-NEXT: v_readlane_b32 s30, v40, 0
@@ -486,14 +486,14 @@ define void @func_indirect_use_workitem_id_z() #1 {
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[6:7]
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s4, 2
+; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_z at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_z at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GCN-NEXT: v_readlane_b32 s30, v40, 0
@@ -939,8 +939,10 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
; GFX7-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[6:7]
-; GFX7-NEXT: s_addk_i32 s32, 0x400
; GFX7-NEXT: v_writelane_b32 v40, s4, 2
+; GFX7-NEXT: v_writelane_b32 v40, s30, 0
+; GFX7-NEXT: s_addk_i32 s32, 0x400
+; GFX7-NEXT: v_writelane_b32 v40, s31, 1
; GFX7-NEXT: s_getpc_b64 s[4:5]
; GFX7-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x at gotpcrel32@lo+4
; GFX7-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x at gotpcrel32@hi+12
@@ -948,7 +950,6 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
; GFX7-NEXT: flat_store_dword v[0:1], v0
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, 0x140
-; GFX7-NEXT: v_writelane_b32 v40, s30, 0
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX7-NEXT: v_mov_b32_e32 v0, 10
; GFX7-NEXT: v_mov_b32_e32 v1, 20
@@ -981,7 +982,6 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
; GFX7-NEXT: v_mov_b32_e32 v28, 0x122
; GFX7-NEXT: v_mov_b32_e32 v29, 0x12c
; GFX7-NEXT: v_mov_b32_e32 v30, 0x136
-; GFX7-NEXT: v_writelane_b32 v40, s31, 1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX7-NEXT: v_readlane_b32 s30, v40, 0
@@ -1003,8 +1003,10 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
; GFX90A-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX90A-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[6:7]
-; GFX90A-NEXT: s_addk_i32 s32, 0x400
; GFX90A-NEXT: v_writelane_b32 v40, s4, 2
+; GFX90A-NEXT: v_writelane_b32 v40, s30, 0
+; GFX90A-NEXT: s_addk_i32 s32, 0x400
+; GFX90A-NEXT: v_writelane_b32 v40, s31, 1
; GFX90A-NEXT: s_getpc_b64 s[4:5]
; GFX90A-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x at gotpcrel32@lo+4
; GFX90A-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x at gotpcrel32@hi+12
@@ -1012,7 +1014,6 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
; GFX90A-NEXT: global_store_dword v[0:1], v0, off
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_mov_b32_e32 v0, 0x140
-; GFX90A-NEXT: v_writelane_b32 v40, s30, 0
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX90A-NEXT: v_mov_b32_e32 v0, 10
; GFX90A-NEXT: v_mov_b32_e32 v1, 20
@@ -1045,7 +1046,6 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
; GFX90A-NEXT: v_mov_b32_e32 v28, 0x122
; GFX90A-NEXT: v_mov_b32_e32 v29, 0x12c
; GFX90A-NEXT: v_mov_b32_e32 v30, 0x136
-; GFX90A-NEXT: v_writelane_b32 v40, s31, 1
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX90A-NEXT: v_readlane_b32 s30, v40, 0
@@ -1081,15 +1081,15 @@ define void @too_many_args_call_too_many_args_use_workitem_id_x(
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[6:7]
-; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s33
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s4, 2
+; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
+; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s33
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s32
; GCN-NEXT: s_waitcnt lgkmcnt(0)
@@ -1396,19 +1396,20 @@ define void @func_call_too_many_args_use_workitem_id_x_byval() #1 {
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[6:7]
-; GCN-NEXT: v_mov_b32_e32 v0, 0x3e7
+; GCN-NEXT: v_writelane_b32 v40, s4, 2
+; GCN-NEXT: v_writelane_b32 v40, s30, 0
; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
+; GCN-NEXT: v_mov_b32_e32 v0, 0x3e7
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, 0x140
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33
-; GCN-NEXT: v_writelane_b32 v40, s4, 2
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x_byval at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x_byval at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
; GCN-NEXT: v_mov_b32_e32 v1, 20
; GCN-NEXT: v_mov_b32_e32 v2, 30
; GCN-NEXT: v_mov_b32_e32 v3, 40
@@ -1439,7 +1440,6 @@ define void @func_call_too_many_args_use_workitem_id_x_byval() #1 {
; GCN-NEXT: v_mov_b32_e32 v28, 0x122
; GCN-NEXT: v_mov_b32_e32 v29, 0x12c
; GCN-NEXT: v_mov_b32_e32 v30, 0x136
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4
; GCN-NEXT: v_mov_b32_e32 v0, 10
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
index f20be656f3af0..718140f82887e 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
@@ -265,14 +265,14 @@ define void @func_indirect_use_workitem_id_x() #1 {
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[6:7]
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s4, 2
+; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_x at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_x at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GCN-NEXT: v_readlane_b32 s30, v40, 0
@@ -298,14 +298,14 @@ define void @func_indirect_use_workitem_id_y() #1 {
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[6:7]
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s4, 2
+; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_y at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_y at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GCN-NEXT: v_readlane_b32 s30, v40, 0
@@ -331,14 +331,14 @@ define void @func_indirect_use_workitem_id_z() #1 {
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[6:7]
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s4, 2
+; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_z at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_z at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GCN-NEXT: v_readlane_b32 s30, v40, 0
@@ -651,8 +651,10 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[6:7]
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s4, 2
+; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x at gotpcrel32@hi+12
@@ -660,7 +662,6 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
; GCN-NEXT: flat_store_dword v[0:1], v0
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, 0x140
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GCN-NEXT: v_mov_b32_e32 v0, 10
; GCN-NEXT: v_mov_b32_e32 v1, 20
@@ -693,7 +694,6 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
; GCN-NEXT: v_mov_b32_e32 v28, 0x122
; GCN-NEXT: v_mov_b32_e32 v29, 0x12c
; GCN-NEXT: v_mov_b32_e32 v30, 0x136
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GCN-NEXT: v_readlane_b32 s30, v40, 0
@@ -729,15 +729,15 @@ define void @too_many_args_call_too_many_args_use_workitem_id_x(
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[6:7]
-; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s33
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s4, 2
+; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
+; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s33
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s32
; GCN-NEXT: s_waitcnt lgkmcnt(0)
@@ -970,19 +970,20 @@ define void @func_call_too_many_args_use_workitem_id_x_byval() #1 {
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[6:7]
-; GCN-NEXT: v_mov_b32_e32 v0, 0x3e7
+; GCN-NEXT: v_writelane_b32 v40, s4, 2
+; GCN-NEXT: v_writelane_b32 v40, s30, 0
; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
+; GCN-NEXT: v_mov_b32_e32 v0, 0x3e7
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, 0x140
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33
-; GCN-NEXT: v_writelane_b32 v40, s4, 2
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x_byval at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x_byval at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
; GCN-NEXT: v_mov_b32_e32 v1, 20
; GCN-NEXT: v_mov_b32_e32 v2, 30
; GCN-NEXT: v_mov_b32_e32 v3, 40
@@ -1013,7 +1014,6 @@ define void @func_call_too_many_args_use_workitem_id_x_byval() #1 {
; GCN-NEXT: v_mov_b32_e32 v28, 0x122
; GCN-NEXT: v_mov_b32_e32 v29, 0x12c
; GCN-NEXT: v_mov_b32_e32 v30, 0x136
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4
; GCN-NEXT: v_mov_b32_e32 v0, 10
@@ -1461,13 +1461,13 @@ define void @func_call_no_workitem_id_hints() #2 {
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[18:19]
; GCN-NEXT: v_writelane_b32 v40, s16, 2
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_getpc_b64 s[16:17]
; GCN-NEXT: s_add_u32 s16, s16, extern_hint at rel32@lo+4
; GCN-NEXT: s_addc_u32 s17, s17, extern_hint at rel32@hi+12
; GCN-NEXT: v_mov_b32_e32 v0, 9
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: v_readlane_b32 s30, v40, 0
; GCN-NEXT: v_readlane_b32 s31, v40, 1
diff --git a/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll b/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
index 0cab17c9bfcfc..9335cc304c294 100644
--- a/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
+++ b/llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
@@ -33,12 +33,12 @@ define float @call_split_type_used_outside_block_v2f32() #0 {
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[18:19]
; GCN-NEXT: v_writelane_b32 v40, s16, 2
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_getpc_b64 s[16:17]
; GCN-NEXT: s_add_u32 s16, s16, func_v2f32 at rel32@lo+4
; GCN-NEXT: s_addc_u32 s17, s17, func_v2f32 at rel32@hi+12
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: v_readlane_b32 s30, v40, 0
; GCN-NEXT: v_readlane_b32 s31, v40, 1
@@ -69,12 +69,12 @@ define float @call_split_type_used_outside_block_v3f32() #0 {
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[18:19]
; GCN-NEXT: v_writelane_b32 v40, s16, 2
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_getpc_b64 s[16:17]
; GCN-NEXT: s_add_u32 s16, s16, func_v3f32 at rel32@lo+4
; GCN-NEXT: s_addc_u32 s17, s17, func_v3f32 at rel32@hi+12
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: v_readlane_b32 s30, v40, 0
; GCN-NEXT: v_readlane_b32 s31, v40, 1
@@ -105,12 +105,12 @@ define half @call_split_type_used_outside_block_v4f16() #0 {
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[18:19]
; GCN-NEXT: v_writelane_b32 v40, s16, 2
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_getpc_b64 s[16:17]
; GCN-NEXT: s_add_u32 s16, s16, func_v4f16 at rel32@lo+4
; GCN-NEXT: s_addc_u32 s17, s17, func_v4f16 at rel32@hi+12
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: v_readlane_b32 s30, v40, 0
; GCN-NEXT: v_readlane_b32 s31, v40, 1
@@ -141,12 +141,12 @@ define { i32, half } @call_split_type_used_outside_block_struct() #0 {
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[18:19]
; GCN-NEXT: v_writelane_b32 v40, s16, 2
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_getpc_b64 s[16:17]
; GCN-NEXT: s_add_u32 s16, s16, func_struct at rel32@lo+4
; GCN-NEXT: s_addc_u32 s17, s17, func_struct at rel32@hi+12
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: v_readlane_b32 s30, v40, 0
; GCN-NEXT: v_readlane_b32 s31, v40, 1
diff --git a/llvm/test/CodeGen/AMDGPU/debug-frame.ll b/llvm/test/CodeGen/AMDGPU/debug-frame.ll
index 7d38cea998256..c3c93c1b606ec 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-frame.ll
+++ b/llvm/test/CodeGen/AMDGPU/debug-frame.ll
@@ -212,118 +212,231 @@ define void @callee_need_to_spill_fp_to_memory() #1 {
; GFX900-NEXT: .cfi_register 65, 72
; GFX900-NEXT: s_mov_b32 s33, s32
; GFX900-NEXT: .cfi_def_cfa_register 65
+; GFX900-NEXT: s_addk_i32 s32, 0x7100
; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:444 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 28416
; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:440 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2601, 32, 17, 64, 28160
; GFX900-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:436 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2602, 32, 17, 64, 27904
; GFX900-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:432 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2603, 32, 17, 64, 27648
; GFX900-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:428 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2604, 32, 17, 64, 27392
; GFX900-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:424 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2605, 32, 17, 64, 27136
; GFX900-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:420 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2606, 32, 17, 64, 26880
; GFX900-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:416 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2607, 32, 17, 64, 26624
; GFX900-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:412 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2616, 32, 17, 64, 26368
; GFX900-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:408 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2617, 32, 17, 64, 26112
; GFX900-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:404 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2618, 32, 17, 64, 25856
; GFX900-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:400 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2619, 32, 17, 64, 25600
; GFX900-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:396 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2620, 32, 17, 64, 25344
; GFX900-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:392 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2621, 32, 17, 64, 25088
; GFX900-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:388 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2622, 32, 17, 64, 24832
; GFX900-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:384 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2623, 32, 17, 64, 24576
; GFX900-NEXT: buffer_store_dword v72, off, s[0:3], s33 offset:380 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2632, 32, 17, 64, 24320
; GFX900-NEXT: buffer_store_dword v73, off, s[0:3], s33 offset:376 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2633, 32, 17, 64, 24064
; GFX900-NEXT: buffer_store_dword v74, off, s[0:3], s33 offset:372 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2634, 32, 17, 64, 23808
; GFX900-NEXT: buffer_store_dword v75, off, s[0:3], s33 offset:368 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2635, 32, 17, 64, 23552
; GFX900-NEXT: buffer_store_dword v76, off, s[0:3], s33 offset:364 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2636, 32, 17, 64, 23296
; GFX900-NEXT: buffer_store_dword v77, off, s[0:3], s33 offset:360 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2637, 32, 17, 64, 23040
; GFX900-NEXT: buffer_store_dword v78, off, s[0:3], s33 offset:356 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2638, 32, 17, 64, 22784
; GFX900-NEXT: buffer_store_dword v79, off, s[0:3], s33 offset:352 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2639, 32, 17, 64, 22528
; GFX900-NEXT: buffer_store_dword v88, off, s[0:3], s33 offset:348 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2648, 32, 17, 64, 22272
; GFX900-NEXT: buffer_store_dword v89, off, s[0:3], s33 offset:344 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2649, 32, 17, 64, 22016
; GFX900-NEXT: buffer_store_dword v90, off, s[0:3], s33 offset:340 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2650, 32, 17, 64, 21760
; GFX900-NEXT: buffer_store_dword v91, off, s[0:3], s33 offset:336 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2651, 32, 17, 64, 21504
; GFX900-NEXT: buffer_store_dword v92, off, s[0:3], s33 offset:332 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2652, 32, 17, 64, 21248
; GFX900-NEXT: buffer_store_dword v93, off, s[0:3], s33 offset:328 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2653, 32, 17, 64, 20992
; GFX900-NEXT: buffer_store_dword v94, off, s[0:3], s33 offset:324 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2654, 32, 17, 64, 20736
; GFX900-NEXT: buffer_store_dword v95, off, s[0:3], s33 offset:320 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2655, 32, 17, 64, 20480
; GFX900-NEXT: buffer_store_dword v104, off, s[0:3], s33 offset:316 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2664, 32, 17, 64, 20224
; GFX900-NEXT: buffer_store_dword v105, off, s[0:3], s33 offset:312 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2665, 32, 17, 64, 19968
; GFX900-NEXT: buffer_store_dword v106, off, s[0:3], s33 offset:308 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2666, 32, 17, 64, 19712
; GFX900-NEXT: buffer_store_dword v107, off, s[0:3], s33 offset:304 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2667, 32, 17, 64, 19456
; GFX900-NEXT: buffer_store_dword v108, off, s[0:3], s33 offset:300 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2668, 32, 17, 64, 19200
; GFX900-NEXT: buffer_store_dword v109, off, s[0:3], s33 offset:296 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2669, 32, 17, 64, 18944
; GFX900-NEXT: buffer_store_dword v110, off, s[0:3], s33 offset:292 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2670, 32, 17, 64, 18688
; GFX900-NEXT: buffer_store_dword v111, off, s[0:3], s33 offset:288 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2671, 32, 17, 64, 18432
; GFX900-NEXT: buffer_store_dword v120, off, s[0:3], s33 offset:284 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2680, 32, 17, 64, 18176
; GFX900-NEXT: buffer_store_dword v121, off, s[0:3], s33 offset:280 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2681, 32, 17, 64, 17920
; GFX900-NEXT: buffer_store_dword v122, off, s[0:3], s33 offset:276 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2682, 32, 17, 64, 17664
; GFX900-NEXT: buffer_store_dword v123, off, s[0:3], s33 offset:272 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2683, 32, 17, 64, 17408
; GFX900-NEXT: buffer_store_dword v124, off, s[0:3], s33 offset:268 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2684, 32, 17, 64, 17152
; GFX900-NEXT: buffer_store_dword v125, off, s[0:3], s33 offset:264 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2685, 32, 17, 64, 16896
; GFX900-NEXT: buffer_store_dword v126, off, s[0:3], s33 offset:260 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2686, 32, 17, 64, 16640
; GFX900-NEXT: buffer_store_dword v127, off, s[0:3], s33 offset:256 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2687, 32, 17, 64, 16384
; GFX900-NEXT: buffer_store_dword v136, off, s[0:3], s33 offset:252 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2696, 32, 17, 64, 16128
; GFX900-NEXT: buffer_store_dword v137, off, s[0:3], s33 offset:248 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2697, 32, 17, 64, 15872
; GFX900-NEXT: buffer_store_dword v138, off, s[0:3], s33 offset:244 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2698, 32, 17, 64, 15616
; GFX900-NEXT: buffer_store_dword v139, off, s[0:3], s33 offset:240 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2699, 32, 17, 64, 15360
; GFX900-NEXT: buffer_store_dword v140, off, s[0:3], s33 offset:236 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2700, 32, 17, 64, 15104
; GFX900-NEXT: buffer_store_dword v141, off, s[0:3], s33 offset:232 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2701, 32, 17, 64, 14848
; GFX900-NEXT: buffer_store_dword v142, off, s[0:3], s33 offset:228 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2702, 32, 17, 64, 14592
; GFX900-NEXT: buffer_store_dword v143, off, s[0:3], s33 offset:224 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2703, 32, 17, 64, 14336
; GFX900-NEXT: buffer_store_dword v152, off, s[0:3], s33 offset:220 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2712, 32, 17, 64, 14080
; GFX900-NEXT: buffer_store_dword v153, off, s[0:3], s33 offset:216 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2713, 32, 17, 64, 13824
; GFX900-NEXT: buffer_store_dword v154, off, s[0:3], s33 offset:212 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2714, 32, 17, 64, 13568
; GFX900-NEXT: buffer_store_dword v155, off, s[0:3], s33 offset:208 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2715, 32, 17, 64, 13312
; GFX900-NEXT: buffer_store_dword v156, off, s[0:3], s33 offset:204 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2716, 32, 17, 64, 13056
; GFX900-NEXT: buffer_store_dword v157, off, s[0:3], s33 offset:200 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2717, 32, 17, 64, 12800
; GFX900-NEXT: buffer_store_dword v158, off, s[0:3], s33 offset:196 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2718, 32, 17, 64, 12544
; GFX900-NEXT: buffer_store_dword v159, off, s[0:3], s33 offset:192 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2719, 32, 17, 64, 12288
; GFX900-NEXT: buffer_store_dword v168, off, s[0:3], s33 offset:188 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2728, 32, 17, 64, 12032
; GFX900-NEXT: buffer_store_dword v169, off, s[0:3], s33 offset:184 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2729, 32, 17, 64, 11776
; GFX900-NEXT: buffer_store_dword v170, off, s[0:3], s33 offset:180 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2730, 32, 17, 64, 11520
; GFX900-NEXT: buffer_store_dword v171, off, s[0:3], s33 offset:176 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2731, 32, 17, 64, 11264
; GFX900-NEXT: buffer_store_dword v172, off, s[0:3], s33 offset:172 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2732, 32, 17, 64, 11008
; GFX900-NEXT: buffer_store_dword v173, off, s[0:3], s33 offset:168 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2733, 32, 17, 64, 10752
; GFX900-NEXT: buffer_store_dword v174, off, s[0:3], s33 offset:164 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2734, 32, 17, 64, 10496
; GFX900-NEXT: buffer_store_dword v175, off, s[0:3], s33 offset:160 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2735, 32, 17, 64, 10240
; GFX900-NEXT: buffer_store_dword v184, off, s[0:3], s33 offset:156 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2744, 32, 17, 64, 9984
; GFX900-NEXT: buffer_store_dword v185, off, s[0:3], s33 offset:152 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2745, 32, 17, 64, 9728
; GFX900-NEXT: buffer_store_dword v186, off, s[0:3], s33 offset:148 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2746, 32, 17, 64, 9472
; GFX900-NEXT: buffer_store_dword v187, off, s[0:3], s33 offset:144 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2747, 32, 17, 64, 9216
; GFX900-NEXT: buffer_store_dword v188, off, s[0:3], s33 offset:140 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2748, 32, 17, 64, 8960
; GFX900-NEXT: buffer_store_dword v189, off, s[0:3], s33 offset:136 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2749, 32, 17, 64, 8704
; GFX900-NEXT: buffer_store_dword v190, off, s[0:3], s33 offset:132 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2750, 32, 17, 64, 8448
; GFX900-NEXT: buffer_store_dword v191, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2751, 32, 17, 64, 8192
; GFX900-NEXT: buffer_store_dword v200, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2760, 32, 17, 64, 7936
; GFX900-NEXT: buffer_store_dword v201, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2761, 32, 17, 64, 7680
; GFX900-NEXT: buffer_store_dword v202, off, s[0:3], s33 offset:116 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2762, 32, 17, 64, 7424
; GFX900-NEXT: buffer_store_dword v203, off, s[0:3], s33 offset:112 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2763, 32, 17, 64, 7168
; GFX900-NEXT: buffer_store_dword v204, off, s[0:3], s33 offset:108 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2764, 32, 17, 64, 6912
; GFX900-NEXT: buffer_store_dword v205, off, s[0:3], s33 offset:104 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2765, 32, 17, 64, 6656
; GFX900-NEXT: buffer_store_dword v206, off, s[0:3], s33 offset:100 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2766, 32, 17, 64, 6400
; GFX900-NEXT: buffer_store_dword v207, off, s[0:3], s33 offset:96 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2767, 32, 17, 64, 6144
; GFX900-NEXT: buffer_store_dword v216, off, s[0:3], s33 offset:92 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2776, 32, 17, 64, 5888
; GFX900-NEXT: buffer_store_dword v217, off, s[0:3], s33 offset:88 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2777, 32, 17, 64, 5632
; GFX900-NEXT: buffer_store_dword v218, off, s[0:3], s33 offset:84 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2778, 32, 17, 64, 5376
; GFX900-NEXT: buffer_store_dword v219, off, s[0:3], s33 offset:80 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2779, 32, 17, 64, 5120
; GFX900-NEXT: buffer_store_dword v220, off, s[0:3], s33 offset:76 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2780, 32, 17, 64, 4864
; GFX900-NEXT: buffer_store_dword v221, off, s[0:3], s33 offset:72 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2781, 32, 17, 64, 4608
; GFX900-NEXT: buffer_store_dword v222, off, s[0:3], s33 offset:68 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2782, 32, 17, 64, 4352
; GFX900-NEXT: buffer_store_dword v223, off, s[0:3], s33 offset:64 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2783, 32, 17, 64, 4096
; GFX900-NEXT: buffer_store_dword v232, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2792, 32, 17, 64, 3840
; GFX900-NEXT: buffer_store_dword v233, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2793, 32, 17, 64, 3584
; GFX900-NEXT: buffer_store_dword v234, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2794, 32, 17, 64, 3328
; GFX900-NEXT: buffer_store_dword v235, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2795, 32, 17, 64, 3072
; GFX900-NEXT: buffer_store_dword v236, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2796, 32, 17, 64, 2816
; GFX900-NEXT: buffer_store_dword v237, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2797, 32, 17, 64, 2560
; GFX900-NEXT: buffer_store_dword v238, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2798, 32, 17, 64, 2304
; GFX900-NEXT: buffer_store_dword v239, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2799, 32, 17, 64, 2048
; GFX900-NEXT: buffer_store_dword v248, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2808, 32, 17, 64, 1792
; GFX900-NEXT: buffer_store_dword v249, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2809, 32, 17, 64, 1536
; GFX900-NEXT: buffer_store_dword v250, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2810, 32, 17, 64, 1280
; GFX900-NEXT: buffer_store_dword v251, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2811, 32, 17, 64, 1024
; GFX900-NEXT: buffer_store_dword v252, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2812, 32, 17, 64, 768
; GFX900-NEXT: buffer_store_dword v253, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2813, 32, 17, 64, 512
; GFX900-NEXT: buffer_store_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2814, 32, 17, 64, 256
; GFX900-NEXT: buffer_store_dword v255, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2815, 32, 17, 64, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; clobber nonpreserved SGPRs
; GFX900-NEXT: ;;#ASMEND
@@ -442,7 +555,6 @@ define void @callee_need_to_spill_fp_to_memory() #1 {
; GFX900-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:436 ; 4-byte Folded Reload
; GFX900-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:440 ; 4-byte Folded Reload
; GFX900-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:444 ; 4-byte Folded Reload
-; GFX900-NEXT: s_addk_i32 s32, 0x7100
; GFX900-NEXT: s_mov_b32 s32, s33
; GFX900-NEXT: .cfi_def_cfa_register 64
; GFX900-NEXT: s_mov_b32 s33, s40
@@ -630,118 +742,231 @@ define void @callee_need_to_spill_fp_to_memory() #1 {
; GFX90A-V2A-DIS-NEXT: .cfi_register 65, 72
; GFX90A-V2A-DIS-NEXT: s_mov_b32 s33, s32
; GFX90A-V2A-DIS-NEXT: .cfi_def_cfa_register 65
+; GFX90A-V2A-DIS-NEXT: s_addk_i32 s32, 0x7100
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:444 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 28416
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:440 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2601, 32, 17, 64, 28160
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:436 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2602, 32, 17, 64, 27904
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:432 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2603, 32, 17, 64, 27648
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:428 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2604, 32, 17, 64, 27392
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:424 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2605, 32, 17, 64, 27136
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:420 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2606, 32, 17, 64, 26880
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:416 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2607, 32, 17, 64, 26624
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:412 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2616, 32, 17, 64, 26368
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:408 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2617, 32, 17, 64, 26112
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:404 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2618, 32, 17, 64, 25856
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:400 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2619, 32, 17, 64, 25600
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:396 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2620, 32, 17, 64, 25344
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:392 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2621, 32, 17, 64, 25088
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:388 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2622, 32, 17, 64, 24832
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:384 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2623, 32, 17, 64, 24576
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v72, off, s[0:3], s33 offset:380 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2632, 32, 17, 64, 24320
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v73, off, s[0:3], s33 offset:376 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2633, 32, 17, 64, 24064
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v74, off, s[0:3], s33 offset:372 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2634, 32, 17, 64, 23808
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v75, off, s[0:3], s33 offset:368 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2635, 32, 17, 64, 23552
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v76, off, s[0:3], s33 offset:364 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2636, 32, 17, 64, 23296
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v77, off, s[0:3], s33 offset:360 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2637, 32, 17, 64, 23040
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v78, off, s[0:3], s33 offset:356 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2638, 32, 17, 64, 22784
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v79, off, s[0:3], s33 offset:352 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2639, 32, 17, 64, 22528
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v88, off, s[0:3], s33 offset:348 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2648, 32, 17, 64, 22272
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v89, off, s[0:3], s33 offset:344 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2649, 32, 17, 64, 22016
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v90, off, s[0:3], s33 offset:340 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2650, 32, 17, 64, 21760
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v91, off, s[0:3], s33 offset:336 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2651, 32, 17, 64, 21504
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v92, off, s[0:3], s33 offset:332 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2652, 32, 17, 64, 21248
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v93, off, s[0:3], s33 offset:328 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2653, 32, 17, 64, 20992
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v94, off, s[0:3], s33 offset:324 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2654, 32, 17, 64, 20736
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v95, off, s[0:3], s33 offset:320 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2655, 32, 17, 64, 20480
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v104, off, s[0:3], s33 offset:316 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2664, 32, 17, 64, 20224
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v105, off, s[0:3], s33 offset:312 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2665, 32, 17, 64, 19968
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v106, off, s[0:3], s33 offset:308 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2666, 32, 17, 64, 19712
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v107, off, s[0:3], s33 offset:304 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2667, 32, 17, 64, 19456
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v108, off, s[0:3], s33 offset:300 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2668, 32, 17, 64, 19200
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v109, off, s[0:3], s33 offset:296 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2669, 32, 17, 64, 18944
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v110, off, s[0:3], s33 offset:292 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2670, 32, 17, 64, 18688
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v111, off, s[0:3], s33 offset:288 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2671, 32, 17, 64, 18432
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v120, off, s[0:3], s33 offset:284 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2680, 32, 17, 64, 18176
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v121, off, s[0:3], s33 offset:280 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2681, 32, 17, 64, 17920
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v122, off, s[0:3], s33 offset:276 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2682, 32, 17, 64, 17664
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v123, off, s[0:3], s33 offset:272 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2683, 32, 17, 64, 17408
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v124, off, s[0:3], s33 offset:268 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2684, 32, 17, 64, 17152
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v125, off, s[0:3], s33 offset:264 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2685, 32, 17, 64, 16896
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v126, off, s[0:3], s33 offset:260 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2686, 32, 17, 64, 16640
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v127, off, s[0:3], s33 offset:256 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2687, 32, 17, 64, 16384
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v136, off, s[0:3], s33 offset:252 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2696, 32, 17, 64, 16128
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v137, off, s[0:3], s33 offset:248 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2697, 32, 17, 64, 15872
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v138, off, s[0:3], s33 offset:244 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2698, 32, 17, 64, 15616
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v139, off, s[0:3], s33 offset:240 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2699, 32, 17, 64, 15360
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v140, off, s[0:3], s33 offset:236 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2700, 32, 17, 64, 15104
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v141, off, s[0:3], s33 offset:232 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2701, 32, 17, 64, 14848
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v142, off, s[0:3], s33 offset:228 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2702, 32, 17, 64, 14592
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v143, off, s[0:3], s33 offset:224 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2703, 32, 17, 64, 14336
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v152, off, s[0:3], s33 offset:220 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2712, 32, 17, 64, 14080
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v153, off, s[0:3], s33 offset:216 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2713, 32, 17, 64, 13824
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v154, off, s[0:3], s33 offset:212 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2714, 32, 17, 64, 13568
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v155, off, s[0:3], s33 offset:208 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2715, 32, 17, 64, 13312
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v156, off, s[0:3], s33 offset:204 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2716, 32, 17, 64, 13056
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v157, off, s[0:3], s33 offset:200 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2717, 32, 17, 64, 12800
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v158, off, s[0:3], s33 offset:196 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2718, 32, 17, 64, 12544
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v159, off, s[0:3], s33 offset:192 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2719, 32, 17, 64, 12288
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v168, off, s[0:3], s33 offset:188 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2728, 32, 17, 64, 12032
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v169, off, s[0:3], s33 offset:184 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2729, 32, 17, 64, 11776
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v170, off, s[0:3], s33 offset:180 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2730, 32, 17, 64, 11520
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v171, off, s[0:3], s33 offset:176 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2731, 32, 17, 64, 11264
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v172, off, s[0:3], s33 offset:172 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2732, 32, 17, 64, 11008
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v173, off, s[0:3], s33 offset:168 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2733, 32, 17, 64, 10752
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v174, off, s[0:3], s33 offset:164 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2734, 32, 17, 64, 10496
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v175, off, s[0:3], s33 offset:160 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2735, 32, 17, 64, 10240
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v184, off, s[0:3], s33 offset:156 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2744, 32, 17, 64, 9984
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v185, off, s[0:3], s33 offset:152 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2745, 32, 17, 64, 9728
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v186, off, s[0:3], s33 offset:148 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2746, 32, 17, 64, 9472
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v187, off, s[0:3], s33 offset:144 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2747, 32, 17, 64, 9216
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v188, off, s[0:3], s33 offset:140 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2748, 32, 17, 64, 8960
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v189, off, s[0:3], s33 offset:136 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2749, 32, 17, 64, 8704
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v190, off, s[0:3], s33 offset:132 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2750, 32, 17, 64, 8448
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v191, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2751, 32, 17, 64, 8192
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v200, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2760, 32, 17, 64, 7936
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v201, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2761, 32, 17, 64, 7680
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v202, off, s[0:3], s33 offset:116 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2762, 32, 17, 64, 7424
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v203, off, s[0:3], s33 offset:112 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2763, 32, 17, 64, 7168
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v204, off, s[0:3], s33 offset:108 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2764, 32, 17, 64, 6912
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v205, off, s[0:3], s33 offset:104 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2765, 32, 17, 64, 6656
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v206, off, s[0:3], s33 offset:100 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2766, 32, 17, 64, 6400
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v207, off, s[0:3], s33 offset:96 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2767, 32, 17, 64, 6144
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v216, off, s[0:3], s33 offset:92 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2776, 32, 17, 64, 5888
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v217, off, s[0:3], s33 offset:88 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2777, 32, 17, 64, 5632
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v218, off, s[0:3], s33 offset:84 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2778, 32, 17, 64, 5376
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v219, off, s[0:3], s33 offset:80 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2779, 32, 17, 64, 5120
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v220, off, s[0:3], s33 offset:76 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2780, 32, 17, 64, 4864
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v221, off, s[0:3], s33 offset:72 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2781, 32, 17, 64, 4608
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v222, off, s[0:3], s33 offset:68 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2782, 32, 17, 64, 4352
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v223, off, s[0:3], s33 offset:64 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2783, 32, 17, 64, 4096
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v232, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2792, 32, 17, 64, 3840
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v233, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2793, 32, 17, 64, 3584
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v234, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2794, 32, 17, 64, 3328
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v235, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2795, 32, 17, 64, 3072
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v236, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2796, 32, 17, 64, 2816
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v237, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2797, 32, 17, 64, 2560
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v238, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2798, 32, 17, 64, 2304
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v239, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2799, 32, 17, 64, 2048
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v248, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2808, 32, 17, 64, 1792
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v249, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2809, 32, 17, 64, 1536
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v250, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2810, 32, 17, 64, 1280
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v251, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2811, 32, 17, 64, 1024
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v252, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2812, 32, 17, 64, 768
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v253, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2813, 32, 17, 64, 512
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2814, 32, 17, 64, 256
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v255, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2815, 32, 17, 64, 0
; GFX90A-V2A-DIS-NEXT: ;;#ASMSTART
; GFX90A-V2A-DIS-NEXT: ; clobber nonpreserved SGPRs
; GFX90A-V2A-DIS-NEXT: ;;#ASMEND
@@ -860,7 +1085,6 @@ define void @callee_need_to_spill_fp_to_memory() #1 {
; GFX90A-V2A-DIS-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:436 ; 4-byte Folded Reload
; GFX90A-V2A-DIS-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:440 ; 4-byte Folded Reload
; GFX90A-V2A-DIS-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:444 ; 4-byte Folded Reload
-; GFX90A-V2A-DIS-NEXT: s_addk_i32 s32, 0x7100
; GFX90A-V2A-DIS-NEXT: s_mov_b32 s32, s33
; GFX90A-V2A-DIS-NEXT: .cfi_def_cfa_register 64
; GFX90A-V2A-DIS-NEXT: s_mov_b32 s33, s40
@@ -1080,118 +1304,231 @@ define void @callee_need_to_spill_fp_to_memory() #1 {
; GFX90A-V2A-EN-NEXT: .cfi_register 65, 72
; GFX90A-V2A-EN-NEXT: s_mov_b32 s33, s32
; GFX90A-V2A-EN-NEXT: .cfi_def_cfa_register 65
+; GFX90A-V2A-EN-NEXT: s_addk_i32 s32, 0x5100
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2600, 3072, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2601, 3073, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2602, 3074, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a3, v43 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2603, 3075, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a4, v44 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2604, 3076, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a5, v45 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2605, 3077, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a6, v46 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2606, 3078, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2607, 3079, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2616, 3080, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2617, 3081, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2618, 3082, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2619, 3083, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2620, 3084, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a13, v61 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2621, 3085, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a14, v62 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2622, 3086, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2623, 3087, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a16, v72 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2632, 3088, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a17, v73 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2633, 3089, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a18, v74 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2634, 3090, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a19, v75 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2635, 3091, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a20, v76 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2636, 3092, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a21, v77 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2637, 3093, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a22, v78 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2638, 3094, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a23, v79 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2639, 3095, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a24, v88 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2648, 3096, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a25, v89 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2649, 3097, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a26, v90 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2650, 3098, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a27, v91 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2651, 3099, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a28, v92 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2652, 3100, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a29, v93 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2653, 3101, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a30, v94 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2654, 3102, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a31, v95 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2655, 3103, 32, 17, 64
; GFX90A-V2A-EN-NEXT: buffer_store_dword v104, off, s[0:3], s33 offset:316 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2664, 32, 17, 64, 20224
; GFX90A-V2A-EN-NEXT: buffer_store_dword v105, off, s[0:3], s33 offset:312 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2665, 32, 17, 64, 19968
; GFX90A-V2A-EN-NEXT: buffer_store_dword v106, off, s[0:3], s33 offset:308 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2666, 32, 17, 64, 19712
; GFX90A-V2A-EN-NEXT: buffer_store_dword v107, off, s[0:3], s33 offset:304 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2667, 32, 17, 64, 19456
; GFX90A-V2A-EN-NEXT: buffer_store_dword v108, off, s[0:3], s33 offset:300 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2668, 32, 17, 64, 19200
; GFX90A-V2A-EN-NEXT: buffer_store_dword v109, off, s[0:3], s33 offset:296 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2669, 32, 17, 64, 18944
; GFX90A-V2A-EN-NEXT: buffer_store_dword v110, off, s[0:3], s33 offset:292 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2670, 32, 17, 64, 18688
; GFX90A-V2A-EN-NEXT: buffer_store_dword v111, off, s[0:3], s33 offset:288 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2671, 32, 17, 64, 18432
; GFX90A-V2A-EN-NEXT: buffer_store_dword v120, off, s[0:3], s33 offset:284 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2680, 32, 17, 64, 18176
; GFX90A-V2A-EN-NEXT: buffer_store_dword v121, off, s[0:3], s33 offset:280 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2681, 32, 17, 64, 17920
; GFX90A-V2A-EN-NEXT: buffer_store_dword v122, off, s[0:3], s33 offset:276 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2682, 32, 17, 64, 17664
; GFX90A-V2A-EN-NEXT: buffer_store_dword v123, off, s[0:3], s33 offset:272 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2683, 32, 17, 64, 17408
; GFX90A-V2A-EN-NEXT: buffer_store_dword v124, off, s[0:3], s33 offset:268 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2684, 32, 17, 64, 17152
; GFX90A-V2A-EN-NEXT: buffer_store_dword v125, off, s[0:3], s33 offset:264 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2685, 32, 17, 64, 16896
; GFX90A-V2A-EN-NEXT: buffer_store_dword v126, off, s[0:3], s33 offset:260 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2686, 32, 17, 64, 16640
; GFX90A-V2A-EN-NEXT: buffer_store_dword v127, off, s[0:3], s33 offset:256 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2687, 32, 17, 64, 16384
; GFX90A-V2A-EN-NEXT: buffer_store_dword v136, off, s[0:3], s33 offset:252 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2696, 32, 17, 64, 16128
; GFX90A-V2A-EN-NEXT: buffer_store_dword v137, off, s[0:3], s33 offset:248 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2697, 32, 17, 64, 15872
; GFX90A-V2A-EN-NEXT: buffer_store_dword v138, off, s[0:3], s33 offset:244 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2698, 32, 17, 64, 15616
; GFX90A-V2A-EN-NEXT: buffer_store_dword v139, off, s[0:3], s33 offset:240 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2699, 32, 17, 64, 15360
; GFX90A-V2A-EN-NEXT: buffer_store_dword v140, off, s[0:3], s33 offset:236 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2700, 32, 17, 64, 15104
; GFX90A-V2A-EN-NEXT: buffer_store_dword v141, off, s[0:3], s33 offset:232 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2701, 32, 17, 64, 14848
; GFX90A-V2A-EN-NEXT: buffer_store_dword v142, off, s[0:3], s33 offset:228 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2702, 32, 17, 64, 14592
; GFX90A-V2A-EN-NEXT: buffer_store_dword v143, off, s[0:3], s33 offset:224 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2703, 32, 17, 64, 14336
; GFX90A-V2A-EN-NEXT: buffer_store_dword v152, off, s[0:3], s33 offset:220 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2712, 32, 17, 64, 14080
; GFX90A-V2A-EN-NEXT: buffer_store_dword v153, off, s[0:3], s33 offset:216 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2713, 32, 17, 64, 13824
; GFX90A-V2A-EN-NEXT: buffer_store_dword v154, off, s[0:3], s33 offset:212 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2714, 32, 17, 64, 13568
; GFX90A-V2A-EN-NEXT: buffer_store_dword v155, off, s[0:3], s33 offset:208 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2715, 32, 17, 64, 13312
; GFX90A-V2A-EN-NEXT: buffer_store_dword v156, off, s[0:3], s33 offset:204 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2716, 32, 17, 64, 13056
; GFX90A-V2A-EN-NEXT: buffer_store_dword v157, off, s[0:3], s33 offset:200 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2717, 32, 17, 64, 12800
; GFX90A-V2A-EN-NEXT: buffer_store_dword v158, off, s[0:3], s33 offset:196 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2718, 32, 17, 64, 12544
; GFX90A-V2A-EN-NEXT: buffer_store_dword v159, off, s[0:3], s33 offset:192 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2719, 32, 17, 64, 12288
; GFX90A-V2A-EN-NEXT: buffer_store_dword v168, off, s[0:3], s33 offset:188 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2728, 32, 17, 64, 12032
; GFX90A-V2A-EN-NEXT: buffer_store_dword v169, off, s[0:3], s33 offset:184 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2729, 32, 17, 64, 11776
; GFX90A-V2A-EN-NEXT: buffer_store_dword v170, off, s[0:3], s33 offset:180 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2730, 32, 17, 64, 11520
; GFX90A-V2A-EN-NEXT: buffer_store_dword v171, off, s[0:3], s33 offset:176 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2731, 32, 17, 64, 11264
; GFX90A-V2A-EN-NEXT: buffer_store_dword v172, off, s[0:3], s33 offset:172 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2732, 32, 17, 64, 11008
; GFX90A-V2A-EN-NEXT: buffer_store_dword v173, off, s[0:3], s33 offset:168 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2733, 32, 17, 64, 10752
; GFX90A-V2A-EN-NEXT: buffer_store_dword v174, off, s[0:3], s33 offset:164 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2734, 32, 17, 64, 10496
; GFX90A-V2A-EN-NEXT: buffer_store_dword v175, off, s[0:3], s33 offset:160 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2735, 32, 17, 64, 10240
; GFX90A-V2A-EN-NEXT: buffer_store_dword v184, off, s[0:3], s33 offset:156 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2744, 32, 17, 64, 9984
; GFX90A-V2A-EN-NEXT: buffer_store_dword v185, off, s[0:3], s33 offset:152 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2745, 32, 17, 64, 9728
; GFX90A-V2A-EN-NEXT: buffer_store_dword v186, off, s[0:3], s33 offset:148 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2746, 32, 17, 64, 9472
; GFX90A-V2A-EN-NEXT: buffer_store_dword v187, off, s[0:3], s33 offset:144 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2747, 32, 17, 64, 9216
; GFX90A-V2A-EN-NEXT: buffer_store_dword v188, off, s[0:3], s33 offset:140 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2748, 32, 17, 64, 8960
; GFX90A-V2A-EN-NEXT: buffer_store_dword v189, off, s[0:3], s33 offset:136 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2749, 32, 17, 64, 8704
; GFX90A-V2A-EN-NEXT: buffer_store_dword v190, off, s[0:3], s33 offset:132 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2750, 32, 17, 64, 8448
; GFX90A-V2A-EN-NEXT: buffer_store_dword v191, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2751, 32, 17, 64, 8192
; GFX90A-V2A-EN-NEXT: buffer_store_dword v200, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2760, 32, 17, 64, 7936
; GFX90A-V2A-EN-NEXT: buffer_store_dword v201, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2761, 32, 17, 64, 7680
; GFX90A-V2A-EN-NEXT: buffer_store_dword v202, off, s[0:3], s33 offset:116 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2762, 32, 17, 64, 7424
; GFX90A-V2A-EN-NEXT: buffer_store_dword v203, off, s[0:3], s33 offset:112 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2763, 32, 17, 64, 7168
; GFX90A-V2A-EN-NEXT: buffer_store_dword v204, off, s[0:3], s33 offset:108 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2764, 32, 17, 64, 6912
; GFX90A-V2A-EN-NEXT: buffer_store_dword v205, off, s[0:3], s33 offset:104 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2765, 32, 17, 64, 6656
; GFX90A-V2A-EN-NEXT: buffer_store_dword v206, off, s[0:3], s33 offset:100 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2766, 32, 17, 64, 6400
; GFX90A-V2A-EN-NEXT: buffer_store_dword v207, off, s[0:3], s33 offset:96 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2767, 32, 17, 64, 6144
; GFX90A-V2A-EN-NEXT: buffer_store_dword v216, off, s[0:3], s33 offset:92 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2776, 32, 17, 64, 5888
; GFX90A-V2A-EN-NEXT: buffer_store_dword v217, off, s[0:3], s33 offset:88 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2777, 32, 17, 64, 5632
; GFX90A-V2A-EN-NEXT: buffer_store_dword v218, off, s[0:3], s33 offset:84 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2778, 32, 17, 64, 5376
; GFX90A-V2A-EN-NEXT: buffer_store_dword v219, off, s[0:3], s33 offset:80 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2779, 32, 17, 64, 5120
; GFX90A-V2A-EN-NEXT: buffer_store_dword v220, off, s[0:3], s33 offset:76 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2780, 32, 17, 64, 4864
; GFX90A-V2A-EN-NEXT: buffer_store_dword v221, off, s[0:3], s33 offset:72 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2781, 32, 17, 64, 4608
; GFX90A-V2A-EN-NEXT: buffer_store_dword v222, off, s[0:3], s33 offset:68 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2782, 32, 17, 64, 4352
; GFX90A-V2A-EN-NEXT: buffer_store_dword v223, off, s[0:3], s33 offset:64 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2783, 32, 17, 64, 4096
; GFX90A-V2A-EN-NEXT: buffer_store_dword v232, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2792, 32, 17, 64, 3840
; GFX90A-V2A-EN-NEXT: buffer_store_dword v233, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2793, 32, 17, 64, 3584
; GFX90A-V2A-EN-NEXT: buffer_store_dword v234, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2794, 32, 17, 64, 3328
; GFX90A-V2A-EN-NEXT: buffer_store_dword v235, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2795, 32, 17, 64, 3072
; GFX90A-V2A-EN-NEXT: buffer_store_dword v236, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2796, 32, 17, 64, 2816
; GFX90A-V2A-EN-NEXT: buffer_store_dword v237, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2797, 32, 17, 64, 2560
; GFX90A-V2A-EN-NEXT: buffer_store_dword v238, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2798, 32, 17, 64, 2304
; GFX90A-V2A-EN-NEXT: buffer_store_dword v239, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2799, 32, 17, 64, 2048
; GFX90A-V2A-EN-NEXT: buffer_store_dword v248, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2808, 32, 17, 64, 1792
; GFX90A-V2A-EN-NEXT: buffer_store_dword v249, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2809, 32, 17, 64, 1536
; GFX90A-V2A-EN-NEXT: buffer_store_dword v250, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2810, 32, 17, 64, 1280
; GFX90A-V2A-EN-NEXT: buffer_store_dword v251, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2811, 32, 17, 64, 1024
; GFX90A-V2A-EN-NEXT: buffer_store_dword v252, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2812, 32, 17, 64, 768
; GFX90A-V2A-EN-NEXT: buffer_store_dword v253, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2813, 32, 17, 64, 512
; GFX90A-V2A-EN-NEXT: buffer_store_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2814, 32, 17, 64, 256
; GFX90A-V2A-EN-NEXT: buffer_store_dword v255, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_offset 2815, 32, 17, 64, 0
; GFX90A-V2A-EN-NEXT: ;;#ASMSTART
; GFX90A-V2A-EN-NEXT: ; clobber nonpreserved SGPRs
; GFX90A-V2A-EN-NEXT: ;;#ASMEND
@@ -1278,7 +1615,6 @@ define void @callee_need_to_spill_fp_to_memory() #1 {
; GFX90A-V2A-EN-NEXT: buffer_load_dword v106, off, s[0:3], s33 offset:308 ; 4-byte Folded Reload
; GFX90A-V2A-EN-NEXT: buffer_load_dword v105, off, s[0:3], s33 offset:312 ; 4-byte Folded Reload
; GFX90A-V2A-EN-NEXT: buffer_load_dword v104, off, s[0:3], s33 offset:316 ; 4-byte Folded Reload
-; GFX90A-V2A-EN-NEXT: s_addk_i32 s32, 0x5100
; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v95, a31 ; Reload Reuse
; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v94, a30 ; Reload Reuse
; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v93, a29 ; Reload Reuse
@@ -1498,118 +1834,231 @@ define void @callee_need_to_spill_fp_to_memory() #1 {
; WAVE32-NEXT: .cfi_register 65, 72
; WAVE32-NEXT: s_mov_b32 s33, s32
; WAVE32-NEXT: .cfi_def_cfa_register 65
+; WAVE32-NEXT: s_addk_i32 s32, 0x3880
; WAVE32-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:444 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1576, 32, 1, 32, 14208
; WAVE32-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:440 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1577, 32, 1, 32, 14080
; WAVE32-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:436 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1578, 32, 1, 32, 13952
; WAVE32-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:432 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1579, 32, 1, 32, 13824
; WAVE32-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:428 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1580, 32, 1, 32, 13696
; WAVE32-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:424 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1581, 32, 1, 32, 13568
; WAVE32-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:420 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1582, 32, 1, 32, 13440
; WAVE32-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:416 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1583, 32, 1, 32, 13312
; WAVE32-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:412 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1592, 32, 1, 32, 13184
; WAVE32-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:408 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1593, 32, 1, 32, 13056
; WAVE32-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:404 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1594, 32, 1, 32, 12928
; WAVE32-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:400 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1595, 32, 1, 32, 12800
; WAVE32-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:396 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1596, 32, 1, 32, 12672
; WAVE32-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:392 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1597, 32, 1, 32, 12544
; WAVE32-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:388 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1598, 32, 1, 32, 12416
; WAVE32-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:384 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1599, 32, 1, 32, 12288
; WAVE32-NEXT: buffer_store_dword v72, off, s[0:3], s33 offset:380 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1608, 32, 1, 32, 12160
; WAVE32-NEXT: buffer_store_dword v73, off, s[0:3], s33 offset:376 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1609, 32, 1, 32, 12032
; WAVE32-NEXT: buffer_store_dword v74, off, s[0:3], s33 offset:372 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1610, 32, 1, 32, 11904
; WAVE32-NEXT: buffer_store_dword v75, off, s[0:3], s33 offset:368 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1611, 32, 1, 32, 11776
; WAVE32-NEXT: buffer_store_dword v76, off, s[0:3], s33 offset:364 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1612, 32, 1, 32, 11648
; WAVE32-NEXT: buffer_store_dword v77, off, s[0:3], s33 offset:360 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1613, 32, 1, 32, 11520
; WAVE32-NEXT: buffer_store_dword v78, off, s[0:3], s33 offset:356 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1614, 32, 1, 32, 11392
; WAVE32-NEXT: buffer_store_dword v79, off, s[0:3], s33 offset:352 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1615, 32, 1, 32, 11264
; WAVE32-NEXT: buffer_store_dword v88, off, s[0:3], s33 offset:348 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1624, 32, 1, 32, 11136
; WAVE32-NEXT: buffer_store_dword v89, off, s[0:3], s33 offset:344 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1625, 32, 1, 32, 11008
; WAVE32-NEXT: buffer_store_dword v90, off, s[0:3], s33 offset:340 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1626, 32, 1, 32, 10880
; WAVE32-NEXT: buffer_store_dword v91, off, s[0:3], s33 offset:336 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1627, 32, 1, 32, 10752
; WAVE32-NEXT: buffer_store_dword v92, off, s[0:3], s33 offset:332 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1628, 32, 1, 32, 10624
; WAVE32-NEXT: buffer_store_dword v93, off, s[0:3], s33 offset:328 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1629, 32, 1, 32, 10496
; WAVE32-NEXT: buffer_store_dword v94, off, s[0:3], s33 offset:324 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1630, 32, 1, 32, 10368
; WAVE32-NEXT: buffer_store_dword v95, off, s[0:3], s33 offset:320 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1631, 32, 1, 32, 10240
; WAVE32-NEXT: buffer_store_dword v104, off, s[0:3], s33 offset:316 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1640, 32, 1, 32, 10112
; WAVE32-NEXT: buffer_store_dword v105, off, s[0:3], s33 offset:312 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1641, 32, 1, 32, 9984
; WAVE32-NEXT: buffer_store_dword v106, off, s[0:3], s33 offset:308 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1642, 32, 1, 32, 9856
; WAVE32-NEXT: buffer_store_dword v107, off, s[0:3], s33 offset:304 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1643, 32, 1, 32, 9728
; WAVE32-NEXT: buffer_store_dword v108, off, s[0:3], s33 offset:300 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1644, 32, 1, 32, 9600
; WAVE32-NEXT: buffer_store_dword v109, off, s[0:3], s33 offset:296 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1645, 32, 1, 32, 9472
; WAVE32-NEXT: buffer_store_dword v110, off, s[0:3], s33 offset:292 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1646, 32, 1, 32, 9344
; WAVE32-NEXT: buffer_store_dword v111, off, s[0:3], s33 offset:288 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1647, 32, 1, 32, 9216
; WAVE32-NEXT: buffer_store_dword v120, off, s[0:3], s33 offset:284 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1656, 32, 1, 32, 9088
; WAVE32-NEXT: buffer_store_dword v121, off, s[0:3], s33 offset:280 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1657, 32, 1, 32, 8960
; WAVE32-NEXT: buffer_store_dword v122, off, s[0:3], s33 offset:276 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1658, 32, 1, 32, 8832
; WAVE32-NEXT: buffer_store_dword v123, off, s[0:3], s33 offset:272 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1659, 32, 1, 32, 8704
; WAVE32-NEXT: buffer_store_dword v124, off, s[0:3], s33 offset:268 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1660, 32, 1, 32, 8576
; WAVE32-NEXT: buffer_store_dword v125, off, s[0:3], s33 offset:264 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1661, 32, 1, 32, 8448
; WAVE32-NEXT: buffer_store_dword v126, off, s[0:3], s33 offset:260 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1662, 32, 1, 32, 8320
; WAVE32-NEXT: buffer_store_dword v127, off, s[0:3], s33 offset:256 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1663, 32, 1, 32, 8192
; WAVE32-NEXT: buffer_store_dword v136, off, s[0:3], s33 offset:252 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1672, 32, 1, 32, 8064
; WAVE32-NEXT: buffer_store_dword v137, off, s[0:3], s33 offset:248 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1673, 32, 1, 32, 7936
; WAVE32-NEXT: buffer_store_dword v138, off, s[0:3], s33 offset:244 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1674, 32, 1, 32, 7808
; WAVE32-NEXT: buffer_store_dword v139, off, s[0:3], s33 offset:240 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1675, 32, 1, 32, 7680
; WAVE32-NEXT: buffer_store_dword v140, off, s[0:3], s33 offset:236 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1676, 32, 1, 32, 7552
; WAVE32-NEXT: buffer_store_dword v141, off, s[0:3], s33 offset:232 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1677, 32, 1, 32, 7424
; WAVE32-NEXT: buffer_store_dword v142, off, s[0:3], s33 offset:228 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1678, 32, 1, 32, 7296
; WAVE32-NEXT: buffer_store_dword v143, off, s[0:3], s33 offset:224 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1679, 32, 1, 32, 7168
; WAVE32-NEXT: buffer_store_dword v152, off, s[0:3], s33 offset:220 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1688, 32, 1, 32, 7040
; WAVE32-NEXT: buffer_store_dword v153, off, s[0:3], s33 offset:216 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1689, 32, 1, 32, 6912
; WAVE32-NEXT: buffer_store_dword v154, off, s[0:3], s33 offset:212 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1690, 32, 1, 32, 6784
; WAVE32-NEXT: buffer_store_dword v155, off, s[0:3], s33 offset:208 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1691, 32, 1, 32, 6656
; WAVE32-NEXT: buffer_store_dword v156, off, s[0:3], s33 offset:204 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1692, 32, 1, 32, 6528
; WAVE32-NEXT: buffer_store_dword v157, off, s[0:3], s33 offset:200 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1693, 32, 1, 32, 6400
; WAVE32-NEXT: buffer_store_dword v158, off, s[0:3], s33 offset:196 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1694, 32, 1, 32, 6272
; WAVE32-NEXT: buffer_store_dword v159, off, s[0:3], s33 offset:192 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1695, 32, 1, 32, 6144
; WAVE32-NEXT: buffer_store_dword v168, off, s[0:3], s33 offset:188 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1704, 32, 1, 32, 6016
; WAVE32-NEXT: buffer_store_dword v169, off, s[0:3], s33 offset:184 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1705, 32, 1, 32, 5888
; WAVE32-NEXT: buffer_store_dword v170, off, s[0:3], s33 offset:180 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1706, 32, 1, 32, 5760
; WAVE32-NEXT: buffer_store_dword v171, off, s[0:3], s33 offset:176 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1707, 32, 1, 32, 5632
; WAVE32-NEXT: buffer_store_dword v172, off, s[0:3], s33 offset:172 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1708, 32, 1, 32, 5504
; WAVE32-NEXT: buffer_store_dword v173, off, s[0:3], s33 offset:168 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1709, 32, 1, 32, 5376
; WAVE32-NEXT: buffer_store_dword v174, off, s[0:3], s33 offset:164 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1710, 32, 1, 32, 5248
; WAVE32-NEXT: buffer_store_dword v175, off, s[0:3], s33 offset:160 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1711, 32, 1, 32, 5120
; WAVE32-NEXT: buffer_store_dword v184, off, s[0:3], s33 offset:156 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1720, 32, 1, 32, 4992
; WAVE32-NEXT: buffer_store_dword v185, off, s[0:3], s33 offset:152 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1721, 32, 1, 32, 4864
; WAVE32-NEXT: buffer_store_dword v186, off, s[0:3], s33 offset:148 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1722, 32, 1, 32, 4736
; WAVE32-NEXT: buffer_store_dword v187, off, s[0:3], s33 offset:144 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1723, 32, 1, 32, 4608
; WAVE32-NEXT: buffer_store_dword v188, off, s[0:3], s33 offset:140 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1724, 32, 1, 32, 4480
; WAVE32-NEXT: buffer_store_dword v189, off, s[0:3], s33 offset:136 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1725, 32, 1, 32, 4352
; WAVE32-NEXT: buffer_store_dword v190, off, s[0:3], s33 offset:132 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1726, 32, 1, 32, 4224
; WAVE32-NEXT: buffer_store_dword v191, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1727, 32, 1, 32, 4096
; WAVE32-NEXT: buffer_store_dword v200, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1736, 32, 1, 32, 3968
; WAVE32-NEXT: buffer_store_dword v201, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1737, 32, 1, 32, 3840
; WAVE32-NEXT: buffer_store_dword v202, off, s[0:3], s33 offset:116 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1738, 32, 1, 32, 3712
; WAVE32-NEXT: buffer_store_dword v203, off, s[0:3], s33 offset:112 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1739, 32, 1, 32, 3584
; WAVE32-NEXT: buffer_store_dword v204, off, s[0:3], s33 offset:108 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1740, 32, 1, 32, 3456
; WAVE32-NEXT: buffer_store_dword v205, off, s[0:3], s33 offset:104 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1741, 32, 1, 32, 3328
; WAVE32-NEXT: buffer_store_dword v206, off, s[0:3], s33 offset:100 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1742, 32, 1, 32, 3200
; WAVE32-NEXT: buffer_store_dword v207, off, s[0:3], s33 offset:96 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1743, 32, 1, 32, 3072
; WAVE32-NEXT: buffer_store_dword v216, off, s[0:3], s33 offset:92 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1752, 32, 1, 32, 2944
; WAVE32-NEXT: buffer_store_dword v217, off, s[0:3], s33 offset:88 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1753, 32, 1, 32, 2816
; WAVE32-NEXT: buffer_store_dword v218, off, s[0:3], s33 offset:84 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1754, 32, 1, 32, 2688
; WAVE32-NEXT: buffer_store_dword v219, off, s[0:3], s33 offset:80 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1755, 32, 1, 32, 2560
; WAVE32-NEXT: buffer_store_dword v220, off, s[0:3], s33 offset:76 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1756, 32, 1, 32, 2432
; WAVE32-NEXT: buffer_store_dword v221, off, s[0:3], s33 offset:72 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1757, 32, 1, 32, 2304
; WAVE32-NEXT: buffer_store_dword v222, off, s[0:3], s33 offset:68 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1758, 32, 1, 32, 2176
; WAVE32-NEXT: buffer_store_dword v223, off, s[0:3], s33 offset:64 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1759, 32, 1, 32, 2048
; WAVE32-NEXT: buffer_store_dword v232, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1768, 32, 1, 32, 1920
; WAVE32-NEXT: buffer_store_dword v233, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1769, 32, 1, 32, 1792
; WAVE32-NEXT: buffer_store_dword v234, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1770, 32, 1, 32, 1664
; WAVE32-NEXT: buffer_store_dword v235, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1771, 32, 1, 32, 1536
; WAVE32-NEXT: buffer_store_dword v236, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1772, 32, 1, 32, 1408
; WAVE32-NEXT: buffer_store_dword v237, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1773, 32, 1, 32, 1280
; WAVE32-NEXT: buffer_store_dword v238, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1774, 32, 1, 32, 1152
; WAVE32-NEXT: buffer_store_dword v239, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1775, 32, 1, 32, 1024
; WAVE32-NEXT: buffer_store_dword v248, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1784, 32, 1, 32, 896
; WAVE32-NEXT: buffer_store_dword v249, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1785, 32, 1, 32, 768
; WAVE32-NEXT: buffer_store_dword v250, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1786, 32, 1, 32, 640
; WAVE32-NEXT: buffer_store_dword v251, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1787, 32, 1, 32, 512
; WAVE32-NEXT: buffer_store_dword v252, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1788, 32, 1, 32, 384
; WAVE32-NEXT: buffer_store_dword v253, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1789, 32, 1, 32, 256
; WAVE32-NEXT: buffer_store_dword v254, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1790, 32, 1, 32, 128
; WAVE32-NEXT: buffer_store_dword v255, off, s[0:3], s33 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1791, 32, 1, 32, 0
; WAVE32-NEXT: ;;#ASMSTART
; WAVE32-NEXT: ; clobber nonpreserved SGPRs
; WAVE32-NEXT: ;;#ASMEND
@@ -1730,7 +2179,6 @@ define void @callee_need_to_spill_fp_to_memory() #1 {
; WAVE32-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:436
; WAVE32-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:440
; WAVE32-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:444
-; WAVE32-NEXT: s_addk_i32 s32, 0x3880
; WAVE32-NEXT: s_mov_b32 s32, s33
; WAVE32-NEXT: .cfi_def_cfa_register 64
; WAVE32-NEXT: s_waitcnt_depctr 0xffe3
@@ -1998,12 +2446,13 @@ define hidden void @func_call_clobber() #0 {
; GFX900-NEXT: v_writelane_b32 v40, s16, 2
; GFX900-NEXT: .cfi_llvm_vector_registers 65, 2600, 2, 32
; GFX900-NEXT: .cfi_def_cfa_register 65
-; GFX900-NEXT: s_addk_i32 s32, 0x400
; GFX900-NEXT: v_writelane_b32 v40, s30, 0
+; GFX900-NEXT: s_addk_i32 s32, 0x400
+; GFX900-NEXT: v_writelane_b32 v40, s31, 1
+; GFX900-NEXT: .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32
; GFX900-NEXT: s_getpc_b64 s[16:17]
; GFX900-NEXT: s_add_u32 s16, s16, ex at rel32@lo+4
; GFX900-NEXT: s_addc_u32 s17, s17, ex at rel32@hi+12
-; GFX900-NEXT: v_writelane_b32 v40, s31, 1
; GFX900-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX900-NEXT: v_readlane_b32 s30, v40, 0
; GFX900-NEXT: v_readlane_b32 s31, v40, 1
@@ -2271,12 +2720,13 @@ define hidden void @func_call_clobber() #0 {
; GFX90A-V2A-DIS-NEXT: v_writelane_b32 v40, s16, 2
; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_registers 65, 2600, 2, 32
; GFX90A-V2A-DIS-NEXT: .cfi_def_cfa_register 65
-; GFX90A-V2A-DIS-NEXT: s_addk_i32 s32, 0x400
; GFX90A-V2A-DIS-NEXT: v_writelane_b32 v40, s30, 0
+; GFX90A-V2A-DIS-NEXT: s_addk_i32 s32, 0x400
+; GFX90A-V2A-DIS-NEXT: v_writelane_b32 v40, s31, 1
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32
; GFX90A-V2A-DIS-NEXT: s_getpc_b64 s[16:17]
; GFX90A-V2A-DIS-NEXT: s_add_u32 s16, s16, ex at rel32@lo+4
; GFX90A-V2A-DIS-NEXT: s_addc_u32 s17, s17, ex at rel32@hi+12
-; GFX90A-V2A-DIS-NEXT: v_writelane_b32 v40, s31, 1
; GFX90A-V2A-DIS-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX90A-V2A-DIS-NEXT: v_readlane_b32 s30, v40, 0
; GFX90A-V2A-DIS-NEXT: v_readlane_b32 s31, v40, 1
@@ -2544,12 +2994,13 @@ define hidden void @func_call_clobber() #0 {
; GFX90A-V2A-EN-NEXT: v_writelane_b32 v40, s16, 2
; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_registers 65, 2600, 2, 32
; GFX90A-V2A-EN-NEXT: .cfi_def_cfa_register 65
-; GFX90A-V2A-EN-NEXT: s_addk_i32 s32, 0x400
; GFX90A-V2A-EN-NEXT: v_writelane_b32 v40, s30, 0
+; GFX90A-V2A-EN-NEXT: s_addk_i32 s32, 0x400
+; GFX90A-V2A-EN-NEXT: v_writelane_b32 v40, s31, 1
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32
; GFX90A-V2A-EN-NEXT: s_getpc_b64 s[16:17]
; GFX90A-V2A-EN-NEXT: s_add_u32 s16, s16, ex at rel32@lo+4
; GFX90A-V2A-EN-NEXT: s_addc_u32 s17, s17, ex at rel32@hi+12
-; GFX90A-V2A-EN-NEXT: v_writelane_b32 v40, s31, 1
; GFX90A-V2A-EN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX90A-V2A-EN-NEXT: v_readlane_b32 s30, v40, 0
; GFX90A-V2A-EN-NEXT: v_readlane_b32 s31, v40, 1
@@ -2788,10 +3239,11 @@ define hidden void @func_call_clobber() #0 {
; WAVE32-NEXT: .cfi_def_cfa_register 65
; WAVE32-NEXT: v_writelane_b32 v40, s30, 0
; WAVE32-NEXT: s_addk_i32 s32, 0x200
+; WAVE32-NEXT: v_writelane_b32 v40, s31, 1
+; WAVE32-NEXT: .cfi_llvm_vector_registers 16, 1791, 0, 32, 1791, 1, 32
; WAVE32-NEXT: s_getpc_b64 s[16:17]
; WAVE32-NEXT: s_add_u32 s16, s16, ex at rel32@lo+4
; WAVE32-NEXT: s_addc_u32 s17, s17, ex at rel32@hi+12
-; WAVE32-NEXT: v_writelane_b32 v40, s31, 1
; WAVE32-NEXT: s_swappc_b64 s[30:31], s[16:17]
; WAVE32-NEXT: v_readlane_b32 s30, v40, 0
; WAVE32-NEXT: v_readlane_b32 s31, v40, 1
@@ -2819,7 +3271,9 @@ define hidden void @func_spill_vgpr_to_vmem() #0 {
; GFX900-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 256
; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2601, 32, 17, 64, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; clobber
; GFX900-NEXT: ;;#ASMEND
@@ -2845,9 +3299,13 @@ define hidden void @func_spill_vgpr_to_vmem() #0 {
; GFX90A-V2A-DIS-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32
; GFX90A-V2A-DIS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 768
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2601, 32, 17, 64, 512
; GFX90A-V2A-DIS-NEXT: buffer_store_dword a32, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 3104, 32, 17, 64, 256
; GFX90A-V2A-DIS-NEXT: buffer_store_dword a33, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 3105, 32, 17, 64, 0
; GFX90A-V2A-DIS-NEXT: ;;#ASMSTART
; GFX90A-V2A-DIS-NEXT: ; clobber
; GFX90A-V2A-DIS-NEXT: ;;#ASMEND
@@ -2879,9 +3337,13 @@ define hidden void @func_spill_vgpr_to_vmem() #0 {
; GFX90A-V2A-EN-NEXT: .cfi_undefined 3073
; GFX90A-V2A-EN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2600, 3072, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2601, 3073, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v0, a32 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 3104, 2560, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v1, a33 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 3105, 2561, 32, 17, 64
; GFX90A-V2A-EN-NEXT: ;;#ASMSTART
; GFX90A-V2A-EN-NEXT: ; clobber
; GFX90A-V2A-EN-NEXT: ;;#ASMEND
@@ -2908,7 +3370,9 @@ define hidden void @func_spill_vgpr_to_vmem() #0 {
; WAVE32-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32
; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; WAVE32-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1576, 32, 1, 32, 128
; WAVE32-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1577, 32, 1, 32, 0
; WAVE32-NEXT: ;;#ASMSTART
; WAVE32-NEXT: ; clobber
; WAVE32-NEXT: ;;#ASMEND
@@ -2943,7 +3407,9 @@ define hidden void @func_spill_vgpr_to_agpr() #2 {
; GFX900-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 256
; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX900-NEXT: .cfi_llvm_vector_offset 2601, 32, 17, 64, 0
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; clobber
; GFX900-NEXT: ;;#ASMEND
@@ -2969,9 +3435,13 @@ define hidden void @func_spill_vgpr_to_agpr() #2 {
; GFX90A-V2A-DIS-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32
; GFX90A-V2A-DIS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 768
; GFX90A-V2A-DIS-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 2601, 32, 17, 64, 512
; GFX90A-V2A-DIS-NEXT: buffer_store_dword a32, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 3104, 32, 17, 64, 256
; GFX90A-V2A-DIS-NEXT: buffer_store_dword a33, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_offset 3105, 32, 17, 64, 0
; GFX90A-V2A-DIS-NEXT: ;;#ASMSTART
; GFX90A-V2A-DIS-NEXT: ; clobber
; GFX90A-V2A-DIS-NEXT: ;;#ASMEND
@@ -3003,9 +3473,13 @@ define hidden void @func_spill_vgpr_to_agpr() #2 {
; GFX90A-V2A-EN-NEXT: .cfi_undefined 3073
; GFX90A-V2A-EN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2600, 3072, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 2601, 3073, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v0, a32 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 3104, 2560, 32, 17, 64
; GFX90A-V2A-EN-NEXT: v_accvgpr_read_b32 v1, a33 ; Reload Reuse
+; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_register_mask 3105, 2561, 32, 17, 64
; GFX90A-V2A-EN-NEXT: ;;#ASMSTART
; GFX90A-V2A-EN-NEXT: ; clobber
; GFX90A-V2A-EN-NEXT: ;;#ASMEND
@@ -3032,7 +3506,9 @@ define hidden void @func_spill_vgpr_to_agpr() #2 {
; WAVE32-NEXT: .cfi_llvm_register_pair 16, 62, 32, 63, 32
; WAVE32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; WAVE32-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1576, 32, 1, 32, 128
; WAVE32-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill
+; WAVE32-NEXT: .cfi_llvm_vector_offset 1577, 32, 1, 32, 0
; WAVE32-NEXT: ;;#ASMSTART
; WAVE32-NEXT: ; clobber
; WAVE32-NEXT: ;;#ASMEND
diff --git a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
index 705d403764503..bc928041ed750 100644
--- a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
@@ -489,20 +489,40 @@ define weak_odr void @test(i32 %0) !dbg !34 {
; CHECK-NEXT: v_writelane_b32 v41, s16, 16
; CHECK-NEXT: .cfi_llvm_vector_registers 65, 2601, 16, 32
; CHECK-NEXT: .cfi_def_cfa_register 65
+; CHECK-NEXT: s_addk_i32 s32, 0x400
+; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
+; CHECK-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 0
; CHECK-NEXT: v_writelane_b32 v41, s34, 0
+; CHECK-NEXT: .cfi_llvm_vector_registers 66, 2622, 0, 32
; CHECK-NEXT: v_writelane_b32 v41, s35, 1
+; CHECK-NEXT: .cfi_llvm_vector_registers 67, 2622, 1, 32
; CHECK-NEXT: v_writelane_b32 v41, s36, 2
+; CHECK-NEXT: .cfi_llvm_vector_registers 68, 2622, 2, 32
; CHECK-NEXT: v_writelane_b32 v41, s37, 3
+; CHECK-NEXT: .cfi_llvm_vector_registers 69, 2622, 3, 32
; CHECK-NEXT: v_writelane_b32 v41, s38, 4
+; CHECK-NEXT: .cfi_llvm_vector_registers 70, 2622, 4, 32
; CHECK-NEXT: v_writelane_b32 v41, s39, 5
+; CHECK-NEXT: .cfi_llvm_vector_registers 71, 2622, 5, 32
; CHECK-NEXT: v_writelane_b32 v41, s48, 6
+; CHECK-NEXT: .cfi_llvm_vector_registers 80, 2622, 6, 32
; CHECK-NEXT: v_writelane_b32 v41, s49, 7
+; CHECK-NEXT: .cfi_llvm_vector_registers 81, 2622, 7, 32
; CHECK-NEXT: v_writelane_b32 v41, s50, 8
+; CHECK-NEXT: .cfi_llvm_vector_registers 82, 2622, 8, 32
; CHECK-NEXT: v_writelane_b32 v41, s51, 9
+; CHECK-NEXT: .cfi_llvm_vector_registers 83, 2622, 9, 32
; CHECK-NEXT: v_writelane_b32 v41, s52, 10
-; CHECK-NEXT: s_addk_i32 s32, 0x400
+; CHECK-NEXT: .cfi_llvm_vector_registers 84, 2622, 10, 32
; CHECK-NEXT: v_writelane_b32 v41, s53, 11
+; CHECK-NEXT: .cfi_llvm_vector_registers 85, 2622, 11, 32
; CHECK-NEXT: v_writelane_b32 v41, s54, 12
+; CHECK-NEXT: .cfi_llvm_vector_registers 86, 2622, 12, 32
+; CHECK-NEXT: v_writelane_b32 v41, s55, 13
+; CHECK-NEXT: .cfi_llvm_vector_registers 87, 2622, 13, 32
+; CHECK-NEXT: v_writelane_b32 v41, s30, 14
+; CHECK-NEXT: v_writelane_b32 v41, s31, 15
+; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2622, 14, 32, 2622, 15, 32
; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5]
; CHECK-NEXT: ;DEBUG_VALUE: dummy:dummy <- undef
; CHECK-NEXT: .Ltmp0:
@@ -510,12 +530,8 @@ define weak_odr void @test(i32 %0) !dbg !34 {
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_add_u32 s4, s4, __kmpc_alloc_shared at gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s5, s5, __kmpc_alloc_shared at gotpcrel32@hi+12
-; CHECK-NEXT: v_writelane_b32 v41, s55, 13
; CHECK-NEXT: s_load_dwordx2 s[54:55], s[4:5], 0x0
-; CHECK-NEXT: v_writelane_b32 v41, s30, 14
; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49]
-; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; CHECK-NEXT: v_writelane_b32 v41, s31, 15
; CHECK-NEXT: v_mov_b32_e32 v40, v31
; CHECK-NEXT: s_mov_b32 s50, s15
; CHECK-NEXT: s_mov_b32 s51, s14
diff --git a/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll b/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
index db48100aa7caf..ebce1e7c836f8 100644
--- a/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
+++ b/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
@@ -286,19 +286,18 @@ define amdgpu_gfx void @amdgpu_gfx() #0 {
; CHECK-TRUE16-NEXT: s_wait_alu 0xfffe
; CHECK-TRUE16-NEXT: s_mov_b32 exec_lo, s1
; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
+; CHECK-TRUE16-NEXT: s_add_co_i32 s32, s32, 16
+; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
+; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 15
; CHECK-TRUE16-NEXT: s_mov_b32 s1, callee at abs32@hi
; CHECK-TRUE16-NEXT: s_mov_b32 s0, callee at abs32@lo
-; CHECK-TRUE16-NEXT: s_add_co_i32 s32, s32, 16
-; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
; CHECK-TRUE16-NEXT: s_wait_storecnt 0x0
; CHECK-TRUE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
; CHECK-TRUE16-NEXT: s_wait_storecnt 0x0
; CHECK-TRUE16-NEXT: v_mov_b32_e32 v0, 0x47
-; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-TRUE16-NEXT: s_wait_alu 0xfffe
; CHECK-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; CHECK-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; CHECK-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
; CHECK-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-TRUE16-NEXT: s_mov_b32 s32, s33
@@ -326,19 +325,18 @@ define amdgpu_gfx void @amdgpu_gfx() #0 {
; CHECK-FAKE16-NEXT: s_wait_alu 0xfffe
; CHECK-FAKE16-NEXT: s_mov_b32 exec_lo, s1
; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
+; CHECK-FAKE16-NEXT: s_add_co_i32 s32, s32, 16
+; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
+; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 15
; CHECK-FAKE16-NEXT: s_mov_b32 s1, callee at abs32@hi
; CHECK-FAKE16-NEXT: s_mov_b32 s0, callee at abs32@lo
-; CHECK-FAKE16-NEXT: s_add_co_i32 s32, s32, 16
-; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
; CHECK-FAKE16-NEXT: s_wait_storecnt 0x0
; CHECK-FAKE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS
; CHECK-FAKE16-NEXT: s_wait_storecnt 0x0
; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 0x47
-; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-FAKE16-NEXT: s_wait_alu 0xfffe
; CHECK-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; CHECK-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; CHECK-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
; CHECK-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; CHECK-FAKE16-NEXT: s_mov_b32 s32, s33
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
index d3a8d983bb22c..3cfb96fede71a 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
@@ -1650,21 +1650,37 @@ body: |
; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55
; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 3840
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 3584
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 3328
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 3072
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 2816
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 2560
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 2304
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec, 64, 2048
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1792
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1536
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 1280
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 1024
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 768
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 512
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec, 64, 256
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec, 64, 0
; GFX8-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX8-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX8-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
@@ -1762,21 +1778,37 @@ body: |
; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55
; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 3840
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 3584
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 3328
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 3072
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 2816
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 2560
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 2304
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec, 64, 2048
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1792
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1536
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 1280
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 1024
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 768
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 512
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec, 64, 256
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec, 64, 0
; GFX900-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX900-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX900-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
@@ -1889,21 +1921,37 @@ body: |
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr40, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr40, $agpr0, 32, $exec, 64
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr41, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr41, $agpr1, 32, $exec, 64
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr42, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr42, $agpr2, 32, $exec, 64
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr43, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr43, $agpr3, 32, $exec, 64
; GFX90A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr44, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr44, $agpr4, 32, $exec, 64
; GFX90A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr45, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr45, $agpr5, 32, $exec, 64
; GFX90A-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr46, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr46, $agpr6, 32, $exec, 64
; GFX90A-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr47, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr47, $agpr7, 32, $exec, 64
; GFX90A-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr56, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr56, $agpr8, 32, $exec, 64
; GFX90A-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr57, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr57, $agpr9, 32, $exec, 64
; GFX90A-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr58, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr58, $agpr10, 32, $exec, 64
; GFX90A-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr59, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr59, $agpr11, 32, $exec, 64
; GFX90A-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr60, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr60, $agpr12, 32, $exec, 64
; GFX90A-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr61, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr61, $agpr13, 32, $exec, 64
; GFX90A-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr62, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr62, $agpr14, 32, $exec, 64
; GFX90A-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr63, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr63, $agpr15, 32, $exec, 64
; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
@@ -2000,21 +2048,37 @@ body: |
; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55
; GFX1010-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 1920
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec_lo, 32, 1792
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 1664
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec_lo, 32, 1536
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec_lo, 32, 1408
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec_lo, 32, 1280
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec_lo, 32, 1152
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec_lo, 32, 1024
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec_lo, 32, 896
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec_lo, 32, 768
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec_lo, 32, 640
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec_lo, 32, 512
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec_lo, 32, 384
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec_lo, 32, 256
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec_lo, 32, 128
; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5)
+ ; GFX1010-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec_lo, 32, 0
; GFX1010-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX1010-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX1010-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
@@ -2109,21 +2173,37 @@ body: |
; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55
; GFX1100-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 1920
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec_lo, 32, 1792
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.4, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 1664
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr43, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.5, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec_lo, 32, 1536
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.6, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec_lo, 32, 1408
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr45, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.7, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec_lo, 32, 1280
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr46, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.8, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec_lo, 32, 1152
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr47, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec_lo, 32, 1024
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr56, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.10, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec_lo, 32, 896
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr57, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.11, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec_lo, 32, 768
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr58, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.12, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec_lo, 32, 640
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr59, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.13, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec_lo, 32, 512
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr60, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.14, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec_lo, 32, 384
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr61, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.15, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec_lo, 32, 256
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr62, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.16, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec_lo, 32, 128
; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr63, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.17, addrspace 5)
+ ; GFX1100-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec_lo, 32, 0
; GFX1100-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX1100-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX1100-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
@@ -2219,21 +2299,37 @@ body: |
; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55
; GFX1200-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 1920
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec_lo, 32, 1792
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.4, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 1664
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr43, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.5, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec_lo, 32, 1536
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.6, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec_lo, 32, 1408
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr45, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.7, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec_lo, 32, 1280
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr46, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.8, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec_lo, 32, 1152
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr47, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec_lo, 32, 1024
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr56, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.10, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec_lo, 32, 896
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr57, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.11, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec_lo, 32, 768
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr58, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.12, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec_lo, 32, 640
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr59, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.13, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec_lo, 32, 512
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr60, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.14, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec_lo, 32, 384
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr61, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.15, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec_lo, 32, 256
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr62, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.16, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec_lo, 32, 128
; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr63, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.17, addrspace 5)
+ ; GFX1200-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec_lo, 32, 0
; GFX1200-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX1200-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX1200-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
diff --git a/llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll b/llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll
index cba5aa8ef3672..f5832e6f307fd 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll
+++ b/llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll
@@ -22,13 +22,14 @@ define void @test_stack_realign(<8 x i32> %val, i32 %idx) #0 {
; GCN-NEXT: v_writelane_b32 v42, s34, 3
; GCN-NEXT: s_mov_b32 s34, s32
; GCN-NEXT: s_addk_i32 s32, 0x3000
+; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GCN-NEXT: v_writelane_b32 v42, s30, 0
+; GCN-NEXT: v_writelane_b32 v42, s31, 1
; GCN-NEXT: s_getpc_b64 s[16:17]
; GCN-NEXT: s_add_u32 s16, s16, extern_func at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s17, s17, extern_func at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; GCN-NEXT: v_writelane_b32 v42, s30, 0
; GCN-NEXT: buffer_store_dword v7, off, s[0:3], s33 offset:92
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:88
@@ -46,7 +47,6 @@ define void @test_stack_realign(<8 x i32> %val, i32 %idx) #0 {
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:64
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, v8
-; GCN-NEXT: v_writelane_b32 v42, s31, 1
; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/frame-index.mir b/llvm/test/CodeGen/AMDGPU/frame-index.mir
index 6d54bb544fb8c..5c14af9673d1e 100644
--- a/llvm/test/CodeGen/AMDGPU/frame-index.mir
+++ b/llvm/test/CodeGen/AMDGPU/frame-index.mir
@@ -501,21 +501,37 @@ body: |
; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55
; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 3840
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 3584
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 3328
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 3072
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 2816
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 2560
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 2304
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec, 64, 2048
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1792
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1536
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 1280
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 1024
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 768
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 512
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec, 64, 256
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec, 64, 0
; GFX8-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX8-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX8-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
@@ -604,21 +620,37 @@ body: |
; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55
; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 3840
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 3584
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 3328
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 3072
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 2816
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 2560
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 2304
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec, 64, 2048
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1792
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1536
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 1280
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 1024
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 768
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 512
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec, 64, 256
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec, 64, 0
; GFX900-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX900-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX900-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
@@ -722,21 +754,37 @@ body: |
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr40, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr40, $agpr0, 32, $exec, 64
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr41, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr41, $agpr1, 32, $exec, 64
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr42, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr42, $agpr2, 32, $exec, 64
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr43, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr43, $agpr3, 32, $exec, 64
; GFX90A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr44, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr44, $agpr4, 32, $exec, 64
; GFX90A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr45, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr45, $agpr5, 32, $exec, 64
; GFX90A-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr46, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr46, $agpr6, 32, $exec, 64
; GFX90A-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr47, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr47, $agpr7, 32, $exec, 64
; GFX90A-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr56, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr56, $agpr8, 32, $exec, 64
; GFX90A-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr57, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr57, $agpr9, 32, $exec, 64
; GFX90A-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr58, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr58, $agpr10, 32, $exec, 64
; GFX90A-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr59, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr59, $agpr11, 32, $exec, 64
; GFX90A-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr60, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr60, $agpr12, 32, $exec, 64
; GFX90A-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr61, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr61, $agpr13, 32, $exec, 64
; GFX90A-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr62, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr62, $agpr14, 32, $exec, 64
; GFX90A-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr63, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr63, $agpr15, 32, $exec, 64
; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
@@ -868,21 +916,37 @@ body: |
; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55
; GFX8-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 3840
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 3584
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 3328
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 3072
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 2816
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 2560
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 2304
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec, 64, 2048
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1792
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1536
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 1280
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 1024
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 768
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 512
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec, 64, 256
; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5)
+ ; GFX8-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec, 64, 0
; GFX8-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX8-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX8-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
@@ -979,21 +1043,37 @@ body: |
; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55
; GFX900-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 3840
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 3584
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 3328
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 3072
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 2816
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 2560
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 2304
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec, 64, 2048
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1792
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1536
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 1280
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 1024
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 768
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 512
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec, 64, 256
; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5)
+ ; GFX900-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec, 64, 0
; GFX900-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX900-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX900-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
@@ -1105,21 +1185,37 @@ body: |
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
; GFX90A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr40, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr40, $agpr0, 32, $exec, 64
; GFX90A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr41, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr41, $agpr1, 32, $exec, 64
; GFX90A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr42, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr42, $agpr2, 32, $exec, 64
; GFX90A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr43, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr43, $agpr3, 32, $exec, 64
; GFX90A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr44, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr44, $agpr4, 32, $exec, 64
; GFX90A-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr45, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr45, $agpr5, 32, $exec, 64
; GFX90A-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr46, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr46, $agpr6, 32, $exec, 64
; GFX90A-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr47, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr47, $agpr7, 32, $exec, 64
; GFX90A-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr56, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr56, $agpr8, 32, $exec, 64
; GFX90A-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr57, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr57, $agpr9, 32, $exec, 64
; GFX90A-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr58, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr58, $agpr10, 32, $exec, 64
; GFX90A-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr59, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr59, $agpr11, 32, $exec, 64
; GFX90A-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr60, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr60, $agpr12, 32, $exec, 64
; GFX90A-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr61, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr61, $agpr13, 32, $exec, 64
; GFX90A-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr62, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr62, $agpr14, 32, $exec, 64
; GFX90A-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr63, implicit $exec
+ ; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_register_mask $vgpr63, $agpr15, 32, $exec, 64
; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
diff --git a/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll b/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
index 6abe5998d6767..2760c7a2187b4 100644
--- a/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
+++ b/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
@@ -16,13 +16,13 @@ define void @callee_with_stack_and_call() #0 {
; SPILL-TO-VGPR-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[8:9]
; SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, s4, 2
-; SPILL-TO-VGPR-NEXT: s_addk_i32 s32, 0x400
; SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, s30, 0
+; SPILL-TO-VGPR-NEXT: s_addk_i32 s32, 0x400
+; SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, s31, 1
; SPILL-TO-VGPR-NEXT: v_mov_b32_e32 v0, 0
; SPILL-TO-VGPR-NEXT: s_getpc_b64 s[4:5]
; SPILL-TO-VGPR-NEXT: s_add_u32 s4, s4, external_void_func_void at rel32@lo+4
; SPILL-TO-VGPR-NEXT: s_addc_u32 s5, s5, external_void_func_void at rel32@hi+12
-; SPILL-TO-VGPR-NEXT: v_writelane_b32 v40, s31, 1
; SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33
; SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
; SPILL-TO-VGPR-NEXT: s_swappc_b64 s[30:31], s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
index 6dd683e6fca53..dfb8428263806 100644
--- a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
@@ -1727,17 +1727,17 @@ define void @caller_void_func_i32_v2float_inreg(i32 inreg %arg0, <2 x float> inr
; GFX9-NEXT: s_or_saveexec_b64 s[20:21], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[20:21]
+; GFX9-NEXT: v_writelane_b32 v40, s19, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_getpc_b64 s[20:21]
; GFX9-NEXT: s_add_u32 s20, s20, caller_void_func_i32_v2float_inreg at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s21, s21, caller_void_func_i32_v2float_inreg at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[20:21], s[20:21], 0x0
-; GFX9-NEXT: v_writelane_b32 v40, s19, 2
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s2, s18
; GFX9-NEXT: s_mov_b32 s1, s17
; GFX9-NEXT: s_mov_b32 s0, s16
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_swappc_b64 s[30:31], s[20:21]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
@@ -1759,17 +1759,16 @@ define void @caller_void_func_i32_v2float_inreg(i32 inreg %arg0, <2 x float> inr
; GFX11-NEXT: s_or_saveexec_b32 s16, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s16
+; GFX11-NEXT: v_writelane_b32 v40, s3, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_getpc_b64 s[16:17]
; GFX11-NEXT: s_add_u32 s16, s16, caller_void_func_i32_v2float_inreg at gotpcrel32@lo+4
; GFX11-NEXT: s_addc_u32 s17, s17, caller_void_func_i32_v2float_inreg at gotpcrel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v40, s3, 2
; GFX11-NEXT: s_load_b64 s[16:17], s[16:17], 0x0
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -2132,21 +2131,24 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p
; GFX9-NEXT: s_or_saveexec_b64 s[40:41], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[40:41]
+; GFX9-NEXT: v_writelane_b32 v40, s29, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v2, s28
; GFX9-NEXT: global_store_dword v[0:1], v2, off offset:48
; GFX9-NEXT: v_mov_b32_e32 v5, s27
; GFX9-NEXT: v_mov_b32_e32 v4, s26
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v2, s24
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: global_store_dwordx4 v[0:1], v[2:5], off offset:32
-; GFX9-NEXT: v_writelane_b32 v40, s29, 2
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_e32 v5, s23
; GFX9-NEXT: v_mov_b32_e32 v4, s22
; GFX9-NEXT: v_mov_b32_e32 v3, s21
; GFX9-NEXT: v_mov_b32_e32 v2, s20
; GFX9-NEXT: global_store_dwordx4 v[0:1], v[2:5], off offset:16
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_mov_b32_e32 v3, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: s_getpc_b64 s[16:17]
@@ -2155,7 +2157,6 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p
; GFX9-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
; GFX9-NEXT: v_mov_b32_e32 v5, s19
; GFX9-NEXT: v_mov_b32_e32 v4, s18
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_swappc_b64 s[30:31], s[16:17]
@@ -2178,7 +2179,10 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p
; GFX11-NEXT: s_or_saveexec_b32 s26, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s26
+; GFX11-NEXT: v_writelane_b32 v40, s25, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v3, s21
; GFX11-NEXT: v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v9, s19
; GFX11-NEXT: s_getpc_b64 s[20:21]
@@ -2187,20 +2191,16 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p
; GFX11-NEXT: v_dual_mov_b32 v8, s18 :: v_dual_mov_b32 v7, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s16 :: v_dual_mov_b32 v13, s3
; GFX11-NEXT: s_load_b64 s[16:17], s[20:21], 0x0
-; GFX11-NEXT: v_writelane_b32 v40, s25, 2
; GFX11-NEXT: v_dual_mov_b32 v14, s24 :: v_dual_mov_b32 v5, s23
; GFX11-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_mov_b32_e32 v10, s0
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: global_store_b32 v[0:1], v14, off offset:48
; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off offset:32
; GFX11-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
; GFX11-NEXT: global_store_b128 v[0:1], v[10:13], off
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll b/llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
index a2f203a111e18..031f25bec26fe 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
@@ -13,6 +13,7 @@ define amdgpu_gfx void @gfx_func() {
; SDAG-NEXT: s_or_saveexec_b64 s[34:35], -1
; SDAG-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; SDAG-NEXT: s_mov_b64 exec, s[34:35]
+; SDAG-NEXT: s_addk_i32 s32, 0x400
; SDAG-NEXT: v_writelane_b32 v40, s4, 0
; SDAG-NEXT: v_writelane_b32 v40, s5, 1
; SDAG-NEXT: v_writelane_b32 v40, s6, 2
@@ -56,11 +57,10 @@ define amdgpu_gfx void @gfx_func() {
; SDAG-NEXT: v_writelane_b32 v40, s94, 40
; SDAG-NEXT: v_writelane_b32 v40, s95, 41
; SDAG-NEXT: v_writelane_b32 v40, s30, 42
+; SDAG-NEXT: v_writelane_b32 v40, s31, 43
; SDAG-NEXT: s_mov_b32 s35, extern_c_func at abs32@hi
; SDAG-NEXT: s_mov_b32 s34, extern_c_func at abs32@lo
; SDAG-NEXT: s_mov_b64 s[8:9], 0
-; SDAG-NEXT: s_addk_i32 s32, 0x400
-; SDAG-NEXT: v_writelane_b32 v40, s31, 43
; SDAG-NEXT: s_swappc_b64 s[30:31], s[34:35]
; SDAG-NEXT: v_readlane_b32 s30, v40, 42
; SDAG-NEXT: v_readlane_b32 s31, v40, 43
@@ -122,6 +122,7 @@ define amdgpu_gfx void @gfx_func() {
; GISEL-NEXT: s_or_saveexec_b64 s[34:35], -1
; GISEL-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GISEL-NEXT: s_mov_b64 exec, s[34:35]
+; GISEL-NEXT: s_addk_i32 s32, 0x400
; GISEL-NEXT: v_writelane_b32 v40, s4, 0
; GISEL-NEXT: v_writelane_b32 v40, s5, 1
; GISEL-NEXT: v_writelane_b32 v40, s6, 2
@@ -165,11 +166,10 @@ define amdgpu_gfx void @gfx_func() {
; GISEL-NEXT: v_writelane_b32 v40, s94, 40
; GISEL-NEXT: v_writelane_b32 v40, s95, 41
; GISEL-NEXT: v_writelane_b32 v40, s30, 42
+; GISEL-NEXT: v_writelane_b32 v40, s31, 43
; GISEL-NEXT: s_mov_b32 s34, extern_c_func at abs32@lo
; GISEL-NEXT: s_mov_b32 s35, extern_c_func at abs32@hi
; GISEL-NEXT: s_mov_b64 s[8:9], 0
-; GISEL-NEXT: s_addk_i32 s32, 0x400
-; GISEL-NEXT: v_writelane_b32 v40, s31, 43
; GISEL-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GISEL-NEXT: v_readlane_b32 s30, v40, 42
; GISEL-NEXT: v_readlane_b32 s31, v40, 43
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
index 39231558934a7..6d9a7d68b5ca1 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
@@ -133,12 +133,12 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_i1 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_i1 at abs32@lo
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
@@ -162,13 +162,13 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: v_mov_b32_e32 v0, 1
; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 1
; GFX10-NEXT: s_mov_b32 s35, external_void_func_i1 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_i1 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -191,15 +191,14 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: v_mov_b32_e32 v0, 1
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: v_mov_b32_e32 v0, 1
; GFX11-NEXT: s_mov_b32 s1, external_void_func_i1 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_i1 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: scratch_store_b8 off, v0, s32
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -221,13 +220,13 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i1 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i1 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -253,14 +252,14 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s35, external_void_func_i1_signext at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_i1_signext at abs32@lo
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
@@ -284,14 +283,14 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
-; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_i1_signext at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_i1_signext at abs32@lo
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_i1_signext at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_i1_signext at abs32@lo
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
@@ -315,14 +314,14 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: global_load_u8 v0, v[0:1], off glc dlc
-; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_i1_signext at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_i1_signext at abs32@lo
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: global_load_u8 v0, v[0:1], off glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_i1_signext at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_i1_signext at abs32@lo
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-NEXT: scratch_store_b8 off, v0, s32
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -346,14 +345,14 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
-; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i1_signext at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i1_signext at abs32@lo
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
+; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i1_signext at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i1_signext at abs32@lo
; GFX10-SCRATCH-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -382,14 +381,14 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s35, external_void_func_i1_zeroext at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_i1_zeroext at abs32@lo
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
@@ -413,14 +412,14 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
-; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_i1_zeroext at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_i1_zeroext at abs32@lo
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_i1_zeroext at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_i1_zeroext at abs32@lo
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
@@ -444,14 +443,14 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: global_load_u8 v0, v[0:1], off glc dlc
-; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_i1_zeroext at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_i1_zeroext at abs32@lo
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: global_load_u8 v0, v[0:1], off glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_i1_zeroext at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_i1_zeroext at abs32@lo
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-NEXT: scratch_store_b8 off, v0, s32
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -475,14 +474,14 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
-; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i1_zeroext at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i1_zeroext at abs32@lo
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
+; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i1_zeroext at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i1_zeroext at abs32@lo
; GFX10-SCRATCH-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -513,11 +512,11 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -540,12 +539,12 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: v_mov_b32_e32 v0, 0x7b
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 0x7b
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -568,14 +567,14 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7b
-; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8 at abs32@hi
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8 at abs32@lo
; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7b
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8 at abs32@hi
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8 at abs32@lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
@@ -596,14 +595,14 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 {
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7b
-; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8 at abs32@hi
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8 at abs32@lo
; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7b
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8 at abs32@hi
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8 at abs32@lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
@@ -625,12 +624,12 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x7b
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x7b
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -656,14 +655,14 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: global_load_sbyte v0, v[0:1], off glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_signext at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_signext at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: global_load_sbyte v0, v[0:1], off glc
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_signext at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_signext at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -685,14 +684,14 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: global_load_sbyte v0, v[0:1], off glc dlc
-; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_signext at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_signext at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: global_load_sbyte v0, v[0:1], off glc dlc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_signext at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_signext at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -714,16 +713,16 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: global_load_d16_i8 v0, v[0:1], off glc dlc
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8_signext at abs32@hi
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8_signext at abs32@lo
; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: global_load_d16_i8 v0, v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8_signext at abs32@hi
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8_signext at abs32@lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
@@ -743,16 +742,16 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: global_load_i8 v0, v[0:1], off glc dlc
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8_signext at abs32@hi
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8_signext at abs32@lo
; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: global_load_i8 v0, v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8_signext at abs32@hi
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8_signext at abs32@lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
@@ -773,14 +772,14 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: global_load_sbyte v0, v[0:1], off glc dlc
-; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_signext at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_signext at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: global_load_sbyte v0, v[0:1], off glc dlc
+; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_signext at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_signext at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -807,14 +806,14 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_zeroext at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_zeroext at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_zeroext at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_zeroext at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -836,14 +835,14 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
-; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_zeroext at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_zeroext at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_zeroext at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_zeroext at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -865,16 +864,16 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off glc dlc
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8_zeroext at abs32@hi
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8_zeroext at abs32@lo
; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8_zeroext at abs32@hi
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8_zeroext at abs32@lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
@@ -894,16 +893,16 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: global_load_u8 v0, v[0:1], off glc dlc
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8_zeroext at abs32@hi
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8_zeroext at abs32@lo
; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: global_load_u8 v0, v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8_zeroext at abs32@hi
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8_zeroext at abs32@lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
@@ -924,14 +923,14 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
-; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_zeroext at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_zeroext at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
+; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_zeroext at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_zeroext at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -960,11 +959,11 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_i16 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_i16 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -987,12 +986,12 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: v_mov_b32_e32 v0, 0x7b
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 0x7b
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -1015,14 +1014,14 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 {
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7b
-; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i16 at abs32@hi
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i16 at abs32@lo
; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7b
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i16 at abs32@hi
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i16 at abs32@lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
@@ -1043,14 +1042,14 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 {
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7b
-; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i16 at abs32@hi
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i16 at abs32@lo
; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7b
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i16 at abs32@hi
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i16 at abs32@lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
@@ -1072,12 +1071,12 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x7b
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x7b
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -1103,14 +1102,14 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: global_load_ushort v0, v[0:1], off glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_i16_signext at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_i16_signext at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: global_load_ushort v0, v[0:1], off glc
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_i16_signext at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_i16_signext at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -1132,14 +1131,14 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: global_load_ushort v0, v[0:1], off glc dlc
-; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16_signext at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16_signext at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: global_load_ushort v0, v[0:1], off glc dlc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16_signext at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16_signext at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -1161,16 +1160,16 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off glc dlc
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i16_signext at abs32@hi
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i16_signext at abs32@lo
; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i16_signext at abs32@hi
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i16_signext at abs32@lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
@@ -1190,16 +1189,16 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off glc dlc
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i16_signext at abs32@hi
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i16_signext at abs32@lo
; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i16_signext at abs32@hi
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i16_signext at abs32@lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
@@ -1220,14 +1219,14 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[0:1], off glc dlc
-; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16_signext at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16_signext at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[0:1], off glc dlc
+; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16_signext at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16_signext at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -1254,14 +1253,14 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: global_load_ushort v0, v[0:1], off glc
-; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_i16_zeroext at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_i16_zeroext at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: global_load_ushort v0, v[0:1], off glc
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_i16_zeroext at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_i16_zeroext at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -1283,14 +1282,14 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: global_load_ushort v0, v[0:1], off glc dlc
-; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16_zeroext at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16_zeroext at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: global_load_ushort v0, v[0:1], off glc dlc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16_zeroext at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16_zeroext at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -1312,16 +1311,16 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off glc dlc
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i16_zeroext at abs32@hi
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i16_zeroext at abs32@lo
; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i16_zeroext at abs32@hi
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i16_zeroext at abs32@lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
@@ -1341,16 +1340,16 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off glc dlc
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i16_zeroext at abs32@hi
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i16_zeroext at abs32@lo
; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off glc dlc
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i16_zeroext at abs32@hi
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i16_zeroext at abs32@lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
@@ -1371,14 +1370,14 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[0:1], off glc dlc
-; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16_zeroext at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16_zeroext at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[0:1], off glc dlc
+; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16_zeroext at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16_zeroext at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -1407,11 +1406,11 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_i32 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 42
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -1434,12 +1433,12 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: v_mov_b32_e32 v0, 42
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_i32 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_i32 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 42
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_i32 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_i32 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -1462,14 +1461,14 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: v_mov_b32_e32 v0, 42
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_i32 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_i32 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: v_mov_b32_e32 v0, 42
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_i32 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_i32 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -1491,12 +1490,12 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 42
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i32 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i32 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 42
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i32 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i32 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -1524,12 +1523,12 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_i64 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_i64 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b
; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -1552,13 +1551,13 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0x7b
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_i64 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_i64 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -1581,14 +1580,14 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 0x7b :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_i64 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_i64 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -1610,13 +1609,13 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x7b
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i64 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i64 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -1642,15 +1641,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i64 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i64 at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -1672,15 +1671,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i64 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i64 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -1702,17 +1701,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i64 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i64 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -1733,15 +1731,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i64 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i64 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -1770,14 +1768,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i64 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i64 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 1
; GFX9-NEXT: v_mov_b32_e32 v1, 2
; GFX9-NEXT: v_mov_b32_e32 v2, 3
; GFX9-NEXT: v_mov_b32_e32 v3, 4
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -1800,15 +1798,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 1
; GFX10-NEXT: v_mov_b32_e32 v1, 2
; GFX10-NEXT: v_mov_b32_e32 v2, 3
; GFX10-NEXT: v_mov_b32_e32 v3, 4
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i64 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i64 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -1831,15 +1829,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2
; GFX11-NEXT: v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i64 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i64 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -1861,15 +1859,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 3
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 4
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i64 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i64 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -1895,17 +1893,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i64 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i64 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v4, 1
; GFX9-NEXT: v_mov_b32_e32 v5, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -1927,17 +1925,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v4, 1
; GFX10-NEXT: v_mov_b32_e32 v5, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i64 at abs32@hi
-; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i64 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -1959,17 +1957,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v5, 2
; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 1
-; GFX11-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i64 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i64 at abs32@lo
; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -1990,17 +1987,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i64 at abs32@hi
-; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i64 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -2029,19 +2026,19 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i64 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i64 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v4, 1
; GFX9-NEXT: v_mov_b32_e32 v5, 2
; GFX9-NEXT: v_mov_b32_e32 v6, 3
; GFX9-NEXT: v_mov_b32_e32 v7, 4
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -2063,19 +2060,19 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v4, 1
; GFX10-NEXT: v_mov_b32_e32 v5, 2
; GFX10-NEXT: v_mov_b32_e32 v6, 3
-; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_mov_b32_e32 v7, 4
+; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i64 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i64 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -2097,18 +2094,18 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v5, 2
; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 1
-; GFX11-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-NEXT: v_dual_mov_b32 v6, 3 :: v_dual_mov_b32 v7, 4
-; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i64 at abs32@hi
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i64 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -2129,19 +2126,19 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 3
-; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 4
+; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i64 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i64 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -2171,11 +2168,11 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_f16 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_f16 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 0x4400
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -2198,12 +2195,12 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: v_mov_b32_e32 v0, 0x4400
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_f16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_f16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 0x4400
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_f16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_f16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -2226,14 +2223,14 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 {
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x4400
-; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_f16 at abs32@hi
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_f16 at abs32@lo
; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x4400
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_f16 at abs32@hi
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_f16 at abs32@lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
@@ -2254,14 +2251,14 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 {
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x4400
-; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_f16 at abs32@hi
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_f16 at abs32@lo
; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x4400
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_f16 at abs32@hi
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_f16 at abs32@lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
@@ -2283,12 +2280,12 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x4400
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x4400
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -2316,11 +2313,11 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_f32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_f32 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 4.0
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -2343,12 +2340,12 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: v_mov_b32_e32 v0, 4.0
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_f32 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_f32 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 4.0
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_f32 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_f32 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -2371,14 +2368,14 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: v_mov_b32_e32 v0, 4.0
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_f32 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_f32 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: v_mov_b32_e32 v0, 4.0
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_f32 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_f32 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -2400,12 +2397,12 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 4.0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f32 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f32 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 4.0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f32 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f32 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -2433,12 +2430,12 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2f32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2f32 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 1.0
; GFX9-NEXT: v_mov_b32_e32 v1, 2.0
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -2461,13 +2458,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 1.0
; GFX10-NEXT: v_mov_b32_e32 v1, 2.0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f32 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -2490,14 +2487,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 1.0 :: v_dual_mov_b32 v1, 2.0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f32 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -2519,13 +2516,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2.0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f32 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -2553,13 +2550,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f32 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 1.0
; GFX9-NEXT: v_mov_b32_e32 v1, 2.0
; GFX9-NEXT: v_mov_b32_e32 v2, 4.0
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -2582,14 +2579,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 1.0
; GFX10-NEXT: v_mov_b32_e32 v1, 2.0
; GFX10-NEXT: v_mov_b32_e32 v2, 4.0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f32 at abs32@hi
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f32 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -2612,15 +2609,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 1.0 :: v_dual_mov_b32 v1, 2.0
; GFX11-NEXT: v_mov_b32_e32 v2, 4.0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f32 at abs32@hi
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f32 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -2642,14 +2639,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 4.0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f32 at abs32@hi
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f32 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -2677,6 +2674,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v5f32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v5f32 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 1.0
@@ -2684,8 +2683,6 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 {
; GFX9-NEXT: v_mov_b32_e32 v2, 4.0
; GFX9-NEXT: v_mov_b32_e32 v3, -1.0
; GFX9-NEXT: v_mov_b32_e32 v4, 0.5
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -2708,16 +2705,16 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 1.0
; GFX10-NEXT: v_mov_b32_e32 v1, 2.0
; GFX10-NEXT: v_mov_b32_e32 v2, 4.0
; GFX10-NEXT: v_mov_b32_e32 v3, -1.0
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 0.5
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5f32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5f32 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -2740,16 +2737,16 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 1.0 :: v_dual_mov_b32 v1, 2.0
; GFX11-NEXT: v_dual_mov_b32 v2, 4.0 :: v_dual_mov_b32 v3, -1.0
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_mov_b32_e32 v4, 0.5
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5f32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5f32 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -2771,16 +2768,16 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 4.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, -1.0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 0.5
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5f32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5f32 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -2808,12 +2805,12 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_f64 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_f64 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0x40100000
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -2836,13 +2833,13 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0x40100000
; GFX10-NEXT: s_mov_b32 s35, external_void_func_f64 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_f64 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -2865,14 +2862,14 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x40100000
; GFX11-NEXT: s_mov_b32 s1, external_void_func_f64 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_f64 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -2894,13 +2891,13 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0x40100000
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f64 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f64 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -2928,14 +2925,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2f64 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2f64 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 2.0
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mov_b32_e32 v3, 0x40100000
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -2958,15 +2955,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 2.0
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0x40100000
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f64 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f64 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -2989,15 +2986,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 2.0
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x40100000
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f64 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f64 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -3019,15 +3016,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 0x40100000
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f64 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f64 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -3055,6 +3052,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f64 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f64 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 0
@@ -3063,8 +3062,6 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 {
; GFX9-NEXT: v_mov_b32_e32 v3, 0x40100000
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0x40200000
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -3087,17 +3084,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 2.0
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0x40100000
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0x40200000
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f64 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f64 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -3120,16 +3117,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 2.0
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x40100000
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0x40200000
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f64 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f64 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -3151,17 +3148,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2.0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 0x40100000
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 0x40200000
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f64 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f64 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -3187,16 +3184,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: global_load_ushort v0, v[0:1], off
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_mov_b32_e32 v1, 8
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i8 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i8 at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
@@ -3220,16 +3217,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i8 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i8 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: global_load_ushort v0, v[0:1], off
; GFX10-NEXT: v_mov_b32_e32 v1, 8
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
@@ -3253,15 +3250,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v2i8 at abs32@hi
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v2i8 at abs32@lo
-; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -3286,15 +3283,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v2i8 at abs32@hi
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v2i8 at abs32@lo
-; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -3320,16 +3317,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i8 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i8 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[0:1], off
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 8
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -3358,15 +3355,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: global_load_dword v0, v[0:1], off
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i8 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i8 at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -3391,15 +3388,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i8 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i8 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: global_load_dword v0, v[0:1], off
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -3424,15 +3421,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i8 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i8 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: global_load_b32 v0, v[0:1], off
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -3457,15 +3454,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i8 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i8 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -3495,15 +3492,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: global_load_dword v0, v[0:1], off
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i8 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i8 at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0
@@ -3529,15 +3526,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i8 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i8 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: global_load_dword v0, v[0:1], off
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -3563,15 +3560,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i8 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i8 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: global_load_b32 v0, v[0:1], off
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -3597,15 +3594,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i8 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i8 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -3636,15 +3633,15 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: global_load_dwordx2 v[5:6], v[0:1], off
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v5i8 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v5i8 at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v5
@@ -3672,15 +3669,15 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i8 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5i8 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: global_load_dwordx2 v[5:6], v[0:1], off
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v5
@@ -3708,15 +3705,15 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5i8 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5i8 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: global_load_b64 v[5:6], v[0:1], off
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v5
@@ -3744,15 +3741,15 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i8 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5i8 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[5:6], v[0:1], off
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v5
@@ -3785,15 +3782,15 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i8 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i8 at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_e32 v8, 8, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -3824,15 +3821,15 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i8 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i8 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v8, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -3863,15 +3860,15 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i8 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8i8 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshrrev_b32_e32 v8, 8, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -3901,15 +3898,15 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i8 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i8 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v8, 8, v0
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -3945,18 +3942,18 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v4, 16
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: global_load_dwordx4 v[16:19], v[4:5], off
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i8 at abs32@hi
+; GFX9-NEXT: global_load_dwordx4 v[16:19], v[4:5], off
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i8 at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v0
@@ -4016,19 +4013,19 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 16
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0
-; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v32i8 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v32i8 at abs32@lo
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX10-NEXT: global_load_dwordx4 v[16:19], v[4:5], off
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_lshrrev_b32_e32 v35, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v0
@@ -4088,17 +4085,18 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 16
; GFX11-NEXT: v_mov_b32_e32 v5, 0
-; GFX11-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v32i8 at abs32@hi
-; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v32i8 at abs32@lo
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off
; GFX11-NEXT: global_load_b128 v[16:19], v[4:5], off
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_lshrrev_b32_e32 v35, 8, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v0
@@ -4155,19 +4153,19 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 16
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v32i8 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v32i8 at abs32@lo
; GFX10-SCRATCH-NEXT: s_clause 0x1
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[16:19], v[4:5], off
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(1)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v35, 8, v0
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v36, 16, v0
@@ -4233,17 +4231,17 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v42, s34, 2
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX9-NEXT: v_writelane_b32 v42, s30, 0
+; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v40, 0
; GFX9-NEXT: v_mov_b32_e32 v41, 0
; GFX9-NEXT: global_load_ubyte v0, v[40:41], off
-; GFX9-NEXT: v_writelane_b32 v42, s34, 2
-; GFX9-NEXT: v_writelane_b32 v42, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_ret at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_ret at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: global_store_byte v[40:41], v0, off
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
@@ -4269,17 +4267,17 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v42, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX10-NEXT: v_writelane_b32 v42, s30, 0
+; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v40, 0
; GFX10-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-NEXT: v_writelane_b32 v42, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_ret at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_ret at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: global_load_ubyte v0, v[40:41], off
-; GFX10-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: global_store_byte v[40:41], v0, off
; GFX10-NEXT: s_clause 0x1
@@ -4305,18 +4303,19 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8_ret at abs32@hi
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8_ret at abs32@lo
-; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: global_load_d16_u8 v0, v[40:41], off
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-TRUE16-NEXT: global_store_b8 v[40:41], v0, off
; GFX11-TRUE16-NEXT: s_clause 0x1
@@ -4341,18 +4340,19 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8_ret at abs32@hi
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8_ret at abs32@lo
-; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: global_load_u8 v0, v[40:41], off
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-FAKE16-NEXT: global_store_b8 v[40:41], v0, off
; GFX11-FAKE16-NEXT: s_clause 0x1
@@ -4378,17 +4378,17 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_ret at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_ret at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[40:41], off
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: global_store_byte v[40:41], v0, off
; GFX10-SCRATCH-NEXT: s_clause 0x1
@@ -4421,18 +4421,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v42, s34, 2
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX9-NEXT: v_writelane_b32 v42, s30, 0
+; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v40, 0
; GFX9-NEXT: v_mov_b32_e32 v41, 0
; GFX9-NEXT: global_load_ushort v0, v[40:41], off
-; GFX9-NEXT: v_writelane_b32 v42, s34, 2
; GFX9-NEXT: v_mov_b32_e32 v1, 8
-; GFX9-NEXT: v_writelane_b32 v42, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i8_ret at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i8_ret at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
@@ -4462,18 +4462,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v42, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX10-NEXT: v_writelane_b32 v42, s30, 0
+; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v40, 0
; GFX10-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-NEXT: v_writelane_b32 v42, s34, 2
; GFX10-NEXT: v_mov_b32_e32 v1, 8
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i8_ret at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i8_ret at abs32@lo
; GFX10-NEXT: global_load_ushort v0, v[40:41], off
-; GFX10-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
@@ -4503,18 +4503,19 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v2i8_ret at abs32@hi
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v2i8_ret at abs32@lo
-; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[40:41], off
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -4547,18 +4548,19 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v2i8_ret at abs32@hi
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v2i8_ret at abs32@lo
-; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: global_load_u16 v0, v[40:41], off
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
@@ -4591,18 +4593,18 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 8
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i8_ret at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i8_ret at abs32@lo
; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[40:41], off
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -4639,17 +4641,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v42, s34, 2
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX9-NEXT: v_writelane_b32 v42, s30, 0
+; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v40, 0
; GFX9-NEXT: v_mov_b32_e32 v41, 0
; GFX9-NEXT: global_load_dword v0, v[40:41], off
-; GFX9-NEXT: v_writelane_b32 v42, s34, 2
-; GFX9-NEXT: v_writelane_b32 v42, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -4683,17 +4685,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v42, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX10-NEXT: v_writelane_b32 v42, s30, 0
+; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v40, 0
; GFX10-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-NEXT: v_writelane_b32 v42, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: global_load_dword v0, v[40:41], off
-; GFX10-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -4727,18 +4729,19 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret at abs32@hi
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret at abs32@lo
-; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
-; GFX11-TRUE16-NEXT: global_load_b32 v0, v[40:41], off
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
+; GFX11-TRUE16-NEXT: global_load_b32 v0, v[40:41], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -4774,18 +4777,19 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret at abs32@hi
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret at abs32@lo
-; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: global_load_b32 v0, v[40:41], off
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -4822,17 +4826,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: global_load_dword v0, v[40:41], off
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -4873,17 +4877,17 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v42, s34, 2
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX9-NEXT: v_writelane_b32 v42, s30, 0
+; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v40, 0
; GFX9-NEXT: v_mov_b32_e32 v41, 0
; GFX9-NEXT: global_load_dword v0, v[40:41], off
-; GFX9-NEXT: v_writelane_b32 v42, s34, 2
-; GFX9-NEXT: v_writelane_b32 v42, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i8_ret at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i8_ret at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v0
@@ -4918,17 +4922,17 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v42, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX10-NEXT: v_writelane_b32 v42, s30, 0
+; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v40, 0
; GFX10-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-NEXT: v_writelane_b32 v42, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i8_ret at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i8_ret at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: global_load_dword v0, v[40:41], off
-; GFX10-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -4963,18 +4967,19 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v4i8_ret at abs32@hi
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v4i8_ret at abs32@lo
-; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[40:41], off
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -5011,18 +5016,19 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v4i8_ret at abs32@hi
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v4i8_ret at abs32@lo
-; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: global_load_b32 v0, v[40:41], off
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -5064,17 +5070,17 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i8_ret at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i8_ret at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: global_load_dword v0, v[40:41], off
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -5116,17 +5122,17 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v42, s34, 2
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX9-NEXT: v_writelane_b32 v42, s30, 0
+; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v40, 0
; GFX9-NEXT: v_mov_b32_e32 v41, 0
; GFX9-NEXT: global_load_dwordx2 v[5:6], v[40:41], off
-; GFX9-NEXT: v_writelane_b32 v42, s34, 2
-; GFX9-NEXT: v_writelane_b32 v42, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v5i8_ret at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v5i8_ret at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v5
@@ -5166,17 +5172,17 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v42, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX10-NEXT: v_writelane_b32 v42, s30, 0
+; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v40, 0
; GFX10-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-NEXT: v_writelane_b32 v42, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i8_ret at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5i8_ret at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: global_load_dwordx2 v[5:6], v[40:41], off
-; GFX10-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v5
@@ -5216,18 +5222,19 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v5i8_ret at abs32@hi
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v5i8_ret at abs32@lo
-; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: global_load_b64 v[5:6], v[40:41], off
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v5
@@ -5268,18 +5275,19 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v5i8_ret at abs32@hi
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v5i8_ret at abs32@lo
-; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: global_load_b64 v[5:6], v[40:41], off
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v5
@@ -5326,17 +5334,17 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i8_ret at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5i8_ret at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[5:6], v[40:41], off
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v5
@@ -5383,17 +5391,17 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v42, s34, 2
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX9-NEXT: v_writelane_b32 v42, s30, 0
+; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v40, 0
; GFX9-NEXT: v_mov_b32_e32 v41, 0
; GFX9-NEXT: global_load_dwordx2 v[0:1], v[40:41], off
-; GFX9-NEXT: v_writelane_b32 v42, s34, 2
-; GFX9-NEXT: v_writelane_b32 v42, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i8_ret at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i8_ret at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_e32 v8, 8, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -5438,17 +5446,17 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v42, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX10-NEXT: v_writelane_b32 v42, s30, 0
+; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v40, 0
; GFX10-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-NEXT: v_writelane_b32 v42, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i8_ret at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i8_ret at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: global_load_dwordx2 v[0:1], v[40:41], off
-; GFX10-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v8, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -5493,18 +5501,19 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v8i8_ret at abs32@hi
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v8i8_ret at abs32@lo
-; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v[40:41], off
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 8, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -5550,18 +5559,19 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v8i8_ret at abs32@hi
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v8i8_ret at abs32@lo
-; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: global_load_b64 v[0:1], v[40:41], off
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 8, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -5615,17 +5625,17 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i8_ret at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i8_ret at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[40:41], off
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v8, 8, v0
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v2, 16, v0
@@ -5677,22 +5687,22 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v44, s34, 2
+; GFX9-NEXT: s_addk_i32 s32, 0x800
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX9-NEXT: v_writelane_b32 v44, s30, 0
+; GFX9-NEXT: v_writelane_b32 v44, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v40, 0
; GFX9-NEXT: v_mov_b32_e32 v42, 16
; GFX9-NEXT: v_mov_b32_e32 v41, 0
; GFX9-NEXT: v_mov_b32_e32 v43, 0
; GFX9-NEXT: global_load_dwordx4 v[0:3], v[40:41], off
; GFX9-NEXT: global_load_dwordx4 v[16:19], v[42:43], off
-; GFX9-NEXT: v_writelane_b32 v44, s34, 2
-; GFX9-NEXT: v_writelane_b32 v44, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x800
-; GFX9-NEXT: v_writelane_b32 v44, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v0
@@ -5799,23 +5809,23 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX10-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v44, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x400
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v43, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX10-NEXT: v_writelane_b32 v44, s30, 0
+; GFX10-NEXT: v_writelane_b32 v44, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v40, 0
; GFX10-NEXT: v_mov_b32_e32 v42, 16
; GFX10-NEXT: v_mov_b32_e32 v41, 0
; GFX10-NEXT: v_mov_b32_e32 v43, 0
-; GFX10-NEXT: v_writelane_b32 v44, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret at abs32@lo
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx4 v[0:3], v[40:41], off
; GFX10-NEXT: global_load_dwordx4 v[16:19], v[42:43], off
-; GFX10-NEXT: v_writelane_b32 v44, s30, 0
-; GFX10-NEXT: s_addk_i32 s32, 0x400
-; GFX10-NEXT: v_writelane_b32 v44, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_lshrrev_b32_e32 v35, 8, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v0
@@ -5922,22 +5932,26 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s0, 2
+; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 32
; GFX11-TRUE16-NEXT: s_clause 0x3
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 offset:8
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:4
+; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s33
+; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s31, 1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v41, 0 :: v_dual_mov_b32 v42, 16
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v43, 0
-; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s0, 2
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret at abs32@hi
-; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v[40:41], off
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret at abs32@lo
+; GFX11-TRUE16-NEXT: s_clause 0x1
+; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v[40:41], off
; GFX11-TRUE16-NEXT: global_load_b128 v[16:19], v[42:43], off
-; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s30, 0
-; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 32
-; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s31, 1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 8, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v0
@@ -6049,22 +6063,26 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s0, 2
+; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 32
; GFX11-FAKE16-NEXT: s_clause 0x3
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:12
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 offset:8
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:4
+; GFX11-FAKE16-NEXT: ; meta instruction
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s33
+; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s31, 1
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v41, 0 :: v_dual_mov_b32 v42, 16
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v43, 0
-; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s0, 2
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret at abs32@hi
-; GFX11-FAKE16-NEXT: global_load_b128 v[0:3], v[40:41], off
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret at abs32@lo
+; GFX11-FAKE16-NEXT: s_clause 0x1
+; GFX11-FAKE16-NEXT: global_load_b128 v[0:3], v[40:41], off
; GFX11-FAKE16-NEXT: global_load_b128 v[16:19], v[42:43], off
-; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s30, 0
-; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 32
-; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s31, 1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 8, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v0
@@ -6201,23 +6219,23 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v44, s33 offset:16 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:12 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 offset:8 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v43, s33 ; 4-byte Folded Spill
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v42, 16
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v43, 0
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s0, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret at abs32@lo
; GFX10-SCRATCH-NEXT: s_clause 0x1
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[40:41], off
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[16:19], v[42:43], off
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s30, 0
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s31, 1
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(1)
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v35, 8, v0
; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v36, 16, v0
@@ -6332,13 +6350,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: global_load_dword v0, v[0:1], off
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -6360,13 +6378,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: global_load_dword v0, v[0:1], off
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: global_load_dword v0, v[0:1], off
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -6388,15 +6406,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -6417,13 +6435,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -6450,13 +6468,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -6478,13 +6496,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -6506,15 +6524,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -6535,13 +6553,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -6568,13 +6586,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -6596,13 +6614,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -6624,15 +6642,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -6653,13 +6671,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -6688,12 +6706,12 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i16 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i16 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 0x20001
; GFX9-NEXT: v_mov_b32_e32 v1, 3
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -6716,13 +6734,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0x20001
; GFX10-NEXT: v_mov_b32_e32 v1, 3
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i16 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -6745,14 +6763,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 0x20001 :: v_dual_mov_b32 v1, 3
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -6774,13 +6792,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x20001
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 3
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i16 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -6808,12 +6826,12 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f16 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f16 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 0x40003c00
; GFX9-NEXT: v_mov_b32_e32 v1, 0x4400
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -6836,13 +6854,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0x40003c00
; GFX10-NEXT: v_mov_b32_e32 v1, 0x4400
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f16 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -6865,15 +6883,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_mov_b32_e32 v0, 0x40003c00
; GFX11-NEXT: v_mov_b32_e32 v1, 0x4400
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f16 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -6895,13 +6913,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x40003c00
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0x4400
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f16 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -6927,13 +6945,13 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -6955,13 +6973,13 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -6983,15 +7001,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -7012,13 +7030,13 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -7047,12 +7065,12 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i16 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i16 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 0x20001
; GFX9-NEXT: v_mov_b32_e32 v1, 0x40003
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -7075,13 +7093,13 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0x20001
; GFX10-NEXT: v_mov_b32_e32 v1, 0x40003
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i16 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -7104,15 +7122,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_mov_b32_e32 v0, 0x20001
; GFX11-NEXT: v_mov_b32_e32 v1, 0x40003
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i16 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -7134,13 +7152,13 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x20001
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0x40003
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i16 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -7166,13 +7184,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2f16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2f16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: global_load_dword v0, v[0:1], off
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2f16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2f16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -7194,13 +7212,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: global_load_dword v0, v[0:1], off
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: global_load_dword v0, v[0:1], off
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -7222,15 +7240,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -7251,13 +7269,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -7284,13 +7302,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i32 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i32 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i32 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i32 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -7312,13 +7330,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i32 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i32 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -7340,15 +7358,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -7369,13 +7387,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i32 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i32 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -7404,12 +7422,12 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i32 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 1
; GFX9-NEXT: v_mov_b32_e32 v1, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -7432,13 +7450,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 1
; GFX10-NEXT: v_mov_b32_e32 v1, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i32 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -7461,14 +7479,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -7490,13 +7508,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -7524,13 +7542,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i32 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 3
; GFX9-NEXT: v_mov_b32_e32 v1, 4
; GFX9-NEXT: v_mov_b32_e32 v2, 5
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -7553,14 +7571,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 3
; GFX10-NEXT: v_mov_b32_e32 v1, 4
; GFX10-NEXT: v_mov_b32_e32 v2, 5
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32 at abs32@hi
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -7583,15 +7601,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 4
; GFX11-NEXT: v_mov_b32_e32 v2, 5
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32 at abs32@hi
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -7613,14 +7631,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 3
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 4
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 5
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32 at abs32@hi
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -7648,14 +7666,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i32_i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i32_i32 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 3
; GFX9-NEXT: v_mov_b32_e32 v1, 4
; GFX9-NEXT: v_mov_b32_e32 v2, 5
; GFX9-NEXT: v_mov_b32_e32 v3, 6
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -7678,15 +7696,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 3
; GFX10-NEXT: v_mov_b32_e32 v1, 4
; GFX10-NEXT: v_mov_b32_e32 v2, 5
; GFX10-NEXT: v_mov_b32_e32 v3, 6
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32_i32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32_i32 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -7709,15 +7727,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 4
; GFX11-NEXT: v_dual_mov_b32 v2, 5 :: v_dual_mov_b32 v3, 6
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -7739,15 +7757,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 3
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 4
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 5
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 6
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -7773,13 +7791,13 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i32 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i32 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i32 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i32 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -7801,13 +7819,13 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
-; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i32 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i32 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -7829,15 +7847,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i32 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i32 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i32 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i32 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -7858,13 +7876,13 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i32 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i32 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i32 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i32 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -7893,14 +7911,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i32 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 1
; GFX9-NEXT: v_mov_b32_e32 v1, 2
; GFX9-NEXT: v_mov_b32_e32 v2, 3
; GFX9-NEXT: v_mov_b32_e32 v3, 4
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -7923,15 +7941,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 1
; GFX10-NEXT: v_mov_b32_e32 v1, 2
; GFX10-NEXT: v_mov_b32_e32 v2, 3
; GFX10-NEXT: v_mov_b32_e32 v3, 4
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i32 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -7954,15 +7972,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2
; GFX11-NEXT: v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i32 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -7984,15 +8002,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 3
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 4
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -8020,6 +8038,8 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v5i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v5i32 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 1
@@ -8027,8 +8047,6 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 {
; GFX9-NEXT: v_mov_b32_e32 v2, 3
; GFX9-NEXT: v_mov_b32_e32 v3, 4
; GFX9-NEXT: v_mov_b32_e32 v4, 5
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -8051,16 +8069,16 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 1
; GFX10-NEXT: v_mov_b32_e32 v1, 2
; GFX10-NEXT: v_mov_b32_e32 v2, 3
; GFX10-NEXT: v_mov_b32_e32 v3, 4
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 5
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5i32 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -8083,16 +8101,16 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2
; GFX11-NEXT: v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_mov_b32_e32 v4, 5
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5i32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5i32 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -8114,16 +8132,16 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 3
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 4
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 5
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -8150,16 +8168,16 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
-; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
+; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx4 v[0:3], v8, s[34:35]
; GFX9-NEXT: global_load_dwordx4 v[4:7], v8, s[34:35] offset:16
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i32 at abs32@lo
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -8182,17 +8200,18 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: v_mov_b32_e32 v8, 0
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx4 v[0:3], v8, s[34:35]
; GFX10-NEXT: global_load_dwordx4 v[4:7], v8, s[34:35] offset:16
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i32 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -8215,19 +8234,19 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX11-NEXT: v_mov_b32_e32 v4, 0
-; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_load_b128 v[0:3], v4, s[0:1]
; GFX11-NEXT: global_load_b128 v[4:7], v4, s[0:1] offset:16
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8i32 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -8249,17 +8268,18 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v8, 0
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: s_clause 0x1
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v8, s[0:1]
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[4:7], v8, s[0:1] offset:16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -8289,6 +8309,8 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i32 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 1
@@ -8299,8 +8321,6 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 {
; GFX9-NEXT: v_mov_b32_e32 v5, 6
; GFX9-NEXT: v_mov_b32_e32 v6, 7
; GFX9-NEXT: v_mov_b32_e32 v7, 8
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -8323,19 +8343,19 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 1
; GFX10-NEXT: v_mov_b32_e32 v1, 2
; GFX10-NEXT: v_mov_b32_e32 v2, 3
; GFX10-NEXT: v_mov_b32_e32 v3, 4
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 5
; GFX10-NEXT: v_mov_b32_e32 v5, 6
; GFX10-NEXT: v_mov_b32_e32 v6, 7
; GFX10-NEXT: v_mov_b32_e32 v7, 8
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i32 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -8358,17 +8378,17 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2
; GFX11-NEXT: v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_dual_mov_b32 v4, 5 :: v_dual_mov_b32 v5, 6
; GFX11-NEXT: v_dual_mov_b32 v6, 7 :: v_dual_mov_b32 v7, 8
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8i32 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -8390,19 +8410,19 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 3
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 4
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 5
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 6
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 7
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 8
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -8429,10 +8449,11 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
-; GFX9-NEXT: v_mov_b32_e32 v16, 0
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
+; GFX9-NEXT: v_mov_b32_e32 v16, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx4 v[0:3], v16, s[34:35]
; GFX9-NEXT: global_load_dwordx4 v[4:7], v16, s[34:35] offset:16
@@ -8440,7 +8461,6 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 {
; GFX9-NEXT: global_load_dwordx4 v[12:15], v16, s[34:35] offset:48
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v16i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v16i32 at abs32@lo
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -8463,19 +8483,20 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: v_mov_b32_e32 v16, 0
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x3
; GFX10-NEXT: global_load_dwordx4 v[0:3], v16, s[34:35]
; GFX10-NEXT: global_load_dwordx4 v[4:7], v16, s[34:35] offset:16
; GFX10-NEXT: global_load_dwordx4 v[8:11], v16, s[34:35] offset:32
; GFX10-NEXT: global_load_dwordx4 v[12:15], v16, s[34:35] offset:48
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16i32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16i32 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -8498,21 +8519,21 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX11-NEXT: v_mov_b32_e32 v12, 0
-; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: global_load_b128 v[0:3], v12, s[0:1]
; GFX11-NEXT: global_load_b128 v[4:7], v12, s[0:1] offset:16
; GFX11-NEXT: global_load_b128 v[8:11], v12, s[0:1] offset:32
; GFX11-NEXT: global_load_b128 v[12:15], v12, s[0:1] offset:48
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16i32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v16i32 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -8534,19 +8555,20 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v16, 0
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: s_clause 0x3
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v16, s[0:1]
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[4:7], v16, s[0:1] offset:16
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[8:11], v16, s[0:1] offset:32
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[12:15], v16, s[0:1] offset:48
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16i32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -8575,10 +8597,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
-; GFX9-NEXT: v_mov_b32_e32 v28, 0
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
+; GFX9-NEXT: v_mov_b32_e32 v28, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx4 v[0:3], v28, s[34:35]
; GFX9-NEXT: global_load_dwordx4 v[4:7], v28, s[34:35] offset:16
@@ -8591,7 +8614,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX9-NEXT: global_load_dwordx4 v[28:31], v28, s[34:35] offset:112
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i32 at abs32@lo
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -8614,9 +8636,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: v_mov_b32_e32 v32, 0
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x7
; GFX10-NEXT: global_load_dwordx4 v[0:3], v32, s[34:35]
@@ -8627,10 +8651,9 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX10-NEXT: global_load_dwordx4 v[20:23], v32, s[34:35] offset:80
; GFX10-NEXT: global_load_dwordx4 v[24:27], v32, s[34:35] offset:96
; GFX10-NEXT: global_load_dwordx4 v[28:31], v32, s[34:35] offset:112
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v32i32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v32i32 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -8653,9 +8676,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX11-NEXT: v_mov_b32_e32 v28, 0
-; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_clause 0x7
; GFX11-NEXT: global_load_b128 v[0:3], v28, s[0:1]
@@ -8666,12 +8691,10 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX11-NEXT: global_load_b128 v[20:23], v28, s[0:1] offset:80
; GFX11-NEXT: global_load_b128 v[24:27], v28, s[0:1] offset:96
; GFX11-NEXT: global_load_b128 v[28:31], v28, s[0:1] offset:112
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v32i32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v32i32 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -8693,9 +8716,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v32, 0
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: s_clause 0x7
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v32, s[0:1]
@@ -8706,10 +8731,9 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 {
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[20:23], v32, s[0:1] offset:80
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[24:27], v32, s[0:1] offset:96
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[28:31], v32, s[0:1] offset:112
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v32i32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v32i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -8738,10 +8762,12 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX9-NEXT: v_mov_b32_e32 v28, 0
; GFX9-NEXT: global_load_dword v32, v[0:1], off
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx4 v[0:3], v28, s[34:35]
; GFX9-NEXT: global_load_dwordx4 v[4:7], v28, s[34:35] offset:16
@@ -8752,10 +8778,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX9-NEXT: global_load_dwordx4 v[24:27], v28, s[34:35] offset:96
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: global_load_dwordx4 v[28:31], v28, s[34:35] offset:112
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i32_i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i32_i32 at abs32@lo
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
@@ -8780,9 +8804,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: v_mov_b32_e32 v32, 0
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: global_load_dword v33, v[0:1], off
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x7
@@ -8794,10 +8820,9 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX10-NEXT: global_load_dwordx4 v[20:23], v32, s[34:35] offset:80
; GFX10-NEXT: global_load_dwordx4 v[24:27], v32, s[34:35] offset:96
; GFX10-NEXT: global_load_dwordx4 v[28:31], v32, s[34:35] offset:112
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v32i32_i32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v32i32_i32 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(8)
; GFX10-NEXT: buffer_store_dword v33, off, s[0:3], s32
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
@@ -8822,9 +8847,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX11-NEXT: v_mov_b32_e32 v28, 0
-; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: global_load_b32 v32, v[0:1], off
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_clause 0x7
@@ -8836,10 +8863,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX11-NEXT: global_load_b128 v[20:23], v28, s[0:1] offset:80
; GFX11-NEXT: global_load_b128 v[24:27], v28, s[0:1] offset:96
; GFX11-NEXT: global_load_b128 v[28:31], v28, s[0:1] offset:112
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v32i32_i32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v32i32_i32 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_waitcnt vmcnt(8)
; GFX11-NEXT: scratch_store_b32 off, v32, s32
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -8864,9 +8889,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v32, 0
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: global_load_dword v33, v[0:1], off
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: s_clause 0x7
@@ -8878,10 +8905,9 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[20:23], v32, s[0:1] offset:80
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[24:27], v32, s[0:1] offset:96
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[28:31], v32, s[0:1] offset:112
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v32i32_i32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v32i32_i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(8)
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v33, s32
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -8913,15 +8939,15 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v42, s34, 2
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: v_writelane_b32 v42, s30, 0
+; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v40, v0
; GFX9-NEXT: s_mov_b32 s35, external_i32_func_i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_i32_func_i32 at abs32@lo
; GFX9-NEXT: v_mov_b32_e32 v0, 42
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v41, v1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: global_store_dword v[40:41], v0, off
@@ -8949,16 +8975,16 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v42, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX10-NEXT: v_writelane_b32 v42, s30, 0
+; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v40, v0
; GFX10-NEXT: v_mov_b32_e32 v0, 42
; GFX10-NEXT: s_mov_b32 s35, external_i32_func_i32 at abs32@hi
-; GFX10-NEXT: v_writelane_b32 v42, s30, 0
; GFX10-NEXT: s_mov_b32 s34, external_i32_func_i32 at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_mov_b32_e32 v41, v1
-; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: global_store_dword v[40:41], v0, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
@@ -8986,16 +9012,18 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX11-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v42, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s33
+; GFX11-NEXT: v_writelane_b32 v42, s30, 0
+; GFX11-NEXT: v_writelane_b32 v42, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v41, v1 :: v_dual_mov_b32 v40, v0
; GFX11-NEXT: v_mov_b32_e32 v0, 42
-; GFX11-NEXT: v_writelane_b32 v42, s30, 0
; GFX11-NEXT: s_mov_b32 s1, external_i32_func_i32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_i32_func_i32 at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v42, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: global_store_b32 v[40:41], v0, off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
@@ -9023,16 +9051,16 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, v0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 42
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_i32_func_i32 at abs32@hi
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_i32_func_i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, v1
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: global_store_dword v[40:41], v0, off
; GFX10-SCRATCH-NEXT: s_waitcnt_vscnt null, 0x0
@@ -9065,16 +9093,16 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_ubyte v0, v2, s[34:35]
; GFX9-NEXT: global_load_dword v1, v2, s[34:35] offset:4
; GFX9-NEXT: s_mov_b32 s35, external_void_func_struct_i8_i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_struct_i8_i32 at abs32@lo
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -9097,17 +9125,18 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_ubyte v0, v2, s[34:35]
; GFX10-NEXT: global_load_dword v1, v2, s[34:35] offset:4
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 s35, external_void_func_struct_i8_i32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_struct_i8_i32 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -9130,19 +9159,19 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: global_load_d16_u8 v0, v1, s[0:1]
; GFX11-TRUE16-NEXT: global_load_b32 v1, v1, s[0:1] offset:4
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_struct_i8_i32 at abs32@hi
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_struct_i8_i32 at abs32@lo
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
@@ -9163,19 +9192,19 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: global_load_u8 v0, v1, s[0:1]
; GFX11-FAKE16-NEXT: global_load_b32 v1, v1, s[0:1] offset:4
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_struct_i8_i32 at abs32@hi
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_struct_i8_i32 at abs32@lo
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
@@ -9197,17 +9226,18 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: s_clause 0x1
; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v2, s[0:1]
; GFX10-SCRATCH-NEXT: global_load_dword v1, v2, s[0:1] offset:4
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_struct_i8_i32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_struct_i8_i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -9235,17 +9265,17 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: v_mov_b32_e32 v0, 3
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: v_mov_b32_e32 v0, 3
; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s33
; GFX9-NEXT: v_mov_b32_e32 v0, 8
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; GFX9-NEXT: s_mov_b32 s35, external_void_func_byval_struct_i8_i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_byval_struct_i8_i32 at abs32@lo
; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, s33
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -9268,16 +9298,16 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 3
; GFX10-NEXT: v_mov_b32_e32 v1, 8
; GFX10-NEXT: s_mov_b32 s35, external_void_func_byval_struct_i8_i32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_byval_struct_i8_i32 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s33
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:4
; GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -9300,19 +9330,18 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:8 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 3
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 8
; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_byval_struct_i8_i32 at abs32@hi
; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_byval_struct_i8_i32 at abs32@lo
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b8 off, v0, s33
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v1, s33 offset:4
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s33
-; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-TRUE16-NEXT: s_mov_b32 s32, s33
@@ -9333,18 +9362,17 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:8 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8
; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_byval_struct_i8_i32 at abs32@hi
; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_byval_struct_i8_i32 at abs32@lo
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_store_b8 off, v0, s33
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v1, s33 offset:4
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s33
-; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-FAKE16-NEXT: s_mov_b32 s32, s33
@@ -9366,16 +9394,16 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 3
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 8
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_byval_struct_i8_i32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_byval_struct_i8_i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s33
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v1, s33 offset:4
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, s33
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -9406,19 +9434,19 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x800
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 3
; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s33
; GFX9-NEXT: v_mov_b32_e32 v0, 8
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, s33
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@lo
; GFX9-NEXT: v_add_u32_e32 v0, 8, v0
; GFX9-NEXT: v_lshrrev_b32_e64 v1, 6, s33
-; GFX9-NEXT: s_addk_i32 s32, 0x800
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: buffer_load_ubyte v0, off, s[0:3], s33 offset:8
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:12
@@ -9447,19 +9475,19 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x400
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 3
; GFX10-NEXT: v_mov_b32_e32 v1, 8
-; GFX10-NEXT: v_writelane_b32 v40, s34, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@lo
; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s33
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:4
; GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_lshrrev_b32_e64 v1, 5, s33
-; GFX10-NEXT: s_addk_i32 s32, 0x400
; GFX10-NEXT: v_add_nc_u32_e32 v0, 8, v0
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: buffer_load_ubyte v0, off, s[0:3], s33 offset:8
@@ -9491,17 +9519,17 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 32
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s33, 8
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 8
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@hi
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@lo
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b8 off, v0, s33
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v1, s33 offset:4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s33
-; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@hi
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@lo
-; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v0, off, s33 offset:8
@@ -9531,17 +9559,17 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:16 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8
; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 32
-; GFX11-FAKE16-NEXT: s_add_i32 s2, s33, 8
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s33, 8
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@hi
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@lo
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_store_b8 off, v0, s33
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v1, s33 offset:4
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s33
-; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@hi
-; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@lo
-; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_load_u8 v0, off, s33 offset:8
@@ -9572,18 +9600,18 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 3
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 8
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32
; GFX10-SCRATCH-NEXT: s_add_i32 s2, s33, 8
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@lo
; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s33
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v1, s33 offset:4
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, s2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, s33
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: s_clause 0x1
; GFX10-SCRATCH-NEXT: scratch_load_ubyte v0, off, s33 offset:8
@@ -9631,11 +9659,11 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx4 v[0:3], v0, s[34:35]
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v16i8 at abs32@hi
@@ -9681,11 +9709,11 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
-; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dwordx4 v[0:3], v0, s[34:35]
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
@@ -9732,11 +9760,11 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1]
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16i8 at abs32@hi
@@ -9780,11 +9808,11 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1]
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
@@ -9836,9 +9864,7 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:16
-; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:20
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s33
+; GFX9-NEXT: s_addk_i32 s32, 0x800
; GFX9-NEXT: v_writelane_b32 v40, s34, 0
; GFX9-NEXT: v_writelane_b32 v40, s35, 1
; GFX9-NEXT: v_writelane_b32 v40, s36, 2
@@ -9853,11 +9879,13 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX9-NEXT: v_writelane_b32 v40, s53, 11
; GFX9-NEXT: v_writelane_b32 v40, s54, 12
; GFX9-NEXT: v_writelane_b32 v40, s55, 13
-; GFX9-NEXT: s_addk_i32 s32, 0x800
; GFX9-NEXT: v_writelane_b32 v40, s30, 14
+; GFX9-NEXT: v_writelane_b32 v40, s31, 15
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:16
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:20
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s33
; GFX9-NEXT: s_mov_b32 s5, byval_align16_f64_arg at abs32@hi
; GFX9-NEXT: s_mov_b32 s4, byval_align16_f64_arg at abs32@lo
-; GFX9-NEXT: v_writelane_b32 v40, s31, 15
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32
; GFX9-NEXT: s_waitcnt vmcnt(2)
@@ -9896,18 +9924,8 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s4
-; GFX10-NEXT: s_clause 0x2
-; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:16
-; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:20
-; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s33
-; GFX10-NEXT: v_writelane_b32 v40, s34, 0
; GFX10-NEXT: s_addk_i32 s32, 0x400
-; GFX10-NEXT: s_mov_b32 s5, byval_align16_f64_arg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s4, byval_align16_f64_arg at abs32@lo
-; GFX10-NEXT: s_waitcnt vmcnt(2)
-; GFX10-NEXT: buffer_store_dword v32, off, s[0:3], s32
-; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4
+; GFX10-NEXT: v_writelane_b32 v40, s34, 0
; GFX10-NEXT: v_writelane_b32 v40, s35, 1
; GFX10-NEXT: v_writelane_b32 v40, s36, 2
; GFX10-NEXT: v_writelane_b32 v40, s37, 3
@@ -9923,6 +9941,16 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s55, 13
; GFX10-NEXT: v_writelane_b32 v40, s30, 14
; GFX10-NEXT: v_writelane_b32 v40, s31, 15
+; GFX10-NEXT: s_clause 0x2
+; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s33 offset:16
+; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:20
+; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s33
+; GFX10-NEXT: s_mov_b32 s5, byval_align16_f64_arg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s4, byval_align16_f64_arg at abs32@lo
+; GFX10-NEXT: s_waitcnt vmcnt(2)
+; GFX10-NEXT: buffer_store_dword v32, off, s[0:3], s32
+; GFX10-NEXT: s_waitcnt vmcnt(1)
+; GFX10-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4
; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX10-NEXT: v_readlane_b32 s30, v40, 14
; GFX10-NEXT: v_readlane_b32 s31, v40, 15
@@ -9957,13 +9985,8 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:24 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: scratch_load_b64 v[32:33], off, s33 offset:16
-; GFX11-NEXT: scratch_load_b32 v31, off, s33
-; GFX11-NEXT: v_writelane_b32 v40, s34, 0
; GFX11-NEXT: s_add_i32 s32, s32, 32
-; GFX11-NEXT: s_mov_b32 s1, byval_align16_f64_arg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, byval_align16_f64_arg at abs32@lo
+; GFX11-NEXT: v_writelane_b32 v40, s34, 0
; GFX11-NEXT: v_writelane_b32 v40, s35, 1
; GFX11-NEXT: v_writelane_b32 v40, s36, 2
; GFX11-NEXT: v_writelane_b32 v40, s37, 3
@@ -9979,6 +10002,11 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s55, 13
; GFX11-NEXT: v_writelane_b32 v40, s30, 14
; GFX11-NEXT: v_writelane_b32 v40, s31, 15
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: scratch_load_b64 v[32:33], off, s33 offset:16
+; GFX11-NEXT: scratch_load_b32 v31, off, s33
+; GFX11-NEXT: s_mov_b32 s1, byval_align16_f64_arg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, byval_align16_f64_arg at abs32@lo
; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: scratch_store_b64 off, v[32:33], s32
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -10015,13 +10043,8 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:24 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s0
-; GFX10-SCRATCH-NEXT: s_clause 0x1
-; GFX10-SCRATCH-NEXT: scratch_load_dwordx2 v[32:33], off, s33 offset:16
-; GFX10-SCRATCH-NEXT: scratch_load_dword v31, off, s33
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s34, 0
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, byval_align16_f64_arg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, byval_align16_f64_arg at abs32@lo
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s34, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s35, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s36, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s37, 3
@@ -10037,6 +10060,11 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s55, 13
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 14
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 15
+; GFX10-SCRATCH-NEXT: s_clause 0x1
+; GFX10-SCRATCH-NEXT: scratch_load_dwordx2 v[32:33], off, s33 offset:16
+; GFX10-SCRATCH-NEXT: scratch_load_dword v31, off, s33
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, byval_align16_f64_arg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, byval_align16_f64_arg at abs32@lo
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(1)
; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[32:33], s32
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -10081,12 +10109,12 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 1
; GFX9-NEXT: s_mov_b32 s35, external_void_func_i1_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_i1_inreg at abs32@lo
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
@@ -10110,13 +10138,13 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: v_mov_b32_e32 v0, 1
; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 1
; GFX10-NEXT: s_mov_b32 s35, external_void_func_i1_inreg at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_i1_inreg at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -10139,15 +10167,14 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: v_mov_b32_e32 v0, 1
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: v_mov_b32_e32 v0, 1
; GFX11-NEXT: s_mov_b32 s1, external_void_func_i1_inreg at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_i1_inreg at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: scratch_store_b8 off, v0, s32
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -10169,13 +10196,13 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i1_inreg at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i1_inreg at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -10202,13 +10229,13 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 3
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s30, 1
+; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_inreg at abs32@lo
; GFX9-NEXT: s_movk_i32 s4, 0x7b
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
; GFX9-NEXT: v_readlane_b32 s31, v40, 2
@@ -10232,13 +10259,13 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_movk_i32 s4, 0x7b
; GFX10-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_inreg at abs32@lo
+; GFX10-NEXT: s_movk_i32 s4, 0x7b
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-NEXT: v_readlane_b32 s31, v40, 2
@@ -10262,15 +10289,14 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 3
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_i8_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_i8_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_movk_i32 s4, 0x7b
; GFX11-NEXT: v_writelane_b32 v40, s30, 1
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_i8_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_i8_inreg at abs32@lo
+; GFX11-NEXT: s_movk_i32 s4, 0x7b
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
@@ -10293,13 +10319,13 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
@@ -10327,13 +10353,13 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 3
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s30, 1
+; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_mov_b32 s35, external_void_func_i16_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_i16_inreg at abs32@lo
; GFX9-NEXT: s_movk_i32 s4, 0x7b
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
; GFX9-NEXT: v_readlane_b32 s31, v40, 2
@@ -10357,13 +10383,13 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_movk_i32 s4, 0x7b
; GFX10-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16_inreg at abs32@lo
+; GFX10-NEXT: s_movk_i32 s4, 0x7b
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-NEXT: v_readlane_b32 s31, v40, 2
@@ -10387,15 +10413,14 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 3
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_i16_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_i16_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_movk_i32 s4, 0x7b
; GFX11-NEXT: v_writelane_b32 v40, s30, 1
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_i16_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_i16_inreg at abs32@lo
+; GFX11-NEXT: s_movk_i32 s4, 0x7b
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
@@ -10418,13 +10443,13 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
@@ -10452,13 +10477,13 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 3
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s30, 1
+; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_mov_b32 s35, external_void_func_i32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_i32_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 42
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
; GFX9-NEXT: v_readlane_b32 s31, v40, 2
@@ -10482,13 +10507,13 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_i32_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_i32_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 42
; GFX10-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_i32_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_i32_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 42
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-NEXT: v_readlane_b32 s31, v40, 2
@@ -10512,15 +10537,14 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 3
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_i32_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_i32_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 42
; GFX11-NEXT: v_writelane_b32 v40, s30, 1
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_i32_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_i32_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 42
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
@@ -10543,13 +10567,13 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i32_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i32_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 42
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i32_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i32_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 42
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
@@ -10577,15 +10601,15 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 4
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s30, 2
+; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_mov_b32 s35, external_void_func_i64_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_i64_inreg at abs32@lo
; GFX9-NEXT: s_movk_i32 s4, 0x7b
; GFX9-NEXT: s_mov_b32 s5, 0
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
; GFX9-NEXT: v_readlane_b32 s31, v40, 3
@@ -10610,15 +10634,15 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_i64_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_i64_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_movk_i32 s4, 0x7b
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, 0
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_i64_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_i64_inreg at abs32@lo
+; GFX10-NEXT: s_movk_i32 s4, 0x7b
+; GFX10-NEXT: s_mov_b32 s5, 0
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-NEXT: v_readlane_b32 s31, v40, 3
@@ -10643,17 +10667,16 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 4
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_i64_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_i64_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_movk_i32 s4, 0x7b
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 0
; GFX11-NEXT: v_writelane_b32 v40, s30, 2
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_i64_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_i64_inreg at abs32@lo
+; GFX11-NEXT: s_movk_i32 s4, 0x7b
+; GFX11-NEXT: s_mov_b32 s5, 0
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -10677,15 +10700,15 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i64_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i64_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i64_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i64_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b
+; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 0
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
@@ -10714,17 +10737,17 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 6
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
-; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_writelane_b32 v40, s7, 3
-; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0
; GFX9-NEXT: v_writelane_b32 v40, s30, 4
+; GFX9-NEXT: v_writelane_b32 v40, s31, 5
+; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i64_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i64_inreg at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 4
; GFX9-NEXT: v_readlane_b32 s31, v40, 5
@@ -10751,17 +10774,17 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 6
-; GFX10-NEXT: s_mov_b64 s[34:35], 0
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
; GFX10-NEXT: v_writelane_b32 v40, s6, 2
; GFX10-NEXT: v_writelane_b32 v40, s7, 3
+; GFX10-NEXT: v_writelane_b32 v40, s30, 4
+; GFX10-NEXT: v_writelane_b32 v40, s31, 5
+; GFX10-NEXT: s_mov_b64 s[34:35], 0
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i64_inreg at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i64_inreg at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 4
-; GFX10-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 4
; GFX10-NEXT: v_readlane_b32 s31, v40, 5
@@ -10788,19 +10811,19 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 6
-; GFX11-NEXT: s_mov_b64 s[0:1], 0
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
; GFX11-NEXT: v_writelane_b32 v40, s7, 3
+; GFX11-NEXT: v_writelane_b32 v40, s30, 4
+; GFX11-NEXT: v_writelane_b32 v40, s31, 5
+; GFX11-NEXT: s_mov_b64 s[0:1], 0
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i64_inreg at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i64_inreg at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 4
-; GFX11-NEXT: v_writelane_b32 v40, s31, 5
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 4
; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
@@ -10826,17 +10849,17 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6
-; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5
+; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0
; GFX10-SCRATCH-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i64_inreg at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i64_inreg at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
@@ -10868,19 +10891,19 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 6
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
; GFX9-NEXT: v_writelane_b32 v40, s7, 3
; GFX9-NEXT: v_writelane_b32 v40, s30, 4
+; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i64_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i64_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 1
; GFX9-NEXT: s_mov_b32 s5, 2
; GFX9-NEXT: s_mov_b32 s6, 3
; GFX9-NEXT: s_mov_b32 s7, 4
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 4
; GFX9-NEXT: v_readlane_b32 s31, v40, 5
@@ -10907,19 +10930,19 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 6
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i64_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i64_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 1
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, 2
; GFX10-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-NEXT: s_mov_b32 s6, 3
; GFX10-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-NEXT: s_mov_b32 s7, 4
; GFX10-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-NEXT: v_writelane_b32 v40, s31, 5
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i64_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i64_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 1
+; GFX10-NEXT: s_mov_b32 s5, 2
+; GFX10-NEXT: s_mov_b32 s6, 3
+; GFX10-NEXT: s_mov_b32 s7, 4
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 4
; GFX10-NEXT: v_readlane_b32 s31, v40, 5
@@ -10946,21 +10969,20 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 6
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i64_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i64_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 1
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 2
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
-; GFX11-NEXT: s_mov_b32 s6, 3
; GFX11-NEXT: v_writelane_b32 v40, s7, 3
-; GFX11-NEXT: s_mov_b32 s7, 4
; GFX11-NEXT: v_writelane_b32 v40, s30, 4
; GFX11-NEXT: v_writelane_b32 v40, s31, 5
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i64_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i64_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 1
+; GFX11-NEXT: s_mov_b32 s5, 2
+; GFX11-NEXT: s_mov_b32 s6, 3
+; GFX11-NEXT: s_mov_b32 s7, 4
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 4
; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
@@ -10986,19 +11008,19 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i64_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i64_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 3
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i64_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i64_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2
+; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 3
+; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 4
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
@@ -11029,21 +11051,21 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 8
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
-; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_writelane_b32 v40, s7, 3
-; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0
; GFX9-NEXT: v_writelane_b32 v40, s8, 4
; GFX9-NEXT: v_writelane_b32 v40, s9, 5
; GFX9-NEXT: v_writelane_b32 v40, s30, 6
+; GFX9-NEXT: v_writelane_b32 v40, s31, 7
+; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i64_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i64_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s8, 1
; GFX9-NEXT: s_mov_b32 s9, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 7
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 6
; GFX9-NEXT: v_readlane_b32 s31, v40, 7
@@ -11072,21 +11094,21 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 8
-; GFX10-NEXT: s_mov_b64 s[34:35], 0
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
; GFX10-NEXT: v_writelane_b32 v40, s6, 2
; GFX10-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i64_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i64_inreg at abs32@lo
; GFX10-NEXT: v_writelane_b32 v40, s8, 4
-; GFX10-NEXT: s_mov_b32 s8, 1
; GFX10-NEXT: v_writelane_b32 v40, s9, 5
-; GFX10-NEXT: s_mov_b32 s9, 2
; GFX10-NEXT: v_writelane_b32 v40, s30, 6
; GFX10-NEXT: v_writelane_b32 v40, s31, 7
+; GFX10-NEXT: s_mov_b64 s[34:35], 0
+; GFX10-NEXT: s_mov_b32 s8, 1
+; GFX10-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i64_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i64_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s9, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 6
; GFX10-NEXT: v_readlane_b32 s31, v40, 7
@@ -11115,23 +11137,22 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 8
-; GFX11-NEXT: s_mov_b64 s[0:1], 0
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
; GFX11-NEXT: v_writelane_b32 v40, s7, 3
-; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i64_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i64_inreg at abs32@lo
; GFX11-NEXT: v_writelane_b32 v40, s8, 4
-; GFX11-NEXT: s_mov_b32 s8, 1
; GFX11-NEXT: v_writelane_b32 v40, s9, 5
-; GFX11-NEXT: s_mov_b32 s9, 2
; GFX11-NEXT: v_writelane_b32 v40, s30, 6
; GFX11-NEXT: v_writelane_b32 v40, s31, 7
+; GFX11-NEXT: s_mov_b64 s[0:1], 0
+; GFX11-NEXT: s_mov_b32 s8, 1
+; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i64_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i64_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s9, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 6
; GFX11-NEXT: v_readlane_b32 s31, v40, 7
; GFX11-NEXT: v_readlane_b32 s9, v40, 5
@@ -11159,21 +11180,21 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 8
-; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-SCRATCH-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i64_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i64_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s8, 4
-; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s9, 5
-; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 6
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 7
+; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 1
+; GFX10-SCRATCH-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i64_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i64_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 2
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 6
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 7
@@ -11209,25 +11230,25 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 10
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
; GFX9-NEXT: v_writelane_b32 v40, s7, 3
-; GFX9-NEXT: s_mov_b64 s[34:35], 0
; GFX9-NEXT: v_writelane_b32 v40, s8, 4
-; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0
; GFX9-NEXT: v_writelane_b32 v40, s9, 5
; GFX9-NEXT: v_writelane_b32 v40, s10, 6
; GFX9-NEXT: v_writelane_b32 v40, s11, 7
; GFX9-NEXT: v_writelane_b32 v40, s30, 8
+; GFX9-NEXT: v_writelane_b32 v40, s31, 9
+; GFX9-NEXT: s_mov_b64 s[34:35], 0
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i64_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i64_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s8, 1
; GFX9-NEXT: s_mov_b32 s9, 2
; GFX9-NEXT: s_mov_b32 s10, 3
; GFX9-NEXT: s_mov_b32 s11, 4
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 9
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 8
; GFX9-NEXT: v_readlane_b32 s31, v40, 9
@@ -11258,25 +11279,25 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 10
-; GFX10-NEXT: s_mov_b64 s[34:35], 0
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
; GFX10-NEXT: v_writelane_b32 v40, s6, 2
; GFX10-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i64_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i64_inreg at abs32@lo
; GFX10-NEXT: v_writelane_b32 v40, s8, 4
-; GFX10-NEXT: s_mov_b32 s8, 1
; GFX10-NEXT: v_writelane_b32 v40, s9, 5
-; GFX10-NEXT: s_mov_b32 s9, 2
; GFX10-NEXT: v_writelane_b32 v40, s10, 6
-; GFX10-NEXT: s_mov_b32 s10, 3
; GFX10-NEXT: v_writelane_b32 v40, s11, 7
-; GFX10-NEXT: s_mov_b32 s11, 4
; GFX10-NEXT: v_writelane_b32 v40, s30, 8
; GFX10-NEXT: v_writelane_b32 v40, s31, 9
+; GFX10-NEXT: s_mov_b64 s[34:35], 0
+; GFX10-NEXT: s_mov_b32 s8, 1
+; GFX10-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i64_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i64_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s9, 2
+; GFX10-NEXT: s_mov_b32 s10, 3
+; GFX10-NEXT: s_mov_b32 s11, 4
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 8
; GFX10-NEXT: v_readlane_b32 s31, v40, 9
@@ -11307,27 +11328,26 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 10
-; GFX11-NEXT: s_mov_b64 s[0:1], 0
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
; GFX11-NEXT: v_writelane_b32 v40, s7, 3
-; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i64_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i64_inreg at abs32@lo
; GFX11-NEXT: v_writelane_b32 v40, s8, 4
-; GFX11-NEXT: s_mov_b32 s8, 1
; GFX11-NEXT: v_writelane_b32 v40, s9, 5
-; GFX11-NEXT: s_mov_b32 s9, 2
; GFX11-NEXT: v_writelane_b32 v40, s10, 6
-; GFX11-NEXT: s_mov_b32 s10, 3
; GFX11-NEXT: v_writelane_b32 v40, s11, 7
-; GFX11-NEXT: s_mov_b32 s11, 4
; GFX11-NEXT: v_writelane_b32 v40, s30, 8
; GFX11-NEXT: v_writelane_b32 v40, s31, 9
+; GFX11-NEXT: s_mov_b64 s[0:1], 0
+; GFX11-NEXT: s_mov_b32 s8, 1
+; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i64_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i64_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s9, 2
+; GFX11-NEXT: s_mov_b32 s10, 3
+; GFX11-NEXT: s_mov_b32 s11, 4
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: v_readlane_b32 s31, v40, 9
; GFX11-NEXT: v_readlane_b32 s11, v40, 7
@@ -11357,25 +11377,25 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 10
-; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-SCRATCH-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i64_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i64_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s8, 4
-; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s9, 5
-; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s10, 6
-; GFX10-SCRATCH-NEXT: s_mov_b32 s10, 3
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s11, 7
-; GFX10-SCRATCH-NEXT: s_mov_b32 s11, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 8
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 9
+; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 1
+; GFX10-SCRATCH-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i64_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i64_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 2
+; GFX10-SCRATCH-NEXT: s_mov_b32 s10, 3
+; GFX10-SCRATCH-NEXT: s_mov_b32 s11, 4
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 8
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 9
@@ -11412,13 +11432,13 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 3
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s30, 1
+; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_mov_b32 s35, external_void_func_f16_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_f16_inreg at abs32@lo
; GFX9-NEXT: s_movk_i32 s4, 0x4400
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
; GFX9-NEXT: v_readlane_b32 s31, v40, 2
@@ -11442,13 +11462,13 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_f16_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_f16_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_movk_i32 s4, 0x4400
; GFX10-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_f16_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_f16_inreg at abs32@lo
+; GFX10-NEXT: s_movk_i32 s4, 0x4400
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-NEXT: v_readlane_b32 s31, v40, 2
@@ -11472,15 +11492,14 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 3
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_f16_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_f16_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_movk_i32 s4, 0x4400
; GFX11-NEXT: v_writelane_b32 v40, s30, 1
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_f16_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_f16_inreg at abs32@lo
+; GFX11-NEXT: s_movk_i32 s4, 0x4400
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
@@ -11503,13 +11522,13 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f16_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f16_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x4400
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f16_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f16_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x4400
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
@@ -11537,13 +11556,13 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 3
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s30, 1
+; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_mov_b32 s35, external_void_func_f32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_f32_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 4.0
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
; GFX9-NEXT: v_readlane_b32 s31, v40, 2
@@ -11567,13 +11586,13 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_f32_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_f32_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 4.0
; GFX10-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_f32_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_f32_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 4.0
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-NEXT: v_readlane_b32 s31, v40, 2
@@ -11597,15 +11616,14 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 3
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_f32_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_f32_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 4.0
; GFX11-NEXT: v_writelane_b32 v40, s30, 1
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_f32_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_f32_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 4.0
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
@@ -11628,13 +11646,13 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f32_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f32_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 4.0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f32_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f32_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 4.0
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
@@ -11662,15 +11680,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 4
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s30, 2
+; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2f32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2f32_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 1.0
; GFX9-NEXT: s_mov_b32 s5, 2.0
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
; GFX9-NEXT: v_readlane_b32 s31, v40, 3
@@ -11695,15 +11713,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f32_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f32_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 1.0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, 2.0
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f32_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f32_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 1.0
+; GFX10-NEXT: s_mov_b32 s5, 2.0
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-NEXT: v_readlane_b32 s31, v40, 3
@@ -11728,17 +11746,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 4
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f32_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f32_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 1.0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 2.0
; GFX11-NEXT: v_writelane_b32 v40, s30, 2
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f32_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f32_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 1.0
+; GFX11-NEXT: s_mov_b32 s5, 2.0
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -11762,15 +11779,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f32_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f32_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f32_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f32_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
@@ -11799,17 +11816,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 5
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 3
+; GFX9-NEXT: v_writelane_b32 v40, s31, 4
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f32_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 1.0
; GFX9-NEXT: s_mov_b32 s5, 2.0
; GFX9-NEXT: s_mov_b32 s6, 4.0
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 4
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 3
; GFX9-NEXT: v_readlane_b32 s31, v40, 4
@@ -11835,17 +11852,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 5
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f32_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f32_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 1.0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, 2.0
; GFX10-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-NEXT: s_mov_b32 s6, 4.0
; GFX10-NEXT: v_writelane_b32 v40, s30, 3
; GFX10-NEXT: v_writelane_b32 v40, s31, 4
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f32_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f32_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 1.0
+; GFX10-NEXT: s_mov_b32 s5, 2.0
+; GFX10-NEXT: s_mov_b32 s6, 4.0
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 3
; GFX10-NEXT: v_readlane_b32 s31, v40, 4
@@ -11871,19 +11888,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 5
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f32_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f32_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 1.0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 2.0
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
-; GFX11-NEXT: s_mov_b32 s6, 4.0
; GFX11-NEXT: v_writelane_b32 v40, s30, 3
; GFX11-NEXT: v_writelane_b32 v40, s31, 4
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f32_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f32_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 1.0
+; GFX11-NEXT: s_mov_b32 s5, 2.0
+; GFX11-NEXT: s_mov_b32 s6, 4.0
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 3
; GFX11-NEXT: v_readlane_b32 s31, v40, 4
; GFX11-NEXT: v_readlane_b32 s6, v40, 2
@@ -11908,17 +11924,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 5
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f32_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f32_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 4.0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 3
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 4
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f32_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f32_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 4.0
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 4
@@ -11948,12 +11964,14 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 7
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
; GFX9-NEXT: v_writelane_b32 v40, s7, 3
; GFX9-NEXT: v_writelane_b32 v40, s8, 4
; GFX9-NEXT: v_writelane_b32 v40, s30, 5
+; GFX9-NEXT: v_writelane_b32 v40, s31, 6
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v5f32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v5f32_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 1.0
@@ -11961,8 +11979,6 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 {
; GFX9-NEXT: s_mov_b32 s6, 4.0
; GFX9-NEXT: s_mov_b32 s7, -1.0
; GFX9-NEXT: s_mov_b32 s8, 0.5
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 6
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 5
; GFX9-NEXT: v_readlane_b32 s31, v40, 6
@@ -11990,21 +12006,21 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 7
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s4, 0
+; GFX10-NEXT: v_writelane_b32 v40, s5, 1
+; GFX10-NEXT: v_writelane_b32 v40, s6, 2
+; GFX10-NEXT: v_writelane_b32 v40, s7, 3
+; GFX10-NEXT: v_writelane_b32 v40, s8, 4
+; GFX10-NEXT: v_writelane_b32 v40, s30, 5
+; GFX10-NEXT: v_writelane_b32 v40, s31, 6
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5f32_inreg at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5f32_inreg at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: s_mov_b32 s4, 1.0
-; GFX10-NEXT: v_writelane_b32 v40, s5, 1
; GFX10-NEXT: s_mov_b32 s5, 2.0
-; GFX10-NEXT: v_writelane_b32 v40, s6, 2
; GFX10-NEXT: s_mov_b32 s6, 4.0
-; GFX10-NEXT: v_writelane_b32 v40, s7, 3
; GFX10-NEXT: s_mov_b32 s7, -1.0
-; GFX10-NEXT: v_writelane_b32 v40, s8, 4
; GFX10-NEXT: s_mov_b32 s8, 0.5
-; GFX10-NEXT: v_writelane_b32 v40, s30, 5
-; GFX10-NEXT: v_writelane_b32 v40, s31, 6
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 5
; GFX10-NEXT: v_readlane_b32 s31, v40, 6
@@ -12032,23 +12048,22 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 7
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5f32_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5f32_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 1.0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 2.0
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
-; GFX11-NEXT: s_mov_b32 s6, 4.0
; GFX11-NEXT: v_writelane_b32 v40, s7, 3
-; GFX11-NEXT: s_mov_b32 s7, -1.0
; GFX11-NEXT: v_writelane_b32 v40, s8, 4
-; GFX11-NEXT: s_mov_b32 s8, 0.5
; GFX11-NEXT: v_writelane_b32 v40, s30, 5
; GFX11-NEXT: v_writelane_b32 v40, s31, 6
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5f32_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5f32_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 1.0
+; GFX11-NEXT: s_mov_b32 s5, 2.0
+; GFX11-NEXT: s_mov_b32 s6, 4.0
+; GFX11-NEXT: s_mov_b32 s7, -1.0
+; GFX11-NEXT: s_mov_b32 s8, 0.5
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 5
; GFX11-NEXT: v_readlane_b32 s31, v40, 6
; GFX11-NEXT: v_readlane_b32 s8, v40, 4
@@ -12075,21 +12090,21 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 7
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5f32_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5f32_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 4.0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-SCRATCH-NEXT: s_mov_b32 s7, -1.0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s8, 4
-; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 0.5
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 5
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 6
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5f32_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5f32_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 4.0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s7, -1.0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 0.5
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 6
@@ -12121,15 +12136,15 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 4
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s30, 2
+; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_mov_b32 s35, external_void_func_f64_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_f64_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 0
; GFX9-NEXT: s_mov_b32 s5, 0x40100000
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
; GFX9-NEXT: v_readlane_b32 s31, v40, 3
@@ -12154,15 +12169,15 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_f64_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_f64_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, 0x40100000
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_f64_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_f64_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 0
+; GFX10-NEXT: s_mov_b32 s5, 0x40100000
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-NEXT: v_readlane_b32 s31, v40, 3
@@ -12187,17 +12202,16 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 4
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_f64_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_f64_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 0x40100000
; GFX11-NEXT: v_writelane_b32 v40, s30, 2
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_f64_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_f64_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 0
+; GFX11-NEXT: s_mov_b32 s5, 0x40100000
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -12221,15 +12235,15 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f64_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f64_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 0x40100000
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f64_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f64_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 0x40100000
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
@@ -12258,19 +12272,19 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 6
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
; GFX9-NEXT: v_writelane_b32 v40, s7, 3
; GFX9-NEXT: v_writelane_b32 v40, s30, 4
+; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2f64_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2f64_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 0
; GFX9-NEXT: s_mov_b32 s5, 2.0
; GFX9-NEXT: s_mov_b32 s6, 0
; GFX9-NEXT: s_mov_b32 s7, 0x40100000
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 4
; GFX9-NEXT: v_readlane_b32 s31, v40, 5
@@ -12297,19 +12311,19 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 6
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f64_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f64_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, 2.0
; GFX10-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-NEXT: s_mov_b32 s6, 0
; GFX10-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-NEXT: s_mov_b32 s7, 0x40100000
; GFX10-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-NEXT: v_writelane_b32 v40, s31, 5
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f64_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f64_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 0
+; GFX10-NEXT: s_mov_b32 s5, 2.0
+; GFX10-NEXT: s_mov_b32 s6, 0
+; GFX10-NEXT: s_mov_b32 s7, 0x40100000
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 4
; GFX10-NEXT: v_readlane_b32 s31, v40, 5
@@ -12336,21 +12350,20 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 6
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f64_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f64_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 2.0
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
-; GFX11-NEXT: s_mov_b32 s6, 0
; GFX11-NEXT: v_writelane_b32 v40, s7, 3
-; GFX11-NEXT: s_mov_b32 s7, 0x40100000
; GFX11-NEXT: v_writelane_b32 v40, s30, 4
; GFX11-NEXT: v_writelane_b32 v40, s31, 5
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f64_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f64_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 0
+; GFX11-NEXT: s_mov_b32 s5, 2.0
+; GFX11-NEXT: s_mov_b32 s6, 0
+; GFX11-NEXT: s_mov_b32 s7, 0x40100000
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 4
; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
@@ -12376,19 +12389,19 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f64_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f64_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 0x40100000
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f64_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f64_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 0x40100000
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
@@ -12419,6 +12432,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 8
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
@@ -12426,6 +12440,7 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 {
; GFX9-NEXT: v_writelane_b32 v40, s8, 4
; GFX9-NEXT: v_writelane_b32 v40, s9, 5
; GFX9-NEXT: v_writelane_b32 v40, s30, 6
+; GFX9-NEXT: v_writelane_b32 v40, s31, 7
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f64_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f64_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 0
@@ -12434,8 +12449,6 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 {
; GFX9-NEXT: s_mov_b32 s7, 0x40100000
; GFX9-NEXT: s_mov_b32 s8, 0
; GFX9-NEXT: s_mov_b32 s9, 0x40200000
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 7
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 6
; GFX9-NEXT: v_readlane_b32 s31, v40, 7
@@ -12464,23 +12477,23 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 8
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f64_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f64_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, 2.0
; GFX10-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-NEXT: s_mov_b32 s6, 0
; GFX10-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-NEXT: s_mov_b32 s7, 0x40100000
; GFX10-NEXT: v_writelane_b32 v40, s8, 4
-; GFX10-NEXT: s_mov_b32 s8, 0
; GFX10-NEXT: v_writelane_b32 v40, s9, 5
-; GFX10-NEXT: s_mov_b32 s9, 0x40200000
; GFX10-NEXT: v_writelane_b32 v40, s30, 6
; GFX10-NEXT: v_writelane_b32 v40, s31, 7
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f64_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f64_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 0
+; GFX10-NEXT: s_mov_b32 s5, 2.0
+; GFX10-NEXT: s_mov_b32 s6, 0
+; GFX10-NEXT: s_mov_b32 s7, 0x40100000
+; GFX10-NEXT: s_mov_b32 s8, 0
+; GFX10-NEXT: s_mov_b32 s9, 0x40200000
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 6
; GFX10-NEXT: v_readlane_b32 s31, v40, 7
@@ -12509,25 +12522,24 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 8
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f64_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f64_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 2.0
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
-; GFX11-NEXT: s_mov_b32 s6, 0
; GFX11-NEXT: v_writelane_b32 v40, s7, 3
-; GFX11-NEXT: s_mov_b32 s7, 0x40100000
; GFX11-NEXT: v_writelane_b32 v40, s8, 4
-; GFX11-NEXT: s_mov_b32 s8, 0
; GFX11-NEXT: v_writelane_b32 v40, s9, 5
-; GFX11-NEXT: s_mov_b32 s9, 0x40200000
; GFX11-NEXT: v_writelane_b32 v40, s30, 6
; GFX11-NEXT: v_writelane_b32 v40, s31, 7
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f64_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f64_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 0
+; GFX11-NEXT: s_mov_b32 s5, 2.0
+; GFX11-NEXT: s_mov_b32 s6, 0
+; GFX11-NEXT: s_mov_b32 s7, 0x40100000
+; GFX11-NEXT: s_mov_b32 s8, 0
+; GFX11-NEXT: s_mov_b32 s9, 0x40200000
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 6
; GFX11-NEXT: v_readlane_b32 s31, v40, 7
; GFX11-NEXT: v_readlane_b32 s9, v40, 5
@@ -12555,23 +12567,23 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 8
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f64_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f64_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 0x40100000
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s8, 4
-; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s9, 5
-; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 0x40200000
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 6
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 7
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f64_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f64_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 0x40100000
+; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 0
+; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 0x40200000
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 6
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 7
@@ -12604,13 +12616,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 3
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
-; GFX9-NEXT: s_load_dword s4, s[34:35], 0x0
; GFX9-NEXT: v_writelane_b32 v40, s30, 1
+; GFX9-NEXT: v_writelane_b32 v40, s31, 2
+; GFX9-NEXT: s_load_dword s4, s[34:35], 0x0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i16_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i16_inreg at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
; GFX9-NEXT: v_readlane_b32 s31, v40, 2
@@ -12636,11 +12648,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
+; GFX10-NEXT: v_writelane_b32 v40, s30, 1
+; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_load_dword s4, s[34:35], 0x0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i16_inreg at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i16_inreg at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 1
-; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-NEXT: v_readlane_b32 s31, v40, 2
@@ -12666,13 +12678,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s0, 3
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
+; GFX11-NEXT: v_writelane_b32 v40, s30, 1
+; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i16_inreg at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i16_inreg at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 1
-; GFX11-NEXT: v_writelane_b32 v40, s31, 2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
@@ -12697,11 +12709,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-SCRATCH-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i16_inreg at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i16_inreg at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
@@ -12730,14 +12742,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 4
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
-; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0
; GFX9-NEXT: v_writelane_b32 v40, s30, 2
+; GFX9-NEXT: v_writelane_b32 v40, s31, 3
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i16_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i16_inreg at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
; GFX9-NEXT: v_readlane_b32 s31, v40, 3
@@ -12765,11 +12777,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
+; GFX10-NEXT: v_writelane_b32 v40, s30, 2
+; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16_inreg at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i16_inreg at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 2
-; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-NEXT: v_readlane_b32 s31, v40, 3
@@ -12797,13 +12809,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 {
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
+; GFX11-NEXT: v_writelane_b32 v40, s30, 2
+; GFX11-NEXT: v_writelane_b32 v40, s31, 3
; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16_inreg at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 2
-; GFX11-NEXT: v_writelane_b32 v40, s31, 3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -12830,11 +12842,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i16_inreg at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
@@ -12864,14 +12876,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 4
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
-; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0
; GFX9-NEXT: v_writelane_b32 v40, s30, 2
+; GFX9-NEXT: v_writelane_b32 v40, s31, 3
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f16_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f16_inreg at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
; GFX9-NEXT: v_readlane_b32 s31, v40, 3
@@ -12899,11 +12911,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
+; GFX10-NEXT: v_writelane_b32 v40, s30, 2
+; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16_inreg at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f16_inreg at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 2
-; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-NEXT: v_readlane_b32 s31, v40, 3
@@ -12931,13 +12943,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 {
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
+; GFX11-NEXT: v_writelane_b32 v40, s30, 2
+; GFX11-NEXT: v_writelane_b32 v40, s31, 3
; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f16_inreg at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 2
-; GFX11-NEXT: v_writelane_b32 v40, s31, 3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -12964,11 +12976,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f16_inreg at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
@@ -12998,15 +13010,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 4
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s30, 2
+; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i16_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i16_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 0x20001
; GFX9-NEXT: s_mov_b32 s5, 3
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
; GFX9-NEXT: v_readlane_b32 s31, v40, 3
@@ -13031,15 +13043,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i16_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 0x20001
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, 3
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i16_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 0x20001
+; GFX10-NEXT: s_mov_b32 s5, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-NEXT: v_readlane_b32 s31, v40, 3
@@ -13064,17 +13076,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 4
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 0x20001
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 3
; GFX11-NEXT: v_writelane_b32 v40, s30, 2
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 0x20001
+; GFX11-NEXT: s_mov_b32 s5, 3
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -13098,15 +13109,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i16_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x20001
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 3
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i16_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x20001
+; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
@@ -13135,15 +13146,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 4
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s30, 2
+; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f16_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f16_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 0x40003c00
; GFX9-NEXT: s_movk_i32 s5, 0x4400
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
; GFX9-NEXT: v_readlane_b32 s31, v40, 3
@@ -13168,15 +13179,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f16_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 0x40003c00
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_movk_i32 s5, 0x4400
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f16_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 0x40003c00
+; GFX10-NEXT: s_movk_i32 s5, 0x4400
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-NEXT: v_readlane_b32 s31, v40, 3
@@ -13200,18 +13211,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 {
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: v_writelane_b32 v40, s0, 4
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f16_inreg at abs32@lo
+; GFX11-NEXT: v_writelane_b32 v40, s0, 4
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 0x40003c00
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_movk_i32 s5, 0x4400
; GFX11-NEXT: v_writelane_b32 v40, s30, 2
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f16_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 0x40003c00
+; GFX11-NEXT: s_movk_i32 s5, 0x4400
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -13235,15 +13245,15 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f16_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x40003c00
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_movk_i32 s5, 0x4400
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f16_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x40003c00
+; GFX10-SCRATCH-NEXT: s_movk_i32 s5, 0x4400
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
@@ -13272,14 +13282,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 4
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
-; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0
; GFX9-NEXT: v_writelane_b32 v40, s30, 2
+; GFX9-NEXT: v_writelane_b32 v40, s31, 3
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i16_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i16_inreg at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
; GFX9-NEXT: v_readlane_b32 s31, v40, 3
@@ -13307,11 +13317,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
+; GFX10-NEXT: v_writelane_b32 v40, s30, 2
+; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16_inreg at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i16_inreg at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 2
-; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-NEXT: v_readlane_b32 s31, v40, 3
@@ -13339,13 +13349,13 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 {
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
+; GFX11-NEXT: v_writelane_b32 v40, s30, 2
+; GFX11-NEXT: v_writelane_b32 v40, s31, 3
; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i16_inreg at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 2
-; GFX11-NEXT: v_writelane_b32 v40, s31, 3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -13372,11 +13382,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i16_inreg at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
@@ -13406,15 +13416,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 4
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s30, 2
+; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i16_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i16_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 0x20001
; GFX9-NEXT: s_mov_b32 s5, 0x40003
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
; GFX9-NEXT: v_readlane_b32 s31, v40, 3
@@ -13439,15 +13449,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i16_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 0x20001
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, 0x40003
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i16_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 0x20001
+; GFX10-NEXT: s_mov_b32 s5, 0x40003
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-NEXT: v_readlane_b32 s31, v40, 3
@@ -13472,17 +13482,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 4
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i16_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 0x20001
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 0x40003
; GFX11-NEXT: v_writelane_b32 v40, s30, 2
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i16_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 0x20001
+; GFX11-NEXT: s_mov_b32 s5, 0x40003
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -13506,15 +13515,15 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i16_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x20001
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 0x40003
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i16_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x20001
+; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 0x40003
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
@@ -13543,13 +13552,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 3
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
-; GFX9-NEXT: s_load_dword s4, s[34:35], 0x0
; GFX9-NEXT: v_writelane_b32 v40, s30, 1
+; GFX9-NEXT: v_writelane_b32 v40, s31, 2
+; GFX9-NEXT: s_load_dword s4, s[34:35], 0x0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2f16_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2f16_inreg at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
; GFX9-NEXT: v_readlane_b32 s31, v40, 2
@@ -13575,11 +13584,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
+; GFX10-NEXT: v_writelane_b32 v40, s30, 1
+; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_load_dword s4, s[34:35], 0x0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f16_inreg at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f16_inreg at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 1
-; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-NEXT: v_readlane_b32 s31, v40, 2
@@ -13605,13 +13614,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s0, 3
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
+; GFX11-NEXT: v_writelane_b32 v40, s30, 1
+; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f16_inreg at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f16_inreg at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 1
-; GFX11-NEXT: v_writelane_b32 v40, s31, 2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: v_readlane_b32 s31, v40, 2
; GFX11-NEXT: v_readlane_b32 s4, v40, 0
@@ -13636,11 +13645,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-SCRATCH-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f16_inreg at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f16_inreg at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 2
@@ -13669,14 +13678,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 4
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
-; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0
; GFX9-NEXT: v_writelane_b32 v40, s30, 2
+; GFX9-NEXT: v_writelane_b32 v40, s31, 3
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i32_inreg at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
; GFX9-NEXT: v_readlane_b32 s31, v40, 3
@@ -13704,11 +13713,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 {
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
+; GFX10-NEXT: v_writelane_b32 v40, s30, 2
+; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32_inreg at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i32_inreg at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 2
-; GFX10-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-NEXT: v_readlane_b32 s31, v40, 3
@@ -13736,13 +13745,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 {
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
+; GFX11-NEXT: v_writelane_b32 v40, s30, 2
+; GFX11-NEXT: v_writelane_b32 v40, s31, 3
; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32_inreg at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 2
-; GFX11-NEXT: v_writelane_b32 v40, s31, 3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -13769,11 +13778,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i32_inreg at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
@@ -13803,15 +13812,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 4
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s30, 2
+; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i32_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 1
; GFX9-NEXT: s_mov_b32 s5, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 2
; GFX9-NEXT: v_readlane_b32 s31, v40, 3
@@ -13836,15 +13845,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i32_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 1
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, 2
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i32_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 1
+; GFX10-NEXT: s_mov_b32 s5, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-NEXT: v_readlane_b32 s31, v40, 3
@@ -13869,17 +13878,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 4
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 1
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 2
; GFX11-NEXT: v_writelane_b32 v40, s30, 2
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 1
+; GFX11-NEXT: s_mov_b32 s5, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -13903,15 +13911,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i32_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 3
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i32_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 2
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 3
@@ -13940,17 +13948,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 5
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 3
+; GFX9-NEXT: v_writelane_b32 v40, s31, 4
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i32_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 3
; GFX9-NEXT: s_mov_b32 s5, 4
; GFX9-NEXT: s_mov_b32 s6, 5
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 4
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 3
; GFX9-NEXT: v_readlane_b32 s31, v40, 4
@@ -13976,17 +13984,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 5
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 3
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, 4
; GFX10-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-NEXT: s_mov_b32 s6, 5
; GFX10-NEXT: v_writelane_b32 v40, s30, 3
; GFX10-NEXT: v_writelane_b32 v40, s31, 4
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 3
+; GFX10-NEXT: s_mov_b32 s5, 4
+; GFX10-NEXT: s_mov_b32 s6, 5
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 3
; GFX10-NEXT: v_readlane_b32 s31, v40, 4
@@ -14012,19 +14020,18 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 5
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 3
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 4
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
-; GFX11-NEXT: s_mov_b32 s6, 5
; GFX11-NEXT: v_writelane_b32 v40, s30, 3
; GFX11-NEXT: v_writelane_b32 v40, s31, 4
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 3
+; GFX11-NEXT: s_mov_b32 s5, 4
+; GFX11-NEXT: s_mov_b32 s6, 5
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 3
; GFX11-NEXT: v_readlane_b32 s31, v40, 4
; GFX11-NEXT: v_readlane_b32 s6, v40, 2
@@ -14049,17 +14056,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 5
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 3
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 5
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 3
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 4
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 3
+; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 4
+; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 5
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 3
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 4
@@ -14089,19 +14096,19 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 6
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
; GFX9-NEXT: v_writelane_b32 v40, s7, 3
; GFX9-NEXT: v_writelane_b32 v40, s30, 4
+; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i32_i32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i32_i32_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 3
; GFX9-NEXT: s_mov_b32 s5, 4
; GFX9-NEXT: s_mov_b32 s6, 5
; GFX9-NEXT: s_mov_b32 s7, 6
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 4
; GFX9-NEXT: v_readlane_b32 s31, v40, 5
@@ -14128,19 +14135,19 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 6
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32_i32_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32_i32_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 3
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, 4
; GFX10-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-NEXT: s_mov_b32 s6, 5
; GFX10-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-NEXT: s_mov_b32 s7, 6
; GFX10-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-NEXT: v_writelane_b32 v40, s31, 5
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32_i32_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32_i32_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 3
+; GFX10-NEXT: s_mov_b32 s5, 4
+; GFX10-NEXT: s_mov_b32 s6, 5
+; GFX10-NEXT: s_mov_b32 s7, 6
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 4
; GFX10-NEXT: v_readlane_b32 s31, v40, 5
@@ -14167,21 +14174,20 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 6
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 3
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 4
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
-; GFX11-NEXT: s_mov_b32 s6, 5
; GFX11-NEXT: v_writelane_b32 v40, s7, 3
-; GFX11-NEXT: s_mov_b32 s7, 6
; GFX11-NEXT: v_writelane_b32 v40, s30, 4
; GFX11-NEXT: v_writelane_b32 v40, s31, 5
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 3
+; GFX11-NEXT: s_mov_b32 s5, 4
+; GFX11-NEXT: s_mov_b32 s6, 5
+; GFX11-NEXT: s_mov_b32 s7, 6
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 4
; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
@@ -14207,19 +14213,19 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 3
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 5
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 6
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 3
+; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 4
+; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 5
+; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 6
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
@@ -14250,16 +14256,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 6
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
; GFX9-NEXT: v_writelane_b32 v40, s7, 3
-; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0
; GFX9-NEXT: v_writelane_b32 v40, s30, 4
+; GFX9-NEXT: v_writelane_b32 v40, s31, 5
+; GFX9-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i32_inreg at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 4
; GFX9-NEXT: v_readlane_b32 s31, v40, 5
@@ -14291,11 +14297,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
; GFX10-NEXT: v_writelane_b32 v40, s6, 2
; GFX10-NEXT: v_writelane_b32 v40, s7, 3
+; GFX10-NEXT: v_writelane_b32 v40, s30, 4
+; GFX10-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[34:35], 0x0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32_inreg at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i32_inreg at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 4
-; GFX10-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 4
; GFX10-NEXT: v_readlane_b32 s31, v40, 5
@@ -14327,13 +14333,13 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
; GFX11-NEXT: v_writelane_b32 v40, s7, 3
+; GFX11-NEXT: v_writelane_b32 v40, s30, 4
+; GFX11-NEXT: v_writelane_b32 v40, s31, 5
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i32_inreg at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i32_inreg at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 4
-; GFX11-NEXT: v_writelane_b32 v40, s31, 5
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 4
; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
@@ -14364,11 +14370,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-SCRATCH-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i32_inreg at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i32_inreg at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
@@ -14400,19 +14406,19 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 6
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
; GFX9-NEXT: v_writelane_b32 v40, s7, 3
; GFX9-NEXT: v_writelane_b32 v40, s30, 4
+; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i32_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 1
; GFX9-NEXT: s_mov_b32 s5, 2
; GFX9-NEXT: s_mov_b32 s6, 3
; GFX9-NEXT: s_mov_b32 s7, 4
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 5
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 4
; GFX9-NEXT: v_readlane_b32 s31, v40, 5
@@ -14439,19 +14445,19 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 6
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i32_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 1
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, 2
; GFX10-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-NEXT: s_mov_b32 s6, 3
; GFX10-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-NEXT: s_mov_b32 s7, 4
; GFX10-NEXT: v_writelane_b32 v40, s30, 4
; GFX10-NEXT: v_writelane_b32 v40, s31, 5
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i32_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 1
+; GFX10-NEXT: s_mov_b32 s5, 2
+; GFX10-NEXT: s_mov_b32 s6, 3
+; GFX10-NEXT: s_mov_b32 s7, 4
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 4
; GFX10-NEXT: v_readlane_b32 s31, v40, 5
@@ -14478,21 +14484,20 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 6
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i32_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i32_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 1
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 2
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
-; GFX11-NEXT: s_mov_b32 s6, 3
; GFX11-NEXT: v_writelane_b32 v40, s7, 3
-; GFX11-NEXT: s_mov_b32 s7, 4
; GFX11-NEXT: v_writelane_b32 v40, s30, 4
; GFX11-NEXT: v_writelane_b32 v40, s31, 5
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i32_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i32_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 1
+; GFX11-NEXT: s_mov_b32 s5, 2
+; GFX11-NEXT: s_mov_b32 s6, 3
+; GFX11-NEXT: s_mov_b32 s7, 4
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 4
; GFX11-NEXT: v_readlane_b32 s31, v40, 5
; GFX11-NEXT: v_readlane_b32 s7, v40, 3
@@ -14518,19 +14523,19 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i32_inreg at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i32_inreg at abs32@lo
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 3
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3
; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 4
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 4
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 5
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 4
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 5
@@ -14561,12 +14566,14 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 7
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
; GFX9-NEXT: v_writelane_b32 v40, s7, 3
; GFX9-NEXT: v_writelane_b32 v40, s8, 4
; GFX9-NEXT: v_writelane_b32 v40, s30, 5
+; GFX9-NEXT: v_writelane_b32 v40, s31, 6
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v5i32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v5i32_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 1
@@ -14574,8 +14581,6 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 {
; GFX9-NEXT: s_mov_b32 s6, 3
; GFX9-NEXT: s_mov_b32 s7, 4
; GFX9-NEXT: s_mov_b32 s8, 5
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 6
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 5
; GFX9-NEXT: v_readlane_b32 s31, v40, 6
@@ -14603,21 +14608,21 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 7
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i32_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5i32_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 1
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, 2
; GFX10-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-NEXT: s_mov_b32 s6, 3
; GFX10-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-NEXT: s_mov_b32 s7, 4
; GFX10-NEXT: v_writelane_b32 v40, s8, 4
-; GFX10-NEXT: s_mov_b32 s8, 5
; GFX10-NEXT: v_writelane_b32 v40, s30, 5
; GFX10-NEXT: v_writelane_b32 v40, s31, 6
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i32_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5i32_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 1
+; GFX10-NEXT: s_mov_b32 s5, 2
+; GFX10-NEXT: s_mov_b32 s6, 3
+; GFX10-NEXT: s_mov_b32 s7, 4
+; GFX10-NEXT: s_mov_b32 s8, 5
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 5
; GFX10-NEXT: v_readlane_b32 s31, v40, 6
@@ -14645,23 +14650,22 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 7
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5i32_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5i32_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 1
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 2
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
-; GFX11-NEXT: s_mov_b32 s6, 3
; GFX11-NEXT: v_writelane_b32 v40, s7, 3
-; GFX11-NEXT: s_mov_b32 s7, 4
; GFX11-NEXT: v_writelane_b32 v40, s8, 4
-; GFX11-NEXT: s_mov_b32 s8, 5
; GFX11-NEXT: v_writelane_b32 v40, s30, 5
; GFX11-NEXT: v_writelane_b32 v40, s31, 6
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5i32_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5i32_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 1
+; GFX11-NEXT: s_mov_b32 s5, 2
+; GFX11-NEXT: s_mov_b32 s6, 3
+; GFX11-NEXT: s_mov_b32 s7, 4
+; GFX11-NEXT: s_mov_b32 s8, 5
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 5
; GFX11-NEXT: v_readlane_b32 s31, v40, 6
; GFX11-NEXT: v_readlane_b32 s8, v40, 4
@@ -14688,21 +14692,21 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 7
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i32_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5i32_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 3
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s8, 4
-; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 5
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 5
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 6
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i32_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5i32_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2
+; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 3
+; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 4
+; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 5
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 5
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 6
@@ -14734,22 +14738,22 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 10
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
-; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX9-NEXT: v_writelane_b32 v40, s7, 3
; GFX9-NEXT: v_writelane_b32 v40, s8, 4
; GFX9-NEXT: v_writelane_b32 v40, s9, 5
; GFX9-NEXT: v_writelane_b32 v40, s10, 6
; GFX9-NEXT: v_writelane_b32 v40, s11, 7
+; GFX9-NEXT: v_writelane_b32 v40, s30, 8
+; GFX9-NEXT: v_writelane_b32 v40, s31, 9
+; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_load_dwordx8 s[4:11], s[34:35], 0x0
-; GFX9-NEXT: v_writelane_b32 v40, s30, 8
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i32_inreg at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 9
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 8
; GFX9-NEXT: v_readlane_b32 s31, v40, 9
@@ -14780,7 +14784,6 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 10
-; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
@@ -14790,12 +14793,13 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s9, 5
; GFX10-NEXT: v_writelane_b32 v40, s10, 6
; GFX10-NEXT: v_writelane_b32 v40, s11, 7
+; GFX10-NEXT: v_writelane_b32 v40, s30, 8
+; GFX10-NEXT: v_writelane_b32 v40, s31, 9
+; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_load_dwordx8 s[4:11], s[34:35], 0x0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i32_inreg at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i32_inreg at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 8
-; GFX10-NEXT: v_writelane_b32 v40, s31, 9
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 8
; GFX10-NEXT: v_readlane_b32 s31, v40, 9
@@ -14826,7 +14830,6 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 10
-; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
@@ -14836,14 +14839,15 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s9, 5
; GFX11-NEXT: v_writelane_b32 v40, s10, 6
; GFX11-NEXT: v_writelane_b32 v40, s11, 7
+; GFX11-NEXT: v_writelane_b32 v40, s30, 8
+; GFX11-NEXT: v_writelane_b32 v40, s31, 9
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_load_b256 s[4:11], s[0:1], 0x0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i32_inreg at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8i32_inreg at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 8
-; GFX11-NEXT: v_writelane_b32 v40, s31, 9
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: v_readlane_b32 s31, v40, 9
; GFX11-NEXT: v_readlane_b32 s11, v40, 7
@@ -14873,7 +14877,6 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 10
-; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
@@ -14883,12 +14886,13 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s9, 5
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s10, 6
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s11, 7
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 8
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 9
+; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i32_inreg at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i32_inreg at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 8
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 9
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 8
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 9
@@ -14925,6 +14929,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 10
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
@@ -14934,6 +14939,7 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 {
; GFX9-NEXT: v_writelane_b32 v40, s10, 6
; GFX9-NEXT: v_writelane_b32 v40, s11, 7
; GFX9-NEXT: v_writelane_b32 v40, s30, 8
+; GFX9-NEXT: v_writelane_b32 v40, s31, 9
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i32_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s4, 1
@@ -14944,8 +14950,6 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 {
; GFX9-NEXT: s_mov_b32 s9, 6
; GFX9-NEXT: s_mov_b32 s10, 7
; GFX9-NEXT: s_mov_b32 s11, 8
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 9
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 8
; GFX9-NEXT: v_readlane_b32 s31, v40, 9
@@ -14976,27 +14980,27 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 10
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i32_inreg at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i32_inreg at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, 1
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, 2
; GFX10-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-NEXT: s_mov_b32 s6, 3
; GFX10-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-NEXT: s_mov_b32 s7, 4
; GFX10-NEXT: v_writelane_b32 v40, s8, 4
-; GFX10-NEXT: s_mov_b32 s8, 5
; GFX10-NEXT: v_writelane_b32 v40, s9, 5
-; GFX10-NEXT: s_mov_b32 s9, 6
; GFX10-NEXT: v_writelane_b32 v40, s10, 6
-; GFX10-NEXT: s_mov_b32 s10, 7
; GFX10-NEXT: v_writelane_b32 v40, s11, 7
-; GFX10-NEXT: s_mov_b32 s11, 8
; GFX10-NEXT: v_writelane_b32 v40, s30, 8
; GFX10-NEXT: v_writelane_b32 v40, s31, 9
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i32_inreg at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i32_inreg at abs32@lo
+; GFX10-NEXT: s_mov_b32 s4, 1
+; GFX10-NEXT: s_mov_b32 s5, 2
+; GFX10-NEXT: s_mov_b32 s6, 3
+; GFX10-NEXT: s_mov_b32 s7, 4
+; GFX10-NEXT: s_mov_b32 s8, 5
+; GFX10-NEXT: s_mov_b32 s9, 6
+; GFX10-NEXT: s_mov_b32 s10, 7
+; GFX10-NEXT: s_mov_b32 s11, 8
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 8
; GFX10-NEXT: v_readlane_b32 s31, v40, 9
@@ -15027,29 +15031,28 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 10
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i32_inreg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8i32_inreg at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, 1
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, 2
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
-; GFX11-NEXT: s_mov_b32 s6, 3
; GFX11-NEXT: v_writelane_b32 v40, s7, 3
-; GFX11-NEXT: s_mov_b32 s7, 4
; GFX11-NEXT: v_writelane_b32 v40, s8, 4
-; GFX11-NEXT: s_mov_b32 s8, 5
; GFX11-NEXT: v_writelane_b32 v40, s9, 5
-; GFX11-NEXT: s_mov_b32 s9, 6
; GFX11-NEXT: v_writelane_b32 v40, s10, 6
-; GFX11-NEXT: s_mov_b32 s10, 7
; GFX11-NEXT: v_writelane_b32 v40, s11, 7
-; GFX11-NEXT: s_mov_b32 s11, 8
; GFX11-NEXT: v_writelane_b32 v40, s30, 8
; GFX11-NEXT: v_writelane_b32 v40, s31, 9
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i32_inreg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8i32_inreg at abs32@lo
+; GFX11-NEXT: s_mov_b32 s4, 1
+; GFX11-NEXT: s_mov_b32 s5, 2
+; GFX11-NEXT: s_mov_b32 s6, 3
+; GFX11-NEXT: s_mov_b32 s7, 4
+; GFX11-NEXT: s_mov_b32 s8, 5
+; GFX11-NEXT: s_mov_b32 s9, 6
+; GFX11-NEXT: s_mov_b32 s10, 7
+; GFX11-NEXT: s_mov_b32 s11, 8
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: v_readlane_b32 s31, v40, 9
; GFX11-NEXT: v_readlane_b32 s11, v40, 7
@@ -15079,27 +15082,27 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 10
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i32_inreg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i32_inreg at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 3
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3
-; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 4
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s8, 4
-; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 5
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s9, 5
-; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 6
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s10, 6
-; GFX10-SCRATCH-NEXT: s_mov_b32 s10, 7
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s11, 7
-; GFX10-SCRATCH-NEXT: s_mov_b32 s11, 8
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 8
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 9
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i32_inreg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i32_inreg at abs32@lo
+; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2
+; GFX10-SCRATCH-NEXT: s_mov_b32 s6, 3
+; GFX10-SCRATCH-NEXT: s_mov_b32 s7, 4
+; GFX10-SCRATCH-NEXT: s_mov_b32 s8, 5
+; GFX10-SCRATCH-NEXT: s_mov_b32 s9, 6
+; GFX10-SCRATCH-NEXT: s_mov_b32 s10, 7
+; GFX10-SCRATCH-NEXT: s_mov_b32 s11, 8
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 8
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 9
@@ -15134,6 +15137,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 18
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
@@ -15145,19 +15149,18 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX9-NEXT: v_writelane_b32 v40, s12, 8
; GFX9-NEXT: v_writelane_b32 v40, s13, 9
; GFX9-NEXT: v_writelane_b32 v40, s14, 10
-; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX9-NEXT: v_writelane_b32 v40, s15, 11
; GFX9-NEXT: v_writelane_b32 v40, s16, 12
; GFX9-NEXT: v_writelane_b32 v40, s17, 13
; GFX9-NEXT: v_writelane_b32 v40, s18, 14
; GFX9-NEXT: v_writelane_b32 v40, s19, 15
+; GFX9-NEXT: v_writelane_b32 v40, s30, 16
+; GFX9-NEXT: v_writelane_b32 v40, s31, 17
+; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_load_dwordx16 s[4:19], s[34:35], 0x0
-; GFX9-NEXT: v_writelane_b32 v40, s30, 16
; GFX9-NEXT: s_mov_b32 s35, external_void_func_v16i32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v16i32_inreg at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 17
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 16
; GFX9-NEXT: v_readlane_b32 s31, v40, 17
@@ -15196,7 +15199,6 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 18
-; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
@@ -15214,12 +15216,13 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s17, 13
; GFX10-NEXT: v_writelane_b32 v40, s18, 14
; GFX10-NEXT: v_writelane_b32 v40, s19, 15
+; GFX10-NEXT: v_writelane_b32 v40, s30, 16
+; GFX10-NEXT: v_writelane_b32 v40, s31, 17
+; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_load_dwordx16 s[4:19], s[34:35], 0x0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16i32_inreg at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16i32_inreg at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 16
-; GFX10-NEXT: v_writelane_b32 v40, s31, 17
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 16
; GFX10-NEXT: v_readlane_b32 s31, v40, 17
@@ -15258,7 +15261,6 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 18
-; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
@@ -15276,14 +15278,15 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s17, 13
; GFX11-NEXT: v_writelane_b32 v40, s18, 14
; GFX11-NEXT: v_writelane_b32 v40, s19, 15
+; GFX11-NEXT: v_writelane_b32 v40, s30, 16
+; GFX11-NEXT: v_writelane_b32 v40, s31, 17
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_load_b512 s[4:19], s[0:1], 0x0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16i32_inreg at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v16i32_inreg at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s30, 16
-; GFX11-NEXT: v_writelane_b32 v40, s31, 17
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 16
; GFX11-NEXT: v_readlane_b32 s31, v40, 17
; GFX11-NEXT: v_readlane_b32 s19, v40, 15
@@ -15321,7 +15324,6 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 18
-; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
@@ -15339,12 +15341,13 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s17, 13
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s18, 14
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s19, 15
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 17
+; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16i32_inreg at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16i32_inreg at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 17
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 16
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 17
@@ -15389,6 +15392,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 28
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
@@ -15405,23 +15409,26 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX9-NEXT: v_writelane_b32 v40, s17, 13
; GFX9-NEXT: v_writelane_b32 v40, s18, 14
; GFX9-NEXT: v_writelane_b32 v40, s19, 15
-; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX9-NEXT: v_writelane_b32 v40, s20, 16
; GFX9-NEXT: v_writelane_b32 v40, s21, 17
; GFX9-NEXT: v_writelane_b32 v40, s22, 18
; GFX9-NEXT: v_writelane_b32 v40, s23, 19
; GFX9-NEXT: v_writelane_b32 v40, s24, 20
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_load_dwordx16 s[36:51], s[34:35], 0x40
-; GFX9-NEXT: s_load_dwordx16 s[4:19], s[34:35], 0x0
; GFX9-NEXT: v_writelane_b32 v40, s25, 21
; GFX9-NEXT: v_writelane_b32 v40, s26, 22
; GFX9-NEXT: v_writelane_b32 v40, s27, 23
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s28, 24
+; GFX9-NEXT: v_writelane_b32 v40, s29, 25
+; GFX9-NEXT: v_writelane_b32 v40, s30, 26
+; GFX9-NEXT: v_writelane_b32 v40, s31, 27
+; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_load_dwordx16 s[36:51], s[34:35], 0x40
+; GFX9-NEXT: s_load_dwordx16 s[4:19], s[34:35], 0x0
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i32_inreg at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i32_inreg at abs32@lo
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s46
-; GFX9-NEXT: v_writelane_b32 v40, s29, 25
; GFX9-NEXT: v_mov_b32_e32 v1, s47
; GFX9-NEXT: v_mov_b32_e32 v2, s48
; GFX9-NEXT: v_mov_b32_e32 v3, s49
@@ -15430,11 +15437,8 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:12
; GFX9-NEXT: v_mov_b32_e32 v0, s50
-; GFX9-NEXT: v_writelane_b32 v40, s30, 26
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
; GFX9-NEXT: v_mov_b32_e32 v0, s51
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i32_inreg at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i32_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s20, s36
; GFX9-NEXT: s_mov_b32 s21, s37
; GFX9-NEXT: s_mov_b32 s22, s38
@@ -15445,7 +15449,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX9-NEXT: s_mov_b32 s27, s43
; GFX9-NEXT: s_mov_b32 s28, s44
; GFX9-NEXT: s_mov_b32 s29, s45
-; GFX9-NEXT: v_writelane_b32 v40, s31, 27
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 26
@@ -15495,7 +15498,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 28
-; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
@@ -15513,29 +15515,40 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX10-NEXT: v_writelane_b32 v40, s17, 13
; GFX10-NEXT: v_writelane_b32 v40, s18, 14
; GFX10-NEXT: v_writelane_b32 v40, s19, 15
+; GFX10-NEXT: v_writelane_b32 v40, s20, 16
+; GFX10-NEXT: v_writelane_b32 v40, s21, 17
+; GFX10-NEXT: v_writelane_b32 v40, s22, 18
+; GFX10-NEXT: v_writelane_b32 v40, s23, 19
+; GFX10-NEXT: v_writelane_b32 v40, s24, 20
+; GFX10-NEXT: v_writelane_b32 v40, s25, 21
+; GFX10-NEXT: v_writelane_b32 v40, s26, 22
+; GFX10-NEXT: v_writelane_b32 v40, s27, 23
+; GFX10-NEXT: v_writelane_b32 v40, s28, 24
+; GFX10-NEXT: v_writelane_b32 v40, s29, 25
+; GFX10-NEXT: v_writelane_b32 v40, s30, 26
+; GFX10-NEXT: v_writelane_b32 v40, s31, 27
+; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx16 s[36:51], s[34:35], 0x40
; GFX10-NEXT: s_load_dwordx16 s[4:19], s[34:35], 0x0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v32i32_inreg at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v32i32_inreg at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s20, 16
-; GFX10-NEXT: v_writelane_b32 v40, s21, 17
-; GFX10-NEXT: v_writelane_b32 v40, s22, 18
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s46
-; GFX10-NEXT: v_writelane_b32 v40, s23, 19
; GFX10-NEXT: v_mov_b32_e32 v1, s47
; GFX10-NEXT: v_mov_b32_e32 v2, s48
; GFX10-NEXT: v_mov_b32_e32 v3, s49
; GFX10-NEXT: s_mov_b32 s20, s36
-; GFX10-NEXT: v_writelane_b32 v40, s24, 20
; GFX10-NEXT: s_mov_b32 s21, s37
; GFX10-NEXT: s_mov_b32 s22, s38
; GFX10-NEXT: s_mov_b32 s23, s39
; GFX10-NEXT: s_mov_b32 s24, s40
-; GFX10-NEXT: v_writelane_b32 v40, s25, 21
; GFX10-NEXT: s_mov_b32 s25, s41
+; GFX10-NEXT: s_mov_b32 s26, s42
+; GFX10-NEXT: s_mov_b32 s27, s43
+; GFX10-NEXT: s_mov_b32 s28, s44
+; GFX10-NEXT: s_mov_b32 s29, s45
; GFX10-NEXT: v_mov_b32_e32 v4, s50
; GFX10-NEXT: v_mov_b32_e32 v5, s51
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32
@@ -15544,16 +15557,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:12
; GFX10-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:16
; GFX10-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:20
-; GFX10-NEXT: v_writelane_b32 v40, s26, 22
-; GFX10-NEXT: s_mov_b32 s26, s42
-; GFX10-NEXT: v_writelane_b32 v40, s27, 23
-; GFX10-NEXT: s_mov_b32 s27, s43
-; GFX10-NEXT: v_writelane_b32 v40, s28, 24
-; GFX10-NEXT: s_mov_b32 s28, s44
-; GFX10-NEXT: v_writelane_b32 v40, s29, 25
-; GFX10-NEXT: s_mov_b32 s29, s45
-; GFX10-NEXT: v_writelane_b32 v40, s30, 26
-; GFX10-NEXT: v_writelane_b32 v40, s31, 27
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 26
; GFX10-NEXT: v_readlane_b32 s31, v40, 27
@@ -15602,10 +15605,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 28
-; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_add_i32 s2, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
@@ -15622,42 +15622,43 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX11-NEXT: v_writelane_b32 v40, s17, 13
; GFX11-NEXT: v_writelane_b32 v40, s18, 14
; GFX11-NEXT: v_writelane_b32 v40, s19, 15
+; GFX11-NEXT: v_writelane_b32 v40, s20, 16
+; GFX11-NEXT: v_writelane_b32 v40, s21, 17
+; GFX11-NEXT: v_writelane_b32 v40, s22, 18
+; GFX11-NEXT: v_writelane_b32 v40, s23, 19
+; GFX11-NEXT: v_writelane_b32 v40, s24, 20
+; GFX11-NEXT: v_writelane_b32 v40, s25, 21
+; GFX11-NEXT: v_writelane_b32 v40, s26, 22
+; GFX11-NEXT: v_writelane_b32 v40, s27, 23
+; GFX11-NEXT: v_writelane_b32 v40, s28, 24
+; GFX11-NEXT: v_writelane_b32 v40, s29, 25
+; GFX11-NEXT: v_writelane_b32 v40, s30, 26
+; GFX11-NEXT: v_writelane_b32 v40, s31, 27
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-NEXT: s_add_i32 s2, s32, 16
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b512 s[36:51], s[0:1], 0x40
; GFX11-NEXT: s_load_b512 s[4:19], s[0:1], 0x0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v32i32_inreg at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v32i32_inreg at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s20, 16
-; GFX11-NEXT: v_writelane_b32 v40, s21, 17
-; GFX11-NEXT: v_writelane_b32 v40, s22, 18
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v4, s50 :: v_dual_mov_b32 v5, s51
-; GFX11-NEXT: v_writelane_b32 v40, s23, 19
; GFX11-NEXT: v_dual_mov_b32 v0, s46 :: v_dual_mov_b32 v1, s47
; GFX11-NEXT: v_dual_mov_b32 v2, s48 :: v_dual_mov_b32 v3, s49
-; GFX11-NEXT: v_writelane_b32 v40, s24, 20
; GFX11-NEXT: s_mov_b32 s20, s36
; GFX11-NEXT: s_mov_b32 s21, s37
; GFX11-NEXT: s_mov_b32 s22, s38
; GFX11-NEXT: s_mov_b32 s23, s39
-; GFX11-NEXT: v_writelane_b32 v40, s25, 21
; GFX11-NEXT: s_mov_b32 s24, s40
; GFX11-NEXT: s_mov_b32 s25, s41
-; GFX11-NEXT: scratch_store_b64 off, v[4:5], s2
-; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32
-; GFX11-NEXT: v_writelane_b32 v40, s26, 22
; GFX11-NEXT: s_mov_b32 s26, s42
-; GFX11-NEXT: v_writelane_b32 v40, s27, 23
; GFX11-NEXT: s_mov_b32 s27, s43
-; GFX11-NEXT: v_writelane_b32 v40, s28, 24
; GFX11-NEXT: s_mov_b32 s28, s44
-; GFX11-NEXT: v_writelane_b32 v40, s29, 25
; GFX11-NEXT: s_mov_b32 s29, s45
-; GFX11-NEXT: v_writelane_b32 v40, s30, 26
-; GFX11-NEXT: v_writelane_b32 v40, s31, 27
+; GFX11-NEXT: scratch_store_b64 off, v[4:5], s2
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 26
; GFX11-NEXT: v_readlane_b32 s31, v40, 27
; GFX11-NEXT: v_readlane_b32 s29, v40, 25
@@ -15705,9 +15706,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 28
-; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: s_add_i32 s2, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
@@ -15724,43 +15723,45 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s17, 13
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s18, 14
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s19, 15
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s20, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s21, 17
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s22, 18
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s23, 19
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s24, 20
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s25, 21
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s26, 22
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s27, 23
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s28, 24
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s29, 25
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 26
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 27
+; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
+; GFX10-SCRATCH-NEXT: s_add_i32 s2, s32, 16
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: s_clause 0x1
; GFX10-SCRATCH-NEXT: s_load_dwordx16 s[36:51], s[0:1], 0x40
; GFX10-SCRATCH-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v32i32_inreg at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v32i32_inreg at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s20, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s21, 17
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s22, 18
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, s50
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s23, 19
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, s51
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, s46
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, s47
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, s48
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s24, 20
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, s49
; GFX10-SCRATCH-NEXT: s_mov_b32 s20, s36
; GFX10-SCRATCH-NEXT: s_mov_b32 s21, s37
; GFX10-SCRATCH-NEXT: s_mov_b32 s22, s38
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s25, 21
; GFX10-SCRATCH-NEXT: s_mov_b32 s23, s39
; GFX10-SCRATCH-NEXT: s_mov_b32 s24, s40
; GFX10-SCRATCH-NEXT: s_mov_b32 s25, s41
-; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[4:5], s2
-; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s26, 22
; GFX10-SCRATCH-NEXT: s_mov_b32 s26, s42
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s27, 23
; GFX10-SCRATCH-NEXT: s_mov_b32 s27, s43
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s28, 24
; GFX10-SCRATCH-NEXT: s_mov_b32 s28, s44
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s29, 25
; GFX10-SCRATCH-NEXT: s_mov_b32 s29, s45
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 26
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 27
+; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[4:5], s2
+; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 26
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 27
@@ -15815,6 +15816,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 28
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s6, 2
@@ -15830,41 +15832,41 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX9-NEXT: v_writelane_b32 v40, s16, 12
; GFX9-NEXT: v_writelane_b32 v40, s17, 13
; GFX9-NEXT: v_writelane_b32 v40, s18, 14
-; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX9-NEXT: v_writelane_b32 v40, s19, 15
; GFX9-NEXT: v_writelane_b32 v40, s20, 16
; GFX9-NEXT: v_writelane_b32 v40, s21, 17
; GFX9-NEXT: v_writelane_b32 v40, s22, 18
; GFX9-NEXT: v_writelane_b32 v40, s23, 19
+; GFX9-NEXT: v_writelane_b32 v40, s24, 20
+; GFX9-NEXT: v_writelane_b32 v40, s25, 21
+; GFX9-NEXT: v_writelane_b32 v40, s26, 22
+; GFX9-NEXT: v_writelane_b32 v40, s27, 23
+; GFX9-NEXT: v_writelane_b32 v40, s28, 24
+; GFX9-NEXT: v_writelane_b32 v40, s29, 25
+; GFX9-NEXT: v_writelane_b32 v40, s30, 26
+; GFX9-NEXT: v_writelane_b32 v40, s31, 27
+; GFX9-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_load_dword s52, s[34:35], 0x0
; GFX9-NEXT: ; kill: killed $sgpr34_sgpr35
; GFX9-NEXT: ; kill: killed $sgpr34_sgpr35
; GFX9-NEXT: s_load_dwordx16 s[36:51], s[34:35], 0x40
; GFX9-NEXT: s_load_dwordx16 s[4:19], s[34:35], 0x0
-; GFX9-NEXT: v_writelane_b32 v40, s24, 20
-; GFX9-NEXT: v_writelane_b32 v40, s25, 21
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s26, 22
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s52
-; GFX9-NEXT: v_writelane_b32 v40, s27, 23
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i32_i32_inreg at abs32@hi
; GFX9-NEXT: v_mov_b32_e32 v0, s46
-; GFX9-NEXT: v_writelane_b32 v40, s28, 24
; GFX9-NEXT: v_mov_b32_e32 v1, s47
; GFX9-NEXT: v_mov_b32_e32 v2, s48
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4
; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
; GFX9-NEXT: v_mov_b32_e32 v0, s49
-; GFX9-NEXT: v_writelane_b32 v40, s29, 25
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12
; GFX9-NEXT: v_mov_b32_e32 v0, s50
-; GFX9-NEXT: v_writelane_b32 v40, s30, 26
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16
; GFX9-NEXT: v_mov_b32_e32 v0, s51
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i32_i32_inreg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i32_i32_inreg at abs32@lo
; GFX9-NEXT: s_mov_b32 s20, s36
; GFX9-NEXT: s_mov_b32 s21, s37
@@ -15876,7 +15878,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX9-NEXT: s_mov_b32 s27, s43
; GFX9-NEXT: s_mov_b32 s28, s44
; GFX9-NEXT: s_mov_b32 s29, s45
-; GFX9-NEXT: v_writelane_b32 v40, s31, 27
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 26
@@ -15926,7 +15927,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 28
-; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
@@ -15944,6 +15944,19 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX10-NEXT: v_writelane_b32 v40, s17, 13
; GFX10-NEXT: v_writelane_b32 v40, s18, 14
; GFX10-NEXT: v_writelane_b32 v40, s19, 15
+; GFX10-NEXT: v_writelane_b32 v40, s20, 16
+; GFX10-NEXT: v_writelane_b32 v40, s21, 17
+; GFX10-NEXT: v_writelane_b32 v40, s22, 18
+; GFX10-NEXT: v_writelane_b32 v40, s23, 19
+; GFX10-NEXT: v_writelane_b32 v40, s24, 20
+; GFX10-NEXT: v_writelane_b32 v40, s25, 21
+; GFX10-NEXT: v_writelane_b32 v40, s26, 22
+; GFX10-NEXT: v_writelane_b32 v40, s27, 23
+; GFX10-NEXT: v_writelane_b32 v40, s28, 24
+; GFX10-NEXT: v_writelane_b32 v40, s29, 25
+; GFX10-NEXT: v_writelane_b32 v40, s30, 26
+; GFX10-NEXT: v_writelane_b32 v40, s31, 27
+; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: s_load_dword s52, s[34:35], 0x0
@@ -15953,43 +15966,31 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX10-NEXT: s_load_dwordx16 s[4:19], s[34:35], 0x0
; GFX10-NEXT: s_mov_b32 s35, external_void_func_v32i32_i32_inreg at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_v32i32_i32_inreg at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s20, 16
-; GFX10-NEXT: v_writelane_b32 v40, s21, 17
-; GFX10-NEXT: v_writelane_b32 v40, s22, 18
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s52
; GFX10-NEXT: v_mov_b32_e32 v1, s47
-; GFX10-NEXT: v_writelane_b32 v40, s23, 19
+; GFX10-NEXT: v_mov_b32_e32 v2, s48
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24
; GFX10-NEXT: v_mov_b32_e32 v0, s46
-; GFX10-NEXT: v_mov_b32_e32 v2, s48
; GFX10-NEXT: v_mov_b32_e32 v3, s49
-; GFX10-NEXT: v_writelane_b32 v40, s24, 20
; GFX10-NEXT: s_mov_b32 s20, s36
; GFX10-NEXT: s_mov_b32 s21, s37
; GFX10-NEXT: s_mov_b32 s22, s38
; GFX10-NEXT: s_mov_b32 s23, s39
-; GFX10-NEXT: v_writelane_b32 v40, s25, 21
; GFX10-NEXT: s_mov_b32 s24, s40
; GFX10-NEXT: s_mov_b32 s25, s41
+; GFX10-NEXT: s_mov_b32 s26, s42
+; GFX10-NEXT: s_mov_b32 s27, s43
+; GFX10-NEXT: s_mov_b32 s28, s44
+; GFX10-NEXT: s_mov_b32 s29, s45
; GFX10-NEXT: v_mov_b32_e32 v4, s50
; GFX10-NEXT: v_mov_b32_e32 v5, s51
-; GFX10-NEXT: v_writelane_b32 v40, s26, 22
-; GFX10-NEXT: s_mov_b32 s26, s42
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
; GFX10-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:12
; GFX10-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:16
; GFX10-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:20
-; GFX10-NEXT: v_writelane_b32 v40, s27, 23
-; GFX10-NEXT: s_mov_b32 s27, s43
-; GFX10-NEXT: v_writelane_b32 v40, s28, 24
-; GFX10-NEXT: s_mov_b32 s28, s44
-; GFX10-NEXT: v_writelane_b32 v40, s29, 25
-; GFX10-NEXT: s_mov_b32 s29, s45
-; GFX10-NEXT: v_writelane_b32 v40, s30, 26
-; GFX10-NEXT: v_writelane_b32 v40, s31, 27
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 26
; GFX10-NEXT: v_readlane_b32 s31, v40, 27
@@ -16038,10 +16039,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 28
-; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_add_i32 s3, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
; GFX11-NEXT: v_writelane_b32 v40, s6, 2
@@ -16058,6 +16056,20 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX11-NEXT: v_writelane_b32 v40, s17, 13
; GFX11-NEXT: v_writelane_b32 v40, s18, 14
; GFX11-NEXT: v_writelane_b32 v40, s19, 15
+; GFX11-NEXT: v_writelane_b32 v40, s20, 16
+; GFX11-NEXT: v_writelane_b32 v40, s21, 17
+; GFX11-NEXT: v_writelane_b32 v40, s22, 18
+; GFX11-NEXT: v_writelane_b32 v40, s23, 19
+; GFX11-NEXT: v_writelane_b32 v40, s24, 20
+; GFX11-NEXT: v_writelane_b32 v40, s25, 21
+; GFX11-NEXT: v_writelane_b32 v40, s26, 22
+; GFX11-NEXT: v_writelane_b32 v40, s27, 23
+; GFX11-NEXT: v_writelane_b32 v40, s28, 24
+; GFX11-NEXT: v_writelane_b32 v40, s29, 25
+; GFX11-NEXT: v_writelane_b32 v40, s30, 26
+; GFX11-NEXT: v_writelane_b32 v40, s31, 27
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-NEXT: s_add_i32 s3, s32, 16
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x0
@@ -16065,39 +16077,26 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX11-NEXT: s_load_b512 s[4:19], s[0:1], 0x0
; GFX11-NEXT: s_mov_b32 s1, external_void_func_v32i32_i32_inreg at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_v32i32_i32_inreg at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s20, 16
-; GFX11-NEXT: v_writelane_b32 v40, s21, 17
-; GFX11-NEXT: v_writelane_b32 v40, s22, 18
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v5, s51
-; GFX11-NEXT: v_writelane_b32 v40, s23, 19
; GFX11-NEXT: v_dual_mov_b32 v4, s50 :: v_dual_mov_b32 v1, s47
; GFX11-NEXT: v_dual_mov_b32 v0, s46 :: v_dual_mov_b32 v3, s49
-; GFX11-NEXT: v_writelane_b32 v40, s24, 20
; GFX11-NEXT: v_mov_b32_e32 v2, s48
; GFX11-NEXT: s_add_i32 s2, s32, 24
; GFX11-NEXT: s_mov_b32 s20, s36
; GFX11-NEXT: s_mov_b32 s21, s37
-; GFX11-NEXT: v_writelane_b32 v40, s25, 21
; GFX11-NEXT: s_mov_b32 s22, s38
; GFX11-NEXT: s_mov_b32 s23, s39
; GFX11-NEXT: s_mov_b32 s24, s40
; GFX11-NEXT: s_mov_b32 s25, s41
-; GFX11-NEXT: v_writelane_b32 v40, s26, 22
; GFX11-NEXT: s_mov_b32 s26, s42
-; GFX11-NEXT: scratch_store_b32 off, v6, s2
-; GFX11-NEXT: scratch_store_b64 off, v[4:5], s3
-; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32
-; GFX11-NEXT: v_writelane_b32 v40, s27, 23
; GFX11-NEXT: s_mov_b32 s27, s43
-; GFX11-NEXT: v_writelane_b32 v40, s28, 24
; GFX11-NEXT: s_mov_b32 s28, s44
-; GFX11-NEXT: v_writelane_b32 v40, s29, 25
; GFX11-NEXT: s_mov_b32 s29, s45
-; GFX11-NEXT: v_writelane_b32 v40, s30, 26
-; GFX11-NEXT: v_writelane_b32 v40, s31, 27
+; GFX11-NEXT: scratch_store_b32 off, v6, s2
+; GFX11-NEXT: scratch_store_b64 off, v[4:5], s3
+; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 26
; GFX11-NEXT: v_readlane_b32 s31, v40, 27
; GFX11-NEXT: v_readlane_b32 s29, v40, 25
@@ -16145,9 +16144,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 28
-; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: s_add_i32 s3, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2
@@ -16164,6 +16161,20 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s17, 13
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s18, 14
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s19, 15
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s20, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s21, 17
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s22, 18
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s23, 19
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s24, 20
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s25, 21
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s26, 22
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s27, 23
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s28, 24
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s29, 25
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 26
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 27
+; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
+; GFX10-SCRATCH-NEXT: s_add_i32 s3, s32, 16
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: s_clause 0x2
; GFX10-SCRATCH-NEXT: s_load_dword s2, s[0:1], 0x0
@@ -16173,40 +16184,28 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 {
; GFX10-SCRATCH-NEXT: s_load_dwordx16 s[4:19], s[0:1], 0x0
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v32i32_i32_inreg at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v32i32_i32_inreg at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s20, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s21, 17
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s22, 18
; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, s2
; GFX10-SCRATCH-NEXT: s_add_i32 s2, s32, 24
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, s50
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s23, 19
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, s51
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, s46
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, s47
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, s48
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s24, 20
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, s49
; GFX10-SCRATCH-NEXT: s_mov_b32 s20, s36
; GFX10-SCRATCH-NEXT: s_mov_b32 s21, s37
; GFX10-SCRATCH-NEXT: s_mov_b32 s22, s38
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s25, 21
; GFX10-SCRATCH-NEXT: s_mov_b32 s23, s39
; GFX10-SCRATCH-NEXT: s_mov_b32 s24, s40
; GFX10-SCRATCH-NEXT: s_mov_b32 s25, s41
-; GFX10-SCRATCH-NEXT: scratch_store_dword off, v6, s2
-; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[4:5], s3
-; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s26, 22
; GFX10-SCRATCH-NEXT: s_mov_b32 s26, s42
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s27, 23
; GFX10-SCRATCH-NEXT: s_mov_b32 s27, s43
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s28, 24
; GFX10-SCRATCH-NEXT: s_mov_b32 s28, s44
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s29, 25
; GFX10-SCRATCH-NEXT: s_mov_b32 s29, s45
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 26
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 27
+; GFX10-SCRATCH-NEXT: scratch_store_dword off, v6, s2
+; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[4:5], s3
+; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 26
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 27
@@ -16261,14 +16260,14 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s33
-; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:4
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
-; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s33
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:4
; GFX9-NEXT: s_mov_b32 s35, stack_passed_f64_arg at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, stack_passed_f64_arg at abs32@lo
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -16294,19 +16293,19 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:4
-; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: s_mov_b32 s35, stack_passed_f64_arg at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, stack_passed_f64_arg at abs32@lo
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: buffer_store_dword v32, off, s[0:3], s32
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -16328,13 +16327,13 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:8 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: scratch_load_b64 v[32:33], off, s33
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: s_mov_b32 s1, stack_passed_f64_arg at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, stack_passed_f64_arg at abs32@lo
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: scratch_load_b64 v[32:33], off, s33
+; GFX11-NEXT: s_mov_b32 s1, stack_passed_f64_arg at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, stack_passed_f64_arg at abs32@lo
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: scratch_store_b64 off, v[32:33], s32
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -16358,13 +16357,13 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d
; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:8 ; 4-byte Folded Spill
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
-; GFX10-SCRATCH-NEXT: scratch_load_dwordx2 v[32:33], off, s33
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, stack_passed_f64_arg at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, stack_passed_f64_arg at abs32@lo
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: scratch_load_dwordx2 v[32:33], off, s33
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, stack_passed_f64_arg at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, stack_passed_f64_arg at abs32@lo
; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0)
; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[32:33], s32
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
@@ -16393,16 +16392,17 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 12
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX9-NEXT: v_mov_b32_e32 v0, 13
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4
; GFX9-NEXT: v_mov_b32_e32 v0, 14
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8
; GFX9-NEXT: v_mov_b32_e32 v0, 15
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12
; GFX9-NEXT: s_mov_b32 s35, external_void_func_12xv3i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_12xv3i32 at abs32@lo
@@ -16438,7 +16438,6 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v29, 9
; GFX9-NEXT: v_mov_b32_e32 v30, 10
; GFX9-NEXT: v_mov_b32_e32 v31, 11
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -16461,12 +16460,14 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 12
; GFX10-NEXT: v_mov_b32_e32 v1, 13
; GFX10-NEXT: v_mov_b32_e32 v2, 14
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_mov_b32_e32 v3, 15
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_mov_b32_e32 v4, 1
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
@@ -16475,7 +16476,6 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 1
-; GFX10-NEXT: v_mov_b32_e32 v4, 1
; GFX10-NEXT: v_mov_b32_e32 v5, 1
; GFX10-NEXT: v_mov_b32_e32 v6, 2
; GFX10-NEXT: v_mov_b32_e32 v7, 2
@@ -16505,7 +16505,6 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX10-NEXT: v_mov_b32_e32 v31, 11
; GFX10-NEXT: s_mov_b32 s35, external_void_func_12xv3i32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_12xv3i32 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -16528,15 +16527,16 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: v_dual_mov_b32 v0, 12 :: v_dual_mov_b32 v1, 13
-; GFX11-NEXT: v_dual_mov_b32 v2, 14 :: v_dual_mov_b32 v3, 15
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: v_dual_mov_b32 v0, 12 :: v_dual_mov_b32 v1, 13
+; GFX11-NEXT: v_dual_mov_b32 v2, 14 :: v_dual_mov_b32 v3, 15
; GFX11-NEXT: v_dual_mov_b32 v4, 1 :: v_dual_mov_b32 v5, 1
+; GFX11-NEXT: v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 2
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 1
-; GFX11-NEXT: v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 2
; GFX11-NEXT: v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 3
; GFX11-NEXT: v_dual_mov_b32 v10, 3 :: v_dual_mov_b32 v11, 3
; GFX11-NEXT: v_dual_mov_b32 v12, 4 :: v_dual_mov_b32 v13, 4
@@ -16551,9 +16551,8 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX11-NEXT: v_dual_mov_b32 v30, 10 :: v_dual_mov_b32 v31, 11
; GFX11-NEXT: s_mov_b32 s1, external_void_func_12xv3i32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_12xv3i32 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -16575,21 +16574,22 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 12
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 13
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 14
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 15
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 1
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 2
+; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 2
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 1
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 2
-; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v8, 2
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v9, 3
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v10, 3
@@ -16616,7 +16616,6 @@ define amdgpu_gfx void @stack_12xv3i32() #0 {
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v31, 11
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_12xv3i32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_12xv3i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -16655,7 +16654,10 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 8
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX9-NEXT: v_mov_b32_e32 v0, 9
@@ -16669,10 +16671,8 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v0, 13
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20
; GFX9-NEXT: v_mov_b32_e32 v0, 14
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24
; GFX9-NEXT: v_mov_b32_e32 v0, 15
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28
; GFX9-NEXT: s_mov_b32 s35, external_void_func_8xv5i32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_8xv5i32 at abs32@lo
@@ -16708,7 +16708,6 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v29, 5
; GFX9-NEXT: v_mov_b32_e32 v30, 6
; GFX9-NEXT: v_mov_b32_e32 v31, 7
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -16730,20 +16729,22 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 8
; GFX10-NEXT: v_mov_b32_e32 v1, 9
; GFX10-NEXT: v_mov_b32_e32 v2, 10
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: v_mov_b32_e32 v3, 14
+; GFX10-NEXT: v_mov_b32_e32 v4, 15
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
; GFX10-NEXT: v_mov_b32_e32 v0, 11
; GFX10-NEXT: v_mov_b32_e32 v1, 12
; GFX10-NEXT: v_mov_b32_e32 v2, 13
-; GFX10-NEXT: v_mov_b32_e32 v3, 14
-; GFX10-NEXT: v_mov_b32_e32 v4, 15
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_mov_b32_e32 v5, 1
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:16
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:20
@@ -16754,7 +16755,6 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 0
-; GFX10-NEXT: v_mov_b32_e32 v5, 1
; GFX10-NEXT: v_mov_b32_e32 v6, 1
; GFX10-NEXT: v_mov_b32_e32 v7, 1
; GFX10-NEXT: v_mov_b32_e32 v8, 1
@@ -16783,7 +16783,6 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX10-NEXT: v_mov_b32_e32 v31, 7
; GFX10-NEXT: s_mov_b32 s35, external_void_func_8xv5i32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_8xv5i32 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -16806,12 +16805,13 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_dual_mov_b32 v0, 8 :: v_dual_mov_b32 v1, 9
; GFX11-NEXT: v_dual_mov_b32 v2, 10 :: v_dual_mov_b32 v3, 11
; GFX11-NEXT: v_dual_mov_b32 v4, 12 :: v_dual_mov_b32 v5, 13
; GFX11-NEXT: v_dual_mov_b32 v6, 14 :: v_dual_mov_b32 v7, 15
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_add_i32 s0, s32, 16
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32
; GFX11-NEXT: scratch_store_b128 off, v[4:7], s0
@@ -16833,9 +16833,8 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX11-NEXT: v_dual_mov_b32 v30, 6 :: v_dual_mov_b32 v31, 7
; GFX11-NEXT: s_mov_b32 s1, external_void_func_8xv5i32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_8xv5i32 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -16857,6 +16856,9 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 8
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 9
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 10
@@ -16865,8 +16867,6 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 13
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 14
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 15
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: s_add_i32 s0, s32, 16
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[4:7], s0
@@ -16904,7 +16904,6 @@ define amdgpu_gfx void @stack_8xv5i32() #0 {
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v31, 7
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_8xv5i32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_8xv5i32 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -16939,7 +16938,10 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
+; GFX9-NEXT: v_writelane_b32 v40, s34, 2
+; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v0, 0x41000000
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX9-NEXT: v_mov_b32_e32 v0, 0x41100000
@@ -16953,10 +16955,8 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v0, 0x41500000
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20
; GFX9-NEXT: v_mov_b32_e32 v0, 0x41600000
-; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24
; GFX9-NEXT: v_mov_b32_e32 v0, 0x41700000
-; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28
; GFX9-NEXT: s_mov_b32 s35, external_void_func_8xv5f32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_8xv5f32 at abs32@lo
@@ -16992,7 +16992,6 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX9-NEXT: v_mov_b32_e32 v29, 0x40a00000
; GFX9-NEXT: v_mov_b32_e32 v30, 0x40c00000
; GFX9-NEXT: v_mov_b32_e32 v31, 0x40e00000
-; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -17014,20 +17013,22 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
+; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v0, 0x41000000
; GFX10-NEXT: v_mov_b32_e32 v1, 0x41100000
; GFX10-NEXT: v_mov_b32_e32 v2, 0x41200000
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s34, 2
+; GFX10-NEXT: v_mov_b32_e32 v3, 0x41600000
+; GFX10-NEXT: v_mov_b32_e32 v4, 0x41700000
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
; GFX10-NEXT: v_mov_b32_e32 v0, 0x41300000
; GFX10-NEXT: v_mov_b32_e32 v1, 0x41400000
; GFX10-NEXT: v_mov_b32_e32 v2, 0x41500000
-; GFX10-NEXT: v_mov_b32_e32 v3, 0x41600000
-; GFX10-NEXT: v_mov_b32_e32 v4, 0x41700000
-; GFX10-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-NEXT: v_mov_b32_e32 v5, 1.0
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12
; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:16
; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:20
@@ -17038,7 +17039,6 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 0
-; GFX10-NEXT: v_mov_b32_e32 v5, 1.0
; GFX10-NEXT: v_mov_b32_e32 v6, 1.0
; GFX10-NEXT: v_mov_b32_e32 v7, 1.0
; GFX10-NEXT: v_mov_b32_e32 v8, 1.0
@@ -17067,7 +17067,6 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX10-NEXT: v_mov_b32_e32 v31, 0x40e00000
; GFX10-NEXT: s_mov_b32 s35, external_void_func_8xv5f32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_8xv5f32 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -17090,6 +17089,9 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s30, 0
+; GFX11-NEXT: v_writelane_b32 v40, s31, 1
; GFX11-NEXT: v_mov_b32_e32 v0, 0x41000000
; GFX11-NEXT: v_mov_b32_e32 v1, 0x41100000
; GFX11-NEXT: v_mov_b32_e32 v2, 0x41200000
@@ -17098,8 +17100,6 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX11-NEXT: v_mov_b32_e32 v5, 0x41500000
; GFX11-NEXT: v_mov_b32_e32 v6, 0x41600000
; GFX11-NEXT: v_mov_b32_e32 v7, 0x41700000
-; GFX11-NEXT: s_add_i32 s32, s32, 16
-; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: s_add_i32 s0, s32, 16
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32
; GFX11-NEXT: scratch_store_b128 off, v[4:7], s0
@@ -17122,9 +17122,8 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX11-NEXT: v_mov_b32_e32 v31, 0x40e00000
; GFX11-NEXT: s_mov_b32 s1, external_void_func_8xv5f32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_8xv5f32 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -17146,6 +17145,9 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
+; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
+; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x41000000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0x41100000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0x41200000
@@ -17154,8 +17156,6 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 0x41500000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 0x41600000
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 0x41700000
-; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: s_add_i32 s0, s32, 16
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[0:3], s32
; GFX10-SCRATCH-NEXT: scratch_store_dwordx4 off, v[4:7], s0
@@ -17193,7 +17193,6 @@ define amdgpu_gfx void @stack_8xv5f32() #0 {
; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v31, 0x40e00000
; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_8xv5f32 at abs32@hi
; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_8xv5f32 at abs32@lo
-; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -17230,10 +17229,10 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_bf16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_bf16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_bf16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_bf16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -17256,11 +17255,11 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_bf16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_bf16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_bf16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_bf16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -17283,13 +17282,13 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_bf16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_bf16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_bf16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_bf16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -17311,11 +17310,11 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_bf16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_bf16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -17344,10 +17343,10 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v1bf16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v1bf16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v1bf16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v1bf16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -17370,11 +17369,11 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v1bf16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v1bf16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v1bf16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v1bf16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -17397,13 +17396,13 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v1bf16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v1bf16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v1bf16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v1bf16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -17425,11 +17424,11 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v1bf16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v1bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v1bf16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v1bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -17458,10 +17457,10 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2bf16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2bf16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2bf16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2bf16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -17484,11 +17483,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2bf16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2bf16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2bf16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2bf16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -17511,13 +17510,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2bf16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2bf16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2bf16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2bf16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -17539,11 +17538,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2bf16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2bf16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -17572,10 +17571,10 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3bf16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3bf16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3bf16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3bf16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -17598,11 +17597,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3bf16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3bf16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3bf16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3bf16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -17625,13 +17624,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3bf16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3bf16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3bf16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3bf16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -17653,11 +17652,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3bf16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3bf16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -17686,10 +17685,10 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4bf16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4bf16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4bf16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4bf16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -17712,11 +17711,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4bf16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4bf16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4bf16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4bf16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -17739,13 +17738,13 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4bf16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4bf16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4bf16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4bf16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -17767,11 +17766,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4bf16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4bf16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -17800,10 +17799,10 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8bf16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8bf16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8bf16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8bf16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -17826,11 +17825,11 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8bf16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8bf16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8bf16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8bf16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -17853,13 +17852,13 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8bf16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8bf16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8bf16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8bf16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -17881,11 +17880,11 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 {
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8bf16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8bf16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -17914,10 +17913,10 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v16bf16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v16bf16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v16bf16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v16bf16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -17940,11 +17939,11 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16bf16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16bf16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16bf16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16bf16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -17967,13 +17966,13 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16bf16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v16bf16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16bf16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v16bf16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -17995,11 +17994,11 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16bf16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16bf16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -18028,10 +18027,10 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg)
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_bf16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_bf16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_bf16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_bf16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -18054,11 +18053,11 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg)
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_bf16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_bf16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_bf16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_bf16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -18081,13 +18080,13 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg)
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_bf16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_bf16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_bf16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_bf16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -18109,11 +18108,11 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg)
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_bf16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_bf16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -18142,10 +18141,10 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v1bf16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v1bf16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v1bf16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v1bf16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -18168,11 +18167,11 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v1bf16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v1bf16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v1bf16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v1bf16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -18195,13 +18194,13 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v1bf16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v1bf16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v1bf16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v1bf16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -18223,11 +18222,11 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v1bf16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v1bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v1bf16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v1bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -18256,10 +18255,10 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2bf16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2bf16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2bf16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2bf16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -18282,11 +18281,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2bf16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2bf16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2bf16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2bf16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -18309,13 +18308,13 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2bf16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2bf16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2bf16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2bf16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -18337,11 +18336,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2bf16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2bf16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -18370,10 +18369,10 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3bf16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3bf16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3bf16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3bf16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -18396,11 +18395,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3bf16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3bf16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3bf16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3bf16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -18423,13 +18422,13 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3bf16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3bf16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3bf16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3bf16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -18451,11 +18450,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3bf16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3bf16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -18484,10 +18483,10 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4bf16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4bf16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4bf16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4bf16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -18510,11 +18509,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4bf16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4bf16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4bf16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4bf16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -18537,13 +18536,13 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4bf16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4bf16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4bf16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4bf16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -18565,11 +18564,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4bf16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4bf16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -18598,10 +18597,10 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8bf16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8bf16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8bf16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8bf16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -18624,11 +18623,11 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8bf16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8bf16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8bf16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8bf16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -18651,13 +18650,13 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8bf16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8bf16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8bf16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8bf16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -18679,11 +18678,11 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8bf16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8bf16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
@@ -18712,10 +18711,10 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_v16bf16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_v16bf16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_v16bf16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_v16bf16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -18738,11 +18737,11 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16bf16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16bf16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16bf16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16bf16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -18765,13 +18764,13 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16bf16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_v16bf16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16bf16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_v16bf16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -18793,11 +18792,11 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in
; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2
-; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16bf16 at abs32@hi
-; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16bf16 at abs32@hi
+; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16bf16 at abs32@lo
; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
index ecf2b33841076..bb415f07ae769 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
@@ -15,13 +15,13 @@ define amdgpu_gfx void @test_call_external_void_func_void_clobber_s30_s31_call_e
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 4
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s5, 1
; GFX9-NEXT: v_writelane_b32 v40, s30, 2
+; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_mov_b32 s5, external_void_func_void at abs32@hi
; GFX9-NEXT: s_mov_b32 s4, external_void_func_void at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 3
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ;;#ASMEND
@@ -51,11 +51,11 @@ define amdgpu_gfx void @test_call_external_void_func_void_clobber_s30_s31_call_e
; GFX10-NEXT: v_writelane_b32 v40, s34, 4
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
-; GFX10-NEXT: s_mov_b32 s4, external_void_func_void at abs32@lo
; GFX10-NEXT: v_writelane_b32 v40, s5, 1
-; GFX10-NEXT: s_mov_b32 s5, external_void_func_void at abs32@hi
; GFX10-NEXT: v_writelane_b32 v40, s30, 2
; GFX10-NEXT: v_writelane_b32 v40, s31, 3
+; GFX10-NEXT: s_mov_b32 s5, external_void_func_void at abs32@hi
+; GFX10-NEXT: s_mov_b32 s4, external_void_func_void at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
@@ -85,16 +85,16 @@ define amdgpu_gfx void @test_call_external_void_func_void_clobber_s30_s31_call_e
; GFX11-NEXT: v_writelane_b32 v40, s0, 4
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
-; GFX11-NEXT: s_mov_b32 s4, external_void_func_void at abs32@lo
; GFX11-NEXT: v_writelane_b32 v40, s5, 1
-; GFX11-NEXT: s_mov_b32 s5, external_void_func_void at abs32@hi
; GFX11-NEXT: v_writelane_b32 v40, s30, 2
; GFX11-NEXT: v_writelane_b32 v40, s31, 3
+; GFX11-NEXT: s_mov_b32 s5, external_void_func_void at abs32@hi
+; GFX11-NEXT: s_mov_b32 s4, external_void_func_void at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 2
; GFX11-NEXT: v_readlane_b32 s31, v40, 3
; GFX11-NEXT: v_readlane_b32 s5, v40, 1
@@ -209,12 +209,12 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1)
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 3
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s30, 1
+; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def s31
; GFX9-NEXT: ;;#ASMEND
@@ -246,12 +246,12 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1)
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: v_writelane_b32 v40, s30, 1
; GFX10-NEXT: v_writelane_b32 v40, s31, 2
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; def s31
; GFX10-NEXT: ;;#ASMEND
@@ -283,12 +283,12 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1)
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 3
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_void at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_void at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s4, 0
; GFX11-NEXT: v_writelane_b32 v40, s30, 1
; GFX11-NEXT: v_writelane_b32 v40, s31, 2
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_void at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_void at abs32@lo
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; def s31
; GFX11-NEXT: ;;#ASMEND
@@ -325,12 +325,12 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_v31(ptr addrspace(1)
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v41, s34, 2
-; GFX9-NEXT: v_writelane_b32 v41, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX9-NEXT: v_writelane_b32 v41, s30, 0
; GFX9-NEXT: v_writelane_b32 v41, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def v31
; GFX9-NEXT: ;;#ASMEND
@@ -362,16 +362,16 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_v31(ptr addrspace(1)
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v41, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: v_writelane_b32 v41, s30, 0
+; GFX10-NEXT: v_writelane_b32 v41, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; def v31
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: v_mov_b32_e32 v40, v31
-; GFX10-NEXT: v_writelane_b32 v41, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_mov_b32_e32 v31, v40
; GFX10-NEXT: ;;#ASMSTART
@@ -399,18 +399,18 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_v31(ptr addrspace(1)
; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:4 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v41, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_void at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_void at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: v_writelane_b32 v41, s30, 0
+; GFX11-NEXT: v_writelane_b32 v41, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_void at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_void at abs32@lo
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; def v31
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: v_mov_b32_e32 v40, v31
-; GFX11-NEXT: v_writelane_b32 v41, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v31, v40
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use v31
@@ -443,12 +443,12 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s33(ptr addrspace(1)
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 3
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s30, 1
+; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def s33
; GFX9-NEXT: ;;#ASMEND
@@ -480,16 +480,16 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s33(ptr addrspace(1)
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s4, 0
+; GFX10-NEXT: v_writelane_b32 v40, s30, 1
+; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; def s33
; GFX10-NEXT: ;;#ASMEND
-; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: s_mov_b32 s4, s33
-; GFX10-NEXT: v_writelane_b32 v40, s30, 1
-; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: s_mov_b32 s33, s4
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
@@ -517,19 +517,18 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s33(ptr addrspace(1)
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 3
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s4, 0
+; GFX11-NEXT: v_writelane_b32 v40, s30, 1
+; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_mov_b32 s1, external_void_func_void at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_void at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; def s33
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: v_writelane_b32 v40, s4, 0
; GFX11-NEXT: s_mov_b32 s4, s33
-; GFX11-NEXT: v_writelane_b32 v40, s30, 1
-; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_mov_b32 s33, s4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s33
@@ -560,16 +559,16 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s34(ptr addrspace(1)
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 3
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
+; GFX9-NEXT: v_writelane_b32 v40, s30, 1
+; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def s34
; GFX9-NEXT: ;;#ASMEND
-; GFX9-NEXT: v_writelane_b32 v40, s30, 1
; GFX9-NEXT: s_mov_b32 s4, s34
; GFX9-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: s_mov_b32 s34, s4
; GFX9-NEXT: v_readlane_b32 s30, v40, 1
@@ -597,16 +596,16 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s34(ptr addrspace(1)
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s4, 0
+; GFX10-NEXT: v_writelane_b32 v40, s30, 1
+; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; def s34
; GFX10-NEXT: ;;#ASMEND
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
-; GFX10-NEXT: s_addk_i32 s32, 0x200
-; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: s_mov_b32 s4, s34
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v40, s30, 1
-; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: s_mov_b32 s34, s4
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
@@ -634,18 +633,17 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s34(ptr addrspace(1)
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 3
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s4, 0
+; GFX11-NEXT: v_writelane_b32 v40, s30, 1
+; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_mov_b32 s1, external_void_func_void at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_void at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; def s34
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: v_writelane_b32 v40, s4, 0
; GFX11-NEXT: s_mov_b32 s4, s34
-; GFX11-NEXT: v_writelane_b32 v40, s30, 1
-; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: s_mov_b32 s34, s4
; GFX11-NEXT: ;;#ASMSTART
@@ -677,12 +675,12 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_v40(ptr addrspace(1)
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v41, s34, 2
-; GFX9-NEXT: v_writelane_b32 v41, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX9-NEXT: v_writelane_b32 v41, s30, 0
; GFX9-NEXT: v_writelane_b32 v41, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def v40
; GFX9-NEXT: ;;#ASMEND
@@ -712,15 +710,15 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_v40(ptr addrspace(1)
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v41, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: v_writelane_b32 v41, s30, 0
+; GFX10-NEXT: v_writelane_b32 v41, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; def v40
; GFX10-NEXT: ;;#ASMEND
-; GFX10-NEXT: v_writelane_b32 v41, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; use v40
@@ -747,15 +745,15 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_v40(ptr addrspace(1)
; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:4 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v41, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_void at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_void at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: v_writelane_b32 v41, s30, 0
+; GFX11-NEXT: v_writelane_b32 v41, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_void at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_void at abs32@lo
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; def v40
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: v_writelane_b32 v41, s31, 1
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use v40
@@ -844,10 +842,10 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s33() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, void_func_void_clobber_s33 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, void_func_void_clobber_s33 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, void_func_void_clobber_s33 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, void_func_void_clobber_s33 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -870,11 +868,11 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s33() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, void_func_void_clobber_s33 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, void_func_void_clobber_s33 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, void_func_void_clobber_s33 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, void_func_void_clobber_s33 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -897,13 +895,13 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s33() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, void_func_void_clobber_s33 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, void_func_void_clobber_s33 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, void_func_void_clobber_s33 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, void_func_void_clobber_s33 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -929,10 +927,10 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s34() #0 {
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, void_func_void_clobber_s34 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, void_func_void_clobber_s34 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, void_func_void_clobber_s34 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, void_func_void_clobber_s34 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v40, 0
; GFX9-NEXT: v_readlane_b32 s31, v40, 1
@@ -955,11 +953,11 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s34() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 2
-; GFX10-NEXT: s_mov_b32 s35, void_func_void_clobber_s34 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, void_func_void_clobber_s34 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, void_func_void_clobber_s34 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, void_func_void_clobber_s34 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 0
; GFX10-NEXT: v_readlane_b32 s31, v40, 1
@@ -982,13 +980,13 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s34() #0 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 2
-; GFX11-NEXT: s_mov_b32 s1, void_func_void_clobber_s34 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, void_func_void_clobber_s34 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v40, s30, 0
; GFX11-NEXT: v_writelane_b32 v40, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, void_func_void_clobber_s34 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, void_func_void_clobber_s34 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 0
; GFX11-NEXT: v_readlane_b32 s31, v40, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -1013,12 +1011,12 @@ define amdgpu_gfx void @callee_saved_sgpr_kernel() #1 {
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v40, s34, 3
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s4, 0
; GFX9-NEXT: v_writelane_b32 v40, s30, 1
+; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 2
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def s40
; GFX9-NEXT: ;;#ASMEND
@@ -1049,16 +1047,16 @@ define amdgpu_gfx void @callee_saved_sgpr_kernel() #1 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v40, s34, 3
+; GFX10-NEXT: s_addk_i32 s32, 0x200
+; GFX10-NEXT: v_writelane_b32 v40, s4, 0
+; GFX10-NEXT: v_writelane_b32 v40, s30, 1
+; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
; GFX10-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
-; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; def s40
; GFX10-NEXT: ;;#ASMEND
-; GFX10-NEXT: v_writelane_b32 v40, s4, 0
; GFX10-NEXT: s_mov_b32 s4, s40
-; GFX10-NEXT: v_writelane_b32 v40, s30, 1
-; GFX10-NEXT: v_writelane_b32 v40, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v40, 1
; GFX10-NEXT: ;;#ASMSTART
@@ -1085,18 +1083,17 @@ define amdgpu_gfx void @callee_saved_sgpr_kernel() #1 {
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v40, s0, 3
+; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v40, s4, 0
+; GFX11-NEXT: v_writelane_b32 v40, s30, 1
+; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_mov_b32 s1, external_void_func_void at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, external_void_func_void at abs32@lo
-; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; def s40
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: v_writelane_b32 v40, s4, 0
; GFX11-NEXT: s_mov_b32 s4, s40
-; GFX11-NEXT: v_writelane_b32 v40, s30, 1
-; GFX11-NEXT: v_writelane_b32 v40, s31, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v40, 1
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s4
@@ -1127,13 +1124,13 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 {
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v41, s34, 3
+; GFX9-NEXT: s_addk_i32 s32, 0x400
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: v_writelane_b32 v41, s4, 0
; GFX9-NEXT: v_writelane_b32 v41, s30, 1
+; GFX9-NEXT: v_writelane_b32 v41, s31, 2
; GFX9-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
; GFX9-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX9-NEXT: v_writelane_b32 v41, s31, 2
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ; def s40
; GFX9-NEXT: ;;#ASMEND
@@ -1172,11 +1169,13 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s35
; GFX10-NEXT: v_writelane_b32 v41, s34, 3
-; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: v_writelane_b32 v41, s4, 0
+; GFX10-NEXT: v_writelane_b32 v41, s30, 1
+; GFX10-NEXT: v_writelane_b32 v41, s31, 2
+; GFX10-NEXT: s_mov_b32 s35, external_void_func_void at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, external_void_func_void at abs32@lo
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; def s40
; GFX10-NEXT: ;;#ASMEND
@@ -1185,8 +1184,6 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 {
; GFX10-NEXT: ; def v32
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: v_mov_b32_e32 v40, v32
-; GFX10-NEXT: v_writelane_b32 v41, s30, 1
-; GFX10-NEXT: v_writelane_b32 v41, s31, 2
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ; use s4
@@ -1217,11 +1214,13 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 {
; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:4 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
; GFX11-NEXT: v_writelane_b32 v41, s0, 3
-; GFX11-NEXT: s_mov_b32 s1, external_void_func_void at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, external_void_func_void at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX11-NEXT: v_writelane_b32 v41, s4, 0
+; GFX11-NEXT: v_writelane_b32 v41, s30, 1
+; GFX11-NEXT: v_writelane_b32 v41, s31, 2
+; GFX11-NEXT: s_mov_b32 s1, external_void_func_void at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, external_void_func_void at abs32@lo
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; def s40
; GFX11-NEXT: ;;#ASMEND
@@ -1230,8 +1229,6 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 {
; GFX11-NEXT: ; def v32
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: v_mov_b32_e32 v40, v32
-; GFX11-NEXT: v_writelane_b32 v41, s30, 1
-; GFX11-NEXT: v_writelane_b32 v41, s31, 2
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s4
diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
index 036c39ce51658..369604e583c95 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
@@ -29,10 +29,10 @@ define amdgpu_gfx void @call_i1() #0 {
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[34:35]
; GFX9-NEXT: v_writelane_b32 v1, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, return_i1 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, return_i1 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v1, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, return_i1 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, return_i1 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v1, 0
; GFX9-NEXT: v_readlane_b32 s31, v1, 1
@@ -54,10 +54,10 @@ define amdgpu_gfx void @call_i1() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: v_writelane_b32 v1, s30, 0
-; GFX10-NEXT: s_mov_b32 s35, return_i1 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, return_i1 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v1, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, return_i1 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, return_i1 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v1, 0
; GFX10-NEXT: v_readlane_b32 s31, v1, 1
@@ -79,12 +79,12 @@ define amdgpu_gfx void @call_i1() #0 {
; GFX11-NEXT: scratch_store_b32 off, v1, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: v_writelane_b32 v1, s30, 0
-; GFX11-NEXT: s_mov_b32 s1, return_i1 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, return_i1 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v1, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, return_i1 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, return_i1 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v1, 0
; GFX11-NEXT: v_readlane_b32 s31, v1, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -131,10 +131,10 @@ define amdgpu_gfx void @call_i16() #0 {
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[34:35]
; GFX9-NEXT: v_writelane_b32 v1, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, return_i16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, return_i16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v1, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, return_i16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, return_i16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v1, 0
; GFX9-NEXT: v_readlane_b32 s31, v1, 1
@@ -156,10 +156,10 @@ define amdgpu_gfx void @call_i16() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: v_writelane_b32 v1, s30, 0
-; GFX10-NEXT: s_mov_b32 s35, return_i16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, return_i16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v1, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, return_i16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, return_i16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v1, 0
; GFX10-NEXT: v_readlane_b32 s31, v1, 1
@@ -181,12 +181,12 @@ define amdgpu_gfx void @call_i16() #0 {
; GFX11-NEXT: scratch_store_b32 off, v1, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: v_writelane_b32 v1, s30, 0
-; GFX11-NEXT: s_mov_b32 s1, return_i16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, return_i16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v1, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, return_i16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, return_i16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v1, 0
; GFX11-NEXT: v_readlane_b32 s31, v1, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -227,10 +227,10 @@ define amdgpu_gfx void @call_2xi16() #0 {
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[34:35]
; GFX9-NEXT: v_writelane_b32 v1, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, return_2xi16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, return_2xi16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v1, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, return_2xi16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, return_2xi16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v1, 0
; GFX9-NEXT: v_readlane_b32 s31, v1, 1
@@ -252,10 +252,10 @@ define amdgpu_gfx void @call_2xi16() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: v_writelane_b32 v1, s30, 0
-; GFX10-NEXT: s_mov_b32 s35, return_2xi16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, return_2xi16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v1, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, return_2xi16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, return_2xi16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v1, 0
; GFX10-NEXT: v_readlane_b32 s31, v1, 1
@@ -277,12 +277,12 @@ define amdgpu_gfx void @call_2xi16() #0 {
; GFX11-NEXT: scratch_store_b32 off, v1, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: v_writelane_b32 v1, s30, 0
-; GFX11-NEXT: s_mov_b32 s1, return_2xi16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, return_2xi16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v1, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, return_2xi16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, return_2xi16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v1, 0
; GFX11-NEXT: v_readlane_b32 s31, v1, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -331,10 +331,10 @@ define amdgpu_gfx void @call_3xi16() #0 {
; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[34:35]
; GFX9-NEXT: v_writelane_b32 v2, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, return_3xi16 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, return_3xi16 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v2, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, return_3xi16 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, return_3xi16 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: v_readlane_b32 s30, v2, 0
; GFX9-NEXT: v_readlane_b32 s31, v2, 1
@@ -356,10 +356,10 @@ define amdgpu_gfx void @call_3xi16() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s34
; GFX10-NEXT: v_writelane_b32 v2, s30, 0
-; GFX10-NEXT: s_mov_b32 s35, return_3xi16 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, return_3xi16 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x200
; GFX10-NEXT: v_writelane_b32 v2, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, return_3xi16 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, return_3xi16 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: v_readlane_b32 s30, v2, 0
; GFX10-NEXT: v_readlane_b32 s31, v2, 1
@@ -381,12 +381,12 @@ define amdgpu_gfx void @call_3xi16() #0 {
; GFX11-NEXT: scratch_store_b32 off, v2, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: v_writelane_b32 v2, s30, 0
-; GFX11-NEXT: s_mov_b32 s1, return_3xi16 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, return_3xi16 at abs32@lo
; GFX11-NEXT: s_add_i32 s32, s32, 16
; GFX11-NEXT: v_writelane_b32 v2, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, return_3xi16 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, return_3xi16 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v2, 0
; GFX11-NEXT: v_readlane_b32 s31, v2, 1
; GFX11-NEXT: s_mov_b32 s32, s33
@@ -680,9 +680,6 @@ define amdgpu_gfx void @call_100xi32() #0 {
; GFX9-NEXT: s_xor_saveexec_b64 s[34:35], -1
; GFX9-NEXT: buffer_store_dword v100, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[34:35]
-; GFX9-NEXT: v_writelane_b32 v100, s30, 0
-; GFX9-NEXT: s_mov_b32 s35, return_100xi32 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s34, return_100xi32 at abs32@lo
; GFX9-NEXT: s_addk_i32 s32, 0x2400
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill
@@ -716,7 +713,10 @@ define amdgpu_gfx void @call_100xi32() #0 {
; GFX9-NEXT: buffer_store_dword v93, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v94, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v95, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX9-NEXT: v_writelane_b32 v100, s30, 0
; GFX9-NEXT: v_writelane_b32 v100, s31, 1
+; GFX9-NEXT: s_mov_b32 s35, return_100xi32 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s34, return_100xi32 at abs32@lo
; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX9-NEXT: buffer_load_dword v95, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v94, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
@@ -769,9 +769,6 @@ define amdgpu_gfx void @call_100xi32() #0 {
; GFX10-NEXT: buffer_store_dword v100, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s34
-; GFX10-NEXT: v_writelane_b32 v100, s30, 0
-; GFX10-NEXT: s_mov_b32 s35, return_100xi32 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s34, return_100xi32 at abs32@lo
; GFX10-NEXT: s_addk_i32 s32, 0x1200
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:124 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:120 ; 4-byte Folded Spill
@@ -805,7 +802,10 @@ define amdgpu_gfx void @call_100xi32() #0 {
; GFX10-NEXT: buffer_store_dword v93, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v94, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v95, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX10-NEXT: v_writelane_b32 v100, s30, 0
; GFX10-NEXT: v_writelane_b32 v100, s31, 1
+; GFX10-NEXT: s_mov_b32 s35, return_100xi32 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s34, return_100xi32 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35]
; GFX10-NEXT: s_clause 0x1f
; GFX10-NEXT: buffer_load_dword v95, off, s[0:3], s33
@@ -859,44 +859,76 @@ define amdgpu_gfx void @call_100xi32() #0 {
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_store_b32 off, v100, s33 offset:128 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-NEXT: v_writelane_b32 v100, s30, 0
-; GFX11-NEXT: s_mov_b32 s1, return_100xi32 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, return_100xi32 at abs32@lo
; GFX11-NEXT: s_addk_i32 s32, 0x90
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:124
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:120
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s33 offset:116
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s33 offset:112
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s33 offset:108
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v45, s33 offset:104
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v46, s33 offset:100
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v47, s33 offset:96
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v56, s33 offset:92
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v57, s33 offset:88
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v58, s33 offset:84
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v59, s33 offset:80
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v60, s33 offset:76
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v61, s33 offset:72
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v62, s33 offset:68
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v63, s33 offset:64
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v72, s33 offset:60
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v73, s33 offset:56
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v74, s33 offset:52
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v75, s33 offset:48
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v76, s33 offset:44
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v77, s33 offset:40
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v78, s33 offset:36
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v79, s33 offset:32
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v88, s33 offset:28
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v89, s33 offset:24
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v90, s33 offset:20
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v91, s33 offset:16
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v92, s33 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v93, s33 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v94, s33 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v95, s33
+; GFX11-NEXT: v_writelane_b32 v100, s30, 0
; GFX11-NEXT: v_writelane_b32 v100, s31, 1
+; GFX11-NEXT: s_mov_b32 s1, return_100xi32 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, return_100xi32 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_clause 0x1f
; GFX11-NEXT: scratch_load_b32 v95, off, s33
@@ -2143,13 +2175,13 @@ define amdgpu_gfx void @call_512xi32() #0 {
; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:2048 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[36:37]
; GFX9-NEXT: v_writelane_b32 v2, s30, 0
-; GFX9-NEXT: s_mov_b32 s37, return_512xi32 at abs32@hi
-; GFX9-NEXT: s_mov_b32 s36, return_512xi32 at abs32@lo
-; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, s33
; GFX9-NEXT: s_mov_b32 s38, s34
; GFX9-NEXT: s_mov_b32 s34, s32
; GFX9-NEXT: s_add_i32 s32, s32, 0x60000
; GFX9-NEXT: v_writelane_b32 v2, s31, 1
+; GFX9-NEXT: s_mov_b32 s37, return_512xi32 at abs32@hi
+; GFX9-NEXT: s_mov_b32 s36, return_512xi32 at abs32@lo
+; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, s33
; GFX9-NEXT: s_swappc_b64 s[30:31], s[36:37]
; GFX9-NEXT: v_readlane_b32 s30, v2, 0
; GFX9-NEXT: v_readlane_b32 s31, v2, 1
@@ -2173,13 +2205,13 @@ define amdgpu_gfx void @call_512xi32() #0 {
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s36
; GFX10-NEXT: v_writelane_b32 v2, s30, 0
-; GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33
-; GFX10-NEXT: s_mov_b32 s37, return_512xi32 at abs32@hi
-; GFX10-NEXT: s_mov_b32 s36, return_512xi32 at abs32@lo
; GFX10-NEXT: s_mov_b32 s38, s34
; GFX10-NEXT: s_mov_b32 s34, s32
; GFX10-NEXT: s_add_i32 s32, s32, 0x30000
; GFX10-NEXT: v_writelane_b32 v2, s31, 1
+; GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33
+; GFX10-NEXT: s_mov_b32 s37, return_512xi32 at abs32@hi
+; GFX10-NEXT: s_mov_b32 s36, return_512xi32 at abs32@lo
; GFX10-NEXT: s_swappc_b64 s[30:31], s[36:37]
; GFX10-NEXT: v_readlane_b32 s30, v2, 0
; GFX10-NEXT: v_readlane_b32 s31, v2, 1
@@ -2204,15 +2236,15 @@ define amdgpu_gfx void @call_512xi32() #0 {
; GFX11-NEXT: scratch_store_b32 off, v5, s33 offset:2048 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: v_writelane_b32 v5, s30, 0
-; GFX11-NEXT: v_mov_b32_e32 v0, s33
-; GFX11-NEXT: s_mov_b32 s1, return_512xi32 at abs32@hi
-; GFX11-NEXT: s_mov_b32 s0, return_512xi32 at abs32@lo
; GFX11-NEXT: s_mov_b32 s36, s34
; GFX11-NEXT: s_mov_b32 s34, s32
; GFX11-NEXT: s_addk_i32 s32, 0x1800
; GFX11-NEXT: v_writelane_b32 v5, s31, 1
+; GFX11-NEXT: v_mov_b32_e32 v0, s33
+; GFX11-NEXT: s_mov_b32 s1, return_512xi32 at abs32@hi
+; GFX11-NEXT: s_mov_b32 s0, return_512xi32 at abs32@lo
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v5, 0
; GFX11-NEXT: v_readlane_b32 s31, v5, 1
; GFX11-NEXT: s_mov_b32 s32, s34
@@ -2520,17 +2552,29 @@ define amdgpu_gfx <72 x i32> @return_72xi32(<72 x i32> %val) #1 {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_clause 0xc
; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:212
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:208
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:204
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:200
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:196
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:192
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:188
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:184
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:180
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:176
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:172
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:168
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:164
; GFX11-NEXT: s_clause 0x11
; GFX11-NEXT: scratch_load_b32 v36, off, s32 offset:16
@@ -2640,7 +2684,6 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX9-NEXT: s_mov_b32 s38, s34
; GFX9-NEXT: s_mov_b32 s34, s32
; GFX9-NEXT: s_add_i32 s32, s32, 0x28000
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
@@ -2656,6 +2699,9 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX9-NEXT: v_writelane_b32 v63, s30, 0
+; GFX9-NEXT: v_writelane_b32 v63, s31, 1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8
@@ -2698,7 +2744,6 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160
; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, s33
-; GFX9-NEXT: v_writelane_b32 v63, s30, 0
; GFX9-NEXT: s_mov_b32 s37, return_72xi32 at abs32@hi
; GFX9-NEXT: s_mov_b32 s36, return_72xi32 at abs32@lo
; GFX9-NEXT: v_add_u32_e32 v0, 0x200, v0
@@ -2733,7 +2778,6 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX9-NEXT: v_mov_b32_e32 v29, 0
; GFX9-NEXT: v_mov_b32_e32 v30, 0
; GFX9-NEXT: v_mov_b32_e32 v31, 0
-; GFX9-NEXT: v_writelane_b32 v63, s31, 1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[36:37]
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:636
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:640
@@ -2910,7 +2954,6 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX10-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:1568 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s36
-; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_mov_b32 s38, s34
; GFX10-NEXT: s_mov_b32 s34, s32
; GFX10-NEXT: s_add_i32 s32, s32, 0x14000
@@ -2929,6 +2972,13 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX10-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v62, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX10-NEXT: v_writelane_b32 v63, s30, 0
+; GFX10-NEXT: v_writelane_b32 v63, s31, 1
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: v_mov_b32_e32 v3, 0
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8
@@ -2971,16 +3021,11 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160
; GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33
-; GFX10-NEXT: v_writelane_b32 v63, s30, 0
-; GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GFX10-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-NEXT: v_mov_b32_e32 v3, 0
-; GFX10-NEXT: v_add_nc_u32_e32 v0, 0x200, v0
-; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_mov_b32_e32 v6, 0
; GFX10-NEXT: v_mov_b32_e32 v7, 0
; GFX10-NEXT: v_mov_b32_e32 v8, 0
+; GFX10-NEXT: v_add_nc_u32_e32 v0, 0x200, v0
; GFX10-NEXT: v_mov_b32_e32 v9, 0
; GFX10-NEXT: v_mov_b32_e32 v10, 0
; GFX10-NEXT: v_mov_b32_e32 v11, 0
@@ -3006,7 +3051,6 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX10-NEXT: v_mov_b32_e32 v31, 0
; GFX10-NEXT: s_mov_b32 s37, return_72xi32 at abs32@hi
; GFX10-NEXT: s_mov_b32 s36, return_72xi32 at abs32@lo
-; GFX10-NEXT: v_writelane_b32 v63, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[36:37]
; GFX10-NEXT: s_clause 0x28
; GFX10-NEXT: buffer_load_dword v9, off, s[0:3], s33 offset:636
@@ -3189,29 +3233,42 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_store_b32 off, v60, s33 offset:1600 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-NEXT: s_mov_b32 s0, 0
-; GFX11-NEXT: v_mov_b32_e32 v4, 0
-; GFX11-NEXT: s_mov_b32 s1, s0
-; GFX11-NEXT: s_mov_b32 s2, s0
-; GFX11-NEXT: s_mov_b32 s3, s0
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: s_mov_b32 s36, s34
; GFX11-NEXT: s_mov_b32 s34, s32
; GFX11-NEXT: s_addk_i32 s32, 0xa00
; GFX11-NEXT: s_clause 0xb
; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:44
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:40
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s33 offset:36
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s33 offset:32
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s33 offset:28
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v45, s33 offset:24
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v46, s33 offset:20
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v47, s33 offset:16
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v56, s33 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v57, s33 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v58, s33 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v59, s33
+; GFX11-NEXT: v_writelane_b32 v60, s30, 0
+; GFX11-NEXT: v_writelane_b32 v60, s31, 1
+; GFX11-NEXT: s_mov_b32 s0, 0
+; GFX11-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-NEXT: s_mov_b32 s1, s0
+; GFX11-NEXT: s_mov_b32 s2, s0
+; GFX11-NEXT: s_mov_b32 s3, s0
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: s_add_i32 s0, s32, 0xa0
; GFX11-NEXT: s_add_i32 s1, s32, 0x90
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s32
@@ -3232,7 +3289,6 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX11-NEXT: s_add_i32 s0, s32, 32
; GFX11-NEXT: s_add_i32 s1, s32, 16
; GFX11-NEXT: s_add_i32 s2, s33, 0x200
-; GFX11-NEXT: v_writelane_b32 v60, s30, 0
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s0
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s1
; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, 0
@@ -3253,7 +3309,7 @@ define amdgpu_gfx void @call_72xi32() #1 {
; GFX11-NEXT: v_dual_mov_b32 v31, 0 :: v_dual_mov_b32 v30, 0
; GFX11-NEXT: s_mov_b32 s1, return_72xi32 at abs32@hi
; GFX11-NEXT: s_mov_b32 s0, return_72xi32 at abs32@lo
-; GFX11-NEXT: v_writelane_b32 v60, s31, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_load_b128 v[45:48], off, s33 offset:624
diff --git a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
index 0bbe2b6a0caa7..424aaaea11722 100644
--- a/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
+++ b/llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
@@ -30,9 +30,9 @@ define void @main(i1 %arg) #0 {
; CHECK-NEXT: v_writelane_b32 v6, s70, 18
; CHECK-NEXT: v_writelane_b32 v6, s71, 19
; CHECK-NEXT: v_writelane_b32 v6, s30, 20
+; CHECK-NEXT: v_writelane_b32 v6, s31, 21
; CHECK-NEXT: s_getpc_b64 s[4:5]
; CHECK-NEXT: s_mov_b64 s[8:9], 0
-; CHECK-NEXT: v_writelane_b32 v6, s31, 21
; CHECK-NEXT: s_mov_b32 s68, 0
; CHECK-NEXT: s_mov_b32 s69, s4
; CHECK-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
index fcc43ffd0140e..3be6682bc4ffa 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
@@ -25,16 +25,15 @@ define void @f0() {
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_store_b32 off, v4, s33 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
+; GFX11-NEXT: v_writelane_b32 v4, s30, 0
; GFX11-NEXT: s_add_i32 s32, s32, 16
+; GFX11-NEXT: v_writelane_b32 v4, s31, 1
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, f1 at gotpcrel32@lo+4
; GFX11-NEXT: s_addc_u32 s1, s1, f1 at gotpcrel32@hi+12
-; GFX11-NEXT: v_writelane_b32 v4, s30, 0
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-NEXT: v_writelane_b32 v4, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v4, 0
; GFX11-NEXT: v_readlane_b32 s31, v4, 1
; GFX11-NEXT: s_mov_b32 s32, s33
diff --git a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
index 19869e85ec9d9..c1c69d9cb8f6e 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
@@ -15,8 +15,11 @@ define fastcc i32 @foo() #0 {
; CHECK-NEXT: $sgpr17 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)
; CHECK-NEXT: $exec_lo = S_MOV_B32 killed $sgpr17
- ; CHECK-NEXT: $sgpr32 = frame-setup S_ADDK_I32 $sgpr32, 512, implicit-def dead $scc
; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr16, 2, undef $vgpr40
+ ; CHECK-NEXT: $sgpr32 = frame-setup S_ADDK_I32 $sgpr32, 512, implicit-def dead $scc
+ ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr30, 0, $vgpr40, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
+ ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr31, 1, $vgpr40, implicit $sgpr30_sgpr31
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr127, 0, 32, $vgpr127, 1, 32
; CHECK-NEXT: BUNDLE implicit-def $sgpr16_sgpr17, implicit-def $sgpr16, implicit-def $scc, implicit-def $sgpr17 {
; CHECK-NEXT: $sgpr16_sgpr17 = S_GETPC_B64
; CHECK-NEXT: $sgpr16 = S_ADD_U32 internal $sgpr16, target-flags(amdgpu-gotprel32-lo) @bar + 4, implicit-def $scc
@@ -26,8 +29,6 @@ define fastcc i32 @foo() #0 {
; CHECK-NEXT: BUFFER_GL1_INV implicit $exec
; CHECK-NEXT: BUFFER_GL0_INV implicit $exec
; CHECK-NEXT: renamable $sgpr16_sgpr17 = S_LOAD_DWORDX2_IMM killed renamable $sgpr16_sgpr17, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
- ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr30, 0, $vgpr40, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
- ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr31, 1, $vgpr40, implicit $sgpr30_sgpr31
; CHECK-NEXT: S_WAITCNT 49279
; CHECK-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr16_sgpr17, @bar, csr_amdgpu, implicit killed $sgpr4_sgpr5, implicit killed $sgpr6_sgpr7, implicit killed $sgpr8_sgpr9, implicit killed $sgpr10_sgpr11, implicit killed $sgpr12, implicit killed $sgpr13, implicit killed $sgpr14, implicit killed $sgpr15, implicit killed $vgpr31, implicit $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK-NEXT: $vcc_lo = S_MOV_B32 $exec_lo
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
index 02d29909c661c..c0b5195f699b9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
@@ -980,10 +980,6 @@ define void @test_readfirstlane_v32f32(ptr addrspace(1) %out, <32 x float> %src)
; CHECK-SDAG-NEXT: s_xor_saveexec_b64 s[4:5], -1
; CHECK-SDAG-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; CHECK-SDAG-NEXT: s_mov_b64 exec, s[4:5]
-; CHECK-SDAG-NEXT: v_readfirstlane_b32 s61, v27
-; CHECK-SDAG-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8
-; CHECK-SDAG-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4
-; CHECK-SDAG-NEXT: buffer_load_dword v27, off, s[0:3], s32
; CHECK-SDAG-NEXT: v_writelane_b32 v31, s36, 0
; CHECK-SDAG-NEXT: v_writelane_b32 v31, s37, 1
; CHECK-SDAG-NEXT: v_writelane_b32 v31, s38, 2
@@ -1000,6 +996,10 @@ define void @test_readfirstlane_v32f32(ptr addrspace(1) %out, <32 x float> %src)
; CHECK-SDAG-NEXT: v_writelane_b32 v31, s65, 13
; CHECK-SDAG-NEXT: v_writelane_b32 v31, s66, 14
; CHECK-SDAG-NEXT: v_writelane_b32 v31, s67, 15
+; CHECK-SDAG-NEXT: v_readfirstlane_b32 s61, v27
+; CHECK-SDAG-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8
+; CHECK-SDAG-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4
+; CHECK-SDAG-NEXT: buffer_load_dword v27, off, s[0:3], s32
; CHECK-SDAG-NEXT: v_readfirstlane_b32 s64, v30
; CHECK-SDAG-NEXT: v_readfirstlane_b32 s55, v21
; CHECK-SDAG-NEXT: v_readfirstlane_b32 s54, v20
@@ -1066,10 +1066,6 @@ define void @test_readfirstlane_v32f32(ptr addrspace(1) %out, <32 x float> %src)
; CHECK-GISEL-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; CHECK-GISEL-NEXT: s_mov_b64 exec, s[4:5]
; CHECK-GISEL-NEXT: v_writelane_b32 v31, s36, 0
-; CHECK-GISEL-NEXT: v_readfirstlane_b32 s36, v2
-; CHECK-GISEL-NEXT: buffer_load_dword v0, off, s[0:3], s32
-; CHECK-GISEL-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4
-; CHECK-GISEL-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8
; CHECK-GISEL-NEXT: v_writelane_b32 v31, s37, 1
; CHECK-GISEL-NEXT: v_writelane_b32 v31, s38, 2
; CHECK-GISEL-NEXT: v_writelane_b32 v31, s39, 3
@@ -1085,6 +1081,10 @@ define void @test_readfirstlane_v32f32(ptr addrspace(1) %out, <32 x float> %src)
; CHECK-GISEL-NEXT: v_writelane_b32 v31, s65, 13
; CHECK-GISEL-NEXT: v_writelane_b32 v31, s66, 14
; CHECK-GISEL-NEXT: v_writelane_b32 v31, s67, 15
+; CHECK-GISEL-NEXT: v_readfirstlane_b32 s36, v2
+; CHECK-GISEL-NEXT: buffer_load_dword v0, off, s[0:3], s32
+; CHECK-GISEL-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4
+; CHECK-GISEL-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8
; CHECK-GISEL-NEXT: v_readfirstlane_b32 s37, v3
; CHECK-GISEL-NEXT: v_readfirstlane_b32 s38, v4
; CHECK-GISEL-NEXT: v_readfirstlane_b32 s39, v5
@@ -1425,10 +1425,6 @@ define void @test_readfirstlane_v32i32(ptr addrspace(1) %out, <32 x i32> %src) {
; CHECK-SDAG-NEXT: s_xor_saveexec_b64 s[4:5], -1
; CHECK-SDAG-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; CHECK-SDAG-NEXT: s_mov_b64 exec, s[4:5]
-; CHECK-SDAG-NEXT: v_readfirstlane_b32 s61, v27
-; CHECK-SDAG-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8
-; CHECK-SDAG-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4
-; CHECK-SDAG-NEXT: buffer_load_dword v27, off, s[0:3], s32
; CHECK-SDAG-NEXT: v_writelane_b32 v31, s36, 0
; CHECK-SDAG-NEXT: v_writelane_b32 v31, s37, 1
; CHECK-SDAG-NEXT: v_writelane_b32 v31, s38, 2
@@ -1445,6 +1441,10 @@ define void @test_readfirstlane_v32i32(ptr addrspace(1) %out, <32 x i32> %src) {
; CHECK-SDAG-NEXT: v_writelane_b32 v31, s65, 13
; CHECK-SDAG-NEXT: v_writelane_b32 v31, s66, 14
; CHECK-SDAG-NEXT: v_writelane_b32 v31, s67, 15
+; CHECK-SDAG-NEXT: v_readfirstlane_b32 s61, v27
+; CHECK-SDAG-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8
+; CHECK-SDAG-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4
+; CHECK-SDAG-NEXT: buffer_load_dword v27, off, s[0:3], s32
; CHECK-SDAG-NEXT: v_readfirstlane_b32 s64, v30
; CHECK-SDAG-NEXT: v_readfirstlane_b32 s55, v21
; CHECK-SDAG-NEXT: v_readfirstlane_b32 s54, v20
@@ -1511,10 +1511,6 @@ define void @test_readfirstlane_v32i32(ptr addrspace(1) %out, <32 x i32> %src) {
; CHECK-GISEL-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; CHECK-GISEL-NEXT: s_mov_b64 exec, s[4:5]
; CHECK-GISEL-NEXT: v_writelane_b32 v31, s36, 0
-; CHECK-GISEL-NEXT: v_readfirstlane_b32 s36, v2
-; CHECK-GISEL-NEXT: buffer_load_dword v0, off, s[0:3], s32
-; CHECK-GISEL-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4
-; CHECK-GISEL-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8
; CHECK-GISEL-NEXT: v_writelane_b32 v31, s37, 1
; CHECK-GISEL-NEXT: v_writelane_b32 v31, s38, 2
; CHECK-GISEL-NEXT: v_writelane_b32 v31, s39, 3
@@ -1530,6 +1526,10 @@ define void @test_readfirstlane_v32i32(ptr addrspace(1) %out, <32 x i32> %src) {
; CHECK-GISEL-NEXT: v_writelane_b32 v31, s65, 13
; CHECK-GISEL-NEXT: v_writelane_b32 v31, s66, 14
; CHECK-GISEL-NEXT: v_writelane_b32 v31, s67, 15
+; CHECK-GISEL-NEXT: v_readfirstlane_b32 s36, v2
+; CHECK-GISEL-NEXT: buffer_load_dword v0, off, s[0:3], s32
+; CHECK-GISEL-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4
+; CHECK-GISEL-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:8
; CHECK-GISEL-NEXT: v_readfirstlane_b32 s37, v3
; CHECK-GISEL-NEXT: v_readfirstlane_b32 s38, v4
; CHECK-GISEL-NEXT: v_readfirstlane_b32 s39, v5
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
index f971080e02c5b..72c4397754ce6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
@@ -2375,6 +2375,12 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX950-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a13, v61 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a14, v62 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse
; GFX950-NEXT: scratch_load_dword v33, off, s32 offset:8
; GFX950-NEXT: scratch_load_dword v32, off, s32 offset:4
; GFX950-NEXT: scratch_load_dword v37, off, s32 offset:16
@@ -2402,12 +2408,6 @@ define <16 x double> @v_maximum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX950-NEXT: scratch_load_dword v31, off, s32
; GFX950-NEXT: scratch_load_dword v35, off, s32 offset:104
; GFX950-NEXT: scratch_load_dword v34, off, s32 offset:100
-; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a13, v61 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a14, v62 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse
; GFX950-NEXT: s_waitcnt vmcnt(25)
; GFX950-NEXT: v_max_f64 v[58:59], v[0:1], v[32:33]
; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[32:33]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
index dfd67873c3b86..526988d1f36ac 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
@@ -2375,6 +2375,12 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX950-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse
; GFX950-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a13, v61 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a14, v62 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse
; GFX950-NEXT: scratch_load_dword v33, off, s32 offset:8
; GFX950-NEXT: scratch_load_dword v32, off, s32 offset:4
; GFX950-NEXT: scratch_load_dword v37, off, s32 offset:16
@@ -2402,12 +2408,6 @@ define <16 x double> @v_minimum_v16f64(<16 x double> %src0, <16 x double> %src1)
; GFX950-NEXT: scratch_load_dword v31, off, s32
; GFX950-NEXT: scratch_load_dword v35, off, s32 offset:104
; GFX950-NEXT: scratch_load_dword v34, off, s32 offset:100
-; GFX950-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a13, v61 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a14, v62 ; Reload Reuse
-; GFX950-NEXT: v_accvgpr_write_b32 a15, v63 ; Reload Reuse
; GFX950-NEXT: s_waitcnt vmcnt(25)
; GFX950-NEXT: v_min_f64 v[58:59], v[0:1], v[32:33]
; GFX950-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[32:33]
diff --git a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
index 4b5a7c207055a..52671f5d3deb4 100644
--- a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
+++ b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
@@ -17,8 +17,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 {
; GFX10_1-NEXT: buffer_store_dword v1, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
; GFX10_1-NEXT: v_writelane_b32 v1, s55, 0
+; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0
; GFX10_1-NEXT: ;;#ASMSTART
@@ -46,8 +46,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 {
; GFX10_3-NEXT: s_add_i32 s5, s32, 0x80880
; GFX10_3-NEXT: buffer_store_dword v1, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s32
; GFX10_3-NEXT: v_writelane_b32 v1, s55, 0
+; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s32
; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0
; GFX10_3-NEXT: ;;#ASMSTART
@@ -74,8 +74,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 {
; GFX11-NEXT: s_add_i32 s1, s32, 0x4044
; GFX11-NEXT: scratch_store_b32 off, v1, s1 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-NEXT: s_add_i32 s0, s32, 64
; GFX11-NEXT: v_writelane_b32 v1, s55, 0
+; GFX11-NEXT: s_add_i32 s0, s32, 64
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
; GFX11-NEXT: s_addc_u32 s0, s32, 0x4040
@@ -108,9 +109,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 {
; GFX12-NEXT: scratch_store_b32 off, v1, s32 offset:16388 ; 4-byte Folded Spill
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s0
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
; GFX12-NEXT: v_writelane_b32 v1, s55, 0
+; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
; GFX12-NEXT: s_add_co_ci_u32 s0, s32, 0x4000
; GFX12-NEXT: v_mov_b32_e32 v0, s32
; GFX12-NEXT: s_wait_alu 0xfffe
@@ -139,9 +139,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 {
; GFX8-NEXT: s_add_i32 s6, s32, 0x101100
; GFX8-NEXT: buffer_store_dword v1, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
+; GFX8-NEXT: v_writelane_b32 v1, s55, 0
; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 64, v0
-; GFX8-NEXT: v_writelane_b32 v1, s55, 0
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use alloca0 v0
; GFX8-NEXT: ;;#ASMEND
@@ -168,6 +168,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 {
; GFX900-NEXT: s_add_i32 s6, s32, 0x101100
; GFX900-NEXT: buffer_store_dword v1, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
+; GFX900-NEXT: v_writelane_b32 v1, s55, 0
; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32
; GFX900-NEXT: v_add_u32_e32 v0, 64, v0
; GFX900-NEXT: ;;#ASMSTART
@@ -175,7 +176,6 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32
; GFX900-NEXT: v_add_u32_e32 v0, 0x4040, v0
-; GFX900-NEXT: v_writelane_b32 v1, s55, 0
; GFX900-NEXT: v_readfirstlane_b32 s55, v0
; GFX900-NEXT: s_and_b64 s[4:5], 0, exec
; GFX900-NEXT: ;;#ASMSTART
@@ -196,13 +196,13 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc() #0 {
; GFX942-NEXT: s_add_i32 s2, s32, 0x4044
; GFX942-NEXT: scratch_store_dword off, v1, s2 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
+; GFX942-NEXT: v_writelane_b32 v1, s55, 0
; GFX942-NEXT: s_add_i32 s0, s32, 64
; GFX942-NEXT: v_mov_b32_e32 v0, s0
; GFX942-NEXT: s_and_b64 s[0:1], 0, exec
; GFX942-NEXT: s_addc_u32 s0, s32, 0x4040
; GFX942-NEXT: s_bitcmp1_b32 s0, 0
; GFX942-NEXT: s_bitset0_b32 s0, 0
-; GFX942-NEXT: v_writelane_b32 v1, s55, 0
; GFX942-NEXT: s_mov_b32 s55, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use alloca0 v0
@@ -397,10 +397,10 @@ define void @scalar_mov_materializes_frame_index_dead_scc() #0 {
; GFX942-NEXT: s_add_i32 s2, s32, 0x4044
; GFX942-NEXT: scratch_store_dword off, v1, s2 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
+; GFX942-NEXT: v_writelane_b32 v1, s55, 0
; GFX942-NEXT: s_add_i32 s0, s32, 64
; GFX942-NEXT: v_mov_b32_e32 v0, s0
; GFX942-NEXT: s_add_i32 s0, s32, 0x4040
-; GFX942-NEXT: v_writelane_b32 v1, s55, 0
; GFX942-NEXT: s_mov_b32 s55, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use alloca0 v0
@@ -433,9 +433,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 {
; GFX10_1-NEXT: buffer_store_dword v1, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s33
-; GFX10_1-NEXT: v_writelane_b32 v1, s55, 0
; GFX10_1-NEXT: s_add_i32 s32, s32, 0x81000
+; GFX10_1-NEXT: v_writelane_b32 v1, s55, 0
+; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s33
; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_1-NEXT: s_mov_b32 s32, s33
; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0
@@ -467,9 +467,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 {
; GFX10_3-NEXT: s_add_i32 s6, s33, 0x80880
; GFX10_3-NEXT: buffer_store_dword v1, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s33
-; GFX10_3-NEXT: v_writelane_b32 v1, s55, 0
; GFX10_3-NEXT: s_add_i32 s32, s32, 0x81000
+; GFX10_3-NEXT: v_writelane_b32 v1, s55, 0
+; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s33
; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_3-NEXT: s_mov_b32 s32, s33
; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0
@@ -501,8 +501,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 {
; GFX11-NEXT: scratch_store_b32 off, v1, s2 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: s_addk_i32 s32, 0x4080
-; GFX11-NEXT: s_add_i32 s0, s33, 64
; GFX11-NEXT: v_writelane_b32 v1, s55, 0
+; GFX11-NEXT: s_add_i32 s0, s33, 64
+; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
; GFX11-NEXT: s_addc_u32 s0, s33, 0x4040
@@ -511,7 +512,7 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 {
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: s_bitcmp1_b32 s0, 0
; GFX11-NEXT: s_bitset0_b32 s0, 0
-; GFX11-NEXT: s_mov_b32 s32, s33
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_mov_b32 s55, s0
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s55, scc
@@ -539,8 +540,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 {
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: s_addk_co_i32 s32, 0x4040
-; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
; GFX12-NEXT: v_writelane_b32 v1, s55, 0
+; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
; GFX12-NEXT: s_add_co_ci_u32 s0, s33, 0x4000
; GFX12-NEXT: v_mov_b32_e32 v0, s33
; GFX12-NEXT: s_wait_alu 0xfffe
@@ -574,16 +575,16 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 {
; GFX8-NEXT: s_add_i32 s7, s33, 0x101100
; GFX8-NEXT: buffer_store_dword v1, off, s[0:3], s7 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
+; GFX8-NEXT: s_add_i32 s32, s32, 0x102000
+; GFX8-NEXT: v_writelane_b32 v1, s55, 0
; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s33
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 64, v0
-; GFX8-NEXT: v_writelane_b32 v1, s55, 0
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use alloca0 v0
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s33
; GFX8-NEXT: s_movk_i32 s55, 0x4040
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s55, v0
-; GFX8-NEXT: s_add_i32 s32, s32, 0x102000
; GFX8-NEXT: v_readfirstlane_b32 s55, v0
; GFX8-NEXT: s_and_b64 s[4:5], 0, exec
; GFX8-NEXT: ;;#ASMSTART
@@ -608,6 +609,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 {
; GFX900-NEXT: s_add_i32 s7, s33, 0x101100
; GFX900-NEXT: buffer_store_dword v1, off, s[0:3], s7 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
+; GFX900-NEXT: s_add_i32 s32, s32, 0x102000
+; GFX900-NEXT: v_writelane_b32 v1, s55, 0
; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s33
; GFX900-NEXT: v_add_u32_e32 v0, 64, v0
; GFX900-NEXT: ;;#ASMSTART
@@ -615,8 +618,6 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 {
; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s33
; GFX900-NEXT: v_add_u32_e32 v0, 0x4040, v0
-; GFX900-NEXT: s_add_i32 s32, s32, 0x102000
-; GFX900-NEXT: v_writelane_b32 v1, s55, 0
; GFX900-NEXT: v_readfirstlane_b32 s55, v0
; GFX900-NEXT: s_and_b64 s[4:5], 0, exec
; GFX900-NEXT: ;;#ASMSTART
@@ -642,13 +643,13 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_fp() #1 {
; GFX942-NEXT: scratch_store_dword off, v1, s3 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: s_addk_i32 s32, 0x4080
+; GFX942-NEXT: v_writelane_b32 v1, s55, 0
; GFX942-NEXT: s_add_i32 s0, s33, 64
; GFX942-NEXT: v_mov_b32_e32 v0, s0
; GFX942-NEXT: s_and_b64 s[0:1], 0, exec
; GFX942-NEXT: s_addc_u32 s0, s33, 0x4040
; GFX942-NEXT: s_bitcmp1_b32 s0, 0
; GFX942-NEXT: s_bitset0_b32 s0, 0
-; GFX942-NEXT: v_writelane_b32 v1, s55, 0
; GFX942-NEXT: s_mov_b32 s55, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use alloca0 v0
@@ -681,8 +682,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset()
; GFX10_1-NEXT: buffer_store_dword v0, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_1-NEXT: v_lshrrev_b32_e64 v1, 5, s32
; GFX10_1-NEXT: v_writelane_b32 v0, s55, 0
+; GFX10_1-NEXT: v_lshrrev_b32_e64 v1, 5, s32
; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_1-NEXT: v_add_nc_u32_e32 v1, 64, v1
; GFX10_1-NEXT: v_readfirstlane_b32 s55, v1
@@ -705,8 +706,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset()
; GFX10_3-NEXT: s_add_i32 s5, s32, 0x80800
; GFX10_3-NEXT: buffer_store_dword v0, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_3-NEXT: v_lshrrev_b32_e64 v1, 5, s32
; GFX10_3-NEXT: v_writelane_b32 v0, s55, 0
+; GFX10_3-NEXT: v_lshrrev_b32_e64 v1, 5, s32
; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_3-NEXT: v_add_nc_u32_e32 v1, 64, v1
; GFX10_3-NEXT: v_readfirstlane_b32 s55, v1
@@ -728,13 +729,12 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset()
; GFX11-NEXT: s_add_i32 s1, s32, 0x4040
; GFX11-NEXT: scratch_store_b32 off, v0, s1 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
; GFX11-NEXT: v_writelane_b32 v0, s55, 0
+; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
; GFX11-NEXT: s_addc_u32 s0, s32, 64
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_bitcmp1_b32 s0, 0
; GFX11-NEXT: s_bitset0_b32 s0, 0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_mov_b32 s55, s0
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s55, scc
@@ -804,9 +804,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset()
; GFX900-NEXT: s_add_i32 s6, s32, 0x101000
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
+; GFX900-NEXT: v_writelane_b32 v0, s55, 0
; GFX900-NEXT: v_lshrrev_b32_e64 v1, 6, s32
; GFX900-NEXT: v_add_u32_e32 v1, 64, v1
-; GFX900-NEXT: v_writelane_b32 v0, s55, 0
; GFX900-NEXT: v_readfirstlane_b32 s55, v1
; GFX900-NEXT: s_and_b64 s[4:5], 0, exec
; GFX900-NEXT: ;;#ASMSTART
@@ -827,11 +827,11 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset()
; GFX942-NEXT: s_add_i32 s2, s32, 0x4040
; GFX942-NEXT: scratch_store_dword off, v0, s2 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
+; GFX942-NEXT: v_writelane_b32 v0, s55, 0
; GFX942-NEXT: s_and_b64 s[0:1], 0, exec
; GFX942-NEXT: s_addc_u32 s0, s32, 64
; GFX942-NEXT: s_bitcmp1_b32 s0, 0
; GFX942-NEXT: s_bitset0_b32 s0, 0
-; GFX942-NEXT: v_writelane_b32 v0, s55, 0
; GFX942-NEXT: s_mov_b32 s55, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s55, scc
@@ -989,8 +989,8 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset() #0
; GFX942-NEXT: s_add_i32 s2, s32, 0x4040
; GFX942-NEXT: scratch_store_dword off, v0, s2 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
-; GFX942-NEXT: s_add_i32 s0, s32, 64
; GFX942-NEXT: v_writelane_b32 v0, s55, 0
+; GFX942-NEXT: s_add_i32 s0, s32, 64
; GFX942-NEXT: s_mov_b32 s55, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s55
@@ -1018,9 +1018,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp
; GFX10_1-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_1-NEXT: v_lshrrev_b32_e64 v1, 5, s33
-; GFX10_1-NEXT: v_writelane_b32 v0, s55, 0
; GFX10_1-NEXT: s_add_i32 s32, s32, 0x81000
+; GFX10_1-NEXT: v_writelane_b32 v0, s55, 0
+; GFX10_1-NEXT: v_lshrrev_b32_e64 v1, 5, s33
; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_1-NEXT: s_mov_b32 s32, s33
; GFX10_1-NEXT: v_add_nc_u32_e32 v1, 64, v1
@@ -1047,9 +1047,9 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp
; GFX10_3-NEXT: s_add_i32 s6, s33, 0x80800
; GFX10_3-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
-; GFX10_3-NEXT: v_lshrrev_b32_e64 v1, 5, s33
-; GFX10_3-NEXT: v_writelane_b32 v0, s55, 0
; GFX10_3-NEXT: s_add_i32 s32, s32, 0x81000
+; GFX10_3-NEXT: v_writelane_b32 v0, s55, 0
+; GFX10_3-NEXT: v_lshrrev_b32_e64 v1, 5, s33
; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_3-NEXT: s_mov_b32 s32, s33
; GFX10_3-NEXT: v_add_nc_u32_e32 v1, 64, v1
@@ -1076,8 +1076,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp
; GFX11-NEXT: scratch_store_b32 off, v0, s2 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: s_addk_i32 s32, 0x4080
-; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
; GFX11-NEXT: v_writelane_b32 v0, s55, 0
+; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
; GFX11-NEXT: s_addc_u32 s0, s33, 64
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_bitcmp1_b32 s0, 0
@@ -1109,13 +1109,14 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp
; GFX12-NEXT: scratch_store_b32 off, v0, s33 offset:16384 ; 4-byte Folded Spill
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s0
-; GFX12-NEXT: v_writelane_b32 v0, s55, 0
; GFX12-NEXT: s_addk_co_i32 s32, 0x4040
+; GFX12-NEXT: v_writelane_b32 v0, s55, 0
; GFX12-NEXT: s_mov_b32 s55, s33
; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s55, scc
; GFX12-NEXT: ;;#ASMEND
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readlane_b32 s55, v0, 0
; GFX12-NEXT: s_mov_b32 s32, s33
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
@@ -1136,11 +1137,11 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp
; GFX8-NEXT: s_add_i32 s7, s33, 0x101000
; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], s7 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
+; GFX8-NEXT: s_add_i32 s32, s32, 0x102000
; GFX8-NEXT: v_writelane_b32 v0, s55, 0
; GFX8-NEXT: v_lshrrev_b32_e64 v1, 6, s33
; GFX8-NEXT: s_mov_b32 s55, 64
; GFX8-NEXT: v_add_u32_e32 v1, vcc, s55, v1
-; GFX8-NEXT: s_add_i32 s32, s32, 0x102000
; GFX8-NEXT: v_readfirstlane_b32 s55, v1
; GFX8-NEXT: s_and_b64 s[4:5], 0, exec
; GFX8-NEXT: ;;#ASMSTART
@@ -1165,10 +1166,10 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp
; GFX900-NEXT: s_add_i32 s7, s33, 0x101000
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s7 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
-; GFX900-NEXT: v_lshrrev_b32_e64 v1, 6, s33
-; GFX900-NEXT: v_add_u32_e32 v1, 64, v1
; GFX900-NEXT: s_add_i32 s32, s32, 0x102000
; GFX900-NEXT: v_writelane_b32 v0, s55, 0
+; GFX900-NEXT: v_lshrrev_b32_e64 v1, 6, s33
+; GFX900-NEXT: v_add_u32_e32 v1, 64, v1
; GFX900-NEXT: v_readfirstlane_b32 s55, v1
; GFX900-NEXT: s_and_b64 s[4:5], 0, exec
; GFX900-NEXT: ;;#ASMSTART
@@ -1194,11 +1195,11 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc_small_offset_fp
; GFX942-NEXT: scratch_store_dword off, v0, s3 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: s_addk_i32 s32, 0x4080
+; GFX942-NEXT: v_writelane_b32 v0, s55, 0
; GFX942-NEXT: s_and_b64 s[0:1], 0, exec
; GFX942-NEXT: s_addc_u32 s0, s33, 64
; GFX942-NEXT: s_bitcmp1_b32 s0, 0
; GFX942-NEXT: s_bitset0_b32 s0, 0
-; GFX942-NEXT: v_writelane_b32 v0, s55, 0
; GFX942-NEXT: s_mov_b32 s55, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s55, scc
@@ -1228,8 +1229,8 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset_fp()
; GFX10_1-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s5
-; GFX10_1-NEXT: v_writelane_b32 v0, s55, 0
; GFX10_1-NEXT: s_add_i32 s32, s32, 0x81000
+; GFX10_1-NEXT: v_writelane_b32 v0, s55, 0
; GFX10_1-NEXT: s_lshr_b32 s55, s33, 5
; GFX10_1-NEXT: s_mov_b32 s32, s33
; GFX10_1-NEXT: s_add_i32 s55, s55, 64
@@ -1255,8 +1256,8 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset_fp()
; GFX10_3-NEXT: s_add_i32 s6, s33, 0x80800
; GFX10_3-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX10_3-NEXT: s_mov_b32 exec_lo, s5
-; GFX10_3-NEXT: v_writelane_b32 v0, s55, 0
; GFX10_3-NEXT: s_add_i32 s32, s32, 0x81000
+; GFX10_3-NEXT: v_writelane_b32 v0, s55, 0
; GFX10_3-NEXT: s_lshr_b32 s55, s33, 5
; GFX10_3-NEXT: s_mov_b32 s32, s33
; GFX10_3-NEXT: s_add_i32 s55, s55, 64
@@ -1281,8 +1282,8 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset_fp()
; GFX11-NEXT: s_add_i32 s2, s33, 0x4040
; GFX11-NEXT: scratch_store_b32 off, v0, s2 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: v_writelane_b32 v0, s55, 0
; GFX11-NEXT: s_addk_i32 s32, 0x4080
+; GFX11-NEXT: v_writelane_b32 v0, s55, 0
; GFX11-NEXT: s_add_i32 s1, s33, 64
; GFX11-NEXT: s_mov_b32 s32, s33
; GFX11-NEXT: s_mov_b32 s55, s1
@@ -1311,14 +1312,15 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset_fp()
; GFX12-NEXT: scratch_store_b32 off, v0, s33 offset:16384 ; 4-byte Folded Spill
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s1
-; GFX12-NEXT: v_writelane_b32 v0, s55, 0
; GFX12-NEXT: s_addk_co_i32 s32, 0x4040
+; GFX12-NEXT: v_writelane_b32 v0, s55, 0
; GFX12-NEXT: s_mov_b32 s55, s33
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s55
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_mov_b32 s32, s33
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readlane_b32 s55, v0, 0
+; GFX12-NEXT: s_mov_b32 s32, s33
; GFX12-NEXT: s_xor_saveexec_b32 s1, -1
; GFX12-NEXT: scratch_load_b32 v0, off, s33 offset:16384 ; 4-byte Folded Reload
; GFX12-NEXT: s_wait_alu 0xfffe
@@ -1390,8 +1392,8 @@ define void @scalar_mov_materializes_frame_index_available_scc_small_offset_fp()
; GFX942-NEXT: scratch_store_dword off, v0, s1 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[2:3]
; GFX942-NEXT: s_addk_i32 s32, 0x4080
-; GFX942-NEXT: s_add_i32 s1, s33, 64
; GFX942-NEXT: v_writelane_b32 v0, s55, 0
+; GFX942-NEXT: s_add_i32 s1, s33, 64
; GFX942-NEXT: s_mov_b32 s55, s1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s55
@@ -1529,8 +1531,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_immoffset(
; GFX8-NEXT: s_add_i32 s6, s32, 0x201000
; GFX8-NEXT: buffer_store_dword v1, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
-; GFX8-NEXT: s_lshr_b32 s4, s32, 6
; GFX8-NEXT: v_writelane_b32 v1, s55, 0
+; GFX8-NEXT: s_lshr_b32 s4, s32, 6
; GFX8-NEXT: s_add_i32 s55, s4, 0x442c
; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 64, v0
@@ -1556,8 +1558,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_immoffset(
; GFX900-NEXT: s_add_i32 s6, s32, 0x201000
; GFX900-NEXT: buffer_store_dword v1, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
-; GFX900-NEXT: s_lshr_b32 s4, s32, 6
; GFX900-NEXT: v_writelane_b32 v1, s55, 0
+; GFX900-NEXT: s_lshr_b32 s4, s32, 6
; GFX900-NEXT: s_add_i32 s55, s4, 0x442c
; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32
; GFX900-NEXT: v_add_u32_e32 v0, 64, v0
@@ -1677,8 +1679,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_sgpr_offse
; GFX11-NEXT: s_add_i32 s2, s32, 0x8040
; GFX11-NEXT: scratch_store_b32 off, v1, s2 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: s_add_i32 s1, s32, 64
; GFX11-NEXT: v_writelane_b32 v1, s55, 0
+; GFX11-NEXT: s_add_i32 s1, s32, 64
; GFX11-NEXT: s_lshl_b32 s0, s0, 2
; GFX11-NEXT: v_mov_b32_e32 v0, s1
; GFX11-NEXT: s_add_i32 s55, s32, s0
@@ -1796,8 +1798,8 @@ define void @scalar_mov_materializes_frame_index_unavailable_scc__gep_sgpr_offse
; GFX942-NEXT: s_add_i32 s1, s32, 0x8040
; GFX942-NEXT: scratch_store_dword off, v1, s1 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[2:3]
-; GFX942-NEXT: s_lshl_b32 s0, s0, 2
; GFX942-NEXT: v_writelane_b32 v1, s55, 0
+; GFX942-NEXT: s_lshl_b32 s0, s0, 2
; GFX942-NEXT: s_add_i32 s55, s32, s0
; GFX942-NEXT: s_addk_i32 s55, 0x4040
; GFX942-NEXT: s_add_i32 s0, s32, 64
diff --git a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
index 8c2c16ccdc2a0..b0fee0fe0aa19 100644
--- a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
@@ -52,11 +52,11 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX7-NEXT: v_writelane_b32 v23, s53, 12
; GFX7-NEXT: v_writelane_b32 v23, s54, 13
; GFX7-NEXT: v_writelane_b32 v23, s55, 14
-; GFX7-NEXT: v_lshr_b32_e64 v0, s32, 6
; GFX7-NEXT: v_writelane_b32 v23, s30, 15
+; GFX7-NEXT: v_writelane_b32 v23, s31, 16
+; GFX7-NEXT: v_lshr_b32_e64 v0, s32, 6
; GFX7-NEXT: v_add_i32_e32 v0, vcc, 64, v0
; GFX7-NEXT: s_and_b64 s[4:5], 0, exec
-; GFX7-NEXT: v_writelane_b32 v23, s31, 16
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use alloca0 v0
; GFX7-NEXT: ;;#ASMEND
@@ -119,11 +119,11 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX8-NEXT: v_writelane_b32 v23, s53, 12
; GFX8-NEXT: v_writelane_b32 v23, s54, 13
; GFX8-NEXT: v_writelane_b32 v23, s55, 14
-; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32
; GFX8-NEXT: v_writelane_b32 v23, s30, 15
+; GFX8-NEXT: v_writelane_b32 v23, s31, 16
+; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 64, v0
; GFX8-NEXT: s_and_b64 s[4:5], 0, exec
-; GFX8-NEXT: v_writelane_b32 v23, s31, 16
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use alloca0 v0
; GFX8-NEXT: ;;#ASMEND
@@ -187,11 +187,11 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX900-NEXT: v_writelane_b32 v23, s53, 12
; GFX900-NEXT: v_writelane_b32 v23, s54, 13
; GFX900-NEXT: v_writelane_b32 v23, s55, 14
-; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32
; GFX900-NEXT: v_writelane_b32 v23, s30, 15
+; GFX900-NEXT: v_writelane_b32 v23, s31, 16
+; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32
; GFX900-NEXT: v_add_u32_e32 v0, 64, v0
; GFX900-NEXT: s_and_b64 s[4:5], 0, exec
-; GFX900-NEXT: v_writelane_b32 v23, s31, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use alloca0 v0
; GFX900-NEXT: ;;#ASMEND
@@ -254,11 +254,12 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX942-NEXT: v_writelane_b32 v23, s53, 12
; GFX942-NEXT: v_writelane_b32 v23, s54, 13
; GFX942-NEXT: v_writelane_b32 v23, s55, 14
-; GFX942-NEXT: s_add_i32 s0, s32, 64
; GFX942-NEXT: v_writelane_b32 v23, s30, 15
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v23, s31, 16
+; GFX942-NEXT: s_add_i32 s0, s32, 64
; GFX942-NEXT: v_mov_b32_e32 v0, s0
; GFX942-NEXT: s_and_b64 s[60:61], 0, exec
-; GFX942-NEXT: v_writelane_b32 v23, s31, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use alloca0 v0
; GFX942-NEXT: ;;#ASMEND
@@ -306,13 +307,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: v_writelane_b32 v23, s33, 0
-; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
-; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_1-NEXT: v_writelane_b32 v23, s34, 1
-; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0
-; GFX10_1-NEXT: ;;#ASMSTART
-; GFX10_1-NEXT: ; use alloca0 v0
-; GFX10_1-NEXT: ;;#ASMEND
; GFX10_1-NEXT: v_writelane_b32 v23, s35, 2
; GFX10_1-NEXT: v_writelane_b32 v23, s36, 3
; GFX10_1-NEXT: v_writelane_b32 v23, s37, 4
@@ -328,6 +323,12 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX10_1-NEXT: v_writelane_b32 v23, s55, 14
; GFX10_1-NEXT: v_writelane_b32 v23, s30, 15
; GFX10_1-NEXT: v_writelane_b32 v23, s31, 16
+; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
+; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo
+; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0
+; GFX10_1-NEXT: ;;#ASMSTART
+; GFX10_1-NEXT: ; use alloca0 v0
+; GFX10_1-NEXT: ;;#ASMEND
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc
; GFX10_1-NEXT: ;;#ASMEND
@@ -371,13 +372,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX10_3-NEXT: buffer_store_dword v23, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
; GFX10_3-NEXT: v_writelane_b32 v23, s33, 0
-; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s32
-; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo
; GFX10_3-NEXT: v_writelane_b32 v23, s34, 1
-; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0
-; GFX10_3-NEXT: ;;#ASMSTART
-; GFX10_3-NEXT: ; use alloca0 v0
-; GFX10_3-NEXT: ;;#ASMEND
; GFX10_3-NEXT: v_writelane_b32 v23, s35, 2
; GFX10_3-NEXT: v_writelane_b32 v23, s36, 3
; GFX10_3-NEXT: v_writelane_b32 v23, s37, 4
@@ -393,6 +388,12 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX10_3-NEXT: v_writelane_b32 v23, s55, 14
; GFX10_3-NEXT: v_writelane_b32 v23, s30, 15
; GFX10_3-NEXT: v_writelane_b32 v23, s31, 16
+; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s32
+; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo
+; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0
+; GFX10_3-NEXT: ;;#ASMSTART
+; GFX10_3-NEXT: ; use alloca0 v0
+; GFX10_3-NEXT: ;;#ASMEND
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc
; GFX10_3-NEXT: ;;#ASMEND
@@ -435,14 +436,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX11-NEXT: scratch_store_b32 off, v23, s1 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: v_writelane_b32 v23, s33, 0
-; GFX11-NEXT: s_add_i32 s0, s32, 64
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_mov_b32_e32 v0, s0
-; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
; GFX11-NEXT: v_writelane_b32 v23, s34, 1
-; GFX11-NEXT: ;;#ASMSTART
-; GFX11-NEXT: ; use alloca0 v0
-; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: v_writelane_b32 v23, s35, 2
; GFX11-NEXT: v_writelane_b32 v23, s36, 3
; GFX11-NEXT: v_writelane_b32 v23, s37, 4
@@ -458,14 +452,21 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX11-NEXT: v_writelane_b32 v23, s55, 14
; GFX11-NEXT: v_writelane_b32 v23, s30, 15
; GFX11-NEXT: v_writelane_b32 v23, s31, 16
+; GFX11-NEXT: s_add_i32 s0, s32, 64
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
+; GFX11-NEXT: ;;#ASMSTART
+; GFX11-NEXT: ; use alloca0 v0
+; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: s_addc_u32 s59, s32, 0x4040
; GFX11-NEXT: ; kill: def $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 killed $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 def $sgpr54
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_bitcmp1_b32 s59, 0
; GFX11-NEXT: s_bitset0_b32 s59, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_mov_b32 s54, s59
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc, s54, scc
@@ -506,11 +507,6 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: v_writelane_b32 v23, s33, 0
-; GFX12-NEXT: v_mov_b32_e32 v0, s32
-; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
-; GFX12-NEXT: ;;#ASMSTART
-; GFX12-NEXT: ; use alloca0 v0
-; GFX12-NEXT: ;;#ASMEND
; GFX12-NEXT: v_writelane_b32 v23, s34, 1
; GFX12-NEXT: v_writelane_b32 v23, s35, 2
; GFX12-NEXT: v_writelane_b32 v23, s36, 3
@@ -527,6 +523,11 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
; GFX12-NEXT: v_writelane_b32 v23, s55, 14
; GFX12-NEXT: v_writelane_b32 v23, s30, 15
; GFX12-NEXT: v_writelane_b32 v23, s31, 16
+; GFX12-NEXT: v_mov_b32_e32 v0, s32
+; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
+; GFX12-NEXT: ;;#ASMSTART
+; GFX12-NEXT: ; use alloca0 v0
+; GFX12-NEXT: ;;#ASMEND
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:22], vcc
; GFX12-NEXT: ;;#ASMEND
@@ -629,8 +630,8 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX7-NEXT: v_writelane_b32 v21, s54, 13
; GFX7-NEXT: v_writelane_b32 v21, s55, 14
; GFX7-NEXT: v_writelane_b32 v21, s30, 15
-; GFX7-NEXT: s_and_b64 s[4:5], 0, exec
; GFX7-NEXT: v_writelane_b32 v21, s31, 16
+; GFX7-NEXT: s_and_b64 s[4:5], 0, exec
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
; GFX7-NEXT: ;;#ASMEND
@@ -687,8 +688,8 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX8-NEXT: v_writelane_b32 v21, s54, 13
; GFX8-NEXT: v_writelane_b32 v21, s55, 14
; GFX8-NEXT: v_writelane_b32 v21, s30, 15
-; GFX8-NEXT: s_and_b64 s[4:5], 0, exec
; GFX8-NEXT: v_writelane_b32 v21, s31, 16
+; GFX8-NEXT: s_and_b64 s[4:5], 0, exec
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
; GFX8-NEXT: ;;#ASMEND
@@ -746,8 +747,8 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX900-NEXT: v_writelane_b32 v21, s54, 13
; GFX900-NEXT: v_writelane_b32 v21, s55, 14
; GFX900-NEXT: v_writelane_b32 v21, s30, 15
-; GFX900-NEXT: s_and_b64 s[4:5], 0, exec
; GFX900-NEXT: v_writelane_b32 v21, s31, 16
+; GFX900-NEXT: s_and_b64 s[4:5], 0, exec
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
; GFX900-NEXT: ;;#ASMEND
@@ -805,9 +806,9 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX942-NEXT: v_writelane_b32 v21, s54, 13
; GFX942-NEXT: v_writelane_b32 v21, s55, 14
; GFX942-NEXT: v_writelane_b32 v21, s30, 15
-; GFX942-NEXT: s_and_b64 s[60:61], 0, exec
-; GFX942-NEXT: s_nop 0
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v21, s31, 16
+; GFX942-NEXT: s_and_b64 s[60:61], 0, exec
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
; GFX942-NEXT: ;;#ASMEND
@@ -852,7 +853,6 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: v_writelane_b32 v21, s33, 0
-; GFX10_1-NEXT: s_and_b32 s59, 0, exec_lo
; GFX10_1-NEXT: v_writelane_b32 v21, s34, 1
; GFX10_1-NEXT: v_writelane_b32 v21, s35, 2
; GFX10_1-NEXT: v_writelane_b32 v21, s36, 3
@@ -874,6 +874,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX10_1-NEXT: ;;#ASMEND
; GFX10_1-NEXT: v_lshrrev_b32_e64 v22, 5, s32
; GFX10_1-NEXT: ; kill: def $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 killed $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 def $sgpr54
+; GFX10_1-NEXT: s_and_b32 s59, 0, exec_lo
; GFX10_1-NEXT: v_add_nc_u32_e32 v22, 16, v22
; GFX10_1-NEXT: v_readfirstlane_b32 s54, v22
; GFX10_1-NEXT: ;;#ASMSTART
@@ -912,7 +913,6 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX10_3-NEXT: buffer_store_dword v21, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
; GFX10_3-NEXT: v_writelane_b32 v21, s33, 0
-; GFX10_3-NEXT: s_and_b32 s59, 0, exec_lo
; GFX10_3-NEXT: v_writelane_b32 v21, s34, 1
; GFX10_3-NEXT: v_writelane_b32 v21, s35, 2
; GFX10_3-NEXT: v_writelane_b32 v21, s36, 3
@@ -934,6 +934,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX10_3-NEXT: ;;#ASMEND
; GFX10_3-NEXT: v_lshrrev_b32_e64 v22, 5, s32
; GFX10_3-NEXT: ; kill: def $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 killed $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 def $sgpr54
+; GFX10_3-NEXT: s_and_b32 s59, 0, exec_lo
; GFX10_3-NEXT: v_add_nc_u32_e32 v22, 16, v22
; GFX10_3-NEXT: v_readfirstlane_b32 s54, v22
; GFX10_3-NEXT: ;;#ASMSTART
@@ -971,7 +972,6 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX11-NEXT: scratch_store_b32 off, v21, s1 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: v_writelane_b32 v21, s33, 0
-; GFX11-NEXT: s_and_b32 s59, 0, exec_lo
; GFX11-NEXT: v_writelane_b32 v21, s34, 1
; GFX11-NEXT: v_writelane_b32 v21, s35, 2
; GFX11-NEXT: v_writelane_b32 v21, s36, 3
@@ -988,6 +988,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX11-NEXT: v_writelane_b32 v21, s55, 14
; GFX11-NEXT: v_writelane_b32 v21, s30, 15
; GFX11-NEXT: v_writelane_b32 v21, s31, 16
+; GFX11-NEXT: s_and_b32 s59, 0, exec_lo
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
; GFX11-NEXT: ;;#ASMEND
@@ -1036,7 +1037,6 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: v_writelane_b32 v21, s33, 0
-; GFX12-NEXT: s_and_b32 s59, 0, exec_lo
; GFX12-NEXT: v_writelane_b32 v21, s34, 1
; GFX12-NEXT: v_writelane_b32 v21, s35, 2
; GFX12-NEXT: v_writelane_b32 v21, s36, 3
@@ -1057,11 +1057,11 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
; GFX12-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
; GFX12-NEXT: ;;#ASMEND
; GFX12-NEXT: ; kill: def $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 killed $sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55 def $sgpr54
+; GFX12-NEXT: s_and_b32 s59, 0, exec_lo
; GFX12-NEXT: s_mov_b32 s54, s32
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc, s54, scc
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readlane_b32 s30, v21, 15
; GFX12-NEXT: v_readlane_b32 s31, v21, 16
; GFX12-NEXT: v_readlane_b32 s55, v21, 14
@@ -1150,16 +1150,16 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX7-NEXT: v_writelane_b32 v23, s52, 11
; GFX7-NEXT: v_writelane_b32 v23, s53, 12
; GFX7-NEXT: v_writelane_b32 v23, s54, 13
-; GFX7-NEXT: s_lshr_b32 s5, s32, 6
; GFX7-NEXT: v_writelane_b32 v23, s55, 14
+; GFX7-NEXT: v_writelane_b32 v23, s30, 15
+; GFX7-NEXT: v_writelane_b32 v23, s31, 16
+; GFX7-NEXT: s_lshr_b32 s5, s32, 6
; GFX7-NEXT: v_lshr_b32_e64 v0, s32, 6
; GFX7-NEXT: s_add_i32 s4, s5, 0x4240
; GFX7-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
-; GFX7-NEXT: v_writelane_b32 v23, s30, 15
; GFX7-NEXT: v_add_i32_e32 v0, vcc, 64, v0
; GFX7-NEXT: v_writelane_b32 v22, s4, 0
; GFX7-NEXT: s_and_b64 s[4:5], 0, exec
-; GFX7-NEXT: v_writelane_b32 v23, s31, 16
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use alloca0 v0
; GFX7-NEXT: ;;#ASMEND
@@ -1221,16 +1221,16 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX8-NEXT: v_writelane_b32 v23, s52, 11
; GFX8-NEXT: v_writelane_b32 v23, s53, 12
; GFX8-NEXT: v_writelane_b32 v23, s54, 13
-; GFX8-NEXT: s_lshr_b32 s5, s32, 6
; GFX8-NEXT: v_writelane_b32 v23, s55, 14
+; GFX8-NEXT: v_writelane_b32 v23, s30, 15
+; GFX8-NEXT: v_writelane_b32 v23, s31, 16
+; GFX8-NEXT: s_lshr_b32 s5, s32, 6
; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32
; GFX8-NEXT: s_add_i32 s4, s5, 0x4240
; GFX8-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
-; GFX8-NEXT: v_writelane_b32 v23, s30, 15
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 64, v0
; GFX8-NEXT: v_writelane_b32 v22, s4, 0
; GFX8-NEXT: s_and_b64 s[4:5], 0, exec
-; GFX8-NEXT: v_writelane_b32 v23, s31, 16
; GFX8-NEXT: ;;#ASMSTART
; GFX8-NEXT: ; use alloca0 v0
; GFX8-NEXT: ;;#ASMEND
@@ -1291,16 +1291,16 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX900-NEXT: v_writelane_b32 v23, s52, 11
; GFX900-NEXT: v_writelane_b32 v23, s53, 12
; GFX900-NEXT: v_writelane_b32 v23, s54, 13
-; GFX900-NEXT: s_lshr_b32 s5, s32, 6
; GFX900-NEXT: v_writelane_b32 v23, s55, 14
+; GFX900-NEXT: v_writelane_b32 v23, s30, 15
+; GFX900-NEXT: v_writelane_b32 v23, s31, 16
+; GFX900-NEXT: s_lshr_b32 s5, s32, 6
; GFX900-NEXT: v_lshrrev_b32_e64 v0, 6, s32
; GFX900-NEXT: s_add_i32 s4, s5, 0x4240
; GFX900-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
-; GFX900-NEXT: v_writelane_b32 v23, s30, 15
; GFX900-NEXT: v_add_u32_e32 v0, 64, v0
; GFX900-NEXT: v_writelane_b32 v22, s4, 0
; GFX900-NEXT: s_and_b64 s[4:5], 0, exec
-; GFX900-NEXT: v_writelane_b32 v23, s31, 16
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; use alloca0 v0
; GFX900-NEXT: ;;#ASMEND
@@ -1360,14 +1360,14 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX942-NEXT: v_writelane_b32 v22, s53, 12
; GFX942-NEXT: v_writelane_b32 v22, s54, 13
; GFX942-NEXT: v_writelane_b32 v22, s55, 14
-; GFX942-NEXT: s_add_i32 s0, s32, 64
; GFX942-NEXT: v_writelane_b32 v22, s30, 15
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v22, s31, 16
+; GFX942-NEXT: s_add_i32 s0, s32, 64
; GFX942-NEXT: v_mov_b32_e32 v0, s0
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use alloca0 v0
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 0
-; GFX942-NEXT: v_writelane_b32 v22, s31, 16
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX942-NEXT: ;;#ASMEND
@@ -1411,15 +1411,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX10_1-NEXT: s_waitcnt_depctr 0xffe3
; GFX10_1-NEXT: s_mov_b32 exec_lo, s4
; GFX10_1-NEXT: v_writelane_b32 v22, s33, 0
-; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
-; GFX10_1-NEXT: s_lshr_b32 s4, s32, 5
-; GFX10_1-NEXT: s_add_i32 s58, s4, 0x4240
; GFX10_1-NEXT: v_writelane_b32 v22, s34, 1
-; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0
-; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo
-; GFX10_1-NEXT: ;;#ASMSTART
-; GFX10_1-NEXT: ; use alloca0 v0
-; GFX10_1-NEXT: ;;#ASMEND
; GFX10_1-NEXT: v_writelane_b32 v22, s35, 2
; GFX10_1-NEXT: v_writelane_b32 v22, s36, 3
; GFX10_1-NEXT: v_writelane_b32 v22, s37, 4
@@ -1435,6 +1427,14 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX10_1-NEXT: v_writelane_b32 v22, s55, 14
; GFX10_1-NEXT: v_writelane_b32 v22, s30, 15
; GFX10_1-NEXT: v_writelane_b32 v22, s31, 16
+; GFX10_1-NEXT: v_lshrrev_b32_e64 v0, 5, s32
+; GFX10_1-NEXT: s_lshr_b32 s4, s32, 5
+; GFX10_1-NEXT: s_add_i32 s58, s4, 0x4240
+; GFX10_1-NEXT: s_and_b32 s4, 0, exec_lo
+; GFX10_1-NEXT: v_add_nc_u32_e32 v0, 64, v0
+; GFX10_1-NEXT: ;;#ASMSTART
+; GFX10_1-NEXT: ; use alloca0 v0
+; GFX10_1-NEXT: ;;#ASMEND
; GFX10_1-NEXT: ;;#ASMSTART
; GFX10_1-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX10_1-NEXT: ;;#ASMEND
@@ -1476,15 +1476,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX10_3-NEXT: buffer_store_dword v22, off, s[0:3], s5 ; 4-byte Folded Spill
; GFX10_3-NEXT: s_mov_b32 exec_lo, s4
; GFX10_3-NEXT: v_writelane_b32 v22, s33, 0
-; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s32
-; GFX10_3-NEXT: s_lshr_b32 s4, s32, 5
-; GFX10_3-NEXT: s_add_i32 s58, s4, 0x4240
; GFX10_3-NEXT: v_writelane_b32 v22, s34, 1
-; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0
-; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo
-; GFX10_3-NEXT: ;;#ASMSTART
-; GFX10_3-NEXT: ; use alloca0 v0
-; GFX10_3-NEXT: ;;#ASMEND
; GFX10_3-NEXT: v_writelane_b32 v22, s35, 2
; GFX10_3-NEXT: v_writelane_b32 v22, s36, 3
; GFX10_3-NEXT: v_writelane_b32 v22, s37, 4
@@ -1500,6 +1492,14 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX10_3-NEXT: v_writelane_b32 v22, s55, 14
; GFX10_3-NEXT: v_writelane_b32 v22, s30, 15
; GFX10_3-NEXT: v_writelane_b32 v22, s31, 16
+; GFX10_3-NEXT: v_lshrrev_b32_e64 v0, 5, s32
+; GFX10_3-NEXT: s_lshr_b32 s4, s32, 5
+; GFX10_3-NEXT: s_add_i32 s58, s4, 0x4240
+; GFX10_3-NEXT: s_and_b32 s4, 0, exec_lo
+; GFX10_3-NEXT: v_add_nc_u32_e32 v0, 64, v0
+; GFX10_3-NEXT: ;;#ASMSTART
+; GFX10_3-NEXT: ; use alloca0 v0
+; GFX10_3-NEXT: ;;#ASMEND
; GFX10_3-NEXT: ;;#ASMSTART
; GFX10_3-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX10_3-NEXT: ;;#ASMEND
@@ -1540,14 +1540,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX11-NEXT: scratch_store_b32 off, v22, s1 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: v_writelane_b32 v22, s33, 0
-; GFX11-NEXT: s_add_i32 s0, s32, 64
-; GFX11-NEXT: s_add_i32 s58, s32, 0x4240
-; GFX11-NEXT: v_mov_b32_e32 v0, s0
-; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
; GFX11-NEXT: v_writelane_b32 v22, s34, 1
-; GFX11-NEXT: ;;#ASMSTART
-; GFX11-NEXT: ; use alloca0 v0
-; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: v_writelane_b32 v22, s35, 2
; GFX11-NEXT: v_writelane_b32 v22, s36, 3
; GFX11-NEXT: v_writelane_b32 v22, s37, 4
@@ -1563,6 +1556,13 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX11-NEXT: v_writelane_b32 v22, s55, 14
; GFX11-NEXT: v_writelane_b32 v22, s30, 15
; GFX11-NEXT: v_writelane_b32 v22, s31, 16
+; GFX11-NEXT: s_add_i32 s0, s32, 64
+; GFX11-NEXT: s_add_i32 s58, s32, 0x4240
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: s_and_b32 s0, 0, exec_lo
+; GFX11-NEXT: ;;#ASMSTART
+; GFX11-NEXT: ; use alloca0 v0
+; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX11-NEXT: ;;#ASMEND
@@ -1571,7 +1571,6 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readlane_b32 s30, v22, 15
; GFX11-NEXT: v_readlane_b32 s31, v22, 16
; GFX11-NEXT: v_readlane_b32 s55, v22, 14
@@ -1608,12 +1607,6 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: v_writelane_b32 v22, s33, 0
-; GFX12-NEXT: s_add_co_i32 s58, s32, 0x4200
-; GFX12-NEXT: v_mov_b32_e32 v0, s32
-; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
-; GFX12-NEXT: ;;#ASMSTART
-; GFX12-NEXT: ; use alloca0 v0
-; GFX12-NEXT: ;;#ASMEND
; GFX12-NEXT: v_writelane_b32 v22, s34, 1
; GFX12-NEXT: v_writelane_b32 v22, s35, 2
; GFX12-NEXT: v_writelane_b32 v22, s36, 3
@@ -1630,6 +1623,12 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX12-NEXT: v_writelane_b32 v22, s55, 14
; GFX12-NEXT: v_writelane_b32 v22, s30, 15
; GFX12-NEXT: v_writelane_b32 v22, s31, 16
+; GFX12-NEXT: s_add_co_i32 s58, s32, 0x4200
+; GFX12-NEXT: v_mov_b32_e32 v0, s32
+; GFX12-NEXT: s_and_b32 s0, 0, exec_lo
+; GFX12-NEXT: ;;#ASMSTART
+; GFX12-NEXT: ; use alloca0 v0
+; GFX12-NEXT: ;;#ASMEND
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX12-NEXT: ;;#ASMEND
diff --git a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
index ca16e251d51cf..e84d3c913328c 100644
--- a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
@@ -8941,6 +8941,9 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX8-LABEL: v_maximumnum_v32bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX8-NEXT: buffer_load_dword v55, off, s[0:3], s32
; GFX8-NEXT: v_and_b32_e32 v31, 0xffff0000, v14
; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v30
@@ -8989,13 +8992,10 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX8-NEXT: v_and_b32_e32 v52, 0xffff0000, v21
; GFX8-NEXT: v_and_b32_e32 v53, 0xffff0000, v20
; GFX8-NEXT: v_and_b32_e32 v54, 0xffff0000, v19
-; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX8-NEXT: v_and_b32_e32 v40, 0xffff0000, v18
; GFX8-NEXT: v_and_b32_e32 v41, 0xffff0000, v17
; GFX8-NEXT: v_and_b32_e32 v42, 0xffff0000, v16
-; GFX8-NEXT: s_waitcnt vmcnt(3)
+; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v35, 16, v55
; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v55
; GFX8-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc
@@ -9563,6 +9563,9 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX900-LABEL: v_maximumnum_v32bf16:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX900-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX900-NEXT: buffer_load_dword v55, off, s[0:3], s32
; GFX900-NEXT: v_and_b32_e32 v31, 0xffff0000, v14
; GFX900-NEXT: v_lshrrev_b32_e32 v34, 16, v30
@@ -9611,14 +9614,11 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX900-NEXT: v_and_b32_e32 v52, 0xffff0000, v21
; GFX900-NEXT: v_and_b32_e32 v53, 0xffff0000, v20
; GFX900-NEXT: v_and_b32_e32 v54, 0xffff0000, v19
-; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX900-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX900-NEXT: v_and_b32_e32 v40, 0xffff0000, v18
; GFX900-NEXT: v_and_b32_e32 v41, 0xffff0000, v17
; GFX900-NEXT: v_and_b32_e32 v42, 0xffff0000, v16
; GFX900-NEXT: s_mov_b32 s4, 0x5040100
-; GFX900-NEXT: s_waitcnt vmcnt(3)
+; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_lshrrev_b32_e32 v35, 16, v55
; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v55
; GFX900-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc
@@ -10170,6 +10170,9 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX950-LABEL: v_maximumnum_v32bf16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse
; GFX950-NEXT: scratch_load_dword v50, off, s32
; GFX950-NEXT: v_and_b32_e32 v31, 0xffff0000, v14
; GFX950-NEXT: v_lshrrev_b32_e32 v34, 16, v30
@@ -10210,21 +10213,18 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v19
; GFX950-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc
; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v34
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v18
+; GFX950-NEXT: v_and_b32_e32 v41, 0xffff0000, v17
; GFX950-NEXT: v_cndmask_b32_e32 v31, v31, v34, vcc
; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v38
-; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse
-; GFX950-NEXT: v_and_b32_e32 v41, 0xffff0000, v17
+; GFX950-NEXT: v_and_b32_e32 v42, 0xffff0000, v16
+; GFX950-NEXT: s_mov_b32 s0, 0x5040100
; GFX950-NEXT: v_cndmask_b32_e32 v34, v35, v38, vcc
; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39
; GFX950-NEXT: v_and_b32_e32 v38, 0xffff0000, v27
; GFX950-NEXT: v_and_b32_e32 v39, 0xffff0000, v26
; GFX950-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc
; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
-; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse
-; GFX950-NEXT: v_and_b32_e32 v42, 0xffff0000, v16
-; GFX950-NEXT: s_mov_b32 s0, 0x5040100
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_lshrrev_b32_e32 v35, 16, v50
; GFX950-NEXT: v_and_b32_e32 v37, 0xffff0000, v50
diff --git a/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll b/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
index 02f39e25cb447..06213ef3e06ea 100644
--- a/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
+++ b/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
@@ -81,7 +81,6 @@ define void @memcpy_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0)
; ALIGNED-LABEL: memcpy_p0_p0_sz2048:
; ALIGNED: ; %bb.0: ; %entry
; ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; ALIGNED-NEXT: s_mov_b64 s[4:5], 0
; ALIGNED-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; ALIGNED-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; ALIGNED-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -90,6 +89,7 @@ define void @memcpy_p0_p0_sz2048(ptr addrspace(0) align 1 %dst, ptr addrspace(0)
; ALIGNED-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; ALIGNED-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; ALIGNED-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; ALIGNED-NEXT: s_mov_b64 s[4:5], 0
; ALIGNED-NEXT: .LBB0_1: ; %load-store-loop
; ALIGNED-NEXT: ; =>This Inner Loop Header: Depth=1
; ALIGNED-NEXT: v_add_co_u32 v24, vcc_lo, v2, s4
@@ -837,7 +837,6 @@ define void @memcpy_p1_p1_sz2048(ptr addrspace(1) align 1 %dst, ptr addrspace(1)
; ALIGNED-LABEL: memcpy_p1_p1_sz2048:
; ALIGNED: ; %bb.0: ; %entry
; ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; ALIGNED-NEXT: s_mov_b64 s[4:5], 0
; ALIGNED-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; ALIGNED-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; ALIGNED-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
@@ -846,6 +845,7 @@ define void @memcpy_p1_p1_sz2048(ptr addrspace(1) align 1 %dst, ptr addrspace(1)
; ALIGNED-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; ALIGNED-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; ALIGNED-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
+; ALIGNED-NEXT: s_mov_b64 s[4:5], 0
; ALIGNED-NEXT: .LBB1_1: ; %load-store-loop
; ALIGNED-NEXT: ; =>This Inner Loop Header: Depth=1
; ALIGNED-NEXT: v_add_co_u32 v24, vcc_lo, v2, s4
@@ -2340,7 +2340,6 @@ define void @memcpy_p5_p5_sz2048(ptr addrspace(5) align 1 %dst, ptr addrspace(5)
; ALIGNED-LABEL: memcpy_p5_p5_sz2048:
; ALIGNED: ; %bb.0: ; %entry
; ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; ALIGNED-NEXT: s_mov_b64 s[4:5], 0
; ALIGNED-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; ALIGNED-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; ALIGNED-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
@@ -2389,6 +2388,7 @@ define void @memcpy_p5_p5_sz2048(ptr addrspace(5) align 1 %dst, ptr addrspace(5)
; ALIGNED-NEXT: buffer_store_dword v125, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; ALIGNED-NEXT: buffer_store_dword v126, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; ALIGNED-NEXT: buffer_store_dword v127, off, s[0:3], s32 ; 4-byte Folded Spill
+; ALIGNED-NEXT: s_mov_b64 s[4:5], 0
; ALIGNED-NEXT: .LBB3_1: ; %load-store-loop
; ALIGNED-NEXT: ; =>This Inner Loop Header: Depth=1
; ALIGNED-NEXT: s_clause 0x34
diff --git a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
index 416a601797617..8184e1927146d 100644
--- a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
@@ -8980,6 +8980,9 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX8-LABEL: v_minimumnum_v32bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX8-NEXT: buffer_load_dword v55, off, s[0:3], s32
; GFX8-NEXT: v_and_b32_e32 v31, 0xffff0000, v14
; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v30
@@ -9029,13 +9032,10 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX8-NEXT: v_and_b32_e32 v52, 0xffff0000, v21
; GFX8-NEXT: v_and_b32_e32 v53, 0xffff0000, v20
; GFX8-NEXT: v_and_b32_e32 v54, 0xffff0000, v19
-; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX8-NEXT: v_and_b32_e32 v40, 0xffff0000, v18
; GFX8-NEXT: v_and_b32_e32 v41, 0xffff0000, v17
; GFX8-NEXT: v_and_b32_e32 v42, 0xffff0000, v16
-; GFX8-NEXT: s_waitcnt vmcnt(3)
+; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v35, 16, v55
; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v55
; GFX8-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc
@@ -9603,6 +9603,9 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX900-LABEL: v_minimumnum_v32bf16:
; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
+; GFX900-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX900-NEXT: buffer_load_dword v55, off, s[0:3], s32
; GFX900-NEXT: v_and_b32_e32 v31, 0xffff0000, v14
; GFX900-NEXT: v_lshrrev_b32_e32 v34, 16, v30
@@ -9652,13 +9655,10 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX900-NEXT: v_and_b32_e32 v52, 0xffff0000, v21
; GFX900-NEXT: v_and_b32_e32 v53, 0xffff0000, v20
; GFX900-NEXT: v_and_b32_e32 v54, 0xffff0000, v19
-; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
-; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
-; GFX900-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX900-NEXT: v_and_b32_e32 v40, 0xffff0000, v18
; GFX900-NEXT: v_and_b32_e32 v41, 0xffff0000, v17
; GFX900-NEXT: v_and_b32_e32 v42, 0xffff0000, v16
-; GFX900-NEXT: s_waitcnt vmcnt(3)
+; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_lshrrev_b32_e32 v35, 16, v55
; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v55
; GFX900-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc
@@ -10211,6 +10211,9 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX950-LABEL: v_minimumnum_v32bf16:
; GFX950: ; %bb.0:
; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse
+; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse
; GFX950-NEXT: scratch_load_dword v50, off, s32
; GFX950-NEXT: v_and_b32_e32 v31, 0xffff0000, v14
; GFX950-NEXT: v_lshrrev_b32_e32 v34, 16, v30
@@ -10252,20 +10255,17 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {
; GFX950-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc
; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v34
; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v19
-; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse
+; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v18
; GFX950-NEXT: v_cndmask_b32_e32 v31, v31, v34, vcc
; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, s0, v38
-; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v18
-; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse
+; GFX950-NEXT: v_and_b32_e32 v41, 0xffff0000, v17
+; GFX950-NEXT: v_and_b32_e32 v42, 0xffff0000, v16
; GFX950-NEXT: v_cndmask_b32_e32 v34, v35, v38, vcc
; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v39
; GFX950-NEXT: v_and_b32_e32 v38, 0xffff0000, v27
; GFX950-NEXT: v_and_b32_e32 v39, 0xffff0000, v26
; GFX950-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc
; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
-; GFX950-NEXT: v_and_b32_e32 v41, 0xffff0000, v17
-; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse
-; GFX950-NEXT: v_and_b32_e32 v42, 0xffff0000, v16
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_lshrrev_b32_e32 v35, 16, v50
; GFX950-NEXT: v_and_b32_e32 v37, 0xffff0000, v50
diff --git a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
index 7b87cb014ecbf..486a08d6ee8cd 100644
--- a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
+++ b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
@@ -195,21 +195,21 @@ define void @slsr1_1(i32 %b.arg, i32 %s.arg) #0 {
; GFX9-NEXT: s_mov_b64 exec, s[6:7]
; GFX9-NEXT: v_writelane_b32 v43, s4, 5
; GFX9-NEXT: s_addk_i32 s32, 0x800
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: v_writelane_b32 v43, s34, 0
; GFX9-NEXT: v_writelane_b32 v43, s36, 1
+; GFX9-NEXT: v_writelane_b32 v43, s37, 2
+; GFX9-NEXT: v_writelane_b32 v43, s30, 3
+; GFX9-NEXT: v_writelane_b32 v43, s31, 4
; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, foo at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, foo at gotpcrel32@hi+12
-; GFX9-NEXT: v_writelane_b32 v43, s37, 2
; GFX9-NEXT: s_load_dwordx2 s[36:37], s[4:5], 0x0
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, v1
; GFX9-NEXT: v_mov_b32_e32 v41, v0
-; GFX9-NEXT: v_writelane_b32 v43, s30, 3
; GFX9-NEXT: v_mul_u32_u24_e32 v0, v41, v40
-; GFX9-NEXT: v_writelane_b32 v43, s31, 4
; GFX9-NEXT: s_mov_b32 s34, s15
; GFX9-NEXT: v_and_b32_e32 v42, 0xffffff, v40
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/nested-calls.ll b/llvm/test/CodeGen/AMDGPU/nested-calls.ll
index 8394b325bee6d..da9463b1329c7 100644
--- a/llvm/test/CodeGen/AMDGPU/nested-calls.ll
+++ b/llvm/test/CodeGen/AMDGPU/nested-calls.ll
@@ -18,15 +18,15 @@ define void @test_func_call_external_void_func_i32_imm() #0 {
; GCN-NEXT: s_or_saveexec_b64 s[18:19], -1
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[18:19]
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s16, 2
+; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_getpc_b64 s[16:17]
; GCN-NEXT: s_add_u32 s16, s16, external_void_func_i32 at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s17, s17, external_void_func_i32 at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
; GCN-NEXT: v_mov_b32_e32 v0, 42
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: v_readlane_b32 s30, v40, 0
@@ -52,20 +52,20 @@ define void @test_func_call_external_void_func_i32_imm_stack_use() #0 {
; GCN-NEXT: s_or_saveexec_b64 s[18:19], -1
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:64 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[18:19]
-; GCN-NEXT: s_addk_i32 s32, 0x1400
; GCN-NEXT: v_writelane_b32 v40, s16, 2
+; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x1400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_getpc_b64 s[16:17]
; GCN-NEXT: s_add_u32 s16, s16, external_void_func_i32 at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s17, s17, external_void_func_i32 at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
; GCN-NEXT: v_mov_b32_e32 v0, 0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:64
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, 42
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: v_readlane_b32 s30, v40, 0
diff --git a/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll b/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
index 133cc166c3311..10c4b825308e1 100644
--- a/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
+++ b/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
@@ -233,6 +233,7 @@ define hidden void @_ZL3barv() #0 !dbg !1644 {
; CHECK-NEXT: s_add_i32 s32, s32, 0x400
; CHECK-NEXT: v_writelane_b32 v40, s30, 0
; CHECK-NEXT: v_writelane_b32 v40, s31, 1
+; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2623, 0, 32, 2623, 1, 32
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: .loc 0 31 3 prologue_end ; lane-info.cpp:31:3
; CHECK-NEXT: s_getpc_b64 s[16:17]
diff --git a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
index 4db196d4dd96c..6f94f719e872e 100644
--- a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
+++ b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
@@ -39,6 +39,7 @@ body: |
; GCN: liveins: $sgpr0, $vgpr8, $vgpr9, $vgpr10
; GCN-NEXT: {{ $}}
; GCN-NEXT: SCRATCH_STORE_DWORD_ST killed $vgpr10, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5)
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr10, 32, $exec_lo, 32, 0
; GCN-NEXT: renamable $vgpr10 = V_MOV_B32_e32 10, implicit $exec
; GCN-NEXT: $vgpr8 = COPY killed renamable $vgpr10
; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc
diff --git a/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir b/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
index a418e5c631b88..71573000555bb 100644
--- a/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
+++ b/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
@@ -25,15 +25,57 @@ machineFunctionInfo:
body: |
bb.0:
liveins: $sgpr30_sgpr31
- ; CHECK-LABEL: name: one_block
- ; CHECK: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $m0 = S_MOV_B32 9
- ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5)
- ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45
- ; CHECK-NEXT: $m0 = S_MOV_B32 9
- ; CHECK-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5)
- ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
+ ; W32-LABEL: name: one_block
+ ; W32: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73
+ ; W32-NEXT: {{ $}}
+ ; W32-NEXT: $m0 = S_MOV_B32 9
+ ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5)
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 0
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec_lo, 32, 96
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr72
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr73
+ ; W32-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45
+ ; W32-NEXT: $m0 = S_MOV_B32 9
+ ; W32-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5)
+ ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
+ ;
+ ; W64-LABEL: name: one_block
+ ; W64: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73
+ ; W64-NEXT: {{ $}}
+ ; W64-NEXT: $m0 = S_MOV_B32 9
+ ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5)
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 0
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 192
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr72
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr73
+ ; W64-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45
+ ; W64-NEXT: $m0 = S_MOV_B32 9
+ ; W64-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5)
+ ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45
S_SETPC_B64_return $sgpr30_sgpr31
...
@@ -49,15 +91,57 @@ machineFunctionInfo:
body: |
bb.0:
liveins: $sgpr30_sgpr31
- ; CHECK-LABEL: name: one_block_csr_only
- ; CHECK: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $m0 = S_MOV_B32 16711935
- ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5)
- ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66
- ; CHECK-NEXT: $m0 = S_MOV_B32 16711935
- ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (load (s1024) from %stack.0, align 4, addrspace 5)
- ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
+ ; W32-LABEL: name: one_block_csr_only
+ ; W32: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71
+ ; W32-NEXT: {{ $}}
+ ; W32-NEXT: $m0 = S_MOV_B32 16711935
+ ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5)
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 0
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec_lo, 32, 32
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 64
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec_lo, 32, 96
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec_lo, 32, 128
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec_lo, 32, 160
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec_lo, 32, 192
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec_lo, 32, 224
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec_lo, 32, 512
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec_lo, 32, 544
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec_lo, 32, 576
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec_lo, 32, 608
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec_lo, 32, 640
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec_lo, 32, 672
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec_lo, 32, 704
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec_lo, 32, 736
+ ; W32-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66
+ ; W32-NEXT: $m0 = S_MOV_B32 16711935
+ ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (load (s1024) from %stack.0, align 4, addrspace 5)
+ ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
+ ;
+ ; W64-LABEL: name: one_block_csr_only
+ ; W64: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71
+ ; W64-NEXT: {{ $}}
+ ; W64-NEXT: $m0 = S_MOV_B32 16711935
+ ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5)
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 0
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 64
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 128
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 192
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr44, 32, $exec, 64, 256
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 320
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr46, 32, $exec, 64, 384
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr47, 32, $exec, 64, 448
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr56, 32, $exec, 64, 1024
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr57, 32, $exec, 64, 1088
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr58, 32, $exec, 64, 1152
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr59, 32, $exec, 64, 1216
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr60, 32, $exec, 64, 1280
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr61, 32, $exec, 64, 1344
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr62, 32, $exec, 64, 1408
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr63, 32, $exec, 64, 1472
+ ; W64-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66
+ ; W64-NEXT: $m0 = S_MOV_B32 16711935
+ ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (load (s1024) from %stack.0, align 4, addrspace 5)
+ ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66
S_SETPC_B64_return $sgpr30_sgpr31
...
@@ -77,23 +161,137 @@ machineFunctionInfo:
body: |
bb.0:
liveins: $sgpr30_sgpr31
- ; CHECK-LABEL: name: multiple_blocks
- ; CHECK: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $m0 = S_MOV_B32 3
- ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5)
- ; CHECK-NEXT: $m0 = S_MOV_B32 65
- ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5)
- ; CHECK-NEXT: $m0 = S_MOV_B32 1
- ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5)
- ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232
- ; CHECK-NEXT: $m0 = S_MOV_B32 1
- ; CHECK-NEXT: $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr233, implicit $vgpr234, implicit $vgpr235, implicit $vgpr236, implicit $vgpr237, implicit $vgpr238, implicit $vgpr239, implicit $vgpr248, implicit $vgpr249, implicit $vgpr250, implicit $vgpr251, implicit $vgpr252, implicit $vgpr253, implicit $vgpr254, implicit $vgpr255 :: (load (s1024) from %stack.2, align 4, addrspace 5)
- ; CHECK-NEXT: $m0 = S_MOV_B32 65
- ; CHECK-NEXT: $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr105, implicit $vgpr106, implicit $vgpr107, implicit $vgpr108, implicit $vgpr109, implicit $vgpr111, implicit $vgpr120, implicit $vgpr121, implicit $vgpr122, implicit $vgpr123, implicit $vgpr124, implicit $vgpr125, implicit $vgpr126, implicit $vgpr127 :: (load (s1024) from %stack.1, align 4, addrspace 5)
- ; CHECK-NEXT: $m0 = S_MOV_B32 3
- ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5)
- ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
+ ; W32-LABEL: name: multiple_blocks
+ ; W32: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263
+ ; W32-NEXT: {{ $}}
+ ; W32-NEXT: $m0 = S_MOV_B32 3
+ ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5)
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 1024
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec_lo, 32, 1056
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
+ ; W32-NEXT: $m0 = S_MOV_B32 65
+ ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5)
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr104, 32, $exec_lo, 32, 128
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr105
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr106
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr107
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr108
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr109
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr110, 32, $exec_lo, 32, 320
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr111
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr120
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr121
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr122
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr123
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr124
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr125
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr126
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr127
+ ; W32-NEXT: $m0 = S_MOV_B32 1
+ ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5)
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr232, 32, $exec_lo, 32, 0
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr233
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr234
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr235
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr236
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr237
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr238
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr239
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr248
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr249
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr250
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr251
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr252
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr253
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr254
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr255
+ ; W32-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232
+ ; W32-NEXT: $m0 = S_MOV_B32 1
+ ; W32-NEXT: $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr233, implicit $vgpr234, implicit $vgpr235, implicit $vgpr236, implicit $vgpr237, implicit $vgpr238, implicit $vgpr239, implicit $vgpr248, implicit $vgpr249, implicit $vgpr250, implicit $vgpr251, implicit $vgpr252, implicit $vgpr253, implicit $vgpr254, implicit $vgpr255 :: (load (s1024) from %stack.2, align 4, addrspace 5)
+ ; W32-NEXT: $m0 = S_MOV_B32 65
+ ; W32-NEXT: $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr105, implicit $vgpr106, implicit $vgpr107, implicit $vgpr108, implicit $vgpr109, implicit $vgpr111, implicit $vgpr120, implicit $vgpr121, implicit $vgpr122, implicit $vgpr123, implicit $vgpr124, implicit $vgpr125, implicit $vgpr126, implicit $vgpr127 :: (load (s1024) from %stack.1, align 4, addrspace 5)
+ ; W32-NEXT: $m0 = S_MOV_B32 3
+ ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5)
+ ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
+ ;
+ ; W64-LABEL: name: multiple_blocks
+ ; W64: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263
+ ; W64-NEXT: {{ $}}
+ ; W64-NEXT: $m0 = S_MOV_B32 3
+ ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5)
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 2048
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 2112
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
+ ; W64-NEXT: $m0 = S_MOV_B32 65
+ ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5)
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr104, 32, $exec, 64, 256
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr105
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr106
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr107
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr108
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr109
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr110, 32, $exec, 64, 640
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr111
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr120
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr121
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr122
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr123
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr124
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr125
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr126
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr127
+ ; W64-NEXT: $m0 = S_MOV_B32 1
+ ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5)
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr232, 32, $exec, 64, 0
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr233
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr234
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr235
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr236
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr237
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr238
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr239
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr248
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr249
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr250
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr251
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr252
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr253
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr254
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr255
+ ; W64-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232
+ ; W64-NEXT: $m0 = S_MOV_B32 1
+ ; W64-NEXT: $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr233, implicit $vgpr234, implicit $vgpr235, implicit $vgpr236, implicit $vgpr237, implicit $vgpr238, implicit $vgpr239, implicit $vgpr248, implicit $vgpr249, implicit $vgpr250, implicit $vgpr251, implicit $vgpr252, implicit $vgpr253, implicit $vgpr254, implicit $vgpr255 :: (load (s1024) from %stack.2, align 4, addrspace 5)
+ ; W64-NEXT: $m0 = S_MOV_B32 65
+ ; W64-NEXT: $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr105, implicit $vgpr106, implicit $vgpr107, implicit $vgpr108, implicit $vgpr109, implicit $vgpr111, implicit $vgpr120, implicit $vgpr121, implicit $vgpr122, implicit $vgpr123, implicit $vgpr124, implicit $vgpr125, implicit $vgpr126, implicit $vgpr127 :: (load (s1024) from %stack.1, align 4, addrspace 5)
+ ; W64-NEXT: $m0 = S_MOV_B32 3
+ ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5)
+ ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232
S_SETPC_B64_return $sgpr30_sgpr31
...
@@ -111,19 +309,97 @@ machineFunctionInfo:
body: |
bb.0:
liveins: $sgpr30_sgpr31
- ; CHECK-LABEL: name: reg_tuples
- ; CHECK: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $m0 = S_MOV_B32 7
- ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5)
- ; CHECK-NEXT: $m0 = S_MOV_B32 3
- ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5)
- ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73
- ; CHECK-NEXT: $m0 = S_MOV_B32 3
- ; CHECK-NEXT: $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr74, implicit $vgpr75, implicit $vgpr76, implicit $vgpr77, implicit $vgpr78, implicit $vgpr79, implicit $vgpr88, implicit $vgpr89, implicit $vgpr90, implicit $vgpr91, implicit $vgpr92, implicit $vgpr93, implicit $vgpr94, implicit $vgpr95 :: (load (s1024) from %stack.1, align 4, addrspace 5)
- ; CHECK-NEXT: $m0 = S_MOV_B32 7
- ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5)
- ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
+ ; W32-LABEL: name: reg_tuples
+ ; W32: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103
+ ; W32-NEXT: {{ $}}
+ ; W32-NEXT: $m0 = S_MOV_B32 7
+ ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5)
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 256
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec_lo, 32, 288
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 320
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
+ ; W32-NEXT: $m0 = S_MOV_B32 3
+ ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5)
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr72, 32, $exec_lo, 32, 0
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr73, 32, $exec_lo, 32, 32
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr74
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr75
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr76
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr77
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr78
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr79
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr88
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr89
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr90
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr91
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr92
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr93
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr94
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr95
+ ; W32-NEXT: S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73
+ ; W32-NEXT: $m0 = S_MOV_B32 3
+ ; W32-NEXT: $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr74, implicit $vgpr75, implicit $vgpr76, implicit $vgpr77, implicit $vgpr78, implicit $vgpr79, implicit $vgpr88, implicit $vgpr89, implicit $vgpr90, implicit $vgpr91, implicit $vgpr92, implicit $vgpr93, implicit $vgpr94, implicit $vgpr95 :: (load (s1024) from %stack.1, align 4, addrspace 5)
+ ; W32-NEXT: $m0 = S_MOV_B32 7
+ ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5)
+ ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
+ ;
+ ; W64-LABEL: name: reg_tuples
+ ; W64: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103
+ ; W64-NEXT: {{ $}}
+ ; W64-NEXT: $m0 = S_MOV_B32 7
+ ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5)
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 512
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr41, 32, $exec, 64, 576
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 640
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
+ ; W64-NEXT: $m0 = S_MOV_B32 3
+ ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5)
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr72, 32, $exec, 64, 0
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr73, 32, $exec, 64, 64
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr74
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr75
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr76
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr77
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr78
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr79
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr88
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr89
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr90
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr91
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr92
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr93
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr94
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr95
+ ; W64-NEXT: S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73
+ ; W64-NEXT: $m0 = S_MOV_B32 3
+ ; W64-NEXT: $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr74, implicit $vgpr75, implicit $vgpr76, implicit $vgpr77, implicit $vgpr78, implicit $vgpr79, implicit $vgpr88, implicit $vgpr89, implicit $vgpr90, implicit $vgpr91, implicit $vgpr92, implicit $vgpr93, implicit $vgpr94, implicit $vgpr95 :: (load (s1024) from %stack.1, align 4, addrspace 5)
+ ; W64-NEXT: $m0 = S_MOV_B32 7
+ ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5)
+ ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73
S_SETPC_B64_return $sgpr30_sgpr31
...
@@ -147,17 +423,61 @@ stack:
body: |
bb.0:
liveins: $sgpr30_sgpr31, $vgpr48
- ; CHECK-LABEL: name: locals
- ; CHECK: liveins: $vgpr48, $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $m0 = S_MOV_B32 1
- ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5)
- ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5)
- ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5)
- ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40
- ; CHECK-NEXT: $m0 = S_MOV_B32 1
- ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.2, align 4, addrspace 5)
- ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
+ ; W32-LABEL: name: locals
+ ; W32: liveins: $vgpr48, $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71
+ ; W32-NEXT: {{ $}}
+ ; W32-NEXT: $m0 = S_MOV_B32 1
+ ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5)
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 0
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr41
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
+ ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5)
+ ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5)
+ ; W32-NEXT: S_NOP 0, implicit-def $vgpr40
+ ; W32-NEXT: $m0 = S_MOV_B32 1
+ ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.2, align 4, addrspace 5)
+ ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
+ ;
+ ; W64-LABEL: name: locals
+ ; W64: liveins: $vgpr48, $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71
+ ; W64-NEXT: {{ $}}
+ ; W64-NEXT: $m0 = S_MOV_B32 1
+ ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5)
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 0
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr41
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr43
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
+ ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5)
+ ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5)
+ ; W64-NEXT: S_NOP 0, implicit-def $vgpr40
+ ; W64-NEXT: $m0 = S_MOV_B32 1
+ ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.2, align 4, addrspace 5)
+ ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
SCRATCH_STORE_DWORD_SADDR $vgpr48, %stack.0, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5)
SCRATCH_STORE_DWORD_SADDR $vgpr48, %stack.1, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5)
S_NOP 0, implicit-def $vgpr40
@@ -191,6 +511,22 @@ body: |
; W32-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0
; W32-NEXT: $m0 = S_MOV_B32 9
; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.4, align 4, addrspace 5)
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec_lo, 32, 0
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr41
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec_lo, 32, 96
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
; W32-NEXT: $vgpr44 = SI_SPILL_S32_TO_VGPR $sgpr48, 0, $vgpr44
; W32-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr43, implicit-def $sgpr22, implicit-def $sgpr48, implicit-def $m0, implicit-def $exec
; W32-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, implicit $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40
@@ -214,6 +550,22 @@ body: |
; W64-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1
; W64-NEXT: $m0 = S_MOV_B32 9
; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.4, align 4, addrspace 5)
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr40, 32, $exec, 64, 0
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr41
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr42
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 192
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr45
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
; W64-NEXT: $vgpr44 = SI_SPILL_S32_TO_VGPR $sgpr48, 0, $vgpr44
; W64-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr43, implicit-def $sgpr22, implicit-def $sgpr48, implicit-def $m0, implicit-def $exec
; W64-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, implicit $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40
@@ -257,29 +609,85 @@ tracksRegLiveness: true
machineFunctionInfo:
stackPtrOffsetReg: $sgpr32
body: |
- ; CHECK-LABEL: name: multiple_basic_blocks
- ; CHECK: bb.0:
- ; CHECK-NEXT: successors: %bb.1(0x80000000)
- ; CHECK-NEXT: liveins: $vgpr44, $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $m0 = S_MOV_B32 11
- ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5)
- ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45
- ; CHECK-NEXT: S_BRANCH %bb.1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: successors: %bb.2(0x80000000)
- ; CHECK-NEXT: liveins: $vgpr44, $sgpr30_sgpr31
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr43, implicit $vgpr44
- ; CHECK-NEXT: S_BRANCH %bb.2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.2:
- ; CHECK-NEXT: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $m0 = S_MOV_B32 11
- ; CHECK-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5)
- ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
+ ; W32-LABEL: name: multiple_basic_blocks
+ ; W32: bb.0:
+ ; W32-NEXT: successors: %bb.1(0x80000000)
+ ; W32-NEXT: liveins: $vgpr44, $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73
+ ; W32-NEXT: {{ $}}
+ ; W32-NEXT: $m0 = S_MOV_B32 11
+ ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5)
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec_lo, 32, 0
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec_lo, 32, 32
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec_lo, 32, 96
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr72
+ ; W32-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr73
+ ; W32-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45
+ ; W32-NEXT: S_BRANCH %bb.1
+ ; W32-NEXT: {{ $}}
+ ; W32-NEXT: bb.1:
+ ; W32-NEXT: successors: %bb.2(0x80000000)
+ ; W32-NEXT: liveins: $vgpr44, $sgpr30_sgpr31
+ ; W32-NEXT: {{ $}}
+ ; W32-NEXT: S_NOP 0, implicit-def $vgpr43, implicit $vgpr44
+ ; W32-NEXT: S_BRANCH %bb.2
+ ; W32-NEXT: {{ $}}
+ ; W32-NEXT: bb.2:
+ ; W32-NEXT: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73
+ ; W32-NEXT: {{ $}}
+ ; W32-NEXT: $m0 = S_MOV_B32 11
+ ; W32-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5)
+ ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
+ ;
+ ; W64-LABEL: name: multiple_basic_blocks
+ ; W64: bb.0:
+ ; W64-NEXT: successors: %bb.1(0x80000000)
+ ; W64-NEXT: liveins: $vgpr44, $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73
+ ; W64-NEXT: {{ $}}
+ ; W64-NEXT: $m0 = S_MOV_B32 11
+ ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5)
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr42, 32, $exec, 64, 0
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr43, 32, $exec, 64, 64
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr44
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_offset $vgpr45, 32, $exec, 64, 192
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr46
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr47
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr56
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr57
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr58
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr59
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr60
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr61
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr62
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr63
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr72
+ ; W64-NEXT: frame-setup CFI_INSTRUCTION same_value $vgpr73
+ ; W64-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45
+ ; W64-NEXT: S_BRANCH %bb.1
+ ; W64-NEXT: {{ $}}
+ ; W64-NEXT: bb.1:
+ ; W64-NEXT: successors: %bb.2(0x80000000)
+ ; W64-NEXT: liveins: $vgpr44, $sgpr30_sgpr31
+ ; W64-NEXT: {{ $}}
+ ; W64-NEXT: S_NOP 0, implicit-def $vgpr43, implicit $vgpr44
+ ; W64-NEXT: S_BRANCH %bb.2
+ ; W64-NEXT: {{ $}}
+ ; W64-NEXT: bb.2:
+ ; W64-NEXT: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73
+ ; W64-NEXT: {{ $}}
+ ; W64-NEXT: $m0 = S_MOV_B32 11
+ ; W64-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5)
+ ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31
bb.0:
liveins: $sgpr30_sgpr31, $vgpr44
S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45
diff --git a/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll b/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
index 1576e951ec422..8f3f865df62fd 100644
--- a/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
+++ b/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
@@ -17,6 +17,13 @@ define void @preserve_wwm_copy_dstreg(ptr %parg0, ptr %parg1, ptr %parg2) #0 {
; GFX906-NEXT: s_mov_b64 exec, -1
; GFX906-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:148 ; 4-byte Folded Spill
; GFX906-NEXT: s_mov_b64 exec, s[18:19]
+; GFX906-NEXT: v_writelane_b32 v41, s16, 4
+; GFX906-NEXT: v_writelane_b32 v41, s34, 2
+; GFX906-NEXT: v_writelane_b32 v41, s35, 3
+; GFX906-NEXT: s_addk_i32 s32, 0x2800
+; GFX906-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX906-NEXT: v_writelane_b32 v41, s30, 0
+; GFX906-NEXT: v_writelane_b32 v41, s31, 1
; GFX906-NEXT: s_mov_b32 s21, s15
; GFX906-NEXT: ; implicit-def: $vgpr39 : SGPR spill to VGPR lane
; GFX906-NEXT: s_mov_b32 s22, s14
@@ -30,17 +37,10 @@ define void @preserve_wwm_copy_dstreg(ptr %parg0, ptr %parg1, ptr %parg2) #0 {
; GFX906-NEXT: v_writelane_b32 v39, s26, 4
; GFX906-NEXT: v_writelane_b32 v39, s27, 5
; GFX906-NEXT: v_writelane_b32 v39, s8, 6
-; GFX906-NEXT: v_writelane_b32 v41, s16, 4
; GFX906-NEXT: v_writelane_b32 v39, s9, 7
-; GFX906-NEXT: v_writelane_b32 v41, s34, 2
; GFX906-NEXT: v_writelane_b32 v39, s6, 8
-; GFX906-NEXT: v_writelane_b32 v41, s35, 3
; GFX906-NEXT: v_writelane_b32 v39, s7, 9
-; GFX906-NEXT: v_writelane_b32 v41, s30, 0
; GFX906-NEXT: v_writelane_b32 v39, s4, 10
-; GFX906-NEXT: s_addk_i32 s32, 0x2800
-; GFX906-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
-; GFX906-NEXT: v_writelane_b32 v41, s31, 1
; GFX906-NEXT: v_mov_b32_e32 v32, v31
; GFX906-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; GFX906-NEXT: s_nop 0
diff --git a/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll b/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
index ef5681798fb19..1260e147fbc53 100644
--- a/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
+++ b/llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
@@ -11,8 +11,8 @@ define void @test_remat_s_getpc_b64() {
; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v2, s30, 0
-; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: v_writelane_b32 v2, s31, 1
+; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: ;;#ASMSTART
@@ -36,16 +36,15 @@ define void @test_remat_s_getpc_b64() {
; GFX11-NEXT: scratch_store_b32 off, v2, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: v_writelane_b32 v2, s30, 0
+; GFX11-NEXT: v_writelane_b32 v2, s31, 1
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ;;#ASMEND
-; GFX11-NEXT: v_writelane_b32 v2, s31, 1
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: s_getpc_b64 s[0:1]
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_readlane_b32 s30, v2, 0
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_readlane_b32 s31, v2, 1
; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
@@ -66,20 +65,20 @@ define void @test_remat_s_getpc_b64() {
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_mov_b32 exec_lo, s0
; GFX12-NEXT: v_writelane_b32 v2, s30, 0
+; GFX12-NEXT: v_writelane_b32 v2, s31, 1
; GFX12-NEXT: s_getpc_b64 s[0:1]
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_sext_i32_i16 s1, s1
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ;;#ASMEND
-; GFX12-NEXT: v_writelane_b32 v2, s31, 1
; GFX12-NEXT: ;;#ASMSTART
; GFX12-NEXT: ;;#ASMEND
; GFX12-NEXT: s_getpc_b64 s[0:1]
+; GFX12-NEXT: v_readlane_b32 s30, v2, 0
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: s_sext_i32_i16 s1, s1
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-NEXT: v_readlane_b32 s30, v2, 0
; GFX12-NEXT: v_readlane_b32 s31, v2, 1
; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off
; GFX12-NEXT: s_xor_saveexec_b32 s0, -1
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
index 4a2829947f9a0..6488b44275f4e 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
@@ -41,73 +41,140 @@ body: |
; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0
; GCN-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 24, implicit-def dead $scc
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr4, $vgpr255, 0, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr5, 1, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr5, $vgpr255, 1, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr6, 2, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr6, $vgpr255, 2, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr7, 3, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr7, $vgpr255, 3, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr8, 4, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr8, $vgpr255, 4, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr9, 5, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr9, $vgpr255, 5, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr10, 6, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr10, $vgpr255, 6, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr11, 7, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr11, $vgpr255, 7, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr12, 8, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr12, $vgpr255, 8, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr13, 9, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr13, $vgpr255, 9, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr14, 10, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr14, $vgpr255, 10, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr15, 11, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr15, $vgpr255, 11, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr16, 12, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr16, $vgpr255, 12, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr17, 13, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr17, $vgpr255, 13, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr18, 14, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr18, $vgpr255, 14, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr19, 15, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr19, $vgpr255, 15, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr20, 16, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr20, $vgpr255, 16, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr21, 17, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr21, $vgpr255, 17, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr22, 18, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr22, $vgpr255, 18, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr23, 19, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr23, $vgpr255, 19, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr24, 20, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr24, $vgpr255, 20, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr25, 21, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr25, $vgpr255, 21, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr26, 22, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr26, $vgpr255, 22, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr27, 23, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr27, $vgpr255, 23, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr28, 24, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr28, $vgpr255, 24, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr29, 25, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr29, $vgpr255, 25, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr64, 26, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr64, $vgpr255, 26, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr65, 27, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr65, $vgpr255, 27, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr66, 28, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr66, $vgpr255, 28, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr67, 29, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr67, $vgpr255, 29, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr68, 30, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr68, $vgpr255, 30, 32
; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr69, 31, $vgpr2
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr69, $vgpr255, 31, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr70, 0, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr70, $vgpr254, 0, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr71, 1, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr71, $vgpr254, 1, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr72, 2, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr72, $vgpr254, 2, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr73, 3, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr73, $vgpr254, 3, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr74, 4, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr74, $vgpr254, 4, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr75, 5, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr75, $vgpr254, 5, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr76, 6, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr76, $vgpr254, 6, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr77, 7, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr77, $vgpr254, 7, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr78, 8, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr78, $vgpr254, 8, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr79, 9, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr79, $vgpr254, 9, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr80, 10, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr80, $vgpr254, 10, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr81, 11, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr81, $vgpr254, 11, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr82, 12, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr82, $vgpr254, 12, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr83, 13, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr83, $vgpr254, 13, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr84, 14, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr84, $vgpr254, 14, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr85, 15, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr85, $vgpr254, 15, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr86, 16, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr86, $vgpr254, 16, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr87, 17, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr87, $vgpr254, 17, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr88, 18, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr88, $vgpr254, 18, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr89, 19, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr89, $vgpr254, 19, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr90, 20, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr90, $vgpr254, 20, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr91, 21, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr91, $vgpr254, 21, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr92, 22, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr92, $vgpr254, 22, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr93, 23, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr93, $vgpr254, 23, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr94, 24, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr94, $vgpr254, 24, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr95, 25, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr95, $vgpr254, 25, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr96, 26, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr96, $vgpr254, 26, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr97, 27, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr97, $vgpr254, 27, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr98, 28, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr98, $vgpr254, 28, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr99, 29, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr99, $vgpr254, 29, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr100, 30, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr100, $vgpr254, 30, 32
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr101, 31, $vgpr3
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr101, $vgpr254, 31, 32
; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr102, 0, $vgpr4
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr102, $vgpr253, 0, 32
; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr103, 1, $vgpr4
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr103, $vgpr253, 1, 32
; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr30, 2, $vgpr4, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr31, 3, $vgpr4, implicit $sgpr30_sgpr31
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr253, 2, 32, $vgpr253, 3, 32
; GCN-NEXT: $sgpr22 = IMPLICIT_DEF
; GCN-NEXT: $vgpr5 = IMPLICIT_DEF
; GCN-NEXT: $vgpr5 = SI_SPILL_S32_TO_VGPR $sgpr22, 0, killed $vgpr5
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
index 2317a30d7c017..7feef49839ed5 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
@@ -14689,10 +14689,10 @@ define void @s_shuffle_v2i64_v8i64__15_2() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:23]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -14718,10 +14718,10 @@ define void @s_shuffle_v2i64_v8i64__15_2() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:23]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -14829,10 +14829,10 @@ define void @s_shuffle_v2i64_v8i64__15_4() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -14858,10 +14858,10 @@ define void @s_shuffle_v2i64_v8i64__15_4() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -14887,18 +14887,19 @@ define void @s_shuffle_v2i64_v8i64__15_4() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:19]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s30
; GFX942-NEXT: s_mov_b32 s9, s31
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
+; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -14923,10 +14924,10 @@ define void @s_shuffle_v2i64_v8i64__15_5() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -14952,10 +14953,10 @@ define void @s_shuffle_v2i64_v8i64__15_5() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -15087,18 +15088,19 @@ define void @s_shuffle_v2i64_v8i64__15_6() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s30
; GFX942-NEXT: s_mov_b32 s9, s31
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
+; GFX942-NEXT: s_mov_b32 s10, s12
+; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -15129,10 +15131,10 @@ define void @s_shuffle_v2i64_v8i64__15_7() {
; GFX900-NEXT: v_writelane_b32 v0, s48, 4
; GFX900-NEXT: v_writelane_b32 v0, s49, 5
; GFX900-NEXT: v_writelane_b32 v0, s50, 6
+; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[36:51]
; GFX900-NEXT: ;;#ASMEND
@@ -15170,10 +15172,10 @@ define void @s_shuffle_v2i64_v8i64__15_7() {
; GFX90A-NEXT: v_writelane_b32 v0, s48, 4
; GFX90A-NEXT: v_writelane_b32 v0, s49, 5
; GFX90A-NEXT: v_writelane_b32 v0, s50, 6
+; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[36:51]
; GFX90A-NEXT: ;;#ASMEND
@@ -15205,11 +15207,11 @@ define void @s_shuffle_v2i64_v8i64__15_7() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
@@ -16256,14 +16258,14 @@ define void @s_shuffle_v2i64_v8i64__12_0() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
-; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ;;#ASMSTART
+; GFX942-NEXT: ; def s[0:15]
+; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s10, s16
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s11, s17
@@ -16980,14 +16982,14 @@ define void @s_shuffle_v2i64_v8i64__12_1() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
-; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ;;#ASMSTART
+; GFX942-NEXT: ; def s[0:15]
+; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s10, s18
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s11, s19
@@ -17565,10 +17567,10 @@ define void @s_shuffle_v2i64_v8i64__9_2() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:23]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -17594,10 +17596,10 @@ define void @s_shuffle_v2i64_v8i64__9_2() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:23]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -17739,10 +17741,10 @@ define void @s_shuffle_v2i64_v8i64__11_2() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:23]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -17768,10 +17770,10 @@ define void @s_shuffle_v2i64_v8i64__11_2() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:23]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -17883,10 +17885,10 @@ define void @s_shuffle_v2i64_v8i64__13_2() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[8:23]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -17912,10 +17914,10 @@ define void @s_shuffle_v2i64_v8i64__13_2() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[8:23]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -19036,10 +19038,10 @@ define void @s_shuffle_v2i64_v8i64__9_4() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -19065,10 +19067,10 @@ define void @s_shuffle_v2i64_v8i64__9_4() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -19094,18 +19096,19 @@ define void @s_shuffle_v2i64_v8i64__9_4() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:19]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s18
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s19
+; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -19186,10 +19189,10 @@ define void @s_shuffle_v2i64_v8i64__11_4() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -19215,10 +19218,10 @@ define void @s_shuffle_v2i64_v8i64__11_4() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -19244,18 +19247,19 @@ define void @s_shuffle_v2i64_v8i64__11_4() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:19]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s22
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s23
+; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -19280,10 +19284,10 @@ define void @s_shuffle_v2i64_v8i64__12_4() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -19309,10 +19313,10 @@ define void @s_shuffle_v2i64_v8i64__12_4() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -19362,10 +19366,10 @@ define void @s_shuffle_v2i64_v8i64__13_4() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -19391,10 +19395,10 @@ define void @s_shuffle_v2i64_v8i64__13_4() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -19420,18 +19424,19 @@ define void @s_shuffle_v2i64_v8i64__13_4() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[4:19]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s26
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s27
+; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -19456,10 +19461,10 @@ define void @s_shuffle_v2i64_v8i64__14_4() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -19485,10 +19490,10 @@ define void @s_shuffle_v2i64_v8i64__14_4() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -19957,10 +19962,10 @@ define void @s_shuffle_v2i64_v8i64__9_5() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -19986,10 +19991,10 @@ define void @s_shuffle_v2i64_v8i64__9_5() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -20095,10 +20100,10 @@ define void @s_shuffle_v2i64_v8i64__11_5() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -20124,10 +20129,10 @@ define void @s_shuffle_v2i64_v8i64__11_5() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -20177,10 +20182,10 @@ define void @s_shuffle_v2i64_v8i64__12_5() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -20206,10 +20211,10 @@ define void @s_shuffle_v2i64_v8i64__12_5() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -20259,10 +20264,10 @@ define void @s_shuffle_v2i64_v8i64__13_5() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -20288,10 +20293,10 @@ define void @s_shuffle_v2i64_v8i64__13_5() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -20341,10 +20346,10 @@ define void @s_shuffle_v2i64_v8i64__14_5() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -20370,10 +20375,10 @@ define void @s_shuffle_v2i64_v8i64__14_5() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -20939,18 +20944,19 @@ define void @s_shuffle_v2i64_v8i64__9_6() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ;;#ASMSTART
+; GFX942-NEXT: ; def s[0:15]
+; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s18
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s19
+; GFX942-NEXT: s_mov_b32 s10, s12
+; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -21113,18 +21119,19 @@ define void @s_shuffle_v2i64_v8i64__11_6() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ;;#ASMSTART
+; GFX942-NEXT: ; def s[0:15]
+; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s22
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s23
+; GFX942-NEXT: s_mov_b32 s10, s12
+; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -21337,18 +21344,19 @@ define void @s_shuffle_v2i64_v8i64__13_6() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
-; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_mov_b32 s10, s12
-; GFX942-NEXT: s_mov_b32 s11, s13
+; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ;;#ASMSTART
+; GFX942-NEXT: ; def s[0:15]
+; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s26
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s27
+; GFX942-NEXT: s_mov_b32 s10, s12
+; GFX942-NEXT: s_mov_b32 s11, s13
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
; GFX942-NEXT: ;;#ASMEND
@@ -21455,11 +21463,11 @@ define void @s_shuffle_v2i64_v8i64__14_6() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
@@ -21924,10 +21932,10 @@ define void @s_shuffle_v2i64_v8i64__9_7() {
; GFX900-NEXT: v_writelane_b32 v0, s48, 4
; GFX900-NEXT: v_writelane_b32 v0, s49, 5
; GFX900-NEXT: v_writelane_b32 v0, s50, 6
+; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[36:51]
; GFX900-NEXT: ;;#ASMEND
@@ -21965,10 +21973,10 @@ define void @s_shuffle_v2i64_v8i64__9_7() {
; GFX90A-NEXT: v_writelane_b32 v0, s48, 4
; GFX90A-NEXT: v_writelane_b32 v0, s49, 5
; GFX90A-NEXT: v_writelane_b32 v0, s50, 6
+; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[36:51]
; GFX90A-NEXT: ;;#ASMEND
@@ -22000,11 +22008,11 @@ define void @s_shuffle_v2i64_v8i64__9_7() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
@@ -22099,10 +22107,10 @@ define void @s_shuffle_v2i64_v8i64__11_7() {
; GFX900-NEXT: v_writelane_b32 v0, s48, 4
; GFX900-NEXT: v_writelane_b32 v0, s49, 5
; GFX900-NEXT: v_writelane_b32 v0, s50, 6
+; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[36:51]
; GFX900-NEXT: ;;#ASMEND
@@ -22140,10 +22148,10 @@ define void @s_shuffle_v2i64_v8i64__11_7() {
; GFX90A-NEXT: v_writelane_b32 v0, s48, 4
; GFX90A-NEXT: v_writelane_b32 v0, s49, 5
; GFX90A-NEXT: v_writelane_b32 v0, s50, 6
+; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[36:51]
; GFX90A-NEXT: ;;#ASMEND
@@ -22175,11 +22183,11 @@ define void @s_shuffle_v2i64_v8i64__11_7() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
@@ -22324,10 +22332,10 @@ define void @s_shuffle_v2i64_v8i64__13_7() {
; GFX900-NEXT: v_writelane_b32 v0, s48, 4
; GFX900-NEXT: v_writelane_b32 v0, s49, 5
; GFX900-NEXT: v_writelane_b32 v0, s50, 6
+; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[36:51]
; GFX900-NEXT: ;;#ASMEND
@@ -22365,10 +22373,10 @@ define void @s_shuffle_v2i64_v8i64__13_7() {
; GFX90A-NEXT: v_writelane_b32 v0, s48, 4
; GFX90A-NEXT: v_writelane_b32 v0, s49, 5
; GFX90A-NEXT: v_writelane_b32 v0, s50, 6
+; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[36:51]
; GFX90A-NEXT: ;;#ASMEND
@@ -22400,11 +22408,11 @@ define void @s_shuffle_v2i64_v8i64__13_7() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
@@ -22519,11 +22527,11 @@ define void @s_shuffle_v2i64_v8i64__14_7() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
@@ -23522,10 +23530,10 @@ define void @s_shuffle_v2i64_v8i64__4_9() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -23551,10 +23559,10 @@ define void @s_shuffle_v2i64_v8i64__4_9() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -23700,10 +23708,10 @@ define void @s_shuffle_v2i64_v8i64__6_9() {
; GFX900-NEXT: v_writelane_b32 v0, s48, 4
; GFX900-NEXT: v_writelane_b32 v0, s49, 5
; GFX900-NEXT: v_writelane_b32 v0, s50, 6
+; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[36:51]
; GFX900-NEXT: ;;#ASMEND
@@ -23741,10 +23749,10 @@ define void @s_shuffle_v2i64_v8i64__6_9() {
; GFX90A-NEXT: v_writelane_b32 v0, s48, 4
; GFX90A-NEXT: v_writelane_b32 v0, s49, 5
; GFX90A-NEXT: v_writelane_b32 v0, s50, 6
+; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[36:51]
; GFX90A-NEXT: ;;#ASMEND
@@ -23776,11 +23784,11 @@ define void @s_shuffle_v2i64_v8i64__6_9() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
@@ -24374,10 +24382,10 @@ define void @s_shuffle_v2i64_v8i64__4_10() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -24403,10 +24411,10 @@ define void @s_shuffle_v2i64_v8i64__4_10() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -24456,10 +24464,10 @@ define void @s_shuffle_v2i64_v8i64__5_10() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -24485,10 +24493,10 @@ define void @s_shuffle_v2i64_v8i64__5_10() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -24545,10 +24553,10 @@ define void @s_shuffle_v2i64_v8i64__6_10() {
; GFX900-NEXT: v_writelane_b32 v0, s48, 4
; GFX900-NEXT: v_writelane_b32 v0, s49, 5
; GFX900-NEXT: v_writelane_b32 v0, s50, 6
+; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[36:51]
; GFX900-NEXT: ;;#ASMEND
@@ -24586,10 +24594,10 @@ define void @s_shuffle_v2i64_v8i64__6_10() {
; GFX90A-NEXT: v_writelane_b32 v0, s48, 4
; GFX90A-NEXT: v_writelane_b32 v0, s49, 5
; GFX90A-NEXT: v_writelane_b32 v0, s50, 6
+; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[36:51]
; GFX90A-NEXT: ;;#ASMEND
@@ -24621,11 +24629,11 @@ define void @s_shuffle_v2i64_v8i64__6_10() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
@@ -24740,17 +24748,18 @@ define void @s_shuffle_v2i64_v8i64__7_10() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
+; GFX942-NEXT: ;;#ASMSTART
+; GFX942-NEXT: ; def s[16:31]
+; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s14
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s15
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[16:31]
-; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s10, s20
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s11, s21
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -25419,10 +25428,10 @@ define void @s_shuffle_v2i64_v8i64__4_11() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -25448,10 +25457,10 @@ define void @s_shuffle_v2i64_v8i64__4_11() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -25563,10 +25572,10 @@ define void @s_shuffle_v2i64_v8i64__6_11() {
; GFX900-NEXT: v_writelane_b32 v0, s48, 4
; GFX900-NEXT: v_writelane_b32 v0, s49, 5
; GFX900-NEXT: v_writelane_b32 v0, s50, 6
+; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[36:51]
; GFX900-NEXT: ;;#ASMEND
@@ -25604,10 +25613,10 @@ define void @s_shuffle_v2i64_v8i64__6_11() {
; GFX90A-NEXT: v_writelane_b32 v0, s48, 4
; GFX90A-NEXT: v_writelane_b32 v0, s49, 5
; GFX90A-NEXT: v_writelane_b32 v0, s50, 6
+; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[36:51]
; GFX90A-NEXT: ;;#ASMEND
@@ -25639,11 +25648,11 @@ define void @s_shuffle_v2i64_v8i64__6_11() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
@@ -26237,10 +26246,10 @@ define void @s_shuffle_v2i64_v8i64__4_12() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -26266,10 +26275,10 @@ define void @s_shuffle_v2i64_v8i64__4_12() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -26319,10 +26328,10 @@ define void @s_shuffle_v2i64_v8i64__5_12() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -26348,10 +26357,10 @@ define void @s_shuffle_v2i64_v8i64__5_12() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -26408,10 +26417,10 @@ define void @s_shuffle_v2i64_v8i64__6_12() {
; GFX900-NEXT: v_writelane_b32 v0, s48, 4
; GFX900-NEXT: v_writelane_b32 v0, s49, 5
; GFX900-NEXT: v_writelane_b32 v0, s50, 6
+; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[36:51]
; GFX900-NEXT: ;;#ASMEND
@@ -26449,10 +26458,10 @@ define void @s_shuffle_v2i64_v8i64__6_12() {
; GFX90A-NEXT: v_writelane_b32 v0, s48, 4
; GFX90A-NEXT: v_writelane_b32 v0, s49, 5
; GFX90A-NEXT: v_writelane_b32 v0, s50, 6
+; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[36:51]
; GFX90A-NEXT: ;;#ASMEND
@@ -26484,11 +26493,11 @@ define void @s_shuffle_v2i64_v8i64__6_12() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
@@ -26603,17 +26612,18 @@ define void @s_shuffle_v2i64_v8i64__7_12() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
+; GFX942-NEXT: ;;#ASMSTART
+; GFX942-NEXT: ; def s[16:31]
+; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s14
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s15
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[16:31]
-; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s10, s24
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s11, s25
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -26984,14 +26994,14 @@ define void @s_shuffle_v2i64_v8i64__1_13() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
-; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ;;#ASMSTART
+; GFX942-NEXT: ; def s[0:15]
+; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s18
; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s19
@@ -27135,10 +27145,10 @@ define void @s_shuffle_v2i64_v8i64__4_13() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -27164,10 +27174,10 @@ define void @s_shuffle_v2i64_v8i64__4_13() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -27217,10 +27227,10 @@ define void @s_shuffle_v2i64_v8i64__5_13() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -27246,10 +27256,10 @@ define void @s_shuffle_v2i64_v8i64__5_13() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -27305,10 +27315,10 @@ define void @s_shuffle_v2i64_v8i64__6_13() {
; GFX900-NEXT: v_writelane_b32 v0, s48, 4
; GFX900-NEXT: v_writelane_b32 v0, s49, 5
; GFX900-NEXT: v_writelane_b32 v0, s50, 6
+; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[36:51]
; GFX900-NEXT: ;;#ASMEND
@@ -27346,10 +27356,10 @@ define void @s_shuffle_v2i64_v8i64__6_13() {
; GFX90A-NEXT: v_writelane_b32 v0, s48, 4
; GFX90A-NEXT: v_writelane_b32 v0, s49, 5
; GFX90A-NEXT: v_writelane_b32 v0, s50, 6
+; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[36:51]
; GFX90A-NEXT: ;;#ASMEND
@@ -27381,11 +27391,11 @@ define void @s_shuffle_v2i64_v8i64__6_13() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
@@ -28093,10 +28103,10 @@ define void @s_shuffle_v2i64_v8i64__4_14() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -28122,10 +28132,10 @@ define void @s_shuffle_v2i64_v8i64__4_14() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -28175,10 +28185,10 @@ define void @s_shuffle_v2i64_v8i64__5_14() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -28204,10 +28214,10 @@ define void @s_shuffle_v2i64_v8i64__5_14() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -28264,10 +28274,10 @@ define void @s_shuffle_v2i64_v8i64__6_14() {
; GFX900-NEXT: v_writelane_b32 v0, s48, 4
; GFX900-NEXT: v_writelane_b32 v0, s49, 5
; GFX900-NEXT: v_writelane_b32 v0, s50, 6
+; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[36:51]
; GFX900-NEXT: ;;#ASMEND
@@ -28305,10 +28315,10 @@ define void @s_shuffle_v2i64_v8i64__6_14() {
; GFX90A-NEXT: v_writelane_b32 v0, s48, 4
; GFX90A-NEXT: v_writelane_b32 v0, s49, 5
; GFX90A-NEXT: v_writelane_b32 v0, s50, 6
+; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[36:51]
; GFX90A-NEXT: ;;#ASMEND
@@ -28340,11 +28350,11 @@ define void @s_shuffle_v2i64_v8i64__6_14() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
@@ -28459,17 +28469,18 @@ define void @s_shuffle_v2i64_v8i64__7_14() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
+; GFX942-NEXT: ;;#ASMSTART
+; GFX942-NEXT: ; def s[16:31]
+; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s8, s14
+; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s9, s15
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[16:31]
-; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s10, s28
-; GFX942-NEXT: v_readlane_b32 s30, v0, 0
; GFX942-NEXT: s_mov_b32 s11, s29
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; use s[8:11]
@@ -29075,10 +29086,10 @@ define void @s_shuffle_v2i64_v8i64__4_15() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -29104,10 +29115,10 @@ define void @s_shuffle_v2i64_v8i64__4_15() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -29157,10 +29168,10 @@ define void @s_shuffle_v2i64_v8i64__5_15() {
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX900-NEXT: s_mov_b64 exec, s[4:5]
; GFX900-NEXT: v_writelane_b32 v0, s30, 0
+; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s31, 1
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[16:31]
; GFX900-NEXT: ;;#ASMEND
@@ -29186,10 +29197,10 @@ define void @s_shuffle_v2i64_v8i64__5_15() {
; GFX90A-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[4:5]
; GFX90A-NEXT: v_writelane_b32 v0, s30, 0
+; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s31, 1
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[16:31]
; GFX90A-NEXT: ;;#ASMEND
@@ -29247,10 +29258,10 @@ define void @s_shuffle_v2i64_v8i64__6_15() {
; GFX900-NEXT: v_writelane_b32 v0, s48, 4
; GFX900-NEXT: v_writelane_b32 v0, s49, 5
; GFX900-NEXT: v_writelane_b32 v0, s50, 6
+; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[4:19]
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: v_writelane_b32 v0, s51, 7
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def s[36:51]
; GFX900-NEXT: ;;#ASMEND
@@ -29288,10 +29299,10 @@ define void @s_shuffle_v2i64_v8i64__6_15() {
; GFX90A-NEXT: v_writelane_b32 v0, s48, 4
; GFX90A-NEXT: v_writelane_b32 v0, s49, 5
; GFX90A-NEXT: v_writelane_b32 v0, s50, 6
+; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[4:19]
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: v_writelane_b32 v0, s51, 7
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s[36:51]
; GFX90A-NEXT: ;;#ASMEND
@@ -29323,11 +29334,11 @@ define void @s_shuffle_v2i64_v8i64__6_15() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[0:15]
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
@@ -29442,14 +29453,14 @@ define void @s_shuffle_v2i64_v8i64__7_15() {
; GFX942-NEXT: scratch_store_dword off, v0, s32 ; 4-byte Folded Spill
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: v_writelane_b32 v0, s30, 0
-; GFX942-NEXT: ;;#ASMSTART
-; GFX942-NEXT: ; def s[0:15]
-; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_writelane_b32 v0, s31, 1
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def s[16:31]
; GFX942-NEXT: ;;#ASMEND
+; GFX942-NEXT: ;;#ASMSTART
+; GFX942-NEXT: ; def s[0:15]
+; GFX942-NEXT: ;;#ASMEND
; GFX942-NEXT: s_mov_b32 s28, s14
; GFX942-NEXT: s_mov_b32 s29, s15
; GFX942-NEXT: s_mov_b64 s[8:9], s[28:29]
diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
index ea67593d72761..9ebf4f57ed7d3 100644
--- a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
@@ -28,6 +28,7 @@ body: |
; SGPR_SPILLED-NEXT: {{ $}}
; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR $sgpr30, 0, $vgpr62, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 1, $vgpr62, implicit killed $sgpr30_sgpr31
+ ; SGPR_SPILLED-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr62, 0, 32, $vgpr62, 1, 32
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr32, 0, [[DEF]]
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr0, 1, [[DEF]], implicit-def $sgpr0_sgpr1, implicit $sgpr0_sgpr1
@@ -93,6 +94,7 @@ body: |
; SGPR_SPILLED-NEXT: {{ $}}
; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR $sgpr30, 0, $vgpr62, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 1, $vgpr62, implicit killed $sgpr30_sgpr31
+ ; SGPR_SPILLED-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr62, 0, 32, $vgpr62, 1, 32
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr32, 0, [[DEF]]
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr2, 1, [[DEF]], implicit-def $sgpr2_sgpr3, implicit $sgpr2_sgpr3
@@ -156,6 +158,7 @@ body: |
; SGPR_SPILLED-NEXT: {{ $}}
; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR $sgpr30, 0, $vgpr62, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31
; SGPR_SPILLED-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR killed $sgpr31, 1, $vgpr62, implicit killed $sgpr30_sgpr31
+ ; SGPR_SPILLED-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr62, 0, 32, $vgpr62, 1, 32
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr32, 0, [[DEF]]
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr0, 1, [[DEF]]
diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
index 2de7d86223eb2..2f769d94f174d 100644
--- a/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
@@ -2,9 +2,14 @@
# CHECK-LABEL: name: empty_entry_block
# CHECK: SI_SPILL_S32_TO_VGPR
+# CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers
# CHECK-NEXT: SI_SPILL_S32_TO_VGPR
+# CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers
# CHECK-NEXT: SI_SPILL_S32_TO_VGPR
+# CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers
# CHECK-NEXT: SI_SPILL_S32_TO_VGPR
+# CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers
+
# CHECK: SI_RESTORE_S32_FROM_VGPR
# CHECK-NEXT: SI_RESTORE_S32_FROM_VGPR
# CHECK-NEXT: SI_RESTORE_S32_FROM_VGPR
diff --git a/llvm/test/CodeGen/AMDGPU/sibling-call.ll b/llvm/test/CodeGen/AMDGPU/sibling-call.ll
index d4b53e9d338f8..98048e7ace538 100644
--- a/llvm/test/CodeGen/AMDGPU/sibling-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/sibling-call.ll
@@ -231,14 +231,14 @@ define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, pt
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[6:7]
-; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s33
; GCN-NEXT: v_writelane_b32 v40, s4, 2
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
+; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s33
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, i32_fastcc_i32_byval_i32 at rel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, i32_fastcc_i32_byval_i32 at rel32@hi+12
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
@@ -382,14 +382,15 @@ define fastcc i32 @no_sibling_call_callee_more_stack_space(i32 %a, i32 %b) #1 {
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[6:7]
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s4, 2
+; GCN-NEXT: v_writelane_b32 v40, s30, 0
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, i32_fastcc_i32_i32_a32i32 at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, i32_fastcc_i32_i32_a32i32 at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GCN-NEXT: v_mov_b32_e32 v2, 0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:4
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
@@ -422,7 +423,6 @@ define fastcc i32 @no_sibling_call_callee_more_stack_space(i32 %a, i32 %b) #1 {
; GCN-NEXT: v_mov_b32_e32 v28, 0
; GCN-NEXT: v_mov_b32_e32 v29, 0
; GCN-NEXT: v_mov_b32_e32 v30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GCN-NEXT: v_readlane_b32 s30, v40, 0
@@ -450,16 +450,16 @@ define fastcc i32 @sibling_call_i32_fastcc_i32_i32_other_call(i32 %a, i32 %b, i3
; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[6:7]
-; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v42, s4, 2
+; GCN-NEXT: s_addk_i32 s32, 0x400
+; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GCN-NEXT: v_writelane_b32 v42, s30, 0
+; GCN-NEXT: v_writelane_b32 v42, s31, 1
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, i32_fastcc_i32_i32 at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, i32_fastcc_i32_i32 at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
-; GCN-NEXT: v_writelane_b32 v42, s30, 0
-; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
-; GCN-NEXT: v_writelane_b32 v42, s31, 1
; GCN-NEXT: v_mov_b32_e32 v40, v1
; GCN-NEXT: v_mov_b32_e32 v41, v0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
@@ -603,6 +603,7 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; FIJI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; FIJI-NEXT: s_mov_b64 exec, s[18:19]
; FIJI-NEXT: v_writelane_b32 v40, s16, 18
+; FIJI-NEXT: s_addk_i32 s32, 0x400
; FIJI-NEXT: v_writelane_b32 v40, s34, 0
; FIJI-NEXT: v_writelane_b32 v40, s35, 1
; FIJI-NEXT: v_writelane_b32 v40, s36, 2
@@ -620,6 +621,7 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; FIJI-NEXT: v_writelane_b32 v40, s64, 14
; FIJI-NEXT: v_writelane_b32 v40, s65, 15
; FIJI-NEXT: v_writelane_b32 v40, s30, 16
+; FIJI-NEXT: v_writelane_b32 v40, s31, 17
; FIJI-NEXT: s_mov_b32 s50, s15
; FIJI-NEXT: s_mov_b32 s51, s14
; FIJI-NEXT: s_mov_b32 s52, s13
@@ -630,8 +632,6 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; FIJI-NEXT: s_mov_b64 s[48:49], s[4:5]
; FIJI-NEXT: v_add_u32_e32 v3, vcc, v3, v4
; FIJI-NEXT: s_mov_b64 s[54:55], exec
-; FIJI-NEXT: s_addk_i32 s32, 0x400
-; FIJI-NEXT: v_writelane_b32 v40, s31, 17
; FIJI-NEXT: .LBB18_1: ; =>This Inner Loop Header: Depth=1
; FIJI-NEXT: v_readfirstlane_b32 s16, v0
; FIJI-NEXT: v_readfirstlane_b32 s17, v1
@@ -694,6 +694,7 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; HAWAII-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; HAWAII-NEXT: s_mov_b64 exec, s[18:19]
; HAWAII-NEXT: v_writelane_b32 v40, s16, 18
+; HAWAII-NEXT: s_addk_i32 s32, 0x400
; HAWAII-NEXT: v_writelane_b32 v40, s34, 0
; HAWAII-NEXT: v_writelane_b32 v40, s35, 1
; HAWAII-NEXT: v_writelane_b32 v40, s36, 2
@@ -711,6 +712,7 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; HAWAII-NEXT: v_writelane_b32 v40, s64, 14
; HAWAII-NEXT: v_writelane_b32 v40, s65, 15
; HAWAII-NEXT: v_writelane_b32 v40, s30, 16
+; HAWAII-NEXT: v_writelane_b32 v40, s31, 17
; HAWAII-NEXT: s_mov_b32 s50, s15
; HAWAII-NEXT: s_mov_b32 s51, s14
; HAWAII-NEXT: s_mov_b32 s52, s13
@@ -721,8 +723,6 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; HAWAII-NEXT: s_mov_b64 s[48:49], s[4:5]
; HAWAII-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; HAWAII-NEXT: s_mov_b64 s[54:55], exec
-; HAWAII-NEXT: s_addk_i32 s32, 0x400
-; HAWAII-NEXT: v_writelane_b32 v40, s31, 17
; HAWAII-NEXT: .LBB18_1: ; =>This Inner Loop Header: Depth=1
; HAWAII-NEXT: v_readfirstlane_b32 s16, v0
; HAWAII-NEXT: v_readfirstlane_b32 s17, v1
@@ -785,6 +785,7 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-NEXT: v_writelane_b32 v40, s16, 18
+; GFX9-NEXT: s_addk_i32 s32, 0x400
; GFX9-NEXT: v_writelane_b32 v40, s34, 0
; GFX9-NEXT: v_writelane_b32 v40, s35, 1
; GFX9-NEXT: v_writelane_b32 v40, s36, 2
@@ -802,6 +803,7 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; GFX9-NEXT: v_writelane_b32 v40, s64, 14
; GFX9-NEXT: v_writelane_b32 v40, s65, 15
; GFX9-NEXT: v_writelane_b32 v40, s30, 16
+; GFX9-NEXT: v_writelane_b32 v40, s31, 17
; GFX9-NEXT: s_mov_b32 s50, s15
; GFX9-NEXT: s_mov_b32 s51, s14
; GFX9-NEXT: s_mov_b32 s52, s13
@@ -812,8 +814,6 @@ define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr
; GFX9-NEXT: s_mov_b64 s[48:49], s[4:5]
; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
; GFX9-NEXT: s_mov_b64 s[54:55], exec
-; GFX9-NEXT: s_addk_i32 s32, 0x400
-; GFX9-NEXT: v_writelane_b32 v40, s31, 17
; GFX9-NEXT: .LBB18_1: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_readfirstlane_b32 s16, v0
; GFX9-NEXT: v_readfirstlane_b32 s17, v1
diff --git a/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
index 24c631ce5e15f..7b3402494f39f 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
@@ -16,10 +16,15 @@ body: |
; CHECK: liveins: $sgpr50, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $vgpr63, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr50, 0, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr50, $vgpr63, 0, 32
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr52, 1, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr52, $vgpr63, 1, 32
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr53, 2, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr53, $vgpr63, 2, 32
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr54, 3, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr54, $vgpr63, 3, 32
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr55, 4, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr55, $vgpr63, 4, 32
; CHECK-NEXT: S_NOP 0, implicit $sgpr50
; CHECK-NEXT: $sgpr50 = S_MOV_B32 0
; CHECK-NEXT: S_NOP 0, implicit $sgpr52
diff --git a/llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir b/llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
index 85a615c3d8ae8..866ce8a0c0293 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
@@ -13,6 +13,7 @@ body: |
; CHECK: liveins: $sgpr50, $vgpr63
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr50, 0, $vgpr63
+ ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr50, $vgpr63, 0, 32
; CHECK-NEXT: S_NOP 0, implicit $sgpr50
; CHECK-NEXT: $sgpr50 = S_MOV_B32 0
S_NOP 0, implicit $sgpr50
diff --git a/llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir b/llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
index fa3fd3bc6da5b..b0be5676e26a2 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
@@ -56,21 +56,37 @@ body: |
; GCN: liveins: $sgpr10, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $vgpr63, $sgpr30_sgpr31, $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71, $sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79, $sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87, $sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95
; GCN-NEXT: {{ $}}
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr64, 0, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr64, $vgpr63, 0, 32
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr65, 1, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr65, $vgpr63, 1, 32
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr66, 2, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr66, $vgpr63, 2, 32
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr67, 3, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr67, $vgpr63, 3, 32
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr68, 4, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr68, $vgpr63, 4, 32
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr69, 5, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr69, $vgpr63, 5, 32
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr70, 6, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr70, $vgpr63, 6, 32
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr71, 7, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr71, $vgpr63, 7, 32
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr80, 8, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr80, $vgpr63, 8, 32
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr81, 9, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr81, $vgpr63, 9, 32
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr82, 10, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr82, $vgpr63, 10, 32
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr83, 11, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr83, $vgpr63, 11, 32
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr84, 12, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr84, $vgpr63, 12, 32
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr85, 13, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr85, $vgpr63, 13, 32
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr86, 14, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr86, $vgpr63, 14, 32
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr87, 15, $vgpr63
+ ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr87, $vgpr63, 15, 32
; GCN-NEXT: S_NOP 0
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, [[DEF]]
diff --git a/llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll b/llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
index bfadfd860edf6..94e5f936a35fd 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
@@ -14,15 +14,15 @@ define i32 @non_entry_func(i32 %x) {
; CHECK-NEXT: scratch_store_b32 off, v2, s32 offset:100 ; 4-byte Folded Spill
; CHECK-NEXT: s_wait_alu 0xfffe
; CHECK-NEXT: s_mov_b32 exec_lo, s0
-; CHECK-NEXT: v_writelane_b32 v2, s48, 0
; CHECK-NEXT: s_mov_b32 m0, 0x110003
-; CHECK-NEXT: v_mov_b32_e32 v1, v0
; CHECK-NEXT: ; transferring at most v40 v41 v56 v60 ; 128-byte Folded Spill
; CHECK-NEXT: scratch_store_block off, v[40:71], s32 offset:4
; CHECK-NEXT: s_mov_b32 m0, 1
-; CHECK-NEXT: v_writelane_b32 v2, s49, 1
; CHECK-NEXT: ; transferring at most v120 ; 128-byte Folded Spill
; CHECK-NEXT: scratch_store_block off, v[120:151], s32
+; CHECK-NEXT: v_writelane_b32 v2, s48, 0
+; CHECK-NEXT: v_mov_b32_e32 v1, v0
+; CHECK-NEXT: v_writelane_b32 v2, s49, 1
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: s_nop
; CHECK-NEXT: ;;#ASMEND
diff --git a/llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll b/llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
index e962d1bad9779..1184d1a94c3dc 100644
--- a/llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
@@ -142,8 +142,8 @@ define void @spill_more_than_wavesize_csr_sgprs_with_stack_object() {
; CHECK-NEXT: v_writelane_b32 v1, s99, 32
; CHECK-NEXT: v_writelane_b32 v1, s100, 33
; CHECK-NEXT: v_writelane_b32 v1, s101, 34
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: v_writelane_b32 v1, s102, 35
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: ;;#ASMSTART
diff --git a/llvm/test/CodeGen/AMDGPU/stack-realign.ll b/llvm/test/CodeGen/AMDGPU/stack-realign.ll
index 1c9ee01807a5f..c975f3a9ba946 100644
--- a/llvm/test/CodeGen/AMDGPU/stack-realign.ll
+++ b/llvm/test/CodeGen/AMDGPU/stack-realign.ll
@@ -291,20 +291,20 @@ define void @func_call_align1024_bp_gets_vgpr_spill(<32 x i32> %a, i32 %b) #0 {
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:1028 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, s[18:19]
; GCN-NEXT: v_writelane_b32 v40, s16, 2
-; GCN-NEXT: v_mov_b32_e32 v32, 0
; GCN-NEXT: v_writelane_b32 v40, s34, 3
+; GCN-NEXT: v_writelane_b32 v40, s30, 0
; GCN-NEXT: s_mov_b32 s34, s32
+; GCN-NEXT: s_add_i32 s32, s32, 0x30000
+; GCN-NEXT: v_writelane_b32 v40, s31, 1
+; GCN-NEXT: v_mov_b32_e32 v32, 0
; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:1024
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s34
; GCN-NEXT: buffer_load_dword v33, off, s[0:3], s34 offset:4
-; GCN-NEXT: s_add_i32 s32, s32, 0x30000
; GCN-NEXT: s_getpc_b64 s[16:17]
; GCN-NEXT: s_add_u32 s16, s16, extern_func at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s17, s17, extern_func at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: v_writelane_b32 v40, s31, 1
; GCN-NEXT: s_waitcnt vmcnt(1)
; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s32
; GCN-NEXT: s_waitcnt vmcnt(1)
@@ -453,7 +453,7 @@ define void @no_free_regs_spill_bp_to_memory(<32 x i32> %a, i32 %b) #5 {
; GCN-NEXT: v_writelane_b32 v39, s4, 32
; GCN-NEXT: v_writelane_b32 v39, s34, 33
; GCN-NEXT: s_mov_b32 s34, s32
-; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s34 offset:4
+; GCN-NEXT: s_addk_i32 s32, 0x6000
; GCN-NEXT: v_writelane_b32 v39, s39, 0
; GCN-NEXT: v_writelane_b32 v39, s48, 1
; GCN-NEXT: v_writelane_b32 v39, s49, 2
@@ -485,8 +485,8 @@ define void @no_free_regs_spill_bp_to_memory(<32 x i32> %a, i32 %b) #5 {
; GCN-NEXT: v_writelane_b32 v39, s99, 28
; GCN-NEXT: v_writelane_b32 v39, s100, 29
; GCN-NEXT: v_writelane_b32 v39, s101, 30
-; GCN-NEXT: s_addk_i32 s32, 0x6000
; GCN-NEXT: v_writelane_b32 v39, s102, 31
+; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s34 offset:4
; GCN-NEXT: s_mov_b32 s32, s34
; GCN-NEXT: v_readlane_b32 s34, v39, 33
; GCN-NEXT: s_waitcnt vmcnt(0)
@@ -576,7 +576,7 @@ define void @spill_bp_to_memory_scratch_reg_needed_mubuf_offset(<32 x i32> %a, i
; GCN-NEXT: v_writelane_b32 v39, s4, 32
; GCN-NEXT: v_writelane_b32 v39, s34, 33
; GCN-NEXT: s_mov_b32 s34, s32
-; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s34 offset:4
+; GCN-NEXT: s_add_i32 s32, s32, 0x46000
; GCN-NEXT: v_writelane_b32 v39, s39, 0
; GCN-NEXT: v_writelane_b32 v39, s48, 1
; GCN-NEXT: v_writelane_b32 v39, s49, 2
@@ -608,9 +608,9 @@ define void @spill_bp_to_memory_scratch_reg_needed_mubuf_offset(<32 x i32> %a, i
; GCN-NEXT: v_writelane_b32 v39, s99, 28
; GCN-NEXT: v_writelane_b32 v39, s100, 29
; GCN-NEXT: v_writelane_b32 v39, s101, 30
-; GCN-NEXT: v_mov_b32_e32 v1, 0x1080
-; GCN-NEXT: s_add_i32 s32, s32, 0x46000
; GCN-NEXT: v_writelane_b32 v39, s102, 31
+; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s34 offset:4
+; GCN-NEXT: v_mov_b32_e32 v1, 0x1080
; GCN-NEXT: s_mov_b32 s32, s34
; GCN-NEXT: v_readlane_b32 s34, v39, 33
; GCN-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll b/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
index 06f1c08d1f04e..70bcb99e05777 100644
--- a/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
+++ b/llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
@@ -1270,13 +1270,13 @@ define void @func_stacksave_stackrestore_call_with_stack_objects() {
; WAVE32-OPT-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill
; WAVE32-OPT-NEXT: s_mov_b32 exec_lo, s16
; WAVE32-OPT-NEXT: v_writelane_b32 v32, s30, 0
+; WAVE32-OPT-NEXT: s_addk_i32 s32, 0x1200
+; WAVE32-OPT-NEXT: v_writelane_b32 v32, s31, 1
; WAVE32-OPT-NEXT: v_mov_b32_e32 v0, 42
; WAVE32-OPT-NEXT: v_mov_b32_e32 v1, 17
-; WAVE32-OPT-NEXT: s_addk_i32 s32, 0x1200
-; WAVE32-OPT-NEXT: s_mov_b32 s17, stack_passed_argument at abs32@hi
; WAVE32-OPT-NEXT: s_mov_b32 s18, s32
+; WAVE32-OPT-NEXT: s_mov_b32 s17, stack_passed_argument at abs32@hi
; WAVE32-OPT-NEXT: s_mov_b32 s16, stack_passed_argument at abs32@lo
-; WAVE32-OPT-NEXT: v_writelane_b32 v32, s31, 1
; WAVE32-OPT-NEXT: s_lshr_b32 s19, s18, 5
; WAVE32-OPT-NEXT: buffer_store_dword v0, off, s[0:3], s33
; WAVE32-OPT-NEXT: s_waitcnt_vscnt null, 0x0
@@ -1305,13 +1305,13 @@ define void @func_stacksave_stackrestore_call_with_stack_objects() {
; WAVE64-OPT-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:128 ; 4-byte Folded Spill
; WAVE64-OPT-NEXT: s_mov_b64 exec, s[16:17]
; WAVE64-OPT-NEXT: v_writelane_b32 v32, s30, 0
+; WAVE64-OPT-NEXT: s_addk_i32 s32, 0x2400
+; WAVE64-OPT-NEXT: v_writelane_b32 v32, s31, 1
; WAVE64-OPT-NEXT: v_mov_b32_e32 v0, 42
; WAVE64-OPT-NEXT: v_mov_b32_e32 v1, 17
-; WAVE64-OPT-NEXT: s_addk_i32 s32, 0x2400
-; WAVE64-OPT-NEXT: s_mov_b32 s17, stack_passed_argument at abs32@hi
; WAVE64-OPT-NEXT: s_mov_b32 s18, s32
+; WAVE64-OPT-NEXT: s_mov_b32 s17, stack_passed_argument at abs32@hi
; WAVE64-OPT-NEXT: s_mov_b32 s16, stack_passed_argument at abs32@lo
-; WAVE64-OPT-NEXT: v_writelane_b32 v32, s31, 1
; WAVE64-OPT-NEXT: s_lshr_b32 s19, s18, 6
; WAVE64-OPT-NEXT: buffer_store_dword v0, off, s[0:3], s33
; WAVE64-OPT-NEXT: s_waitcnt_vscnt null, 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll b/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
index 4232a09d9fc3a..e2e47285c081c 100644
--- a/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
+++ b/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
@@ -184,13 +184,13 @@ define void @outgoing_f16_arg(ptr %ptr) #0 {
; GFX7-NEXT: s_or_saveexec_b64 s[18:19], -1
; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[18:19]
-; GFX7-NEXT: flat_load_ushort v0, v[0:1]
; GFX7-NEXT: v_writelane_b32 v40, s16, 2
; GFX7-NEXT: v_writelane_b32 v40, s30, 0
-; GFX7-NEXT: s_mov_b32 s17, f16_user at abs32@hi
-; GFX7-NEXT: s_mov_b32 s16, f16_user at abs32@lo
; GFX7-NEXT: s_addk_i32 s32, 0x400
; GFX7-NEXT: v_writelane_b32 v40, s31, 1
+; GFX7-NEXT: flat_load_ushort v0, v[0:1]
+; GFX7-NEXT: s_mov_b32 s17, f16_user at abs32@hi
+; GFX7-NEXT: s_mov_b32 s16, f16_user at abs32@lo
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
@@ -218,13 +218,13 @@ define void @outgoing_v2f16_arg(ptr %ptr) #0 {
; GFX7-NEXT: s_or_saveexec_b64 s[18:19], -1
; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[18:19]
-; GFX7-NEXT: flat_load_dword v1, v[0:1]
; GFX7-NEXT: v_writelane_b32 v40, s16, 2
; GFX7-NEXT: v_writelane_b32 v40, s30, 0
-; GFX7-NEXT: s_mov_b32 s17, v2f16_user at abs32@hi
-; GFX7-NEXT: s_mov_b32 s16, v2f16_user at abs32@lo
; GFX7-NEXT: s_addk_i32 s32, 0x400
; GFX7-NEXT: v_writelane_b32 v40, s31, 1
+; GFX7-NEXT: flat_load_dword v1, v[0:1]
+; GFX7-NEXT: s_mov_b32 s17, v2f16_user at abs32@hi
+; GFX7-NEXT: s_mov_b32 s16, v2f16_user at abs32@lo
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v1
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
@@ -255,13 +255,13 @@ define void @outgoing_f16_return(ptr %ptr) #0 {
; GFX7-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[18:19]
; GFX7-NEXT: v_writelane_b32 v42, s16, 2
-; GFX7-NEXT: v_writelane_b32 v42, s30, 0
-; GFX7-NEXT: s_mov_b32 s17, f16_result at abs32@hi
-; GFX7-NEXT: s_mov_b32 s16, f16_result at abs32@lo
; GFX7-NEXT: s_addk_i32 s32, 0x400
; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX7-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX7-NEXT: v_writelane_b32 v42, s30, 0
; GFX7-NEXT: v_writelane_b32 v42, s31, 1
+; GFX7-NEXT: s_mov_b32 s17, f16_result at abs32@hi
+; GFX7-NEXT: s_mov_b32 s16, f16_result at abs32@lo
; GFX7-NEXT: v_mov_b32_e32 v41, v1
; GFX7-NEXT: v_mov_b32_e32 v40, v0
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
@@ -297,13 +297,13 @@ define void @outgoing_v2f16_return(ptr %ptr) #0 {
; GFX7-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[18:19]
; GFX7-NEXT: v_writelane_b32 v42, s16, 2
-; GFX7-NEXT: v_writelane_b32 v42, s30, 0
-; GFX7-NEXT: s_mov_b32 s17, v2f16_result at abs32@hi
-; GFX7-NEXT: s_mov_b32 s16, v2f16_result at abs32@lo
; GFX7-NEXT: s_addk_i32 s32, 0x400
; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX7-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX7-NEXT: v_writelane_b32 v42, s30, 0
; GFX7-NEXT: v_writelane_b32 v42, s31, 1
+; GFX7-NEXT: s_mov_b32 s17, v2f16_result at abs32@hi
+; GFX7-NEXT: s_mov_b32 s16, v2f16_result at abs32@lo
; GFX7-NEXT: v_mov_b32_e32 v41, v1
; GFX7-NEXT: v_mov_b32_e32 v40, v0
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
@@ -345,13 +345,13 @@ define void @outgoing_v4f16_return(ptr %ptr) #0 {
; GFX7-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[18:19]
; GFX7-NEXT: v_writelane_b32 v42, s16, 2
-; GFX7-NEXT: v_writelane_b32 v42, s30, 0
-; GFX7-NEXT: s_mov_b32 s17, v4f16_result at abs32@hi
-; GFX7-NEXT: s_mov_b32 s16, v4f16_result at abs32@lo
; GFX7-NEXT: s_addk_i32 s32, 0x400
; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX7-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX7-NEXT: v_writelane_b32 v42, s30, 0
; GFX7-NEXT: v_writelane_b32 v42, s31, 1
+; GFX7-NEXT: s_mov_b32 s17, v4f16_result at abs32@hi
+; GFX7-NEXT: s_mov_b32 s16, v4f16_result at abs32@lo
; GFX7-NEXT: v_mov_b32_e32 v41, v1
; GFX7-NEXT: v_mov_b32_e32 v40, v0
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
@@ -406,13 +406,13 @@ define void @outgoing_v8f16_return(ptr %ptr) #0 {
; GFX7-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX7-NEXT: s_mov_b64 exec, s[18:19]
; GFX7-NEXT: v_writelane_b32 v42, s16, 2
-; GFX7-NEXT: v_writelane_b32 v42, s30, 0
-; GFX7-NEXT: s_mov_b32 s17, v8f16_result at abs32@hi
-; GFX7-NEXT: s_mov_b32 s16, v8f16_result at abs32@lo
; GFX7-NEXT: s_addk_i32 s32, 0x400
; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX7-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX7-NEXT: v_writelane_b32 v42, s30, 0
; GFX7-NEXT: v_writelane_b32 v42, s31, 1
+; GFX7-NEXT: s_mov_b32 s17, v8f16_result at abs32@hi
+; GFX7-NEXT: s_mov_b32 s16, v8f16_result at abs32@lo
; GFX7-NEXT: v_mov_b32_e32 v41, v1
; GFX7-NEXT: v_mov_b32_e32 v40, v0
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
@@ -494,10 +494,10 @@ define half @call_split_type_used_outside_block_v8f16() #0 {
; GFX7-NEXT: s_mov_b64 exec, s[18:19]
; GFX7-NEXT: v_writelane_b32 v40, s16, 2
; GFX7-NEXT: v_writelane_b32 v40, s30, 0
-; GFX7-NEXT: s_mov_b32 s17, v8f16_result at abs32@hi
-; GFX7-NEXT: s_mov_b32 s16, v8f16_result at abs32@lo
; GFX7-NEXT: s_addk_i32 s32, 0x400
; GFX7-NEXT: v_writelane_b32 v40, s31, 1
+; GFX7-NEXT: s_mov_b32 s17, v8f16_result at abs32@hi
+; GFX7-NEXT: s_mov_b32 s16, v8f16_result at abs32@lo
; GFX7-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: v_cvt_f16_f32_e32 v7, v7
diff --git a/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll b/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
index 13cde61ff16a0..20443fd5574e7 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
+++ b/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
@@ -10,16 +10,16 @@ define void @test_load_zext() #0 {
; CHECK-NEXT: s_or_saveexec_b64 s[2:3], -1
; CHECK-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[2:3]
-; CHECK-NEXT: s_add_i32 s32, s32, 16
; CHECK-NEXT: v_writelane_b32 v40, s0, 2
+; CHECK-NEXT: v_writelane_b32 v40, s30, 0
+; CHECK-NEXT: s_add_i32 s32, s32, 16
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-NEXT: s_getpc_b64 s[0:1]
; CHECK-NEXT: s_add_u32 s0, s0, has_spgr_args at gotpcrel32@lo+4
; CHECK-NEXT: s_addc_u32 s1, s1, has_spgr_args at gotpcrel32@hi+12
; CHECK-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; CHECK-NEXT: v_writelane_b32 v40, s30, 0
; CHECK-NEXT: s_mov_b32 s0, DescriptorBuffer at abs32@lo
-; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_swappc_b64 s[30:31], s[2:3]
; CHECK-NEXT: v_readlane_b32 s30, v40, 0
diff --git a/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll b/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
index 07f9d64fe71fc..58efd1ae72ec1 100644
--- a/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
+++ b/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
@@ -13,14 +13,14 @@ define internal fastcc void @widget() #0 {
; GFX90A-NEXT: s_or_saveexec_b64 s[18:19], -1
; GFX90A-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX90A-NEXT: s_mov_b64 exec, s[18:19]
-; GFX90A-NEXT: s_addk_i32 s32, 0x400
; GFX90A-NEXT: v_writelane_b32 v40, s16, 2
+; GFX90A-NEXT: v_writelane_b32 v40, s30, 0
+; GFX90A-NEXT: s_addk_i32 s32, 0x400
+; GFX90A-NEXT: v_writelane_b32 v40, s31, 1
; GFX90A-NEXT: s_getpc_b64 s[16:17]
; GFX90A-NEXT: s_add_u32 s16, s16, wobble at gotpcrel32@lo+4
; GFX90A-NEXT: s_addc_u32 s17, s17, wobble at gotpcrel32@hi+12
; GFX90A-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX90A-NEXT: v_writelane_b32 v40, s30, 0
-; GFX90A-NEXT: v_writelane_b32 v40, s31, 1
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_swappc_b64 s[30:31], s[16:17]
bb:
diff --git a/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll b/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll
index e5215fe1acdef..0c87ed574a1e6 100644
--- a/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll
+++ b/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll
@@ -646,25 +646,23 @@ define i32 @s_in_multiuse_A(i32 inreg %x, i32 inreg %y, i32 inreg %z, i32 inreg
; GCN-NEXT: s_or_saveexec_b32 s16, -1
; GCN-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b32 exec_lo, s16
+; GCN-NEXT: v_writelane_b32 v40, s2, 4
; GCN-NEXT: s_add_i32 s32, s32, 16
+; GCN-NEXT: v_writelane_b32 v40, s34, 0
+; GCN-NEXT: v_writelane_b32 v40, s35, 1
+; GCN-NEXT: v_writelane_b32 v40, s30, 2
+; GCN-NEXT: v_writelane_b32 v40, s31, 3
; GCN-NEXT: s_getpc_b64 s[16:17]
; GCN-NEXT: s_add_u32 s16, s16, use32 at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s17, s17, use32 at gotpcrel32@hi+12
-; GCN-NEXT: v_writelane_b32 v40, s2, 4
-; GCN-NEXT: s_load_b64 s[16:17], s[16:17], 0x0
; GCN-NEXT: s_xor_b32 s0, s0, s1
-; GCN-NEXT: v_writelane_b32 v40, s34, 0
-; GCN-NEXT: s_mov_b32 s34, s1
-; GCN-NEXT: v_writelane_b32 v40, s35, 1
+; GCN-NEXT: s_load_b64 s[16:17], s[16:17], 0x0
; GCN-NEXT: s_and_b32 s35, s0, s3
-; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GCN-NEXT: s_mov_b32 s34, s1
; GCN-NEXT: v_mov_b32_e32 v0, s35
-; GCN-NEXT: v_writelane_b32 v40, s30, 2
-; GCN-NEXT: v_writelane_b32 v40, s31, 3
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: s_xor_b32 s0, s35, s34
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_readlane_b32 s30, v40, 2
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_readlane_b32 s31, v40, 3
@@ -694,25 +692,23 @@ define i32 @s_in_multiuse_B(i32 inreg %x, i32 inreg %y, i32 inreg %z, i32 inreg
; GCN-NEXT: s_or_saveexec_b32 s16, -1
; GCN-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b32 exec_lo, s16
+; GCN-NEXT: v_writelane_b32 v40, s2, 4
; GCN-NEXT: s_add_i32 s32, s32, 16
+; GCN-NEXT: v_writelane_b32 v40, s34, 0
+; GCN-NEXT: v_writelane_b32 v40, s35, 1
+; GCN-NEXT: v_writelane_b32 v40, s30, 2
+; GCN-NEXT: v_writelane_b32 v40, s31, 3
; GCN-NEXT: s_getpc_b64 s[16:17]
; GCN-NEXT: s_add_u32 s16, s16, use32 at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s17, s17, use32 at gotpcrel32@hi+12
-; GCN-NEXT: v_writelane_b32 v40, s2, 4
-; GCN-NEXT: s_load_b64 s[16:17], s[16:17], 0x0
; GCN-NEXT: s_xor_b32 s0, s0, s1
-; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GCN-NEXT: s_load_b64 s[16:17], s[16:17], 0x0
; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_writelane_b32 v40, s34, 0
; GCN-NEXT: s_mov_b32 s34, s1
-; GCN-NEXT: v_writelane_b32 v40, s35, 1
; GCN-NEXT: s_and_b32 s35, s0, s3
-; GCN-NEXT: v_writelane_b32 v40, s30, 2
-; GCN-NEXT: v_writelane_b32 v40, s31, 3
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GCN-NEXT: s_xor_b32 s0, s35, s34
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT: v_readlane_b32 s30, v40, 2
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_readlane_b32 s31, v40, 3
diff --git a/llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll b/llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
index a81d9a458e23a..a82453ee23ee9 100644
--- a/llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
+++ b/llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
@@ -8,10 +8,6 @@ define void @eliminate_spill_after_mfma_rewrite(i32 %x, i32 %y, <4 x i32> %arg,
; CHECK-LABEL: eliminate_spill_after_mfma_rewrite:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: v_accvgpr_write_b32 a3, v5
-; CHECK-NEXT: v_accvgpr_write_b32 a2, v4
-; CHECK-NEXT: v_accvgpr_write_b32 a1, v3
-; CHECK-NEXT: v_accvgpr_write_b32 a0, v2
; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
@@ -60,6 +56,11 @@ define void @eliminate_spill_after_mfma_rewrite(i32 %x, i32 %y, <4 x i32> %arg,
; CHECK-NEXT: buffer_store_dword a61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword a62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword a63, off, s[0:3], s32 ; 4-byte Folded Spill
+; CHECK-NEXT: v_accvgpr_write_b32 a3, v5
+; CHECK-NEXT: v_accvgpr_write_b32 a2, v4
+; CHECK-NEXT: v_accvgpr_write_b32 a1, v3
+; CHECK-NEXT: v_accvgpr_write_b32 a0, v2
+; CHECK-NEXT: s_nop 1
; CHECK-NEXT: v_mfma_i32_4x4x4i8 a[0:3], v0, v1, a[0:3]
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; def v[32:63], v[0:31]
@@ -212,10 +213,6 @@ define void @eliminate_spill_after_mfma_rewrite_x2(i32 %x, i32 %y, <4 x i32> %ar
; CHECK-LABEL: eliminate_spill_after_mfma_rewrite_x2:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: v_accvgpr_write_b32 a3, v5
-; CHECK-NEXT: v_accvgpr_write_b32 a2, v4
-; CHECK-NEXT: v_accvgpr_write_b32 a1, v3
-; CHECK-NEXT: v_accvgpr_write_b32 a0, v2
; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
@@ -264,6 +261,11 @@ define void @eliminate_spill_after_mfma_rewrite_x2(i32 %x, i32 %y, <4 x i32> %ar
; CHECK-NEXT: buffer_store_dword a61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword a62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; CHECK-NEXT: buffer_store_dword a63, off, s[0:3], s32 ; 4-byte Folded Spill
+; CHECK-NEXT: v_accvgpr_write_b32 a3, v5
+; CHECK-NEXT: v_accvgpr_write_b32 a2, v4
+; CHECK-NEXT: v_accvgpr_write_b32 a1, v3
+; CHECK-NEXT: v_accvgpr_write_b32 a0, v2
+; CHECK-NEXT: s_nop 1
; CHECK-NEXT: v_mfma_i32_4x4x4i8 a[0:3], v0, v1, a[0:3]
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; def v[32:63], v[0:31]
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll b/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
index c902ac6173935..79cf7f49b6cd8 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
@@ -16,15 +16,19 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[6:7]
+; GFX9-NEXT: v_writelane_b32 v44, s4, 2
+; GFX9-NEXT: s_addk_i32 s32, 0x800
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX9-NEXT: v_writelane_b32 v44, s30, 0
+; GFX9-NEXT: v_writelane_b32 v44, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v36, v16
; GFX9-NEXT: v_mov_b32_e32 v35, v15
; GFX9-NEXT: v_mov_b32_e32 v34, v14
; GFX9-NEXT: v_mov_b32_e32 v33, v13
; GFX9-NEXT: v_mov_b32_e32 v32, v12
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: ;;#ASMSTART
@@ -34,14 +38,10 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX9-NEXT: ;;#ASMSTART
; GFX9-NEXT: ;;#ASMEND
; GFX9-NEXT: image_gather4_c_b_cl v[40:43], v[32:36], s[4:11], s[4:7] dmask:0x1
-; GFX9-NEXT: s_addk_i32 s32, 0x800
-; GFX9-NEXT: v_writelane_b32 v44, s4, 2
; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, extern_func at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, extern_func at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
-; GFX9-NEXT: v_writelane_b32 v44, s30, 0
-; GFX9-NEXT: v_writelane_b32 v44, s31, 1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v0, v40
@@ -72,15 +72,19 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX10-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s5
+; GFX10-NEXT: v_writelane_b32 v44, s4, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x400
+; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
+; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GFX10-NEXT: buffer_store_dword v43, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX10-NEXT: v_writelane_b32 v44, s30, 0
+; GFX10-NEXT: v_writelane_b32 v44, s31, 1
; GFX10-NEXT: v_mov_b32_e32 v36, v16
; GFX10-NEXT: v_mov_b32_e32 v35, v15
; GFX10-NEXT: v_mov_b32_e32 v34, v14
; GFX10-NEXT: v_mov_b32_e32 v33, v13
; GFX10-NEXT: v_mov_b32_e32 v32, v12
-; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
-; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GFX10-NEXT: buffer_store_dword v43, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: ;;#ASMSTART
@@ -90,14 +94,11 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: image_gather4_c_b_cl v[40:43], v[32:36], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
-; GFX10-NEXT: s_addk_i32 s32, 0x400
-; GFX10-NEXT: v_writelane_b32 v44, s4, 2
+; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_getpc_b64 s[4:5]
; GFX10-NEXT: s_add_u32 s4, s4, extern_func at gotpcrel32@lo+4
; GFX10-NEXT: s_addc_u32 s5, s5, extern_func at gotpcrel32@hi+12
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
-; GFX10-NEXT: v_writelane_b32 v44, s30, 0
-; GFX10-NEXT: v_writelane_b32 v44, s31, 1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX10-NEXT: v_mov_b32_e32 v0, v40
@@ -129,14 +130,21 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
-; GFX11-NEXT: v_dual_mov_b32 v36, v16 :: v_dual_mov_b32 v35, v15
-; GFX11-NEXT: v_dual_mov_b32 v34, v14 :: v_dual_mov_b32 v33, v13
-; GFX11-NEXT: v_mov_b32_e32 v32, v12
+; GFX11-NEXT: v_writelane_b32 v44, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 32
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s33 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s33
+; GFX11-NEXT: v_writelane_b32 v44, s30, 0
+; GFX11-NEXT: v_writelane_b32 v44, s31, 1
+; GFX11-NEXT: v_dual_mov_b32 v36, v16 :: v_dual_mov_b32 v35, v15
+; GFX11-NEXT: v_dual_mov_b32 v34, v14 :: v_dual_mov_b32 v33, v13
+; GFX11-NEXT: v_mov_b32_e32 v32, v12
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: ;;#ASMSTART
@@ -146,14 +154,10 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX11-NEXT: ;;#ASMSTART
; GFX11-NEXT: ;;#ASMEND
; GFX11-NEXT: image_gather4_c_b_cl v[40:43], v[32:36], s[0:7], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D
-; GFX11-NEXT: s_add_i32 s32, s32, 32
-; GFX11-NEXT: v_writelane_b32 v44, s0, 2
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, extern_func at gotpcrel32@lo+4
; GFX11-NEXT: s_addc_u32 s1, s1, extern_func at gotpcrel32@hi+12
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-NEXT: v_writelane_b32 v44, s30, 0
-; GFX11-NEXT: v_writelane_b32 v44, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: v_dual_mov_b32 v0, v40 :: v_dual_mov_b32 v1, v41
@@ -206,25 +210,25 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[6:7]
+; GFX9-NEXT: v_writelane_b32 v45, s4, 2
+; GFX9-NEXT: s_addk_i32 s32, 0x800
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX9-NEXT: v_writelane_b32 v45, s30, 0
+; GFX9-NEXT: v_writelane_b32 v45, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v44, v16
; GFX9-NEXT: v_mov_b32_e32 v43, v15
; GFX9-NEXT: v_mov_b32_e32 v42, v14
; GFX9-NEXT: v_mov_b32_e32 v41, v13
; GFX9-NEXT: v_mov_b32_e32 v40, v12
; GFX9-NEXT: image_gather4_c_b_cl v[0:3], v[40:44], s[4:11], s[4:7] dmask:0x1
-; GFX9-NEXT: s_addk_i32 s32, 0x800
-; GFX9-NEXT: v_writelane_b32 v45, s4, 2
; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, extern_func at gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, extern_func at gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
-; GFX9-NEXT: v_writelane_b32 v45, s30, 0
-; GFX9-NEXT: v_writelane_b32 v45, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
@@ -256,25 +260,26 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX10-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s5
+; GFX10-NEXT: v_writelane_b32 v45, s4, 2
+; GFX10-NEXT: s_addk_i32 s32, 0x400
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GFX10-NEXT: buffer_store_dword v44, off, s[0:3], s33 ; 4-byte Folded Spill
+; GFX10-NEXT: v_writelane_b32 v45, s30, 0
+; GFX10-NEXT: v_writelane_b32 v45, s31, 1
; GFX10-NEXT: image_gather4_c_b_cl v[0:3], v[12:16], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
-; GFX10-NEXT: s_addk_i32 s32, 0x400
-; GFX10-NEXT: v_writelane_b32 v45, s4, 2
+; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_getpc_b64 s[4:5]
; GFX10-NEXT: s_add_u32 s4, s4, extern_func at gotpcrel32@lo+4
; GFX10-NEXT: s_addc_u32 s5, s5, extern_func at gotpcrel32@hi+12
; GFX10-NEXT: v_mov_b32_e32 v40, v16
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX10-NEXT: v_mov_b32_e32 v41, v15
-; GFX10-NEXT: v_writelane_b32 v45, s30, 0
; GFX10-NEXT: v_mov_b32_e32 v42, v14
; GFX10-NEXT: v_mov_b32_e32 v43, v13
; GFX10-NEXT: v_mov_b32_e32 v44, v12
-; GFX10-NEXT: v_writelane_b32 v45, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
@@ -306,24 +311,28 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX11-NEXT: s_or_saveexec_b32 s1, -1
; GFX11-NEXT: scratch_store_b32 off, v45, s33 offset:20 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-NEXT: v_writelane_b32 v45, s0, 2
+; GFX11-NEXT: s_add_i32 s32, s32, 32
; GFX11-NEXT: s_clause 0x4
; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:16
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:12
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v42, s33 offset:8
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v43, s33 offset:4
+; GFX11-NEXT: ; meta instruction
; GFX11-NEXT: scratch_store_b32 off, v44, s33
+; GFX11-NEXT: v_writelane_b32 v45, s30, 0
+; GFX11-NEXT: v_writelane_b32 v45, s31, 1
; GFX11-NEXT: image_gather4_c_b_cl v[0:3], v[12:16], s[0:7], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D
-; GFX11-NEXT: s_add_i32 s32, s32, 32
-; GFX11-NEXT: v_writelane_b32 v45, s0, 2
; GFX11-NEXT: s_getpc_b64 s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, extern_func at gotpcrel32@lo+4
; GFX11-NEXT: s_addc_u32 s1, s1, extern_func at gotpcrel32@hi+12
; GFX11-NEXT: v_dual_mov_b32 v40, v16 :: v_dual_mov_b32 v41, v15
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
-; GFX11-NEXT: v_writelane_b32 v45, s30, 0
; GFX11-NEXT: v_dual_mov_b32 v42, v14 :: v_dual_mov_b32 v43, v13
; GFX11-NEXT: v_mov_b32_e32 v44, v12
-; GFX11-NEXT: v_writelane_b32 v45, s31, 1
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll
index a76f4495f85d5..14b02213658cd 100644
--- a/llvm/test/CodeGen/AMDGPU/wave32.ll
+++ b/llvm/test/CodeGen/AMDGPU/wave32.ll
@@ -3076,14 +3076,14 @@ define void @callee_no_stack_with_call() #1 {
; GFX1032-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX1032-NEXT: s_waitcnt_depctr 0xffe3
; GFX1032-NEXT: s_mov_b32 exec_lo, s17
-; GFX1032-NEXT: s_addk_i32 s32, 0x200
; GFX1032-NEXT: v_writelane_b32 v40, s16, 2
+; GFX1032-NEXT: s_addk_i32 s32, 0x200
+; GFX1032-NEXT: v_writelane_b32 v40, s30, 0
+; GFX1032-NEXT: v_writelane_b32 v40, s31, 1
; GFX1032-NEXT: s_getpc_b64 s[16:17]
; GFX1032-NEXT: s_add_u32 s16, s16, external_void_func_void at gotpcrel32@lo+4
; GFX1032-NEXT: s_addc_u32 s17, s17, external_void_func_void at gotpcrel32@hi+12
; GFX1032-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX1032-NEXT: v_writelane_b32 v40, s30, 0
-; GFX1032-NEXT: v_writelane_b32 v40, s31, 1
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX1032-NEXT: v_readlane_b32 s30, v40, 0
@@ -3107,14 +3107,14 @@ define void @callee_no_stack_with_call() #1 {
; GFX1064-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; GFX1064-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_mov_b64 exec, s[18:19]
-; GFX1064-NEXT: s_addk_i32 s32, 0x400
; GFX1064-NEXT: v_writelane_b32 v40, s16, 2
+; GFX1064-NEXT: s_addk_i32 s32, 0x400
+; GFX1064-NEXT: v_writelane_b32 v40, s30, 0
+; GFX1064-NEXT: v_writelane_b32 v40, s31, 1
; GFX1064-NEXT: s_getpc_b64 s[16:17]
; GFX1064-NEXT: s_add_u32 s16, s16, external_void_func_void at gotpcrel32@lo+4
; GFX1064-NEXT: s_addc_u32 s17, s17, external_void_func_void at gotpcrel32@hi+12
; GFX1064-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX1064-NEXT: v_writelane_b32 v40, s30, 0
-; GFX1064-NEXT: v_writelane_b32 v40, s31, 1
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: s_swappc_b64 s[30:31], s[16:17]
; GFX1064-NEXT: v_readlane_b32 s30, v40, 0
diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll b/llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
index 3fe54cd045c0f..9eea46172ce81 100644
--- a/llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
+++ b/llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
@@ -22,9 +22,9 @@ define void @vector_reg_liverange_split() #0 {
; GFX90A-NEXT: v_writelane_b32 v40, s28, 2
; GFX90A-NEXT: v_writelane_b32 v40, s29, 3
; GFX90A-NEXT: v_writelane_b32 v40, s30, 0
-; GFX90A-NEXT: ; implicit-def: $vgpr39 : SGPR spill to VGPR lane
; GFX90A-NEXT: s_addk_i32 s32, 0x400
; GFX90A-NEXT: v_writelane_b32 v40, s31, 1
+; GFX90A-NEXT: ; implicit-def: $vgpr39 : SGPR spill to VGPR lane
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def s20
; GFX90A-NEXT: ;;#ASMEND
diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll b/llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
index b5c0023bd5c2a..b3ad8880b85a9 100644
--- a/llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
+++ b/llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
@@ -27,9 +27,9 @@ define void @test() #0 {
; GCN-NEXT: v_writelane_b32 v40, s28, 2
; GCN-NEXT: v_writelane_b32 v40, s29, 3
; GCN-NEXT: v_writelane_b32 v40, s30, 0
-; GCN-NEXT: ; implicit-def: $vgpr39 : SGPR spill to VGPR lane
; GCN-NEXT: s_addk_i32 s32, 0x400
; GCN-NEXT: v_writelane_b32 v40, s31, 1
+; GCN-NEXT: ; implicit-def: $vgpr39 : SGPR spill to VGPR lane
; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ; def s16
; GCN-NEXT: ;;#ASMEND
>From 8e9bc38f1dc75a496545f7c9a827ac84645fdbda Mon Sep 17 00:00:00 2001
From: Scott Linder <Scott.Linder at amd.com>
Date: Fri, 21 Nov 2025 18:26:50 +0000
Subject: [PATCH 3/3] WIP attempt to avoid MCRegAliasIterator
---
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 43 ++++++---
.../AMDGPU/accvgpr-spill-scc-clobber.mir | 24 ++---
.../AMDGPU/tail-call-inreg-arguments.error.ll | 8 +-
.../CodeGen/AMDGPU/whole-wave-functions.ll | 94 +++++++++----------
4 files changed, 91 insertions(+), 78 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index 6b0af497dfa98..366d782c60d59 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -2234,16 +2234,6 @@ bool SIFrameLowering::allocateScavengingFrameIndexesNearIncomingSP(
return true;
}
-static bool isLiveIntoMBB(MCRegister Reg, MachineBasicBlock &MBB,
- const TargetRegisterInfo *TRI) {
- for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R) {
- if (MBB.isLiveIn(*R)) {
- return true;
- }
- }
- return false;
-}
-
bool SIFrameLowering::spillCalleeSavedRegisters(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
@@ -2251,8 +2241,36 @@ bool SIFrameLowering::spillCalleeSavedRegisters(
const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
const SIInstrInfo *TII = ST.getInstrInfo();
const SIRegisterInfo *SITRI = static_cast<const SIRegisterInfo *>(TRI);
+ const MachineRegisterInfo &MRI = MF->getRegInfo();
if (!ST.useVGPRBlockOpsForCSR()) {
+ SparseBitVector<> LiveInRoots;
+ if (MRI.tracksLiveness()) {
+ for (const auto &LI : MBB.liveins()) {
+ for (MCRegUnitMaskIterator MI(LI.PhysReg, TRI); MI.isValid(); ++MI) {
+ auto [Unit, UnitLaneMask] = *MI;
+ if ((LI.LaneMask & UnitLaneMask).none())
+ continue;
+ for (MCRegUnitRootIterator RI(Unit, TRI); RI.isValid(); ++RI)
+ LiveInRoots.set(*RI);
+ }
+ }
+ }
+
+ auto UpdateLiveInCheckCanKill = [&](MCRegister Reg) {
+ if (!MRI.tracksLiveness())
+ return false;
+ for (MCRegUnitIterator UI(Reg, TRI); UI.isValid(); ++UI) {
+ for (MCRegUnitRootIterator RI(*UI, TRI); RI.isValid(); ++RI) {
+ if (LiveInRoots.test(*RI))
+ return false;
+ }
+ }
+ // Reg is live in to the spill
+ MBB.addLiveIn(Reg);
+ return true;
+ };
+
for (const CalleeSavedInfo &CS : CSI) {
// Insert the spill to the stack frame.
unsigned Reg = CS.getReg();
@@ -2268,9 +2286,8 @@ bool SIFrameLowering::spillCalleeSavedRegisters(
// the incoming register value, so don't kill at the spill point. This
// happens since we pass some special inputs (workgroup IDs) in the
// callee saved range.
- const bool IsLiveIn = isLiveIntoMBB(Reg, MBB, TRI);
- TII->storeRegToStackSlotCFI(MBB, MI, Reg, !IsLiveIn, CS.getFrameIdx(),
- RC, TRI);
+ TII->storeRegToStackSlotCFI(MBB, MI, Reg, UpdateLiveInCheckCanKill(Reg),
+ CS.getFrameIdx(), RC, TRI);
}
}
return true;
diff --git a/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir b/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
index 23cae4b6a6baa..bf28de714a85a 100644
--- a/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+++ b/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
@@ -367,7 +367,7 @@ body: |
; GFX90A-LABEL: name: agpr32_restore_clobber_scc
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GFX90A-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
+ ; GFX90A-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $agpr64, $agpr65, $agpr66, $agpr67, $agpr68, $agpr69, $agpr70, $agpr71, $agpr72, $agpr73, $agpr74, $agpr75, $agpr76, $agpr77, $agpr78, $agpr79, $agpr80, $agpr81, $agpr82, $agpr83, $agpr84, $agpr85, $agpr86, $agpr87, $agpr88, $agpr89, $agpr90, $agpr91, $agpr92, $agpr93, $agpr94, $agpr95, $agpr96, $agpr97, $agpr98, $agpr99, $agpr100, $agpr101, $agpr102, $agpr103, $agpr104, $agpr105, $agpr106, $agpr107, $agpr108, $agpr109, $agpr110, $agpr111, $agpr112, $agpr113, $agpr114, $agpr115, $agpr116, $agpr117, $agpr118, $agpr119, $agpr120, $agpr121, $agpr122, $agpr123, $agpr124, $agpr125, $agpr126, $agpr127, $agpr128, $agpr129, $agpr130, $agpr131, $agpr132, $agpr133, $agpr134, $agpr135, $agpr136, $agpr137, $agpr138, $agpr139, $agpr140, $agpr141, $agpr142, $agpr143, $agpr144, $agpr145, $agpr146, $agpr147, $agpr148, $agpr149, $agpr150, $agpr151, $agpr152, $agpr153, $agpr154, $agpr155, $agpr156, $agpr157, $agpr158, $agpr159, $agpr160, $agpr161, $agpr162, $agpr163, $agpr164, $agpr165, $agpr166, $agpr167, $agpr168, $agpr169, $agpr170, $agpr171, $agpr172, $agpr173, $agpr174, $agpr175, $agpr176, $agpr177, $agpr178, $agpr179, $agpr180, $agpr181, $agpr182, $agpr183, $agpr184, $agpr185, $agpr186, $agpr187, $agpr188, $agpr189, $agpr190, $agpr191, $agpr192, $agpr193, $agpr194, $agpr195, $agpr196, $agpr197, $agpr198, $agpr199, $agpr200, $agpr201, $agpr202, $agpr203, $agpr204, $agpr205, $agpr206, $agpr207, $agpr208, $agpr209, $agpr210, $agpr211, $agpr212, $agpr213, $agpr214, $agpr215, $agpr216, $agpr217, $agpr218, $agpr219, $agpr220, $agpr221, $agpr222, $agpr223, $agpr224, $agpr225, $agpr226, $agpr227, $agpr228, $agpr229, $agpr230, $agpr231, $agpr232, $agpr233, $agpr234, $agpr235, $agpr236, $agpr237, $agpr238, $agpr239, $agpr240, $agpr241, $agpr242, $agpr243, $agpr244, $agpr245, $agpr246, $agpr247, $agpr248, $agpr249, $agpr250, $agpr251, $agpr252, $agpr253, $agpr254, $agpr255, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
@@ -1550,7 +1550,7 @@ body: |
; GFX90A-FLATSCR-LABEL: name: agpr32_restore_clobber_scc
; GFX90A-FLATSCR: bb.0:
; GFX90A-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GFX90A-FLATSCR-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
+ ; GFX90A-FLATSCR-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $agpr64, $agpr65, $agpr66, $agpr67, $agpr68, $agpr69, $agpr70, $agpr71, $agpr72, $agpr73, $agpr74, $agpr75, $agpr76, $agpr77, $agpr78, $agpr79, $agpr80, $agpr81, $agpr82, $agpr83, $agpr84, $agpr85, $agpr86, $agpr87, $agpr88, $agpr89, $agpr90, $agpr91, $agpr92, $agpr93, $agpr94, $agpr95, $agpr96, $agpr97, $agpr98, $agpr99, $agpr100, $agpr101, $agpr102, $agpr103, $agpr104, $agpr105, $agpr106, $agpr107, $agpr108, $agpr109, $agpr110, $agpr111, $agpr112, $agpr113, $agpr114, $agpr115, $agpr116, $agpr117, $agpr118, $agpr119, $agpr120, $agpr121, $agpr122, $agpr123, $agpr124, $agpr125, $agpr126, $agpr127, $agpr128, $agpr129, $agpr130, $agpr131, $agpr132, $agpr133, $agpr134, $agpr135, $agpr136, $agpr137, $agpr138, $agpr139, $agpr140, $agpr141, $agpr142, $agpr143, $agpr144, $agpr145, $agpr146, $agpr147, $agpr148, $agpr149, $agpr150, $agpr151, $agpr152, $agpr153, $agpr154, $agpr155, $agpr156, $agpr157, $agpr158, $agpr159, $agpr160, $agpr161, $agpr162, $agpr163, $agpr164, $agpr165, $agpr166, $agpr167, $agpr168, $agpr169, $agpr170, $agpr171, $agpr172, $agpr173, $agpr174, $agpr175, $agpr176, $agpr177, $agpr178, $agpr179, $agpr180, $agpr181, $agpr182, $agpr183, $agpr184, $agpr185, $agpr186, $agpr187, $agpr188, $agpr189, $agpr190, $agpr191, $agpr192, $agpr193, $agpr194, $agpr195, $agpr196, $agpr197, $agpr198, $agpr199, $agpr200, $agpr201, $agpr202, $agpr203, $agpr204, $agpr205, $agpr206, $agpr207, $agpr208, $agpr209, $agpr210, $agpr211, $agpr212, $agpr213, $agpr214, $agpr215, $agpr216, $agpr217, $agpr218, $agpr219, $agpr220, $agpr221, $agpr222, $agpr223, $agpr224, $agpr225, $agpr226, $agpr227, $agpr228, $agpr229, $agpr230, $agpr231, $agpr232, $agpr233, $agpr234, $agpr235, $agpr236, $agpr237, $agpr238, $agpr239, $agpr240, $agpr241, $agpr242, $agpr243, $agpr244, $agpr245, $agpr246, $agpr247, $agpr248, $agpr249, $agpr250, $agpr251, $agpr252, $agpr253, $agpr254, $agpr255, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
; GFX90A-FLATSCR-NEXT: {{ $}}
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
@@ -2763,7 +2763,7 @@ body: |
; GFX90A-LABEL: name: agpr64_restore_clobber_scc
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GFX90A-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
+ ; GFX90A-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $agpr64, $agpr65, $agpr66, $agpr67, $agpr68, $agpr69, $agpr70, $agpr71, $agpr72, $agpr73, $agpr74, $agpr75, $agpr76, $agpr77, $agpr78, $agpr79, $agpr80, $agpr81, $agpr82, $agpr83, $agpr84, $agpr85, $agpr86, $agpr87, $agpr88, $agpr89, $agpr90, $agpr91, $agpr92, $agpr93, $agpr94, $agpr95, $agpr96, $agpr97, $agpr98, $agpr99, $agpr100, $agpr101, $agpr102, $agpr103, $agpr104, $agpr105, $agpr106, $agpr107, $agpr108, $agpr109, $agpr110, $agpr111, $agpr112, $agpr113, $agpr114, $agpr115, $agpr116, $agpr117, $agpr118, $agpr119, $agpr120, $agpr121, $agpr122, $agpr123, $agpr124, $agpr125, $agpr126, $agpr127, $agpr128, $agpr129, $agpr130, $agpr131, $agpr132, $agpr133, $agpr134, $agpr135, $agpr136, $agpr137, $agpr138, $agpr139, $agpr140, $agpr141, $agpr142, $agpr143, $agpr144, $agpr145, $agpr146, $agpr147, $agpr148, $agpr149, $agpr150, $agpr151, $agpr152, $agpr153, $agpr154, $agpr155, $agpr156, $agpr157, $agpr158, $agpr159, $agpr160, $agpr161, $agpr162, $agpr163, $agpr164, $agpr165, $agpr166, $agpr167, $agpr168, $agpr169, $agpr170, $agpr171, $agpr172, $agpr173, $agpr174, $agpr175, $agpr176, $agpr177, $agpr178, $agpr179, $agpr180, $agpr181, $agpr182, $agpr183, $agpr184, $agpr185, $agpr186, $agpr187, $agpr188, $agpr189, $agpr190, $agpr191, $agpr192, $agpr193, $agpr194, $agpr195, $agpr196, $agpr197, $agpr198, $agpr199, $agpr200, $agpr201, $agpr202, $agpr203, $agpr204, $agpr205, $agpr206, $agpr207, $agpr208, $agpr209, $agpr210, $agpr211, $agpr212, $agpr213, $agpr214, $agpr215, $agpr216, $agpr217, $agpr218, $agpr219, $agpr220, $agpr221, $agpr222, $agpr223, $agpr224, $agpr225, $agpr226, $agpr227, $agpr228, $agpr229, $agpr230, $agpr231, $agpr232, $agpr233, $agpr234, $agpr235, $agpr236, $agpr237, $agpr238, $agpr239, $agpr240, $agpr241, $agpr242, $agpr243, $agpr244, $agpr245, $agpr246, $agpr247, $agpr248, $agpr249, $agpr250, $agpr251, $agpr252, $agpr253, $agpr254, $agpr255, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
@@ -3949,7 +3949,7 @@ body: |
; GFX90A-FLATSCR-LABEL: name: agpr64_restore_clobber_scc
; GFX90A-FLATSCR: bb.0:
; GFX90A-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GFX90A-FLATSCR-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
+ ; GFX90A-FLATSCR-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $agpr64, $agpr65, $agpr66, $agpr67, $agpr68, $agpr69, $agpr70, $agpr71, $agpr72, $agpr73, $agpr74, $agpr75, $agpr76, $agpr77, $agpr78, $agpr79, $agpr80, $agpr81, $agpr82, $agpr83, $agpr84, $agpr85, $agpr86, $agpr87, $agpr88, $agpr89, $agpr90, $agpr91, $agpr92, $agpr93, $agpr94, $agpr95, $agpr96, $agpr97, $agpr98, $agpr99, $agpr100, $agpr101, $agpr102, $agpr103, $agpr104, $agpr105, $agpr106, $agpr107, $agpr108, $agpr109, $agpr110, $agpr111, $agpr112, $agpr113, $agpr114, $agpr115, $agpr116, $agpr117, $agpr118, $agpr119, $agpr120, $agpr121, $agpr122, $agpr123, $agpr124, $agpr125, $agpr126, $agpr127, $agpr128, $agpr129, $agpr130, $agpr131, $agpr132, $agpr133, $agpr134, $agpr135, $agpr136, $agpr137, $agpr138, $agpr139, $agpr140, $agpr141, $agpr142, $agpr143, $agpr144, $agpr145, $agpr146, $agpr147, $agpr148, $agpr149, $agpr150, $agpr151, $agpr152, $agpr153, $agpr154, $agpr155, $agpr156, $agpr157, $agpr158, $agpr159, $agpr160, $agpr161, $agpr162, $agpr163, $agpr164, $agpr165, $agpr166, $agpr167, $agpr168, $agpr169, $agpr170, $agpr171, $agpr172, $agpr173, $agpr174, $agpr175, $agpr176, $agpr177, $agpr178, $agpr179, $agpr180, $agpr181, $agpr182, $agpr183, $agpr184, $agpr185, $agpr186, $agpr187, $agpr188, $agpr189, $agpr190, $agpr191, $agpr192, $agpr193, $agpr194, $agpr195, $agpr196, $agpr197, $agpr198, $agpr199, $agpr200, $agpr201, $agpr202, $agpr203, $agpr204, $agpr205, $agpr206, $agpr207, $agpr208, $agpr209, $agpr210, $agpr211, $agpr212, $agpr213, $agpr214, $agpr215, $agpr216, $agpr217, $agpr218, $agpr219, $agpr220, $agpr221, $agpr222, $agpr223, $agpr224, $agpr225, $agpr226, $agpr227, $agpr228, $agpr229, $agpr230, $agpr231, $agpr232, $agpr233, $agpr234, $agpr235, $agpr236, $agpr237, $agpr238, $agpr239, $agpr240, $agpr241, $agpr242, $agpr243, $agpr244, $agpr245, $agpr246, $agpr247, $agpr248, $agpr249, $agpr250, $agpr251, $agpr252, $agpr253, $agpr254, $agpr255, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
; GFX90A-FLATSCR-NEXT: {{ $}}
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
@@ -5164,7 +5164,7 @@ body: |
; GFX90A-LABEL: name: agpr96_restore_clobber_scc
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GFX90A-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
+ ; GFX90A-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $agpr64, $agpr65, $agpr66, $agpr67, $agpr68, $agpr69, $agpr70, $agpr71, $agpr72, $agpr73, $agpr74, $agpr75, $agpr76, $agpr77, $agpr78, $agpr79, $agpr80, $agpr81, $agpr82, $agpr83, $agpr84, $agpr85, $agpr86, $agpr87, $agpr88, $agpr89, $agpr90, $agpr91, $agpr92, $agpr93, $agpr94, $agpr95, $agpr96, $agpr97, $agpr98, $agpr99, $agpr100, $agpr101, $agpr102, $agpr103, $agpr104, $agpr105, $agpr106, $agpr107, $agpr108, $agpr109, $agpr110, $agpr111, $agpr112, $agpr113, $agpr114, $agpr115, $agpr116, $agpr117, $agpr118, $agpr119, $agpr120, $agpr121, $agpr122, $agpr123, $agpr124, $agpr125, $agpr126, $agpr127, $agpr128, $agpr129, $agpr130, $agpr131, $agpr132, $agpr133, $agpr134, $agpr135, $agpr136, $agpr137, $agpr138, $agpr139, $agpr140, $agpr141, $agpr142, $agpr143, $agpr144, $agpr145, $agpr146, $agpr147, $agpr148, $agpr149, $agpr150, $agpr151, $agpr152, $agpr153, $agpr154, $agpr155, $agpr156, $agpr157, $agpr158, $agpr159, $agpr160, $agpr161, $agpr162, $agpr163, $agpr164, $agpr165, $agpr166, $agpr167, $agpr168, $agpr169, $agpr170, $agpr171, $agpr172, $agpr173, $agpr174, $agpr175, $agpr176, $agpr177, $agpr178, $agpr179, $agpr180, $agpr181, $agpr182, $agpr183, $agpr184, $agpr185, $agpr186, $agpr187, $agpr188, $agpr189, $agpr190, $agpr191, $agpr192, $agpr193, $agpr194, $agpr195, $agpr196, $agpr197, $agpr198, $agpr199, $agpr200, $agpr201, $agpr202, $agpr203, $agpr204, $agpr205, $agpr206, $agpr207, $agpr208, $agpr209, $agpr210, $agpr211, $agpr212, $agpr213, $agpr214, $agpr215, $agpr216, $agpr217, $agpr218, $agpr219, $agpr220, $agpr221, $agpr222, $agpr223, $agpr224, $agpr225, $agpr226, $agpr227, $agpr228, $agpr229, $agpr230, $agpr231, $agpr232, $agpr233, $agpr234, $agpr235, $agpr236, $agpr237, $agpr238, $agpr239, $agpr240, $agpr241, $agpr242, $agpr243, $agpr244, $agpr245, $agpr246, $agpr247, $agpr248, $agpr249, $agpr250, $agpr251, $agpr252, $agpr253, $agpr254, $agpr255, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
@@ -6353,7 +6353,7 @@ body: |
; GFX90A-FLATSCR-LABEL: name: agpr96_restore_clobber_scc
; GFX90A-FLATSCR: bb.0:
; GFX90A-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GFX90A-FLATSCR-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
+ ; GFX90A-FLATSCR-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $agpr64, $agpr65, $agpr66, $agpr67, $agpr68, $agpr69, $agpr70, $agpr71, $agpr72, $agpr73, $agpr74, $agpr75, $agpr76, $agpr77, $agpr78, $agpr79, $agpr80, $agpr81, $agpr82, $agpr83, $agpr84, $agpr85, $agpr86, $agpr87, $agpr88, $agpr89, $agpr90, $agpr91, $agpr92, $agpr93, $agpr94, $agpr95, $agpr96, $agpr97, $agpr98, $agpr99, $agpr100, $agpr101, $agpr102, $agpr103, $agpr104, $agpr105, $agpr106, $agpr107, $agpr108, $agpr109, $agpr110, $agpr111, $agpr112, $agpr113, $agpr114, $agpr115, $agpr116, $agpr117, $agpr118, $agpr119, $agpr120, $agpr121, $agpr122, $agpr123, $agpr124, $agpr125, $agpr126, $agpr127, $agpr128, $agpr129, $agpr130, $agpr131, $agpr132, $agpr133, $agpr134, $agpr135, $agpr136, $agpr137, $agpr138, $agpr139, $agpr140, $agpr141, $agpr142, $agpr143, $agpr144, $agpr145, $agpr146, $agpr147, $agpr148, $agpr149, $agpr150, $agpr151, $agpr152, $agpr153, $agpr154, $agpr155, $agpr156, $agpr157, $agpr158, $agpr159, $agpr160, $agpr161, $agpr162, $agpr163, $agpr164, $agpr165, $agpr166, $agpr167, $agpr168, $agpr169, $agpr170, $agpr171, $agpr172, $agpr173, $agpr174, $agpr175, $agpr176, $agpr177, $agpr178, $agpr179, $agpr180, $agpr181, $agpr182, $agpr183, $agpr184, $agpr185, $agpr186, $agpr187, $agpr188, $agpr189, $agpr190, $agpr191, $agpr192, $agpr193, $agpr194, $agpr195, $agpr196, $agpr197, $agpr198, $agpr199, $agpr200, $agpr201, $agpr202, $agpr203, $agpr204, $agpr205, $agpr206, $agpr207, $agpr208, $agpr209, $agpr210, $agpr211, $agpr212, $agpr213, $agpr214, $agpr215, $agpr216, $agpr217, $agpr218, $agpr219, $agpr220, $agpr221, $agpr222, $agpr223, $agpr224, $agpr225, $agpr226, $agpr227, $agpr228, $agpr229, $agpr230, $agpr231, $agpr232, $agpr233, $agpr234, $agpr235, $agpr236, $agpr237, $agpr238, $agpr239, $agpr240, $agpr241, $agpr242, $agpr243, $agpr244, $agpr245, $agpr246, $agpr247, $agpr248, $agpr249, $agpr250, $agpr251, $agpr252, $agpr253, $agpr254, $agpr255, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
; GFX90A-FLATSCR-NEXT: {{ $}}
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
@@ -7564,7 +7564,7 @@ body: |
; GFX90A-LABEL: name: agpr32_save_clobber_scc
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GFX90A-NEXT: liveins: $agpr0, $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
+ ; GFX90A-NEXT: liveins: $agpr0, $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $agpr64, $agpr65, $agpr66, $agpr67, $agpr68, $agpr69, $agpr70, $agpr71, $agpr72, $agpr73, $agpr74, $agpr75, $agpr76, $agpr77, $agpr78, $agpr79, $agpr80, $agpr81, $agpr82, $agpr83, $agpr84, $agpr85, $agpr86, $agpr87, $agpr88, $agpr89, $agpr90, $agpr91, $agpr92, $agpr93, $agpr94, $agpr95, $agpr96, $agpr97, $agpr98, $agpr99, $agpr100, $agpr101, $agpr102, $agpr103, $agpr104, $agpr105, $agpr106, $agpr107, $agpr108, $agpr109, $agpr110, $agpr111, $agpr112, $agpr113, $agpr114, $agpr115, $agpr116, $agpr117, $agpr118, $agpr119, $agpr120, $agpr121, $agpr122, $agpr123, $agpr124, $agpr125, $agpr126, $agpr127, $agpr128, $agpr129, $agpr130, $agpr131, $agpr132, $agpr133, $agpr134, $agpr135, $agpr136, $agpr137, $agpr138, $agpr139, $agpr140, $agpr141, $agpr142, $agpr143, $agpr144, $agpr145, $agpr146, $agpr147, $agpr148, $agpr149, $agpr150, $agpr151, $agpr152, $agpr153, $agpr154, $agpr155, $agpr156, $agpr157, $agpr158, $agpr159, $agpr160, $agpr161, $agpr162, $agpr163, $agpr164, $agpr165, $agpr166, $agpr167, $agpr168, $agpr169, $agpr170, $agpr171, $agpr172, $agpr173, $agpr174, $agpr175, $agpr176, $agpr177, $agpr178, $agpr179, $agpr180, $agpr181, $agpr182, $agpr183, $agpr184, $agpr185, $agpr186, $agpr187, $agpr188, $agpr189, $agpr190, $agpr191, $agpr192, $agpr193, $agpr194, $agpr195, $agpr196, $agpr197, $agpr198, $agpr199, $agpr200, $agpr201, $agpr202, $agpr203, $agpr204, $agpr205, $agpr206, $agpr207, $agpr208, $agpr209, $agpr210, $agpr211, $agpr212, $agpr213, $agpr214, $agpr215, $agpr216, $agpr217, $agpr218, $agpr219, $agpr220, $agpr221, $agpr222, $agpr223, $agpr224, $agpr225, $agpr226, $agpr227, $agpr228, $agpr229, $agpr230, $agpr231, $agpr232, $agpr233, $agpr234, $agpr235, $agpr236, $agpr237, $agpr238, $agpr239, $agpr240, $agpr241, $agpr242, $agpr243, $agpr244, $agpr245, $agpr246, $agpr247, $agpr248, $agpr249, $agpr250, $agpr251, $agpr252, $agpr253, $agpr254, $agpr255, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
@@ -8747,7 +8747,7 @@ body: |
; GFX90A-FLATSCR-LABEL: name: agpr32_save_clobber_scc
; GFX90A-FLATSCR: bb.0:
; GFX90A-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GFX90A-FLATSCR-NEXT: liveins: $agpr0, $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
+ ; GFX90A-FLATSCR-NEXT: liveins: $agpr0, $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $agpr64, $agpr65, $agpr66, $agpr67, $agpr68, $agpr69, $agpr70, $agpr71, $agpr72, $agpr73, $agpr74, $agpr75, $agpr76, $agpr77, $agpr78, $agpr79, $agpr80, $agpr81, $agpr82, $agpr83, $agpr84, $agpr85, $agpr86, $agpr87, $agpr88, $agpr89, $agpr90, $agpr91, $agpr92, $agpr93, $agpr94, $agpr95, $agpr96, $agpr97, $agpr98, $agpr99, $agpr100, $agpr101, $agpr102, $agpr103, $agpr104, $agpr105, $agpr106, $agpr107, $agpr108, $agpr109, $agpr110, $agpr111, $agpr112, $agpr113, $agpr114, $agpr115, $agpr116, $agpr117, $agpr118, $agpr119, $agpr120, $agpr121, $agpr122, $agpr123, $agpr124, $agpr125, $agpr126, $agpr127, $agpr128, $agpr129, $agpr130, $agpr131, $agpr132, $agpr133, $agpr134, $agpr135, $agpr136, $agpr137, $agpr138, $agpr139, $agpr140, $agpr141, $agpr142, $agpr143, $agpr144, $agpr145, $agpr146, $agpr147, $agpr148, $agpr149, $agpr150, $agpr151, $agpr152, $agpr153, $agpr154, $agpr155, $agpr156, $agpr157, $agpr158, $agpr159, $agpr160, $agpr161, $agpr162, $agpr163, $agpr164, $agpr165, $agpr166, $agpr167, $agpr168, $agpr169, $agpr170, $agpr171, $agpr172, $agpr173, $agpr174, $agpr175, $agpr176, $agpr177, $agpr178, $agpr179, $agpr180, $agpr181, $agpr182, $agpr183, $agpr184, $agpr185, $agpr186, $agpr187, $agpr188, $agpr189, $agpr190, $agpr191, $agpr192, $agpr193, $agpr194, $agpr195, $agpr196, $agpr197, $agpr198, $agpr199, $agpr200, $agpr201, $agpr202, $agpr203, $agpr204, $agpr205, $agpr206, $agpr207, $agpr208, $agpr209, $agpr210, $agpr211, $agpr212, $agpr213, $agpr214, $agpr215, $agpr216, $agpr217, $agpr218, $agpr219, $agpr220, $agpr221, $agpr222, $agpr223, $agpr224, $agpr225, $agpr226, $agpr227, $agpr228, $agpr229, $agpr230, $agpr231, $agpr232, $agpr233, $agpr234, $agpr235, $agpr236, $agpr237, $agpr238, $agpr239, $agpr240, $agpr241, $agpr242, $agpr243, $agpr244, $agpr245, $agpr246, $agpr247, $agpr248, $agpr249, $agpr250, $agpr251, $agpr252, $agpr253, $agpr254, $agpr255, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
; GFX90A-FLATSCR-NEXT: {{ $}}
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
@@ -9959,7 +9959,7 @@ body: |
; GFX90A-LABEL: name: agpr64_save_clobber_scc
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GFX90A-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
+ ; GFX90A-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $agpr64, $agpr65, $agpr66, $agpr67, $agpr68, $agpr69, $agpr70, $agpr71, $agpr72, $agpr73, $agpr74, $agpr75, $agpr76, $agpr77, $agpr78, $agpr79, $agpr80, $agpr81, $agpr82, $agpr83, $agpr84, $agpr85, $agpr86, $agpr87, $agpr88, $agpr89, $agpr90, $agpr91, $agpr92, $agpr93, $agpr94, $agpr95, $agpr96, $agpr97, $agpr98, $agpr99, $agpr100, $agpr101, $agpr102, $agpr103, $agpr104, $agpr105, $agpr106, $agpr107, $agpr108, $agpr109, $agpr110, $agpr111, $agpr112, $agpr113, $agpr114, $agpr115, $agpr116, $agpr117, $agpr118, $agpr119, $agpr120, $agpr121, $agpr122, $agpr123, $agpr124, $agpr125, $agpr126, $agpr127, $agpr128, $agpr129, $agpr130, $agpr131, $agpr132, $agpr133, $agpr134, $agpr135, $agpr136, $agpr137, $agpr138, $agpr139, $agpr140, $agpr141, $agpr142, $agpr143, $agpr144, $agpr145, $agpr146, $agpr147, $agpr148, $agpr149, $agpr150, $agpr151, $agpr152, $agpr153, $agpr154, $agpr155, $agpr156, $agpr157, $agpr158, $agpr159, $agpr160, $agpr161, $agpr162, $agpr163, $agpr164, $agpr165, $agpr166, $agpr167, $agpr168, $agpr169, $agpr170, $agpr171, $agpr172, $agpr173, $agpr174, $agpr175, $agpr176, $agpr177, $agpr178, $agpr179, $agpr180, $agpr181, $agpr182, $agpr183, $agpr184, $agpr185, $agpr186, $agpr187, $agpr188, $agpr189, $agpr190, $agpr191, $agpr192, $agpr193, $agpr194, $agpr195, $agpr196, $agpr197, $agpr198, $agpr199, $agpr200, $agpr201, $agpr202, $agpr203, $agpr204, $agpr205, $agpr206, $agpr207, $agpr208, $agpr209, $agpr210, $agpr211, $agpr212, $agpr213, $agpr214, $agpr215, $agpr216, $agpr217, $agpr218, $agpr219, $agpr220, $agpr221, $agpr222, $agpr223, $agpr224, $agpr225, $agpr226, $agpr227, $agpr228, $agpr229, $agpr230, $agpr231, $agpr232, $agpr233, $agpr234, $agpr235, $agpr236, $agpr237, $agpr238, $agpr239, $agpr240, $agpr241, $agpr242, $agpr243, $agpr244, $agpr245, $agpr246, $agpr247, $agpr248, $agpr249, $agpr250, $agpr251, $agpr252, $agpr253, $agpr254, $agpr255, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
@@ -11145,7 +11145,7 @@ body: |
; GFX90A-FLATSCR-LABEL: name: agpr64_save_clobber_scc
; GFX90A-FLATSCR: bb.0:
; GFX90A-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GFX90A-FLATSCR-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
+ ; GFX90A-FLATSCR-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $agpr64, $agpr65, $agpr66, $agpr67, $agpr68, $agpr69, $agpr70, $agpr71, $agpr72, $agpr73, $agpr74, $agpr75, $agpr76, $agpr77, $agpr78, $agpr79, $agpr80, $agpr81, $agpr82, $agpr83, $agpr84, $agpr85, $agpr86, $agpr87, $agpr88, $agpr89, $agpr90, $agpr91, $agpr92, $agpr93, $agpr94, $agpr95, $agpr96, $agpr97, $agpr98, $agpr99, $agpr100, $agpr101, $agpr102, $agpr103, $agpr104, $agpr105, $agpr106, $agpr107, $agpr108, $agpr109, $agpr110, $agpr111, $agpr112, $agpr113, $agpr114, $agpr115, $agpr116, $agpr117, $agpr118, $agpr119, $agpr120, $agpr121, $agpr122, $agpr123, $agpr124, $agpr125, $agpr126, $agpr127, $agpr128, $agpr129, $agpr130, $agpr131, $agpr132, $agpr133, $agpr134, $agpr135, $agpr136, $agpr137, $agpr138, $agpr139, $agpr140, $agpr141, $agpr142, $agpr143, $agpr144, $agpr145, $agpr146, $agpr147, $agpr148, $agpr149, $agpr150, $agpr151, $agpr152, $agpr153, $agpr154, $agpr155, $agpr156, $agpr157, $agpr158, $agpr159, $agpr160, $agpr161, $agpr162, $agpr163, $agpr164, $agpr165, $agpr166, $agpr167, $agpr168, $agpr169, $agpr170, $agpr171, $agpr172, $agpr173, $agpr174, $agpr175, $agpr176, $agpr177, $agpr178, $agpr179, $agpr180, $agpr181, $agpr182, $agpr183, $agpr184, $agpr185, $agpr186, $agpr187, $agpr188, $agpr189, $agpr190, $agpr191, $agpr192, $agpr193, $agpr194, $agpr195, $agpr196, $agpr197, $agpr198, $agpr199, $agpr200, $agpr201, $agpr202, $agpr203, $agpr204, $agpr205, $agpr206, $agpr207, $agpr208, $agpr209, $agpr210, $agpr211, $agpr212, $agpr213, $agpr214, $agpr215, $agpr216, $agpr217, $agpr218, $agpr219, $agpr220, $agpr221, $agpr222, $agpr223, $agpr224, $agpr225, $agpr226, $agpr227, $agpr228, $agpr229, $agpr230, $agpr231, $agpr232, $agpr233, $agpr234, $agpr235, $agpr236, $agpr237, $agpr238, $agpr239, $agpr240, $agpr241, $agpr242, $agpr243, $agpr244, $agpr245, $agpr246, $agpr247, $agpr248, $agpr249, $agpr250, $agpr251, $agpr252, $agpr253, $agpr254, $agpr255, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
; GFX90A-FLATSCR-NEXT: {{ $}}
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
@@ -12358,7 +12358,7 @@ body: |
; GFX90A-LABEL: name: agpr96_save_clobber_scc
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GFX90A-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
+ ; GFX90A-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $agpr64, $agpr65, $agpr66, $agpr67, $agpr68, $agpr69, $agpr70, $agpr71, $agpr72, $agpr73, $agpr74, $agpr75, $agpr76, $agpr77, $agpr78, $agpr79, $agpr80, $agpr81, $agpr82, $agpr83, $agpr84, $agpr85, $agpr86, $agpr87, $agpr88, $agpr89, $agpr90, $agpr91, $agpr92, $agpr93, $agpr94, $agpr95, $agpr96, $agpr97, $agpr98, $agpr99, $agpr100, $agpr101, $agpr102, $agpr103, $agpr104, $agpr105, $agpr106, $agpr107, $agpr108, $agpr109, $agpr110, $agpr111, $agpr112, $agpr113, $agpr114, $agpr115, $agpr116, $agpr117, $agpr118, $agpr119, $agpr120, $agpr121, $agpr122, $agpr123, $agpr124, $agpr125, $agpr126, $agpr127, $agpr128, $agpr129, $agpr130, $agpr131, $agpr132, $agpr133, $agpr134, $agpr135, $agpr136, $agpr137, $agpr138, $agpr139, $agpr140, $agpr141, $agpr142, $agpr143, $agpr144, $agpr145, $agpr146, $agpr147, $agpr148, $agpr149, $agpr150, $agpr151, $agpr152, $agpr153, $agpr154, $agpr155, $agpr156, $agpr157, $agpr158, $agpr159, $agpr160, $agpr161, $agpr162, $agpr163, $agpr164, $agpr165, $agpr166, $agpr167, $agpr168, $agpr169, $agpr170, $agpr171, $agpr172, $agpr173, $agpr174, $agpr175, $agpr176, $agpr177, $agpr178, $agpr179, $agpr180, $agpr181, $agpr182, $agpr183, $agpr184, $agpr185, $agpr186, $agpr187, $agpr188, $agpr189, $agpr190, $agpr191, $agpr192, $agpr193, $agpr194, $agpr195, $agpr196, $agpr197, $agpr198, $agpr199, $agpr200, $agpr201, $agpr202, $agpr203, $agpr204, $agpr205, $agpr206, $agpr207, $agpr208, $agpr209, $agpr210, $agpr211, $agpr212, $agpr213, $agpr214, $agpr215, $agpr216, $agpr217, $agpr218, $agpr219, $agpr220, $agpr221, $agpr222, $agpr223, $agpr224, $agpr225, $agpr226, $agpr227, $agpr228, $agpr229, $agpr230, $agpr231, $agpr232, $agpr233, $agpr234, $agpr235, $agpr236, $agpr237, $agpr238, $agpr239, $agpr240, $agpr241, $agpr242, $agpr243, $agpr244, $agpr245, $agpr246, $agpr247, $agpr248, $agpr249, $agpr250, $agpr251, $agpr252, $agpr253, $agpr254, $agpr255, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6
; GFX90A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
@@ -13547,7 +13547,7 @@ body: |
; GFX90A-FLATSCR-LABEL: name: agpr96_save_clobber_scc
; GFX90A-FLATSCR: bb.0:
; GFX90A-FLATSCR-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; GFX90A-FLATSCR-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
+ ; GFX90A-FLATSCR-NEXT: liveins: $agpr32, $agpr33, $agpr34, $agpr35, $agpr36, $agpr37, $agpr38, $agpr39, $agpr40, $agpr41, $agpr42, $agpr43, $agpr44, $agpr45, $agpr46, $agpr47, $agpr48, $agpr49, $agpr50, $agpr51, $agpr52, $agpr53, $agpr54, $agpr55, $agpr56, $agpr57, $agpr58, $agpr59, $agpr60, $agpr61, $agpr62, $agpr63, $agpr64, $agpr65, $agpr66, $agpr67, $agpr68, $agpr69, $agpr70, $agpr71, $agpr72, $agpr73, $agpr74, $agpr75, $agpr76, $agpr77, $agpr78, $agpr79, $agpr80, $agpr81, $agpr82, $agpr83, $agpr84, $agpr85, $agpr86, $agpr87, $agpr88, $agpr89, $agpr90, $agpr91, $agpr92, $agpr93, $agpr94, $agpr95, $agpr96, $agpr97, $agpr98, $agpr99, $agpr100, $agpr101, $agpr102, $agpr103, $agpr104, $agpr105, $agpr106, $agpr107, $agpr108, $agpr109, $agpr110, $agpr111, $agpr112, $agpr113, $agpr114, $agpr115, $agpr116, $agpr117, $agpr118, $agpr119, $agpr120, $agpr121, $agpr122, $agpr123, $agpr124, $agpr125, $agpr126, $agpr127, $agpr128, $agpr129, $agpr130, $agpr131, $agpr132, $agpr133, $agpr134, $agpr135, $agpr136, $agpr137, $agpr138, $agpr139, $agpr140, $agpr141, $agpr142, $agpr143, $agpr144, $agpr145, $agpr146, $agpr147, $agpr148, $agpr149, $agpr150, $agpr151, $agpr152, $agpr153, $agpr154, $agpr155, $agpr156, $agpr157, $agpr158, $agpr159, $agpr160, $agpr161, $agpr162, $agpr163, $agpr164, $agpr165, $agpr166, $agpr167, $agpr168, $agpr169, $agpr170, $agpr171, $agpr172, $agpr173, $agpr174, $agpr175, $agpr176, $agpr177, $agpr178, $agpr179, $agpr180, $agpr181, $agpr182, $agpr183, $agpr184, $agpr185, $agpr186, $agpr187, $agpr188, $agpr189, $agpr190, $agpr191, $agpr192, $agpr193, $agpr194, $agpr195, $agpr196, $agpr197, $agpr198, $agpr199, $agpr200, $agpr201, $agpr202, $agpr203, $agpr204, $agpr205, $agpr206, $agpr207, $agpr208, $agpr209, $agpr210, $agpr211, $agpr212, $agpr213, $agpr214, $agpr215, $agpr216, $agpr217, $agpr218, $agpr219, $agpr220, $agpr221, $agpr222, $agpr223, $agpr224, $agpr225, $agpr226, $agpr227, $agpr228, $agpr229, $agpr230, $agpr231, $agpr232, $agpr233, $agpr234, $agpr235, $agpr236, $agpr237, $agpr238, $agpr239, $agpr240, $agpr241, $agpr242, $agpr243, $agpr244, $agpr245, $agpr246, $agpr247, $agpr248, $agpr249, $agpr250, $agpr251, $agpr252, $agpr253, $agpr254, $agpr255, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
; GFX90A-FLATSCR-NEXT: {{ $}}
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02
; GFX90A-FLATSCR-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
diff --git a/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll b/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll
index 837b66dadbba5..49113a3d45340 100644
--- a/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll
+++ b/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll
@@ -18,8 +18,8 @@ define void @tail_call_i32_inreg_divergent(i32 %vgpr) #0 {
; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
; CHECK-NEXT: v_writelane_b32 v40, s16, 2
-; CHECK-NEXT: s_addk_i32 s32, 0x400
; CHECK-NEXT: v_writelane_b32 v40, s30, 0
+; CHECK-NEXT: s_addk_i32 s32, 0x400
; CHECK-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-NEXT: s_getpc_b64 s[16:17]
; CHECK-NEXT: s_add_u32 s16, s16, void_func_i32_inreg at rel32@lo+4
@@ -51,14 +51,14 @@ define void @indirect_tail_call_i32_inreg_divergent(i32 %vgpr) #0 {
; CHECK-NEXT: s_or_saveexec_b64 s[18:19], -1
; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; CHECK-NEXT: s_mov_b64 exec, s[18:19]
-; CHECK-NEXT: s_addk_i32 s32, 0x400
; CHECK-NEXT: v_writelane_b32 v40, s16, 2
+; CHECK-NEXT: v_writelane_b32 v40, s30, 0
+; CHECK-NEXT: s_addk_i32 s32, 0x400
+; CHECK-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-NEXT: s_getpc_b64 s[16:17]
; CHECK-NEXT: s_add_u32 s16, s16, constant at rel32@lo+4
; CHECK-NEXT: s_addc_u32 s17, s17, constant at rel32@hi+12
; CHECK-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; CHECK-NEXT: v_writelane_b32 v40, s30, 0
-; CHECK-NEXT: v_writelane_b32 v40, s31, 1
; CHECK-NEXT: ; illegal copy v0 to s0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
index c44fff4ad82be..381ed25dfa9ba 100644
--- a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
+++ b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
@@ -369,10 +369,10 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) #0 {
; DAGISEL-NEXT: scratch_store_b32 off, v49, s32 offset:16
; DAGISEL-NEXT: s_mov_b32 exec_lo, -1
; DAGISEL-NEXT: scratch_store_b32 off, v40, s32 offset:12 ; 4-byte Folded Spill
+; DAGISEL-NEXT: v_writelane_b32 v2, s20, 0
; DAGISEL-NEXT: ;;#ASMSTART
; DAGISEL-NEXT: ; clobber CSR
; DAGISEL-NEXT: ;;#ASMEND
-; DAGISEL-NEXT: v_writelane_b32 v2, s20, 0
; DAGISEL-NEXT: ;;#ASMSTART
; DAGISEL-NEXT: ; clobber non-CSR
; DAGISEL-NEXT: ;;#ASMEND
@@ -408,10 +408,10 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) #0 {
; GISEL-NEXT: scratch_store_b32 off, v49, s32 offset:16
; GISEL-NEXT: s_mov_b32 exec_lo, -1
; GISEL-NEXT: scratch_store_b32 off, v40, s32 offset:12 ; 4-byte Folded Spill
+; GISEL-NEXT: v_writelane_b32 v2, s20, 0
; GISEL-NEXT: ;;#ASMSTART
; GISEL-NEXT: ; clobber CSR
; GISEL-NEXT: ;;#ASMEND
-; GISEL-NEXT: v_writelane_b32 v2, s20, 0
; GISEL-NEXT: ;;#ASMSTART
; GISEL-NEXT: ; clobber non-CSR
; GISEL-NEXT: ;;#ASMEND
@@ -447,10 +447,10 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) #0 {
; DAGISEL64-NEXT: scratch_store_b32 off, v49, s32 offset:16
; DAGISEL64-NEXT: s_mov_b64 exec, -1
; DAGISEL64-NEXT: scratch_store_b32 off, v40, s32 offset:12 ; 4-byte Folded Spill
+; DAGISEL64-NEXT: v_writelane_b32 v2, s20, 0
; DAGISEL64-NEXT: ;;#ASMSTART
; DAGISEL64-NEXT: ; clobber CSR
; DAGISEL64-NEXT: ;;#ASMEND
-; DAGISEL64-NEXT: v_writelane_b32 v2, s20, 0
; DAGISEL64-NEXT: ;;#ASMSTART
; DAGISEL64-NEXT: ; clobber non-CSR
; DAGISEL64-NEXT: ;;#ASMEND
@@ -487,10 +487,10 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) #0 {
; GISEL64-NEXT: scratch_store_b32 off, v49, s32 offset:16
; GISEL64-NEXT: s_mov_b64 exec, -1
; GISEL64-NEXT: scratch_store_b32 off, v40, s32 offset:12 ; 4-byte Folded Spill
+; GISEL64-NEXT: v_writelane_b32 v2, s20, 0
; GISEL64-NEXT: ;;#ASMSTART
; GISEL64-NEXT: ; clobber CSR
; GISEL64-NEXT: ;;#ASMEND
-; GISEL64-NEXT: v_writelane_b32 v2, s20, 0
; GISEL64-NEXT: ;;#ASMSTART
; GISEL64-NEXT: ; clobber non-CSR
; GISEL64-NEXT: ;;#ASMEND
@@ -525,11 +525,11 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) #0 {
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1
; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s32 offset:12 ; 4-byte Folded Spill
+; GFX1250-DAGISEL-NEXT: v_writelane_b32 v2, s20, 0
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: ;;#ASMSTART
; GFX1250-DAGISEL-NEXT: ; clobber CSR
; GFX1250-DAGISEL-NEXT: ;;#ASMEND
-; GFX1250-DAGISEL-NEXT: v_writelane_b32 v2, s20, 0
; GFX1250-DAGISEL-NEXT: ;;#ASMSTART
; GFX1250-DAGISEL-NEXT: ; clobber non-CSR
; GFX1250-DAGISEL-NEXT: ;;#ASMEND
@@ -1582,17 +1582,16 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; DAGISEL-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; DAGISEL-NEXT: s_wait_alu 0xfffe
; DAGISEL-NEXT: v_writelane_b32 v40, s0, 3
+; DAGISEL-NEXT: s_addk_co_i32 s32, 0x250
+; DAGISEL-NEXT: v_writelane_b32 v40, s4, 0
+; DAGISEL-NEXT: v_writelane_b32 v40, s30, 1
+; DAGISEL-NEXT: v_writelane_b32 v40, s31, 2
; DAGISEL-NEXT: v_mov_b32_e32 v2, v0
; DAGISEL-NEXT: v_swap_b32 v0, v1
; DAGISEL-NEXT: s_mov_b32 s1, gfx_callee at abs32@hi
-; DAGISEL-NEXT: v_writelane_b32 v40, s4, 0
; DAGISEL-NEXT: s_mov_b32 s0, gfx_callee at abs32@lo
-; DAGISEL-NEXT: s_addk_co_i32 s32, 0x250
-; DAGISEL-NEXT: v_writelane_b32 v40, s30, 1
-; DAGISEL-NEXT: v_writelane_b32 v40, s31, 2
; DAGISEL-NEXT: s_wait_alu 0xfffe
; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL-NEXT: v_readlane_b32 s30, v40, 1
; DAGISEL-NEXT: v_readlane_b32 s31, v40, 2
; DAGISEL-NEXT: v_readlane_b32 s4, v40, 0
@@ -1918,17 +1917,16 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; GISEL-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GISEL-NEXT: s_wait_alu 0xfffe
; GISEL-NEXT: v_writelane_b32 v40, s0, 3
+; GISEL-NEXT: s_addk_co_i32 s32, 0x250
+; GISEL-NEXT: v_writelane_b32 v40, s4, 0
+; GISEL-NEXT: v_writelane_b32 v40, s30, 1
+; GISEL-NEXT: v_writelane_b32 v40, s31, 2
; GISEL-NEXT: v_mov_b32_e32 v2, v0
; GISEL-NEXT: v_swap_b32 v0, v1
; GISEL-NEXT: s_mov_b32 s0, gfx_callee at abs32@lo
-; GISEL-NEXT: v_writelane_b32 v40, s4, 0
; GISEL-NEXT: s_mov_b32 s1, gfx_callee at abs32@hi
-; GISEL-NEXT: s_addk_co_i32 s32, 0x250
-; GISEL-NEXT: v_writelane_b32 v40, s30, 1
-; GISEL-NEXT: v_writelane_b32 v40, s31, 2
; GISEL-NEXT: s_wait_alu 0xfffe
; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-NEXT: v_readlane_b32 s30, v40, 1
; GISEL-NEXT: v_readlane_b32 s31, v40, 2
; GISEL-NEXT: v_readlane_b32 s4, v40, 0
@@ -2254,18 +2252,17 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; DAGISEL64-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; DAGISEL64-NEXT: s_wait_alu 0xfffe
; DAGISEL64-NEXT: v_writelane_b32 v40, s0, 4
-; DAGISEL64-NEXT: v_mov_b32_e32 v2, v0
-; DAGISEL64-NEXT: v_swap_b32 v0, v1
-; DAGISEL64-NEXT: s_mov_b32 s1, gfx_callee at abs32@hi
-; DAGISEL64-NEXT: v_writelane_b32 v40, s4, 0
-; DAGISEL64-NEXT: s_mov_b32 s0, gfx_callee at abs32@lo
; DAGISEL64-NEXT: s_addk_co_i32 s32, 0x250
+; DAGISEL64-NEXT: v_writelane_b32 v40, s4, 0
; DAGISEL64-NEXT: v_writelane_b32 v40, s5, 1
; DAGISEL64-NEXT: v_writelane_b32 v40, s30, 2
; DAGISEL64-NEXT: v_writelane_b32 v40, s31, 3
+; DAGISEL64-NEXT: v_mov_b32_e32 v2, v0
+; DAGISEL64-NEXT: v_swap_b32 v0, v1
+; DAGISEL64-NEXT: s_mov_b32 s1, gfx_callee at abs32@hi
+; DAGISEL64-NEXT: s_mov_b32 s0, gfx_callee at abs32@lo
; DAGISEL64-NEXT: s_wait_alu 0xfffe
; DAGISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; DAGISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; DAGISEL64-NEXT: v_readlane_b32 s30, v40, 2
; DAGISEL64-NEXT: v_readlane_b32 s31, v40, 3
; DAGISEL64-NEXT: v_readlane_b32 s5, v40, 1
@@ -2592,18 +2589,17 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; GISEL64-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GISEL64-NEXT: s_wait_alu 0xfffe
; GISEL64-NEXT: v_writelane_b32 v40, s0, 4
-; GISEL64-NEXT: v_mov_b32_e32 v2, v0
-; GISEL64-NEXT: v_swap_b32 v0, v1
-; GISEL64-NEXT: s_mov_b32 s0, gfx_callee at abs32@lo
-; GISEL64-NEXT: v_writelane_b32 v40, s4, 0
-; GISEL64-NEXT: s_mov_b32 s1, gfx_callee at abs32@hi
; GISEL64-NEXT: s_addk_co_i32 s32, 0x250
+; GISEL64-NEXT: v_writelane_b32 v40, s4, 0
; GISEL64-NEXT: v_writelane_b32 v40, s5, 1
; GISEL64-NEXT: v_writelane_b32 v40, s30, 2
; GISEL64-NEXT: v_writelane_b32 v40, s31, 3
+; GISEL64-NEXT: v_mov_b32_e32 v2, v0
+; GISEL64-NEXT: v_swap_b32 v0, v1
+; GISEL64-NEXT: s_mov_b32 s0, gfx_callee at abs32@lo
+; GISEL64-NEXT: s_mov_b32 s1, gfx_callee at abs32@hi
; GISEL64-NEXT: s_wait_alu 0xfffe
; GISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GISEL64-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL64-NEXT: v_readlane_b32 s30, v40, 2
; GISEL64-NEXT: v_readlane_b32 s31, v40, 3
; GISEL64-NEXT: v_readlane_b32 s5, v40, 1
@@ -3710,15 +3706,15 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2
; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
; GFX1250-DAGISEL-NEXT: v_writelane_b32 v40, s0, 3
-; GFX1250-DAGISEL-NEXT: v_mov_b32_e32 v2, v0
-; GFX1250-DAGISEL-NEXT: v_swap_b32 v0, v1
-; GFX1250-DAGISEL-NEXT: s_mov_b64 s[0:1], gfx_callee at abs64
-; GFX1250-DAGISEL-NEXT: v_writelane_b32 v40, s4, 0
; GFX1250-DAGISEL-NEXT: s_addk_co_i32 s32, 0xe50
+; GFX1250-DAGISEL-NEXT: v_writelane_b32 v40, s4, 0
; GFX1250-DAGISEL-NEXT: v_writelane_b32 v40, s30, 1
; GFX1250-DAGISEL-NEXT: v_writelane_b32 v40, s31, 2
+; GFX1250-DAGISEL-NEXT: v_mov_b32_e32 v2, v0
+; GFX1250-DAGISEL-NEXT: v_swap_b32 v0, v1
+; GFX1250-DAGISEL-NEXT: s_mov_b64 s[0:1], gfx_callee at abs64
+; GFX1250-DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-DAGISEL-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
-; GFX1250-DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-DAGISEL-NEXT: v_readlane_b32 s30, v40, 1
; GFX1250-DAGISEL-NEXT: v_readlane_b32 s31, v40, 2
; GFX1250-DAGISEL-NEXT: v_readlane_b32 s4, v40, 0
@@ -8038,13 +8034,13 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; DAGISEL-NEXT: scratch_store_b32 off, v41, s33 offset:168
; DAGISEL-NEXT: s_wait_alu 0xfffe
; DAGISEL-NEXT: v_writelane_b32 v42, s0, 3
-; DAGISEL-NEXT: s_mov_b32 s1, callee at abs32@hi
-; DAGISEL-NEXT: s_mov_b32 s0, callee at abs32@lo
; DAGISEL-NEXT: s_addk_co_i32 s32, 0x250
-; DAGISEL-NEXT: v_dual_mov_b32 v41, v9 :: v_dual_mov_b32 v40, v8
; DAGISEL-NEXT: v_writelane_b32 v42, s4, 0
; DAGISEL-NEXT: v_writelane_b32 v42, s30, 1
; DAGISEL-NEXT: v_writelane_b32 v42, s31, 2
+; DAGISEL-NEXT: s_mov_b32 s1, callee at abs32@hi
+; DAGISEL-NEXT: s_mov_b32 s0, callee at abs32@lo
+; DAGISEL-NEXT: v_dual_mov_b32 v41, v9 :: v_dual_mov_b32 v40, v8
; DAGISEL-NEXT: s_wait_alu 0xfffe
; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; DAGISEL-NEXT: flat_store_b32 v[40:41], v0
@@ -8379,13 +8375,13 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; GISEL-NEXT: scratch_store_b32 off, v41, s33 offset:168
; GISEL-NEXT: s_wait_alu 0xfffe
; GISEL-NEXT: v_writelane_b32 v42, s0, 3
-; GISEL-NEXT: s_mov_b32 s0, callee at abs32@lo
-; GISEL-NEXT: s_mov_b32 s1, callee at abs32@hi
; GISEL-NEXT: s_addk_co_i32 s32, 0x250
-; GISEL-NEXT: v_dual_mov_b32 v40, v8 :: v_dual_mov_b32 v41, v9
; GISEL-NEXT: v_writelane_b32 v42, s4, 0
; GISEL-NEXT: v_writelane_b32 v42, s30, 1
; GISEL-NEXT: v_writelane_b32 v42, s31, 2
+; GISEL-NEXT: s_mov_b32 s0, callee at abs32@lo
+; GISEL-NEXT: s_mov_b32 s1, callee at abs32@hi
+; GISEL-NEXT: v_dual_mov_b32 v40, v8 :: v_dual_mov_b32 v41, v9
; GISEL-NEXT: s_wait_alu 0xfffe
; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GISEL-NEXT: flat_store_b32 v[40:41], v0
@@ -8720,15 +8716,15 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; DAGISEL64-NEXT: scratch_store_b32 off, v41, s33 offset:168
; DAGISEL64-NEXT: s_wait_alu 0xfffe
; DAGISEL64-NEXT: v_writelane_b32 v42, s0, 4
-; DAGISEL64-NEXT: s_mov_b32 s1, callee at abs32@hi
-; DAGISEL64-NEXT: s_mov_b32 s0, callee at abs32@lo
; DAGISEL64-NEXT: s_addk_co_i32 s32, 0x250
-; DAGISEL64-NEXT: v_mov_b32_e32 v41, v9
; DAGISEL64-NEXT: v_writelane_b32 v42, s4, 0
-; DAGISEL64-NEXT: v_mov_b32_e32 v40, v8
; DAGISEL64-NEXT: v_writelane_b32 v42, s5, 1
; DAGISEL64-NEXT: v_writelane_b32 v42, s30, 2
; DAGISEL64-NEXT: v_writelane_b32 v42, s31, 3
+; DAGISEL64-NEXT: s_mov_b32 s1, callee at abs32@hi
+; DAGISEL64-NEXT: s_mov_b32 s0, callee at abs32@lo
+; DAGISEL64-NEXT: v_mov_b32_e32 v41, v9
+; DAGISEL64-NEXT: v_mov_b32_e32 v40, v8
; DAGISEL64-NEXT: s_wait_alu 0xfffe
; DAGISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1]
; DAGISEL64-NEXT: flat_store_b32 v[40:41], v0
@@ -9064,15 +9060,15 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; GISEL64-NEXT: scratch_store_b32 off, v41, s33 offset:168
; GISEL64-NEXT: s_wait_alu 0xfffe
; GISEL64-NEXT: v_writelane_b32 v42, s0, 4
-; GISEL64-NEXT: s_mov_b32 s0, callee at abs32@lo
-; GISEL64-NEXT: s_mov_b32 s1, callee at abs32@hi
; GISEL64-NEXT: s_addk_co_i32 s32, 0x250
-; GISEL64-NEXT: v_mov_b32_e32 v40, v8
; GISEL64-NEXT: v_writelane_b32 v42, s4, 0
-; GISEL64-NEXT: v_mov_b32_e32 v41, v9
; GISEL64-NEXT: v_writelane_b32 v42, s5, 1
; GISEL64-NEXT: v_writelane_b32 v42, s30, 2
; GISEL64-NEXT: v_writelane_b32 v42, s31, 3
+; GISEL64-NEXT: s_mov_b32 s0, callee at abs32@lo
+; GISEL64-NEXT: s_mov_b32 s1, callee at abs32@hi
+; GISEL64-NEXT: v_mov_b32_e32 v40, v8
+; GISEL64-NEXT: v_mov_b32_e32 v41, v9
; GISEL64-NEXT: s_wait_alu 0xfffe
; GISEL64-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GISEL64-NEXT: flat_store_b32 v[40:41], v0
@@ -10188,13 +10184,13 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float>
; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41, s33 offset:168
; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x2
; GFX1250-DAGISEL-NEXT: v_writelane_b32 v42, s0, 3
-; GFX1250-DAGISEL-NEXT: s_mov_b64 s[0:1], callee at abs64
; GFX1250-DAGISEL-NEXT: s_addk_co_i32 s32, 0xe50
-; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
-; GFX1250-DAGISEL-NEXT: v_dual_mov_b32 v41, v9 :: v_dual_mov_b32 v40, v8
; GFX1250-DAGISEL-NEXT: v_writelane_b32 v42, s4, 0
; GFX1250-DAGISEL-NEXT: v_writelane_b32 v42, s30, 1
; GFX1250-DAGISEL-NEXT: v_writelane_b32 v42, s31, 2
+; GFX1250-DAGISEL-NEXT: s_mov_b64 s[0:1], callee at abs64
+; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0
+; GFX1250-DAGISEL-NEXT: v_dual_mov_b32 v41, v9 :: v_dual_mov_b32 v40, v8
; GFX1250-DAGISEL-NEXT: s_swap_pc_i64 s[30:31], s[0:1]
; GFX1250-DAGISEL-NEXT: flat_store_b32 v[40:41], v0
; GFX1250-DAGISEL-NEXT: v_readlane_b32 s30, v42, 1
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