[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: RegBankLegalize rules for G_FABS and G_FNEG (PR #168411)

[Petar Avramovic via llvm-branch-commits]

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@@ -629,10 +629,23 @@ void RegBankLegalizeHelper::lowerSplitTo32(MachineInstr &MI) {
 void RegBankLegalizeHelper::lowerSplitTo16(MachineInstr &MI) {
   Register Dst = MI.getOperand(0).getReg();
   assert(MRI.getType(Dst) == V2S16);
-  auto [Op1Lo32, Op1Hi32] = unpackAExt(MI.getOperand(1).getReg());
-  auto [Op2Lo32, Op2Hi32] = unpackAExt(MI.getOperand(2).getReg());
   unsigned Opc = MI.getOpcode();
   auto Flags = MI.getFlags();
+
+  if (MI.getNumOperands() == 2) {
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petar-avramovic wrote:

it is for unary opcodes, old one below was for binary

https://github.com/llvm/llvm-project/pull/168411