[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (PR #132385)

[Petar Avramovic via llvm-branch-commits]

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@@ -70,14 +70,29 @@ define i8 @v_ashr_i8_7(i8 %value) {
 }
 
 define amdgpu_ps i8 @s_ashr_i8(i8 inreg %value, i8 inreg %amount) {
-; GCN-LABEL: s_ashr_i8:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_sext_i32_i8 s0, s0
-; GCN-NEXT:    s_ashr_i32 s0, s0, s1
-; GCN-NEXT:    ; return to shader part epilog
+; GFX6-LABEL: s_ashr_i8:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_sext_i32_i8 s0, s0
+; GFX6-NEXT:    s_ashr_i32 s0, s0, s1
+; GFX6-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_ashr_i8:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_and_b32 s1, s1, 0xff
+; GFX8-NEXT:    s_sext_i32_i8 s0, s0
+; GFX8-NEXT:    s_ashr_i32 s0, s0, s1
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_ashr_i8:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_and_b32 s1, s1, 0xff
+; GFX9-NEXT:    s_sext_i32_i8 s0, s0
+; GFX9-NEXT:    s_ashr_i32 s0, s0, s1
+; GFX9-NEXT:    ; return to shader part epilog
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petar-avramovic wrote:

Not related to this patch. https://github.com/llvm/llvm-project/pull/131308 changed input to be s16. Old global-isel was doing s16->s32. However new regbankselect leaves s16 as is since a lot of tablegen patterns rely on s16 type check. Fix is todo somewhere in post reg bank combine (s16 AND + ZEXT to s32 -> AND s32)

https://github.com/llvm/llvm-project/pull/132385